Display device, display panel and manufacturing method thereof

Abstract

A display device, a display panel, and a method for manufacturing the same are disclosed. The display panel includes: a driving backplate (1) comprising a substrate (101), a wiring layer (103), and a planarization layer (104), wherein the wiring layer (103) is disposed on one side of the substrate (101); the planarization layer (104) covers the wiring layer (103) and has a groove (1041); a first electrode layer (2) disposed on the surface of the planarization layer (104) away from the substrate (101) and includes a plurality of first electrodes (21); and a pixel definition layer. (3) is disposed on the surface of the planarization layer (104) away from the substrate (101); the pixel definition layer (3) forms a partition groove (32) at the groove (1041); the conductive shielding layer (4) is at least partially disposed in the groove (1041); the light-emitting layer (5) covers the pixel definition layer (3) and the conductive shielding layer (4); the second electrode (6) covers the light-emitting layer (5); the color filter layer (7) is disposed on the side of the second electrode (6) away from the substrate (101) and includes a plurality of filter portions (71).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display device, a display panel, and a method for manufacturing the display panel. Background Technology

[0002] With the development of display technology, display panels have been widely used in various electronic devices such as mobile phones to achieve image display and touch operation. Among them, OLED (Organic Light-Emitting Diode) display panels are relatively common. However, the color gamut of existing display panels still needs to be improved.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display device, a display panel, and a method for manufacturing the display panel.

[0005] According to one aspect of this disclosure, a display panel is provided, comprising:

[0006] A drive backplane includes a substrate, at least one wiring layer, and a planarization layer, wherein the wiring layer is disposed on one side of the substrate; the planarization layer covers the wiring layer and has grooves.

[0007] A first electrode layer is disposed on the surface of the planarization layer opposite to the substrate, and includes a plurality of first electrodes spaced apart; the orthographic projection of the groove on the planarization layer is located outside the first electrodes;

[0008] A pixel definition layer is disposed on the surface of the planarization layer opposite to the substrate, and exposes each of the first electrodes; the pixel definition layer forms a partition groove at the groove;

[0009] A conductive shielding layer is at least partially disposed within the groove and is insulated from the first electrode;

[0010] A light-emitting layer covers the pixel definition layer, the first electrode, and the conductive shielding layer. The light-emitting layer is recessed at the partition groove and is in direct contact with at least a portion of the conductive shielding layer.

[0011] The second electrode covers the light-emitting layer.

[0012] In one exemplary embodiment of this disclosure, the pixel definition layer covers the bottom surface of the groove, and the pixel definition layer covering the bottom surface of the groove is the bottom surface of the partition groove; the conductive shielding layer is at least partially stacked on the bottom surface of the partition groove.

[0013] In one exemplary embodiment of this disclosure, the conductive shielding layer is disposed on the bottom surface of the groove; the pixel definition layer exposes at least a portion of the conductive shielding layer.

[0014] In one exemplary embodiment of this disclosure, the conductive shielding layer is connected to the second electrode.

[0015] In one exemplary embodiment of this disclosure, the dividing groove includes at least one annular groove body, one of the groove bodies surrounding a first electrode;

[0016] The conductive shielding layer includes at least one shielding ring, and one of the shielding rings is disposed in the groove.

[0017] Each of the aforementioned tanks and the shielding rings within them surround the same first electrode.

[0018] In one exemplary embodiment of this disclosure, the number of the grooves is the same as the number of the first electrodes, and each first electrode is surrounded by a groove, and each groove is provided with a shielding ring.

[0019] In one exemplary embodiment of this disclosure, the grooves are connected to form an integral structure, and the shielding rings are connected to form an integral structure.

[0020] In one exemplary embodiment of this disclosure, each of the shielding rings is connected to the second electrode.

[0021] In one exemplary embodiment of this disclosure, the driving backplate includes a pixel region and a peripheral region located outside the pixel region; the orthographic projection of the first electrode on the driving backplate is located within the pixel region; the orthographic projection of the edge of the second electrode on the driving backplate is located in the peripheral region.

[0022] The conductive shielding layer also includes a connector connected to the shielding ring, and the orthographic projection of the connector on the driving backplate extends from the pixel area to the peripheral area;

[0023] The second electrode is connected to the shielding ring via the connector.

[0024] In one exemplary embodiment of this disclosure, at least a portion of the shielding ring is connected to the second electrode through a first via penetrating the light-emitting layer, and the orthographic projection of at least one of the first vias on the planar layer is located between two adjacent first electrodes.

[0025] In one exemplary embodiment of this disclosure, at least one of the wiring layers includes a connection portion connected to the second electrode, and the shielding ring is connected to the connection portion through a second via penetrating the planarization layer.

[0026] In one exemplary embodiment of this disclosure, the shielding ring has a circumferentially extending ridge on the surface opposite to the substrate.

[0027] In one exemplary embodiment of this disclosure, the surface of the shielding ring facing away from the substrate is provided with a circumferentially extending recess, and the protrusions and the recess are distributed radially along the shielding ring.

[0028] In one exemplary embodiment of this disclosure, the thickness of the conductive shielding layer is less than the depth of the groove.

[0029] In one exemplary embodiment of this disclosure, the ratio of the width of the shielding ring to the width of the groove is less than 4:5.

[0030] In one exemplary embodiment of this disclosure, the thickness of the conductive shielding layer is greater than the thickness of the pixel definition layer.

[0031] In one exemplary embodiment of this disclosure, the conductive shielding layer is located on the side of the first electrode closer to the substrate.

[0032] In one exemplary embodiment of this disclosure, the bottom surface of the partition groove includes a central region and an edge region located outside the central region, and the orthographic projection of the conductive shielding layer on the bottom surface of the partition groove coincides with the central region; at least a portion of the edge region is located on the side of the central region away from the substrate.

[0033] In one exemplary embodiment of this disclosure, the conductive shielding layer includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially in a direction away from the substrate.

[0034] In one exemplary embodiment of this disclosure, the first conductive layer and the third conductive layer are both made of titanium, and the second conductive layer is made of aluminum.

[0035] In one exemplary embodiment of this disclosure, the depth of the dividing groove is 800μm-1000μm.

[0036] In one exemplary embodiment of this disclosure, the light-emitting layer includes multiple light-emitting sub-layers connected in series, and at least one of the light-emitting sub-layers is connected in series with an adjacent light-emitting sub-layer through a charge generation layer.

[0037] In one exemplary embodiment of this disclosure, the second electrode is recessed at the partition groove to form a recessed region, and the bottom of the recessed region, corresponding to the area of ​​the conductive shielding layer, protrudes in a direction away from the conductive shielding layer.

[0038] According to one aspect of this disclosure, a method for manufacturing a display panel is provided, comprising:

[0039] A driving backplane is formed, the driving backplane including a substrate, at least one wiring layer and a planarization layer, the wiring layer being disposed on one side of the substrate; the planarization layer covering the wiring layer.

[0040] A groove is formed in the flat layer;

[0041] A first electrode layer is formed on the surface of the planarization layer opposite to the substrate, the first electrode layer comprising a plurality of first electrodes spaced apart; the orthogonal projection of the groove on the planarization layer is located outside the first electrodes;

[0042] A pixel definition layer is formed on the surface of the planar layer opposite to the substrate, exposing each of the first electrodes, and the pixel definition layer forms a separation groove at the groove;

[0043] A conductive shielding layer is formed at least within the partition groove;

[0044] A light-emitting layer is formed covering the pixel definition layer, the first electrode, and the conductive shielding layer. The light-emitting layer is recessed at the partition groove and is in direct contact with at least a portion of the conductive shielding layer.

[0045] A second electrode is formed to cover the light-emitting layer.

[0046] According to one aspect of this disclosure, a method for manufacturing a display panel is provided, comprising:

[0047] A driving backplane is formed, the driving backplane including a substrate, at least one wiring layer and a planarization layer, the wiring layer being disposed on one side of the substrate; the planarization layer covering the wiring layer.

[0048] A groove is formed in the planarization layer, and the orthographic projection of the groove on the planarization layer is located outside the first electrode;

[0049] A conductive shielding layer is formed at least within the groove;

[0050] A first electrode layer is formed on the surface of the planarization layer opposite to the substrate, the first electrode layer comprising a plurality of first electrodes spaced apart; the orthogonal projection of the groove on the planarization layer is located outside the first electrodes;

[0051] A pixel definition layer is formed on the surface of the planar layer opposite to the substrate, exposing each of the first electrodes and the conductive shielding layer, and the pixel definition layer forms a separation groove at the groove;

[0052] A light-emitting layer is formed covering the pixel definition layer, the first electrode, and the conductive shielding layer. The light-emitting layer is recessed at the partition groove and is in direct contact with at least a portion of the conductive shielding layer.

[0053] A second electrode is formed to cover the light-emitting layer.

[0054] According to one aspect of this disclosure, a display device is provided, comprising the display panel described in any of the preceding claims.

[0055] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0056] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0057] Figure 1 This is a circuit diagram illustrating leakage current in a light-emitting unit in a related technology.

[0058] Figure 2 This is a schematic diagram of the leakage current structure of the light-emitting unit in related technologies.

[0059] Figure 3 This is a spectral diagram of the light-emitting unit in the related technology.

[0060] Figure 4 This is a schematic diagram of one embodiment of the display panel of this disclosure.

[0061] Figure 5 This is a top view of the drive backplate in one embodiment of the display panel of this disclosure.

[0062] Figure 6 This is a top view of the pixel definition layer and conductive shielding layer in one embodiment of the display panel of this disclosure.

[0063] Figure 7 This is a schematic diagram of the light-emitting layer in one embodiment of the display panel of this disclosure.

[0064] Figure 8 This is a schematic diagram of another embodiment of the display panel of this disclosure.

[0065] Figure 9 This is a schematic diagram of another embodiment of the display panel of this disclosure.

[0066] Figure 10 This is a schematic diagram of yet another embodiment of the display panel of this disclosure.

[0067] Figure 11 This is a schematic diagram of the middle and edge areas of the partition groove in one embodiment of the display panel of this disclosure.

[0068] Figure 12 This is a schematic diagram of the middle and edge areas of the partition groove in another embodiment of the display panel of this disclosure.

[0069] Figure 13 This is a schematic diagram of the protruding ridge of the shielding ring in one embodiment of the display panel of this disclosure.

[0070] Figure 14 This is a schematic diagram of the protruding ridges and recesses of the shielding ring in one embodiment of the display panel of this disclosure.

[0071] Figure 15 This is a circuit diagram for preventing leakage current in the display panel disclosed herein.

[0072] Figure 16 This is a spectral diagram of one embodiment of the display panel of this disclosure.

[0073] Figure 17 This is a voltage-brightness schematic diagram of one embodiment of the display panel of this disclosure.

[0074] Figure 18 This is a schematic diagram of the voltage-color coordinates of the red sub-pixel in one embodiment of the display panel of this disclosure.

[0075] Figure 19 This is a schematic diagram of the voltage-color coordinates of the blue sub-pixel in one embodiment of the display panel of this disclosure.

[0076] Figure 20 This is a schematic diagram of the voltage-color coordinates of a green sub-pixel in one embodiment of the display panel of this disclosure.

[0077] Figures 21-25 This is a structural schematic diagram of some steps in one embodiment of the method for manufacturing a display panel according to the present disclosure.

[0078] Figure 26 This is a schematic diagram of step S230 in another embodiment of the method for manufacturing the display panel of this disclosure.

[0079] Explanation of reference numerals in the attached figures:

[0080] 1. Driving backplane; 110. Pixel area; 120. Peripheral area; 101. Substrate; 1011. Well region; 1012. Doped region; 102. Gate; 103. Wiring layer; 1031. First wiring layer; 1031S. Source; 1031D. Drain; 1032. Second wiring layer; 1032a. Connector; 104. Planarization layer; 1041. Groove;

[0081] 2. First electrode layer; 21. First electrode; 201. First layer; 202. Second layer; 203. Third layer; 204. Fourth layer;

[0082] 3. Pixel definition layer; 31. Opening; 32. Divider slot; 321. Slot body; 322. Middle area; 323. Edge area;

[0083] 4. Conductive shielding layer; 401. First conductive layer; 402. Second conductive layer; 403. Third conductive layer; 41. Shielding ring; 42. Connector; 4011. Raised ridge; 4012. Dent;

[0084] 5. Light-emitting layer; 51. Light-emitting sublayer; 52. Charge generation layer; 001. Light-emitting unit; 0011. Light-emitting device;

[0085] 6. Second electrode; 61. Recessed area;

[0086] 7. Color filter layer; 71. Filter section; 72. Light-shielding section;

[0087] 8. First encapsulation layer; 81. First encapsulation sublayer; 82. Second encapsulation sublayer; 83. Third encapsulation sublayer;

[0088] 9. Second encapsulation layer;

[0089] 10. Transparent cover;

[0090] 11. Light extraction layer;

[0091] H1, first via; H2, second via. Detailed Implementation

[0092] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0093] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0094] Among related technologies, Micro OLED (Micro Organic Light-Emitting Diode) display panels are a type of display panel that has emerged in recent years. The Micro OLED light-emitting devices they contain typically have a size of less than 100μm. Silicon-based OLED display panels are a common type. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of CMOS circuits, including pixel circuits, timing control (TCON) circuits, and overcurrent protection (OCP) circuits, on a silicon substrate using semiconductor manufacturing processes. This facilitates a reduction in system size and achieves lightweight design.

[0095] Taking a silicon-based OLED display panel as an example, it may include a driving backplane and an emissive layer. The emissive functional layer is located on one side of the driving backplane and includes multiple emissive devices. The emissive unit may include one or more OLED emissive devices connected in series. Each emissive device includes a first electrode (anode), an emissive layer and a second electrode (cathode) stacked sequentially in the direction away from the driving backplane. By applying an electrical signal to the first electrode and the second electrode, the emissive layer can be driven to emit light. The specific light-emitting principle of the OLED emissive device will not be detailed here.

[0096] Furthermore, the light-emitting layers of each light-emitting device can be directly deposited using a fine mask (FMM). The light-emitting layers of each device are spaced apart and emit light independently, achieving color display. However, due to limitations in the fine mask manufacturing process, achieving a high PPI (pixel density) is difficult. Therefore, color display can also be achieved using monochromatic light or white light in conjunction with a color filter. This involves each light-emitting device sharing the same continuous light-emitting layer, which can emit white light or other monochromatic light. The color filter layer has multiple filter areas corresponding one-to-one with the light-emitting units. One filter area and its corresponding light-emitting unit constitute a sub-pixel. Multiple sub-pixels constitute one pixel. Different filter areas can transmit different colors of light, allowing different sub-pixels to emit different colors. A single pixel can include multiple sub-pixels of different colors; for example, a pixel can include three sub-pixels emitting red (R), green (G), and blue (B) colors. Thus, color display can be achieved using multiple pixels.

[0097] However, if the light-emitting layer is a continuous monolithic structure, leakage can easily occur between one light-emitting unit and surrounding light-emitting units, leading to color crosstalk. The causes of color crosstalk are analyzed below with reference to the attached diagram:

[0098] like Figure 1 As shown, each light-emitting unit may include two light-emitting devices connected in series. The two light-emitting devices share a first electrode 2a and a second electrode 3a. Two light-emitting sub-layers 1a are located between the first electrode 2a and the second electrode 3a, and the two light-emitting sub-layers 1a are connected in series through a charge generation layer 4a to form a light-emitting layer. Figure 1 and Figure 2 It can be seen that positive charges (holes) are transferred between two adjacent light-emitting units through the charge generation layer 4a, while Figure 2 It can be seen that when the light-emitting unit of the red filter area R in the corresponding color filter layer 5a emits light, due to the influence of leakage current, the light-emitting unit of the green filter area G in the corresponding color filter layer 5a will also emit light, resulting in a decrease in the light emission purity of a single pixel and a decrease in the color gamut of the entire display panel.

[0099] like Figure 3 As shown, Figure 3 The image shows the spectrum of red (R), green (G), and blue (B) sub-pixels in the same pixel when they are lit simultaneously. Figure 3 (as shown in a) and the respective illuminated spectra ( Figure 3 (As shown in bc). Based on the wavelengths, it can be seen that when the three sub-pixels are lit respectively, light of different colors escapes from adjacent sub-pixels. For example, Figure 3 As shown in 'a', when the R sub-pixel emits red light, there are peaks at the wavelengths corresponding to blue and green light, meaning it is emitted by blue and green light. This causes a reduction in the color gamut of the entire display panel. According to calculations, the color gamut index (NTSC) of this display panel is only 30%.

[0100] This disclosure provides a display panel, such as... Figures 4-8 As shown, the display panel may include a driving backplate 1, a first electrode layer 2, a pixel definition layer 3, a conductive shielding layer 4, a light-emitting layer 5, a second electrode 6, and a color filter layer 7, wherein:

[0101] The drive backplane 1 includes a substrate 101, at least one wiring layer 103 and a planarization layer 104. The wiring layer 103 is disposed on one side of the substrate 101. The planarization layer 104 covers the wiring layer 103 and has a groove 1041.

[0102] The first electrode layer 2 is disposed on the surface of the planarization layer 104 away from the substrate 101, and includes a plurality of first electrodes 21 spaced apart. The orthographic projection of the groove 1041 on the planarization layer 104 is located outside the first electrodes 21. The pixel definition layer 3 is disposed on the surface of the planarization layer 104 away from the substrate 101, and exposes each of the first electrodes 21; the pixel definition layer 3 forms a partition groove 32 at the groove 1041. The conductive shielding layer 4 is at least partially disposed within the groove 1041. The light-emitting layer 5 covers the pixel definition layer 3, the first electrodes 21 and the conductive shielding layer 4, and the light-emitting layer 5 is recessed at the partition groove 32 and is in direct contact with at least a portion of the conductive shielding layer 4. The second electrode 6 covers the light-emitting layer 5.

[0103] In the display panel of this embodiment, any first electrode 21 and its corresponding light-emitting layer 5 and second electrode 6 can constitute a light-emitting unit 001. Since the conductive shielding layer 4 is located within the groove 1041 and is insulated from the first electrode 21, and simultaneously, the conductive shielding layer 4 is in direct contact with the light-emitting layer 5, and the orthogonal projection of the groove 1041 onto the planarization layer 104 is outside the first electrode 21, the conductive shielding layer 4 can absorb charge carriers (e.g., holes) generated in the light-emitting layer 5 that move along the distribution direction of the first electrode 21, preventing leakage between light-emitting units 001 and thus improving color crosstalk. Simultaneously, the groove 1041 gives the pixel definition layer 3 a separating groove 32, which can separate each light-emitting unit 001. The light-emitting layer 5 is recessed at the separating groove 32, which facilitates thinning or even breaking of the light-emitting layer 5 at the separating groove 32, and also prevents leakage between adjacent light-emitting units 001, improving color crosstalk.

[0104] The following is a detailed description of the structure by which the display panel of this disclosure implements its display function:

[0105] like Figure 4 , Figure 5 and Figure 8 As shown, the driving backplate 1 may include a pixel area 110 and a peripheral area 120. The peripheral area 120 is located outside the pixel area 110 and may be disposed around the pixel area 110. The driving backplate 1 is used to form a driving circuit for driving the light-emitting unit 001 to emit light. The driving circuit may include pixel circuitry and peripheral circuitry, wherein:

[0106] The number of pixel circuits and light-emitting units 001 can both be multiple, and the pixel circuits are located within the pixel area 110. The pixel circuits can be 2T1C, 4T2C, 6T1C, or 7T1C, etc., as long as they can drive the light-emitting units 001 to emit light; no special restrictions are placed on their structure here. The number of pixel circuits is the same as the number of first electrodes 21, and they are connected to the first electrodes 21 in a one-to-one correspondence, so as to control the light emission of each light-emitting unit 001 respectively. Here, nTmC indicates that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C").

[0107] The peripheral circuit is located in the peripheral area 120 and is connected to the pixel circuit. The peripheral circuit may include at least one of a light-emitting control circuit, a gate 102 driving circuit, a source driving circuit, and a power supply circuit. It may also include other circuits, as long as they can drive the light-emitting unit 001 to emit light through the pixel circuit. Simultaneously, the peripheral circuit may also include a power supply circuit connected to the second electrode 6 for inputting a power signal to the second electrode 6. The peripheral circuit can input a driving signal to the first electrode 21 and a power signal to the second electrode 6 through the pixel circuit, thereby causing the light-emitting unit 001 to emit light.

[0108] In some embodiments of this disclosure, such as Figure 4 and Figure 8 As shown, the driving backplane 1 may include a substrate 101, which may be a silicon substrate. The driving circuit described above can be formed on the silicon substrate by semiconductor processes. For example, both the pixel circuit and the peripheral circuit may include multiple transistors. A well region 1011 can be formed in the silicon substrate by a doping process. The well region 1011 has two doped regions 1012 spaced apart. Taking one well region 1011 as an example: a gate 102 is provided on one side of the driving backplane 1, that is, the orthogonal projection of the gate 102 on the driving backplane 1 is located between the two doped regions 1012. The driving backplane 1 may also include at least one wiring layer 103 and a planarization layer 104. The wiring layer 103 is disposed on one side of the substrate 101, and the planarization layer 104 covers the wiring layer 103. The doped regions 1012 of the at least one wiring layer 103 are connected, and include the source 1031S and drain 1031D of the two doped regions 1012 connected to the same well region 1011.

[0109] For example, the number of wiring layers 103 is two, and they are located within the planarization layer 104. For example, the wiring layer 103 includes a first wiring layer 1031 and a second wiring layer 1032. The first wiring layer 1031 is disposed on one side of the substrate 101, and a portion of the planarization layer 104 is disposed between it and the substrate 101. The first wiring layer 1031 includes a source 1031S and a drain 1031D. The source 1031S and drain 1031D of the same transistor are respectively connected to the two doped regions 1012 of the same well region 1011, so that a transistor can be formed through a well region 1011 and its corresponding gate 102, source 1031S and drain 1031D. The second wiring layer 1032 is disposed on the side of the first wiring layer 1031 facing away from the substrate 101. It is separated from the first wiring layer 1031 by a portion of the planarization layer 104, and at least a portion of the second wiring layer 1032 is connected to the first wiring layer 1031. Transistors can be connected through each wiring layer 103 to form a driving circuit. The specific connection lines and wiring patterns depend on the circuit structure and are not specifically limited here.

[0110] Each wiring layer 103 can be formed by sputtering. The planarization layer 104 can be made of silicon oxide, silicon oxynitride, or silicon nitride, and is formed layer by layer through multiple deposition and polishing processes. In other words, the planarization layer 104 can be formed by stacking multiple insulating film layers.

[0111] like Figure 4 and Figure 8 As shown, the array of light-emitting units 001 of the display panel is distributed on one side of the driving backplate 1. For example, each light-emitting unit 001 is disposed on the surface of the planarization layer 104 facing away from the substrate 101. Each light-emitting unit 001 may include a first electrode 21, a second electrode 6, and a light-emitting layer 5 located between the first electrode 21 and the second electrode 6. Both the first electrode 21 and the second electrode 6 can be connected to the wiring layer 103. A driving signal is applied to the first electrode 21 and a power signal is applied to the second electrode 6 through the driving backplate 1, thereby driving the light-emitting layer 5 to emit light.

[0112] To achieve color display, each light-emitting unit 001 can emit light of the same color. This, combined with the color filter layer 7 located on the side of the second electrode 6 facing away from the driving backplate 1, enables color display. The embodiments described herein use this color display scheme as an example. Alternatively, each light-emitting unit 001 can emit light independently, and the emitted colors of different light-emitting units 001 can be different.

[0113] In some embodiments of this disclosure, such as Figure 4 and Figure 6 As shown, multiple light-emitting units 001 can be formed through the first electrode layer 2, the pixel definition layer 3, the light-emitting layer 5, and the second electrode 6, wherein:

[0114] The first electrode layer 2 is disposed on one side of the driving backplate 1. For example, the first electrode layer 2 is disposed on the surface of the planarization layer 104 facing away from the substrate 101. The first electrode layer 2 may include a plurality of spaced first electrodes 21, and the orthogonal projection of each first electrode 21 on the driving backplate 1 is located in the pixel region 110 and connected to the pixel circuit. One first electrode 21 is connected to one pixel circuit. For example, the first electrode 21 may be connected to the second wiring layer 1032.

[0115] The first electrode layer 2 can be a single-layer or multi-layer structure, and its material is not specifically limited here. For example, the first electrode layer 2 may include a first layer 201, a second layer 202, a third layer 203, and a fourth layer 204 stacked sequentially in the direction away from the drive backplate 1. The first layer 201 and the third layer 203 may be made of the same metal material, such as titanium; the fourth layer 204 may be made of a transparent conductive material such as ITO (indium tin oxide); the second layer 202 may be made of a different metal material than the first layer 201, the third layer 203, and the fourth layer 204, and its resistivity is lower than that of the first layer 201 and the third layer 203. For example, the material of the second layer 202 may be aluminum.

[0116] like Figure 4 and Figure 6 As shown, the pixel definition layer 3 and the first electrode layer 2 are disposed on the same surface of the driving backplate 1, that is, the planarization layer 104 is away from the surface of the substrate 101, and the pixel definition layer 3 exposes each of the first electrodes 21. Specifically, the pixel definition layer 3 has an opening 31 exposing the first electrodes 21, and the range of each light-emitting unit 001 can be defined by the pixel definition layer 3 and its opening 31. The material of the pixel definition layer 3 can be an insulating material such as silicon oxide or silicon nitride, and no special limitation is made here.

[0117] The orthographic projection of any opening 31 onto the drive backplate 1 lies within the exposed first electrode 21; that is, the opening 31 is no larger than the exposed first electrode 21. Figure 6 As shown, the shape of the opening 31 can be a rectangle, pentagon, hexagon, or other polygon, but it does not have to be a regular polygon. The shape of the opening 31 can also be an ellipse or other shapes, without any special restrictions.

[0118] like Figure 4 and Figure 7 As shown, the light-emitting layer 5 covers the pixel definition layer 3 and the first electrode 21. The area of ​​the light-emitting layer 5 located within an opening 31 and overlapping with the first electrode layer 2 is used to form a light-emitting unit 001. That is, each light-emitting unit 001 can share the same light-emitting layer 5, meaning that the portions of the light-emitting layer 5 located within different openings 31 belong to different light-emitting units 001. Furthermore, since each light-emitting unit 001 shares the light-emitting layer 5, the light emitted by different light-emitting units 001 is the same.

[0119] In some embodiments of this disclosure, such as Figure 7 As shown, the light-emitting unit 001 may include multiple light-emitting devices 0011. Each light-emitting device 0011 includes a first electrode 21, a second electrode 6, and multiple light-emitting sub-layers 51 between the first electrode 21 and the second electrode 6. Each light-emitting device 0011 of the same light-emitting unit 001 may share the same first electrode 21 and the same second electrode 6. That is to say, the same light-emitting unit 001 may have only one first electrode 21 and one second electrode 6.

[0120] For example: Figure 7 As shown, the light-emitting layer 5 may include multiple light-emitting sub-layers 51 connected in series along the direction away from the driving backplate 1, and at least one light-emitting sub-layer 51 is connected in series with an adjacent light-emitting sub-layer 51 through a charge generation layer 52. When an electrical signal is applied to the first electrode 21 and the second electrode 6, each light-emitting sub-layer 51 can emit light, and different light-emitting sub-layers 51 can be used to emit light of different colors.

[0121] Furthermore, such as Figure 7 As shown, any light-emitting sublayer 51 may include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting material layer (EL), an electron transport layer (ETL), and an electron injection layer (EIL) distributed along the direction away from the driving backplate 1. The specific light-emitting principle will not be detailed here. The number of hole injection layers, hole transport layers, electron transport layers, and electron injection layers is not specifically limited here, and each light-emitting sublayer 51 may share one or more of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer. At the same time, a charge generation layer 52 may be provided between at least two adjacent light-emitting sublayers 51, thereby connecting the two light-emitting sublayers 51 in series.

[0122] In some embodiments of this disclosure, such as Figure 7 As shown, the light-emitting layer 5 may include three light-emitting sub-layers 51 of different colors: a first light-emitting sub-layer 51 emitting red light, a second light-emitting sub-layer 51 emitting green light, and a third light-emitting sub-layer 51 emitting blue light. When the first, second, and third light-emitting sub-layers 51 emit light simultaneously, the light-emitting layer 5 can emit white light. The first and second light-emitting sub-layers 51 share a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The light-emitting material layer of the second light-emitting sub-layer 51 is disposed on the surface of the first light-emitting sub-layer 51 facing away from the driving backplate 1, thereby directly connecting the first and second light-emitting sub-layers 51 in series. A charge generation layer 52 may be provided on the surface of the second light-emitting sub-layer 51 facing away from the driving backplate 1. The third light-emitting sub-layer 51 shares an electron injection layer with the first light-emitting sub-layer 51 and the second light-emitting sub-layer 51. The hole injection layer of the third light-emitting sub-layer 51 is located on the surface of the charge generation layer 52 away from the driving backplate 1, so that the third light-emitting sub-layer 51 and the second light-emitting sub-layer 51 can be connected in series.

[0123] like Figure 4 and Figure 8 As shown, the second electrode 6 covers the light-emitting layer 5, and the orthographic projection of the second electrode 6 on the driving backplate 1 covers the pixel area 110 and extends into the peripheral area 120. Each light-emitting unit 001 can share the same second electrode 6. When the voltage difference between the second electrode 6 and the first electrode 21 reaches a voltage difference that enables the light-emitting layer 5 to emit light, the light-emitting layer 5 can emit light. Therefore, the light-emitting layer 5 can be controlled to emit light by controlling the voltage of the power supply signal input to the second electrode 6 and the driving signal input to the first electrode 21.

[0124] like Figure 4 and Figure 8 As shown, the color filter layer 7 is disposed on the side of the second electrode 6 away from the driving backplate 1, and includes multiple filter sections 71. Each first electrode 21 and each filter section 71 are arranged opposite to each other in a direction perpendicular to the substrate 101, that is, the orthogonal projection of a filter section 71 on the planarization layer 104 at least partially overlaps with a first electrode 21. Each filter section 71 includes at least three color filters 71, for example, a filter section 71 that transmits red light, a filter section 71 that transmits green light, and a filter section 71 that transmits blue light. After the light emitted by each light-emitting unit 001 is filtered by the filter section 71, different colors of monochromatic light can be obtained, thereby realizing color display. A filter section 71 and its corresponding light-emitting unit 001 can constitute a sub-pixel. The color emitted by any sub-pixel is the color of the light transmitted by its filter section 71. Multiple sub-pixels can constitute a pixel, and the sub-pixels of the same pixel emit different colors.

[0125] The shape of the orthographic projection of the filter section 71 on the planarization layer 104 can be the same as the shape of the opening 31 of the pixel definition layer 3, and the orthographic projection of each opening 31 on the planarization layer 104 is located within the orthographic projection of each filter section 71 on the planarization layer 104.

[0126] like Figure 4 and Figure 8 As shown, the color filter layer 7 may further include a light-shielding portion 72 that separates the light-filtering portion 71. The light-shielding portion 72 is opaque and blocks the area between the two light-emitting units 001. The light-filtering portion 71 may be directly made of a light-shielding material and spaced apart from the light-filtering portion 71; or, in some embodiments of this disclosure, adjacent light-filtering portions 71 may be stacked in the area corresponding to two adjacent light-emitting units 001, and the colors of the light transmitted by the two are different, so that the stacked area is opaque.

[0127] Furthermore, in some embodiments of this disclosure, in order to improve the brightness of the image, the color filter layer 7 may also include a transparent portion in addition to the white light emitted by the light-emitting layer 5. In a direction perpendicular to the substrate 101, a transparent portion may be disposed opposite to a light-emitting unit 001, so that the color filter layer 7 can also transmit white light, thereby increasing the brightness through the white light.

[0128] To improve light extraction efficiency, a light extraction layer 11 can be covered on the side of the second electrode 6 away from the driving backplate 1 to improve brightness. Furthermore, the light extraction layer 11 can directly cover the surface of the second electrode 6 away from the driving backplate 1.

[0129] To facilitate the connection of the second electrode 6 to the driving circuit, in some embodiments of this disclosure, the first electrode layer 2 further includes a transition ring. The orthographic projection of the transition ring on the driving backplate 1 is located in the peripheral region 120. The transition ring can be connected to the peripheral circuit and surrounds the pixel region 110. The second electrode 6 can be connected to the transition ring, thereby connecting the second electrode 6 to the peripheral circuit so that a driving signal can be applied to the second electrode 6 by the peripheral circuit. The pattern of the transition ring can be the same as the pattern of the first electrode 21 in the pixel region 110 to improve the uniformity of the pattern of the first electrode layer 2.

[0130] like Figure 4 and Figure 8 As shown, in some embodiments of this disclosure, the display panel may further include a first encapsulation layer 8, which may be disposed on the side of the second electrode 6 away from the driving backplate 1 and located between the color filter layer 7 and the second electrode 6, for blocking external water and oxygen erosion. The first encapsulation layer 8 may be a single-layer or multi-layer structure. For example, the first encapsulation layer 8 may include a first encapsulation sub-layer 81, a second encapsulation sub-layer 82, and a third encapsulation sub-layer 83 stacked sequentially in the direction away from the driving backplate 1. The materials of the first encapsulation sub-layer 81 and the second encapsulation sub-layer 82 may be inorganic insulating materials such as silicon nitride and silicon oxide, and the second encapsulation sub-layer 82 may be formed using ALD (Atomic layer deposition) technology; the material of the third encapsulation sub-layer 83 may be an organic material, which may be formed using MLD (Molecular Layer Deposition) technology. Of course, the first encapsulation layer 8 may also adopt other structures, and no special limitation is made to the structure of the first encapsulation layer 8 here.

[0131] In addition, in some embodiments of this disclosure, the display panel may also include a transparent cover plate 10, which may cover the side of the color filter layer 7 away from the driving back plate 1. The transparent cover plate 10 may be a single layer or a multi-layer structure, and its material is not specifically limited herein.

[0132] In some embodiments of this disclosure, the display panel may further include a second encapsulation layer 9, which may cover the surface of the color filter layer 7 facing away from the driving backplate 1 to achieve planarization, facilitate the covering of the transparent cover plate 10, and improve the encapsulation effect, further blocking water and oxygen. The second encapsulation layer 9 may be a single-layer or multi-layer structure, and may include inorganic materials such as silicon nitride and silicon oxide, or may include organic materials. No special limitation is made to the structure of the second encapsulation layer 9 here.

[0133] The following is a detailed explanation of the solution to the color mixing problem in the display panel disclosed herein:

[0134] Based on the above analysis of related technologies, since all light-emitting units 001 share the light-emitting layer 5, charge carriers (e.g., holes) in one light-emitting unit 001 may move to other light-emitting units 001 through the charge generation layer 52 and other film layers, especially to adjacent light-emitting units 001, resulting in leakage and affecting the purity of light emission. Therefore, as... Figure 4 and Figure 8 As shown, a conductive shielding layer 4 can be disposed in the area between the planarization layer 104 and the light-emitting layer 5, and between two adjacent light-emitting units 001. The conductive shielding layer 4 is insulated from the first electrode 21, but is conductive. The conductive shielding layer 4 can absorb charge carriers and prevent charge carriers from moving between the light-emitting units 001, thereby avoiding cross-coloring caused by leakage.

[0135] like Figure 4 and Figure 8 As shown, the conductive shielding layer 4 can be a single-layer or multi-layer structure. For example, in some embodiments of this disclosure, the conductive shielding layer 4 includes a first conductive layer 401, a second conductive layer 402, and a third conductive layer 403 sequentially stacked in the direction away from the driving backplate 1. The materials of the first conductive layer 401 and the third conductive layer 403 can be the same as the second layer 202 and the fourth layer 204 of the first electrode layer 2. For example, the materials of the first conductive layer 401 and the third conductive layer 403 are both titanium. The material of the second conductive layer 402 can be the same as the material of the third electrode layer of the first electrode layer 2. For example, the material of the second conductive layer 402 is aluminum. Thus, the conductive shielding layer 4 can be formed using at least part of the process for forming the first electrode layer 2, thereby saving costs. At the same time, the conductivity of the conductive shielding layer 4 can be made similar to that of the first electrode layer 2, avoiding any impact on the normal light emission of the first electrode 21.

[0136] like Figure 4 and Figure 6 As shown, the pixel definition layer 3 can be made to correspond to the area outside the light-emitting unit 001, that is, the area outside the opening 31, to form a partition groove 32, so that the light-emitting layer 5 is recessed at the partition groove 32, which is beneficial to thinning, or even cutting off the charge generation layer 52 and at least part of the light-emitting sub-layer 51 in the light-emitting layer 5, thereby further preventing leakage.

[0137] In order to form the partition slot 32 in the pixel definition layer 3, such as Figure 4 and Figure 21 As shown, a groove 1041 can be provided on the planarization layer 104 of the driving backplate 1. The orthographic projection of the groove 1041 on the planarization layer 104 is located outside the first electrode 21. The pixel definition layer 3 can form a partition groove 32 at the groove 1041. The light-emitting layer 5 is recessed at the partition groove 32, and correspondingly, it is also recessed at the groove 1041.

[0138] At least a portion of the conductive shielding layer 4 is located within the groove 1041 and is insulated from the first electrode 21. For example, the conductive shielding layer 4 and the first electrode 21 are spaced apart and not connected to each other. Simultaneously, the conductive shielding layer 4 is at most partially covered by the pixel definition layer 3, thus allowing direct contact with the light-emitting layer 5 recessed within the groove 1041, thereby facilitating the extraction of charge carriers from the light-emitting layer 5 between the two light-emitting units 001. Furthermore, the thickness of the conductive shielding layer 4 can be less than the depth of the groove 1041, ensuring that the light-emitting layer 5 can be recessed into the groove 1041. This facilitates thinning and even cuts off the charge generation layer 52 and at least a portion of the light-emitting sublayer 51 in the light-emitting layer 5, further preventing leakage.

[0139] like Figure 4 , Figure 20 and Figure 21 As shown, in some embodiments of this disclosure, the thickness of the pixel definition layer 3 is less than the depth of the groove 1041, and a partition groove 32 is formed in the groove 1041. The bottom surface of the partition groove 32 covers the bottom surface of the groove 1041, meaning that the partition groove 32 does not penetrate the pixel definition layer 3 in the depth direction. To avoid the groove 1041 exposing the wiring layer 103, each wiring layer 103 can be located on the side of the bottom surface of the groove 1041 close to the substrate 101, and not exposed by the groove 1041. At the same time, at least a portion of the conductive shielding layer 4 is located within the partition groove 32. For example, the conductive shielding layer 4 is at least partially stacked on the bottom surface of the partition groove 32, meaning that the conductive shielding layer 4 is at least partially disposed on the side of the bottom surface of the partition groove 32 away from the substrate 101. Furthermore, the area of ​​the conductive shielding layer 4 located at the bottom of the partition groove 32 is smaller than the area of ​​the bottom surface of the partition groove 32, meaning that the conductive shielding layer 4 does not completely cover the bottom surface of the partition groove 32.

[0140] like Figure 4 and Figure 20 As shown, to ensure that the partition groove 32 can recess the light-emitting layer 5, the depth L of the partition groove 32 can be 800μm-1000μm, for example, 800μm, 900μm, or 1000μm. It should be noted that the bottom surface of the partition groove 32 is not limited to a plane, but can be a curved surface or an irregular surface. The depth of the partition groove 32 refers to the distance between the bottom surface of the partition groove 32 and the substrate 101, which is the closest point to the substrate 101.

[0141] like Figure 8 and Figure 25 As shown, in some other embodiments of this disclosure, the pixel defining layer 3 may be recessed along the groove 1041, but at least a portion of the bottom surface of the groove 1041 is exposed, thus covering the sidewalls of the groove 1041. The conductive shielding layer 4 is disposed on the bottom surface of the groove 1041 and is exposed by the pixel defining layer 3 in at least a portion, so that the light-emitting layer 5 recessed into the groove 1041 can directly contact the conductive shielding layer 4. Since the conductive shielding layer 4 and the first electrode layer 21 are both stacked on the planarization layer 104, the conductive shielding layer 4 and the first electrode layer 21 can be formed simultaneously using the same process, simplifying the process. Of course, they can also be formed independently.

[0142] In other embodiments of this disclosure, the pixel defining layer 3 may be located outside the boundary of the groove 1041 without extending into the groove 1041. That is, the pixel defining layer 3 does not cover the sidewalls and bottom surface of the groove 1041, so that the pixel defining layer 3 forms a dividing groove 32 penetrating the pixel defining layer 3 at the groove 1041. The sidewall of the dividing groove 32 may be flush with the sidewall of the groove 1041 or located outside the sidewall of the groove 1041, thereby exposing the groove 1041. The conductive shielding layer 4 may be disposed on the bottom surface of the groove 1041 and is not covered by the pixel defining layer 3, so that the light-emitting layer 5 recessed into the groove 1041 can directly contact the conductive shielding layer 4. Since the conductive shielding layer 4 and the first electrode layer 21 are both stacked on the planarization layer 104, the conductive shielding layer 4 and the first electrode layer 21 can be formed simultaneously by the same process to simplify the process. Of course, they can also be formed independently.

[0143] To minimize leakage, the light-emitting unit 001 can be surrounded by a conductive shielding layer 4 and a partition groove 32. Taking the embodiment described above, where the conductive shielding layer 4 is stacked on the bottom surface of the partition groove 32, as an example... Figure 4 and Figure 6 As shown, in some embodiments of this disclosure, the partition groove 32 includes at least one annular groove 321, which surrounds a first electrode 21. Correspondingly, the conductive shielding layer 4 may include at least one shielding ring 41, with a shielding ring 41 disposed within the groove 321. The shielding ring 41 may be stacked on the bottom surface of the groove 321. The first electrode 21, i.e., a light-emitting unit 001, can be surrounded by the groove 321 and the shielding ring 41 within the groove 321. Simultaneously, each shielding ring 41 can be connected to the second electrode 6 to conduct the charge carriers absorbed by the conductive shielding layer 4, making it difficult for the light-emitting unit 001 to leak current to adjacent light-emitting units 001.

[0144] The width ratio of the shielding ring 41 to the width of the groove 1041 can be less than 4:5, so that there is a certain distance between the shielding ring 41 and the sidewall of the groove 1041. Of course, this width ratio can also be larger or smaller. The width of the shielding ring 41 is the distance between the inner wall and the outer wall of the shielding ring 41. At the same time, the thickness of the conductive shielding layer 4 can be greater than the thickness of the pixel definition layer 3. In addition, the conductive shielding layer 4 can be located on the side of the first electrode 21 near the substrate 101, that is, the conductive shielding layer 4 does not extend beyond the groove 1041, that is, the conductive shielding layer 4 is located on the side of the planarization layer 104 where the first electrode 21 is disposed, near the substrate 101.

[0145] Furthermore, such as Figure 6 As shown, the partition groove 32 may include multiple grooves 321, and the conductive shielding layer 4 may include multiple shielding rings 41. The number of grooves 321 and shielding rings 41 may be the same as the number of first electrodes 21. Each groove 321 contains one shielding ring 41, and the two may be arranged in a concentric ring structure. Each groove 321 and its shielding ring 41 may surround a first electrode 21.

[0146] It should be noted that the shape of the partition groove 32 formed by the recess into the groove 1041 directly limits the shape of the partition groove 32. Therefore, if the partition groove 32 includes the above-mentioned multiple annular grooves 321, then the groove 1041 also includes multiple annular grooves.

[0147] like Figure 11 As shown, in some embodiments of this disclosure, the bottom surface of the partition groove 32 may include a middle region 322 and an edge region 323 located outside the middle region 322. The orthographic projection of the conductive shielding layer 4 on the bottom surface of the partition groove 32 coincides with the middle region 322. The thickness of the middle region 322 is greater than the thickness of the edge region 323. That is, in the bottom surface of the partition groove 32, the thickness of the area covered by the conductive shielding layer 4 is greater than the thickness of the area not covered by the conductive shielding layer 4.

[0148] like Figure 12 As shown, in some other embodiments of this disclosure, at least a portion of the edge region 323 is located on the side of the intermediate region 322 facing away from the substrate 101. That is, the maximum distance between the edge region 323 and the substrate 101 is greater than the maximum distance between the intermediate region 322 and the substrate 101, such that the intermediate region 322 is recessed into the substrate 101 with respect to the edge region 323. Furthermore, the edge region 323 may be a curved surface that bulges outward from the substrate 101 towards the intermediate region 322 and connects the sidewall of the partition groove 32 and the intermediate region 322.

[0149] Furthermore, in order to form the aforementioned structure where the intermediate region 322 is recessed towards the substrate 101 relative to the edge region 323, the bottom surface of the groove 1041 of the planarization layer 104 can be formed with a central portion and two side portions on either side of the central portion. The side portions protrude towards the side of the central portion away from the substrate 101, making the central portion recessed relative to the side portions. When forming the pixel definition layer 3, the pixel definition layer 3 covering the bottom surface of the groove 1041 forms a shape that matches the bottom surface of the groove 1041, that is, forming the aforementioned intermediate region 322 and edge region 323. Of course, when the bottom surface of the groove 1041 is planar or has other shapes, the aforementioned intermediate region 322 and edge region 323 can also be formed by controlling the thickness of the pixel definition layer 3 within the groove 1041.

[0150] In the direction perpendicular to the substrate 101, the shielding ring 41 can have an uneven structure, for example:

[0151] like Figure 13 As shown, in some embodiments of this disclosure, the surface of the shielding ring 41 facing away from the substrate 101 may be provided with a circumferentially extending protrusion 4011, and the area on both sides of the protrusion 4011 on the surface of the shielding ring 41 facing away from the substrate 101 may be a plane. Meanwhile, the protrusion 4011 and the shielding ring 41 are an integral structure, which may be formed by the protrusion of the third conductive layer 403. The protrusion of the third conductive layer 403 may be formed by increasing its own thickness, or it may be formed by the protrusion of the first conductive layer 401 and the second conductive layer 402.

[0152] like Figure 14 As shown, in some other embodiments of this disclosure, the shielding ring 41 has the aforementioned protruding ridge 4011 on the surface opposite to the substrate 101, and may also have circumferentially extending recesses 4012. The protruding ridge 4011 and recesses 4012 may be distributed radially along the shielding ring 41, i.e., distributed from the inner wall to the outer wall of the shielding ring 41. For example, there may be two recesses 4012, which are concentrically arranged, and one protruding ridge 4011, which is located between the two recesses 4012. Of course, the number of protruding ridges 4011 and recesses 4012 is not limited to this, as long as they are distributed radially along the shielding ring 41.

[0153] To facilitate the extraction of charge carriers absorbed by the conductive shielding layer 4, it can be connected to an external circuit. Simultaneously, a power signal can be input to the conductive shielding layer 4. The voltage difference between this power signal and the power signal input to the second electrode 6 is less than the activation voltage difference required for the light-emitting layer 5 to emit light, thus preventing the light-emitting layer 5 between the conductive shielding layer 4 and the second electrode 6 from emitting light; only the light-emitting layer 5 between the first electrode 21 and the second electrode 6 will emit light. For example, the conductive shielding layer 4 can be connected to the second electrode 6. Although a light-emitting layer 5 exists between the conductive shielding layer 4 and the second electrode 6, because the conductive shielding layer 4 is connected to the second electrode 6 and has the same potential as the second electrode 6, the voltage difference is zero, and therefore it will not drive the light-emitting layer 5 to emit light. Of course, the conductive shielding layer 4 can also be directly grounded through an external circuit or connected to other signals, as long as it can extract charge carriers, prevent leakage between adjacent light-emitting units 001, and prevent the light-emitting layer 5 from emitting light in the area corresponding to the conductive shielding layer 4.

[0154] The connection method between the shielding ring 41 and the second electrode 6 is described in detail below:

[0155] In some embodiments of this disclosure, such as Figure 6 As shown, to facilitate the connection between the shielding ring 41 and the second electrode 6, the shielding ring 41 can be integrated into a single structure. Correspondingly, the grooves 321 of the partition groove 32 can be connected into a single structure. For example, the conductive shielding layer 4 may also include a connector 42. The orthographic projection of the connector 42 on the driving backplate 1 extends from the pixel area 110 to the peripheral area 120, and the connector 42 is connected to at least one shielding ring 41 and connected to the second electrode 6 in the area corresponding to the peripheral area 120. The number of connectors 42 can be multiple and distributed around the pixel area 110. Each connector 42 can be connected to one shielding ring 41. Since the shielding rings 41 are integrated, each connector 42 is electrically connected to each shielding ring 41. The structure of the connector 42 can be a wire, etc., and is not specifically limited here, as long as it can serve the function of conductive connection.

[0156] Furthermore, the orthographic projection of the light-emitting layer 5 onto the driving backplate 1 covers the pixel area 110 and extends into the peripheral area 120, with a certain distance between it and the boundary of the peripheral area 120. The boundary of the orthographic projection of the second electrode 6 onto the driving backplate 1 is located outside the boundary of the light-emitting layer 5; the connector 42 can extend outside the boundary of the light-emitting layer 5 and directly contact the area of ​​the second electrode 6 located outside the boundary of the light-emitting layer 5, thereby connecting the second electrode 6 to the shielding ring 41 through the connector 42.

[0157] like Figure 9As shown, in some other embodiments of this disclosure, at least a portion of the shielding rings 41 can be connected to the second electrode 6 through a first via H1 penetrating the light-emitting layer 5, and the orthographic projection of at least one first via H1 on the planarization layer 104 is located between two adjacent first electrodes 21. If each shielding ring 41 is an integral structure, then at least one shielding ring 41 needs to be connected to the second electrode 6. Of course, multiple first vias H1 can be provided to connect multiple shielding rings 41 to the second electrode 6, but they can be used to connect each shielding ring 41 to the second electrode 6, and the orthographic projection of each first via H1 on the driving backplate 1 is located within the pixel area 110.

[0158] like Figure 10 As shown, in other embodiments of this disclosure, at least one routing layer 103 may include a connection portion 1032a. For example, the second routing layer 1032 may include a connection portion 1032a. The potential of the connection portion 1032a may be the same as that of the second electrode 6. For example, the connection portion 1032a may extend to the peripheral area and be connected to the second electrode 6. Alternatively, a signal with a potential equal to that of the power signal input to the second electrode 6 may be input to the connection portion 1032a. Simultaneously, a second via H2 connected to the connection portion 1032a may be provided in the planarization layer 104. The second via H2 may be connected to the shielding ring 41, thereby connecting the shielding ring 41 to the second electrode 6; or, the potential of the shielding ring 41 and the second electrode 6 may be made equal, thereby preventing the light-emitting layer 5 between the shielding ring 41 and the second electrode 6 from emitting light.

[0159] It should be noted that if the conductive shielding layer 4 is stacked on the pixel definition layer 3, that is, on the bottom surface of the partition groove 32, then the second via H2 can penetrate the pixel definition layer 3. If the conductive shielding layer 4 is disposed on the bottom surface of the groove 1041, then the second via H2 does not need to penetrate the pixel definition layer 3.

[0160] Furthermore, due to the presence of the partition groove 32, the second electrode 6 is recessed at the partition groove 32, forming a recessed region 61, the depth of which is no greater than the depth of the partition groove 32. Simultaneously, since at least a portion of the conductive shielding layer 4 is provided within the partition groove 32, the bottom surface of the recessed region 61, corresponding to the area of ​​the conductive shielding layer 4, protrudes in a direction away from the conductive shielding layer 4, and the height of the protrusion is less than the depth of the partition groove 32.

[0161] The following is a description of the display panel's effect:

[0162] like Figure 15 As shown, Figure 15 The circuit principle of the conductive shielding layer 4 absorbing charge carriers is shown. It can be seen that the charge carriers (holes) between two adjacent light-emitting units 001 are absorbed by the conductive shielding layer 4, thus avoiding leakage between the two light-emitting units 001.

[0163] like Figure 16 As shown, Figure 16 The image shows the spectrum of red (R), green (G), and blue (B) sub-pixels lit simultaneously, as well as the spectrum of each sub-pixel lit individually. Figure 3 A comparison of the spectral data of related technologies reveals that, in the display panel disclosed herein, when the three sub-pixels are illuminated individually, the amount of light of different colors is significantly reduced, resulting in an improvement in the color gamut of the entire display panel. Calculations show that the color gamut (NTSC) of this display panel can reach 80%.

[0164] like Figure 17 As shown, Figure 17 The voltage-brightness curves of three sub-pixels, namely red (R), green (G), and blue (B), are shown. The R, G, and B curves are the curves of the three sub-pixels in one embodiment of this disclosure, and R-071, G-071, and B-071 are the curves of the three sub-pixels in related technologies. Figures 18-20 The voltage-color coordinate curves of three sub-pixels, namely red (R), green (G), and blue (B), are shown respectively. Among them, the sample-Rx, sample-Ry, sample-Gx, sample-Gy, sample-Bx, and sample-By curves are the color coordinate curves of the three sub-pixels in one embodiment of this disclosure; the Rx, Ry, Gx, Gy, Bx, and By curves are the color coordinate curves of the three sub-pixels in related technologies.

[0165] Depend on Figures 18-20 As can be seen, the display panels in the related technologies exhibit significant changes in brightness and color coordinates under low voltage (left side of the dotted line), and these changes are accompanied by jumps and flips with voltage variations, making Gamma adjustment difficult at low grayscale levels and prone to color bar issues. The display panel of this disclosure, however, shows a significantly reduced amplitude of color coordinate changes with voltage for each monochrome color, which is beneficial for Gamma adjustment, and the curve transitions smoothly without jumps.

[0166] In summary, it can be seen that some embodiments of the display panel disclosed herein can prevent leakage current, thereby avoiding color bleeding problems.

[0167] This disclosure also provides a method for manufacturing a display panel, which can be any of the display panels described in the above embodiments, such as... Figure 4 as well as Figures 21-25 As shown, the manufacturing method may include steps S110-S170, wherein:

[0168] Step S110: Forming a driving backplane; the driving backplane includes a substrate, at least one wiring layer, and a planarization layer, wherein the wiring layer is disposed on one side of the substrate; the planarization layer covers the wiring layer. Figure 25 As shown.

[0169] Step S120: Create grooves in the flat layer. For example... Figure 20 and Figure 21 As shown.

[0170] Step S130: A first electrode layer is formed on the surface of the planarization layer opposite to the substrate. The first electrode layer includes a plurality of first electrodes spaced apart. The orthogonal projection of the groove on the planarization layer is located outside the first electrodes. Figure 24 As shown.

[0171] Step S140: A pixel definition layer exposing each of the first electrodes is formed on the surface of the planarization layer opposite to the substrate, and the pixel definition layer forms a separation groove at the recess. Figure 22 and Figure 23 As shown

[0172] Step S150: Form a conductive shielding layer at least within the partition groove. For example... Figure 21 As shown.

[0173] Step S160: Form a light-emitting layer covering the pixel definition layer, the first electrode, and the conductive shielding layer. The light-emitting layer is recessed at the separator groove and is in direct contact with at least a portion of the conductive shielding layer. Figure 4 As shown.

[0174] Step S170: Form a second electrode covering the light-emitting layer. (e.g.) Figure 4 As shown.

[0175] The structures in each step of the manufacturing method of this disclosure have been described in detail in the above-displayed panel embodiments, and will not be described in detail here.

[0176] In some embodiments of this disclosure, step S110 includes steps S1110 and S1120, wherein:

[0177] Step S1110: Form a substrate.

[0178] Step S1120: Form at least one wiring layer and a planarization layer covering the wiring layer on one side of the substrate; the first electrode layer is disposed on the surface of the planarization layer opposite to the substrate.

[0179] Furthermore, the manufacturing method disclosed herein may also include step S180:

[0180] A color filter layer comprising multiple filter sections is formed on the side of the second electrode facing away from the driving backplate, and each of the first electrodes and each of the filter sections are disposed opposite to each other in a direction perpendicular to the substrate. Figure 4 As shown.

[0181] This disclosure also provides a method for manufacturing a display panel, which can be any of the display panels described in the above embodiments, such as... Figure 8 as well as Figure 26 As shown, the manufacturing method may include steps S210-S270, wherein:

[0182] Step S210: Form a driving backplane, the driving backplane including a substrate, at least one wiring layer and a planarization layer, the wiring layer being disposed on one side of the substrate; the planarization layer covering the wiring layer;

[0183] Step S220: A groove is formed in the planarization layer, the orthographic projection of the groove on the planarization layer being located outside the first electrode; as shown Figure 26 As shown.

[0184] Step S230: Form a conductive shielding layer at least within the groove; such as Figure 26 As shown.

[0185] Step S240: A first electrode layer is formed on the surface of the planarization layer opposite to the substrate. The first electrode layer includes a plurality of first electrodes spaced apart. The orthogonal projection of the groove on the planarization layer is located outside the first electrodes.

[0186] Step S250: A pixel definition layer is formed on the surface of the planarization layer opposite to the substrate, exposing each of the first electrodes and the conductive shielding layer, wherein the pixel definition layer forms a separation groove at the groove;

[0187] Step S260: Form a light-emitting layer covering the pixel definition layer, the first electrode and the conductive shielding layer, wherein the light-emitting layer is recessed at the partition groove and is in direct contact with at least a portion of the conductive shielding layer;

[0188] Step S270: Form a second electrode covering the light-emitting layer.

[0189] Furthermore, the manufacturing method disclosed herein may also include step S280:

[0190] A color filter layer comprising multiple filter sections is formed on the side of the second electrode facing away from the driving backplate, and each of the first electrodes and each of the filter sections are disposed opposite to each other in a direction perpendicular to the substrate. Figure 8 As shown.

[0191] The specific details of the manufacturing method described above have been explained in detail in the implementation method of the display panel above. Please refer to the implementation method of the display panel for further details.

[0192] It should be noted that although the various steps of the manufacturing method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0193] This disclosure also provides a display device, including a display panel as described in any of the above embodiments. The structure of the display panel can be referred to the embodiments of the display surface described above, and will not be repeated here. The display device of this disclosure can be an electronic device with image display function, such as a mobile phone or a tablet computer, which will not be listed here.

[0194] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, wherein, include: A drive backplane includes a substrate, at least one wiring layer, and a planarization layer, wherein the wiring layer is disposed on one side of the substrate; The planarization layer covers the wiring layer, and the planarization layer is provided with grooves; A first electrode layer is disposed on the surface of the planarization layer opposite to the substrate, and includes a plurality of first electrodes spaced apart; the orthographic projection of the groove on the planarization layer is located outside the first electrodes; A pixel definition layer is disposed on the surface of the planarization layer opposite to the substrate, and exposes each of the first electrodes; the pixel definition layer forms a separation groove at the groove; A conductive shielding layer is at least partially disposed within the groove and is insulated from the first electrode; A light-emitting layer covers the pixel definition layer, the first electrode, and the conductive shielding layer. The light-emitting layer is recessed at the partition groove and is in direct contact with at least a portion of the conductive shielding layer. The second electrode covers the light-emitting layer; the conductive shielding layer is connected to the second electrode. The pixel definition layer covers the bottom surface of the groove, and the pixel definition layer covering the bottom surface of the groove is the bottom surface of the partition groove; the conductive shielding layer is at least partially stacked on the bottom surface of the partition groove, and the conductive shielding layer does not completely cover the bottom surface of the partition groove; or, the conductive shielding layer is disposed on the bottom surface of the groove; the pixel definition layer exposes at least a portion of the conductive shielding layer, and the conductive shielding layer does not completely cover the bottom surface of the groove.

2. The display panel according to claim 1, wherein, The dividing groove includes at least one annular groove, one of the grooves surrounding the first electrode; The conductive shielding layer includes at least one shielding ring, and one of the shielding rings is disposed in the groove. Each of the aforementioned tanks and the shielding rings within them surround the same first electrode.

3. The display panel according to claim 2, wherein, The number of the grooves is the same as the number of the first electrodes, and each first electrode is surrounded by a groove, and each groove is provided with a shielding ring.

4. The display panel according to claim 3, wherein, The grooves are connected to form a single structure, and the shielding rings are connected to form a single structure.

5. The display panel according to claim 4, wherein, Each of the shielding rings is connected to the second electrode.

6. The display panel according to claim 5, wherein, The driving backplate includes a pixel area and a peripheral area located outside the pixel area; the orthographic projection of the first electrode on the driving backplate is located within the pixel area; the orthographic projection of the edge of the second electrode on the driving backplate is located in the peripheral area. The conductive shielding layer also includes a connector connected to the shielding ring, and the orthographic projection of the connector on the driving backplate extends from the pixel area to the peripheral area; The second electrode is connected to the shielding ring via the connector.

7. The display panel according to claim 2, wherein, At least a portion of the shielding ring is connected to the second electrode through a first via penetrating the light-emitting layer, and the orthogonal projection of at least one of the first vias on the planar layer is located between two adjacent first electrodes.

8. The display panel according to claim 2, wherein, At least one of the wiring layers includes a connection portion connected to the second electrode, and the shielding ring is connected to the connection portion through a second via penetrating the planarization layer.

9. The display panel according to claim 2, wherein, The shielding ring has circumferentially extending ridges on the surface opposite to the substrate.

10. The display panel according to claim 9, wherein, The shielding ring has circumferentially extending recesses on the surface opposite to the substrate, and the protrusions and the recesses are distributed radially along the shielding ring.

11. The display panel according to claim 1, wherein, The thickness of the conductive shielding layer is less than the depth of the groove.

12. The display panel according to claim 2, wherein, The ratio of the width of the shielding ring to the width of the groove is less than 4:

5.

13. The display panel according to claim 1, wherein, The thickness of the conductive shielding layer is greater than the thickness of the pixel definition layer.

14. The display panel according to claim 1, wherein, The conductive shielding layer is located on the side of the first electrode closer to the substrate.

15. The display panel according to claim 1, wherein, The bottom surface of the partition groove includes a central region and an edge region located outside the central region. The orthographic projection of the conductive shielding layer on the bottom surface of the partition groove coincides with the central region. At least a portion of the edge region is located on the side of the central region away from the substrate.

16. The display panel according to claim 1, wherein, The conductive shielding layer includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially in a direction away from the substrate.

17. The display panel according to claim 16, wherein, The first conductive layer and the third conductive layer are both made of titanium, and the second conductive layer is made of aluminum.

18. The display panel according to any one of claims 1-17, wherein, The depth of the dividing groove is 800μm-1000μm.

19. The display panel according to any one of claims 1-17, wherein, The light-emitting layer comprises multiple light-emitting sub-layers connected in series, and at least one of the light-emitting sub-layers is connected in series with an adjacent light-emitting sub-layer through a charge generation layer.

20. The display panel according to any one of claims 1-17, wherein, The second electrode is recessed at the partition groove to form a recessed area, and the bottom of the recessed area, corresponding to the area of ​​the conductive shielding layer, protrudes in a direction away from the conductive shielding layer.

21. A method for manufacturing a display panel, wherein, include: A driving backplane is formed, the driving backplane including a substrate, at least one wiring layer and a planarization layer, the wiring layer being disposed on one side of the substrate; The planarization layer covers the wiring layer; A groove is formed in the flat layer; A first electrode layer is formed on the surface of the planarization layer opposite to the substrate, the first electrode layer comprising a plurality of first electrodes spaced apart; the orthogonal projection of the groove on the planarization layer is located outside the first electrodes; A pixel definition layer is formed on the surface of the planar layer opposite to the substrate, exposing each of the first electrodes, and the pixel definition layer forms a separation groove at the groove; The pixel definition layer covers the bottom surface of the groove, and the pixel definition layer covering the bottom surface of the groove is the bottom surface of the partition groove; A conductive shielding layer is formed at least on the bottom surface of the partition groove; the conductive shielding layer does not completely cover the bottom surface of the partition groove. A light-emitting layer is formed covering the pixel definition layer, the first electrode, and the conductive shielding layer. The light-emitting layer is recessed at the partition groove and is in direct contact with at least a portion of the conductive shielding layer. A second electrode is formed to cover the light-emitting layer.

22. A method for manufacturing a display panel, wherein, include: A driving backplane is formed, the driving backplane including a substrate, at least one wiring layer and a planarization layer, the wiring layer being disposed on one side of the substrate; The planarization layer covers the wiring layer; A groove is formed in the flat layer; A conductive shielding layer is formed at least on the bottom surface of the groove, the conductive shielding layer not completely covering the bottom surface of the groove; A first electrode layer is formed on the surface of the planarization layer opposite to the substrate, the first electrode layer comprising a plurality of first electrodes spaced apart; the orthogonal projection of the groove on the planarization layer is located outside the first electrodes; A pixel definition layer is formed on the surface of the planar layer opposite to the substrate, exposing each of the first electrodes and the conductive shielding layer, and the pixel definition layer forms a separation groove at the groove; The pixel definition layer exposes at least a portion of the conductive shielding layer; A light-emitting layer is formed covering the pixel definition layer, the first electrode, and the conductive shielding layer. The light-emitting layer is recessed at the partition groove and is in direct contact with at least a portion of the conductive shielding layer. A second electrode is formed to cover the light-emitting layer.

23. A display device, wherein, Includes the display panel as described in any one of claims 1-20.

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