Display devices and electronic devices

Abstract

A display device and an electronic device are provided. In the display device of the present invention, a pixel includes: a light-emitting element including an anode and a cathode; a first transistor connected between a first power line and the anode of the light-emitting element, and operating according to the potential of a first node; a second transistor connected between the first node and a data line, and receiving a first scan signal; a third transistor connected between a second node and a reference voltage line, and receiving the first scan signal; a fourth transistor connected between the second node and an initialization voltage line, and receiving a second scan signal; and a storage capacitor connected between the first node and the second node.

Description

Technical Field

[0001] The present invention relates to a display device and an electronic device, and more specifically, to a display device and an electronic device with improved display quality. Background Technology

[0002] In display devices, light-emitting display devices use light-emitting elements that generate light through the recombination of electrons and holes to display images. These light-emitting display devices have the advantages of fast response times and low power consumption.

[0003] A light-emitting display device includes pixels connected to data lines and scan lines. A pixel typically includes a light-emitting element and pixel circuitry for controlling the amount of current flowing through the light-emitting element. The pixel circuitry controls the amount of current flowing through the light-emitting element in response to the data signal. At this time, light of a predetermined brightness is generated corresponding to the amount of current flowing through the light-emitting diode. Summary of the Invention

[0004] One object of the present invention is to provide a display device in which the circuit configuration of the display panel is simplified and the display quality is improved.

[0005] A display device according to the present invention includes: a display panel including pixels. Each pixel includes: a light-emitting element including an anode and a cathode; a first transistor connected between a first power line and a second node, and operating according to the potential of the first node; a second transistor connected between the first node and a data line, and having a gate electrode for receiving a first scan signal; a third transistor connected between the second node and a reference voltage line, and having a gate electrode for receiving the first scan signal; a fourth transistor connected between the second node and an initialization voltage line, and having a gate electrode for receiving a second scan signal; and a storage capacitor connected between the first node and the second node.

[0006] A display device according to the present invention includes: a display panel including pixels. Each pixel includes: a light-emitting element including an anode and a cathode; a first transistor connected between a first power line and a second node, and operating according to the potential of the first node; a second transistor connected between the first node and a data line, and having a gate electrode for receiving a first scan signal; a third transistor connected between the second node and a reference voltage line, and having a gate electrode for receiving the first scan signal; a first light-emitting control transistor connected between the second node and the anode of the light-emitting element, and having a gate electrode for receiving a first light-emitting control signal; a fourth transistor connected between the anode of the light-emitting element and an initialization voltage line, and having a gate electrode for receiving a second scan signal; and a storage capacitor connected between the first node and the second node.

[0007] An electronic device according to the present invention includes: a display module including pixels; and a processor driving the display module.

[0008] The pixel includes: a light-emitting element including an anode and a cathode; a first transistor connected between a first power line and a second node, and operating according to the potential of the first node; a second transistor connected between the first node and a data line, and having a gate electrode for receiving a first scan signal; a third transistor connected between the second node and a reference voltage line, and having a gate electrode for receiving the first scan signal; a fourth transistor connected between the second node and an initialization voltage line, and having a gate electrode for receiving a second scan signal; and a storage capacitor connected between the first node and the second node.

[0009] According to the present invention, the number of transistors and capacitors constituting a pixel can be reduced, thereby simplifying the circuit configuration.

[0010] Furthermore, even if the data voltage used to represent black grayscale does not have a negative voltage, it can prevent the problem of inaccurate representation of black grayscale caused by leakage of current through the drive transistor. As a result, the overall display quality can be improved. Attached Figure Description

[0011] Figure 1 This is a block diagram of a display device according to an embodiment of the present invention.

[0012] Figure 2 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0013] Figure 3A and Figure 3B This is a diagram illustrating the operation of a pixel during a data writing interval according to an embodiment of the present invention.

[0014] Figure 4A and Figure 4B This is a diagram illustrating the operation of a pixel during the initialization interval according to an embodiment of the present invention.

[0015] Figure 5A and Figure 5B This is a diagram illustrating the operation of a pixel during the light-emitting region according to an embodiment of the present invention.

[0016] Figure 6 This is a waveform diagram showing the i-th write scan signal and the i-th initialization scan signal in a variable frequency mode according to an embodiment of the present invention.

[0017] Figure 7 This is a block diagram of a display device according to an embodiment of the present invention.

[0018] Figure 8 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0019] Figure 9A and Figure 9B This is a diagram illustrating the operation of a pixel during a data writing interval according to an embodiment of the present invention.

[0020] Figure 10A and Figure 10B This is a diagram illustrating the operation of a pixel during the initialization interval according to an embodiment of the present invention.

[0021] Figure 11A and Figure 11B This is a diagram illustrating the operation of a pixel during the light-emitting region according to an embodiment of the present invention.

[0022] Figure 12 This is a waveform diagram showing the i-th write scan signal, the i-th initialization scan signal, and the i-th light emission control signal in a variable frequency mode according to an embodiment of the present invention.

[0023] Figure 13 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0024] Figure 14A and Figure 14B This is a diagram illustrating the operation of a pixel during a data writing interval according to an embodiment of the present invention.

[0025] Figure 15A and Figure 15B This is a diagram illustrating the operation of a pixel during the initialization interval according to an embodiment of the present invention.

[0026] Figure 16A and Figure 16B This is a diagram illustrating the operation of a pixel during the light-emitting region according to an embodiment of the present invention.

[0027] Figure 17 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0028] Figure 18 This is a block diagram of an electronic device according to an embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures DD: Display device; PX, PXij: Pixel PXC: Pixel circuit; ED: Light-emitting element T1: First transistor; T2: Second transistor T3: Third transistor; T4: Fourth transistor Cst: Storage capacitor; ET1, ET1a: First light-emitting control transistor ET2: Second light-emitting control transistor; GWi: i-th write scan signal GIi: The i-th initialization scan signal; VRL: The reference voltage line. VIL: Initialization voltage line; Tw: Data write interval Ti: Initialization interval; Te: Emission interval VL1: First power line VL2: Second power line WF1: First write frame WF2: Second write frame HF: Hold Frame Detailed Implementation

[0030] In this specification, when referring to a component (or region, layer, part, etc.) being "on", "connected to", or "integrated into" another component, it means that it may be directly arranged on / connected to / integrated into the other component, or that a third component may be arranged between them.

[0031] The same reference numerals refer to the same constituent elements. Furthermore, in the drawings, the thickness, proportions, and dimensions of the constituent elements are exaggerated for the purpose of effectively illustrating the technical content. "And / or" includes all but one combination that can be defined for a constituent element.

[0032] Terms such as “first,” “second,” “first,” and “second” can be used to describe multiple constituent elements, but the constituent elements are not limited by these terms. These terms are used only to distinguish one constituent element, component, region, layer, or part from another. For example, without departing from the scope of the invention, a first constituent element, first component, first region, first layer, or first part may be named a second constituent element, second component, second region, second layer, or second part; similarly, a second constituent element, second component, second region, second layer, or second part may also be named a first constituent element, first component, first region, first layer, or first part. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0033] Furthermore, terms such as "below," "under," "above," and "on top" are used to describe the relationships between the constituent elements shown in the accompanying drawings. These terms are relative concepts and are explained based on the directions shown in the drawings.

[0034] Terms such as “including” or “having” should be understood to indicate the presence of features, figures, steps, operations, constituent elements, components or combinations thereof as described in the specification, rather than precluding the presence or additional possibility of one or more other features or figures, steps, operations, constituent elements, components or combinations thereof.

[0035] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant art, and shall not be construed as having overly ideal or formal meanings unless expressly defined herein.

[0036] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0037] Figure 1 This is a block diagram of a display device DD according to an embodiment of the present invention.

[0038] Reference Figure 1 The display device DD may include a display panel DP, a drive controller 100, and a panel driver. As an example of the present invention, the panel driver may include a data drive circuit (or data driver) 200, a scan drive circuit (or scan driver) 300, and a voltage generator 400.

[0039] The display panel DP may include a display area DA and a non-display area NDA surrounding at least a portion of the display area DA. The display panel DP may include a plurality of pixels PX arranged in the display area DA. The display panel DP may include data lines DL1 to DLm, write scan lines GWL1 to GWLn, and initialization scan lines GIL1 to GILn. The data lines DL1 to DLm may be arranged along a first direction DR1, and each of the data lines DL1 to DLm may extend along a second direction DR2. The write scan lines GWL1 to GWLn and the initialization scan lines GIL1 to GILn may extend along the first direction DR1 and be arranged along the second direction DR2. The write scan lines GWL1 to GWLn may be referred to as first scan lines, and the initialization scan lines GIL1 to GILn may be referred to as second scan lines.

[0040] The drive controller 100 receives an image signal RGB and a control signal CTRL. The drive controller 100 converts the data format of the image signal RGB into an interface specification conforming to the data drive circuit 200 to generate image data I_DAT. The drive controller 100 can generate a first control signal DCS and a second control signal SCS based on the control signal CTRL.

[0041] The data driving circuit 200 receives a first control signal DCS and image data I_DAT from the drive controller 100. The data driving circuit 200 converts the image data I_DAT into a data signal and outputs the data signal to data lines DL1 to DLm. The data signal is an analog voltage corresponding to the grayscale value of the image data I_DAT.

[0042] The scan drive circuit 300 can be arranged in the non-display area NDA of the display panel DP. The scan drive circuit 300 receives a second control signal SCS from the drive controller 100 and outputs a scan signal in response to the second control signal SCS. The scan drive circuit 300 can output write scan signals to write scan lines GWL1 to GWLn and can output initialization scan signals to initialization scan lines GIL1 to GILn. The write scan signal can be referred to as the first scan signal, and the initialization scan signal can be referred to as the second scan signal.

[0043] According to one embodiment of the present invention, each of the plurality of pixels PX includes a light-emitting element ED (see reference). Figure 2 ) and the pixel circuit PXC (refer to) that controls the light emission of the light-emitting element ED. Figure 2 A pixel circuit (PXC) may include at least one transistor and at least one capacitor. The pixel circuit (PXC) may be referred to as a pixel circuit section.

[0044] A voltage generator (or power supply unit) 400 generates the voltages required for the operation of the display panel DP. In one embodiment of the present invention, the voltage generator 400 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a reference voltage Vref, and an initialization voltage Vint.

[0045] Figure 2 This is a circuit diagram of pixel PXij according to an embodiment of the present invention.

[0046] Figure 2 The example shown in the text is as follows Figure 1 The image shows one of the multiple pixels PX, PXij. Pixels PX have the same circuit structure, therefore they will... Figure 2 The description of a single pixel PXij omits the description of the other pixels PX.

[0047] Reference Figure 2 Pixel PXij and written scan lines GWL1 to GGLn (refer to) Figure 1 Write the i-th scan line GWLi and initialize scan lines GIL1 to GILn (refer to) Figure 1 The i-th initialization scan line GILi and data lines DL1 to DLm in (refer to) Figure 1The j-th data line DLj in ) is connected.

[0048] Pixel PXij may include a pixel circuit (or pixel circuit section) PXC and a light-emitting element ED electrically connected to the pixel circuit PXC. In this embodiment, the pixel circuit PXC may include four transistors (referred to as first transistor T1 to fourth transistor T4) and a capacitor (hereinafter referred to as storage capacitor Cst). In one embodiment of the present invention, one of the four transistors of the pixel circuit PXC is omitted, or the pixel circuit PXC may also include additional transistors.

[0049] The i-th write scan line GWLi supplies the i-th write scan signal GWi to pixel PXij, and the i-th initialization scan line GILi supplies the i-th initialization scan signal Gii to pixel PXij. The j-th data line DLj supplies the j-th data signal DSj to pixel PXij. The j-th data signal DSj may have the same characteristics as the drive controller 100 (see reference). Figure 1 The output image data I_DAT (refer to) Figure 1 The voltage level corresponding to the grayscale value of ().

[0050] Furthermore, pixel PXij can be connected to a first power line VL1 that receives a first driving voltage ELVDD, a second power line VL2 that receives a second driving voltage ELVSS, a reference voltage line VRL that receives a reference voltage Vref, and an initialization voltage line VIL that receives an initialization voltage Vint. The first driving voltage ELVDD can have a voltage level higher than the second driving voltage ELVSS, and the reference voltage Vref can have a voltage level lower than the first driving voltage ELVDD but higher than the second driving voltage ELVSS. The initialization voltage Vint can have a voltage level lower than or equal to the second driving voltage ELVSS.

[0051] In this embodiment, each of the first transistor T1 to the fourth transistor T4 may be an N-type transistor. Each of the first transistor T1 to the fourth transistor T4 may include an oxide semiconductor as a semiconductor layer.

[0052] The light-emitting element (ED) may include an anode and a cathode. When the ED is an organic light-emitting element, it may further include an organic layer disposed between the anode and the cathode. The cathode of the ED may be connected to a second power line VL2. In this embodiment, the cathode of the ED may be directly connected to the second power line VL2. The anode of the ED may be connected to the pixel circuit PXC. The ED emits light in response to the amount of current flowing through the first transistor T1 of the pixel circuit PXC.

[0053] A first transistor T1 is connected between a first power supply line VL1 receiving the first driving voltage ELVDD and the anode of the light-emitting element ED. The first transistor T1 can be referred to as a driving transistor. The first transistor T1 may include a first electrode, a second electrode, and a gate electrode. The gate electrode of the first transistor T1 is connected to a first node N1, the first electrode of the first transistor T1 is connected to the first power supply line VL1 receiving the first driving voltage ELVDD, and the second electrode of the first transistor T1 may be connected to a second node N2. The first electrode can be referred to as the drain of the first transistor T1, and the second electrode can be referred to as the source of the first transistor T1. The first transistor T1 operates according to the potential of the first node N1. In this embodiment, the first transistor T1 may further include a back gate electrode BGE. The back gate electrode BGE may be opposite to the gate electrode of the first transistor T1 and connected to the second electrode of the first transistor T1.

[0054] The second transistor T2 is connected between the j-th data line DLj and the first node N1, and receives the i-th write scan signal (or first scan signal) GWi. The second transistor T2 can be referred to as a switching transistor. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first node N1, and a gate electrode connected to the i-th write scan line GWLi. The second transistor T2 can transmit the j-th data signal DSj received via the j-th data line DLj to the first node N1 in response to the i-th write scan signal GWi received via the i-th write scan line GWLi.

[0055] A storage capacitor Cst can be connected between a first node N1 and a second node N2. The storage capacitor Cst may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The storage capacitor Cst can store the voltage difference between the first node N1 and the second node N2.

[0056] The first node N1 can be defined as a node connected to the gate electrode of the first transistor T1, the second electrode of the second transistor T2, and the first electrode of the storage capacitor Cst.

[0057] A third transistor T3 is connected between the reference voltage line VRL and the second node N2, and receives the i-th write scan signal GWi. The third transistor T3 may include a first electrode connected to the reference voltage line VRL, a second electrode connected to the second node N2, and a gate electrode connected to the i-th write scan line GWLi. The third transistor T3 can be turned on by the i-th write scan signal GWi received through the i-th write scan line GWLi, thereby transmitting the reference voltage Vref to the second node N2.

[0058] A fourth transistor T4 is connected between the initialization voltage line VIL and the second node N2, and receives the i-th initialization scan signal GIi. The fourth transistor T4 may include a first electrode connected to the initialization voltage line VIL, a second electrode connected to the second node N2, and a gate electrode connected to the i-th initialization scan line GILi. The fourth transistor T4 can be turned on by the i-th initialization scan signal GIi received through the i-th initialization scan line GILi, thereby transmitting the initialization voltage Vint to the second node N2.

[0059] The second node N2 can be defined as a node connected to the second electrode of the first transistor T1, the second electrode of the storage capacitor Cst, the second electrode of the third transistor T3, and the second electrode of the fourth transistor T4.

[0060] In this embodiment, the second transistor T2 and the third transistor T3 can receive the same scan signal (i.e., the i-th write scan signal GWi). Therefore, the number of scan signals required to drive pixel PXij can be reduced to two, and consequently, the number of driving circuits (e.g., scan driving circuits) required to drive pixel PXij can be reduced to two. With the reduction in the number of scan driving circuits, the display panel DP (refer to...) can be reduced. Figure 1 The non-display area NDA (refer to) Figure 1 The width of the display panel (DP) can be adjusted to solve the problem of increased dead zone in the DP.

[0061] Figure 3A and Figure 3B This is a diagram illustrating the operation of pixel PXij during the data writing interval Tw according to an embodiment of the present invention.

[0062] Reference Figure 3A and Figure 3B The i-th write scan signal GWi can have an active level (e.g., high level) during the data write interval Tw, and the i-th initialization scan signal GIi can have an inactive level (e.g., low level) during the data write interval Tw.

[0063] During the data write interval Tw, the second transistor T2 and the third transistor T3 are turned on in response to the i-th write scan signal GWi, and the fourth transistor T4 is turned off in response to the i-th initialization scan signal GIi. Therefore, during the data write interval Tw, the j-th data signal DSj supplied from the j-th data line DLj is applied (or written) to the first node N1 through the turned-on second transistor T2. In this case, the first node N1 may have a voltage level corresponding to the j-th data signal DSj (i.e., referred to as the data voltage "Vd"). Furthermore, during the data write interval Tw, the second node N2 is initialized to a reference voltage Vref through the turned-on third transistor T3. As an example of the invention, the reference voltage Vref may have a voltage level higher than the second drive voltage ELVSS.

[0064] Therefore, during the data writing interval Tw, the gate-source voltage “Vgs” of the first transistor T1 can be “Vd-Vref”.

[0065] The data writing interval Tw can end at the time point when the i-th write scan signal GWi is deactivated.

[0066] Figure 4A and Figure 4B This is a diagram illustrating the operation of pixel PXij during the initialization interval Ti according to an embodiment of the present invention.

[0067] Reference Figure 4A and Figure 4B If data is written to interval Tw (refer to...) Figure 3B When the process ends, the initialization interval Ti occurs. That is, data is written to interval Tw before the initialization interval Ti.

[0068] During the initialization interval Ti, the i-th initialization scan signal Gii can have an active level (e.g., high level), and the i-th write scan signal GWi can have an inactive level (e.g., low level).

[0069] During the initialization interval Ti, the fourth transistor T4 can be turned on in response to the i-th initialization scan signal GIi, and the second transistor T2 and the third transistor T3 can be turned off in response to the i-th write scan signal GWi. Therefore, during the initialization interval Ti, the initialization voltage Vint is applied to the second node N2. When the potential "Vs" of the second node N2 changes to the initialization voltage Vint, the change in potential ΔV of the second node N2 can be "Vref - Vint". As an example of the present invention, the initialization voltage Vint can have a voltage level lower than or equal to the second drive voltage ELVSS.

[0070] Here, the first node N1 is coupled to the second node N2 via the storage capacitor Cst. Therefore, the potential "Vg" of the first node N1 can change according to the change in the potential of the second node N2 (ΔV = Vref - Vint). That is, during the initialization interval Ti, the potential "Vg" of the first node N1 changes to "Vd - Vref + Vint". Therefore, during the initialization interval Ti, the gate-source voltage "Vgs" of the first transistor T1 can be "(Vd - Vref + Vint) - Vint = Vd - Vref". In other words, even if the potential "Vs" of the second node N2 changes due to the change from the data write interval Tw to the initialization interval Ti, the gate-source voltage "Vgs" of the first transistor T1 can remain at "Vd - Vref".

[0071] Furthermore, regardless of the voltage level of the initialization voltage Vint, the gate-source voltage "Vgs" of the first transistor T1 can remain at "Vd-Vref". That is, the gate-source voltage "Vgs" of the first transistor T1 in the data writing interval Tw can be the same as the gate-source voltage "Vgs" of the first transistor T1 in the initialization interval Ti.

[0072] As an example of the present invention, when the reference voltage Vref is 3V and the initialization voltage Vint is 0V, and the j-th data signal DSj is used to represent black grayscale, the data voltage "Vd" can be 0V. That is, even if a 0V data voltage "Vd" is applied to the gate electrode of the first transistor T1 to represent black grayscale, the gate-source voltage "Vgs" of the first transistor T1 can be "Vd-Vref=-3V", which is lower than the 0V data voltage "Vd". Therefore, when representing black grayscale, since the gate-source voltage "Vgs" of the first transistor T1 is lower than 0V, the first transistor T1 can be reliably kept in the off state. As a result, even if the data voltage used to represent black grayscale does not have a negative voltage, the problem of inaccurate representation of black grayscale due to current leakage through the first transistor T1 can be prevented.

[0073] Figure 5A and Figure 5B This is a diagram illustrating the operation of pixel PXij during the light-emitting region Te according to an embodiment of the present invention.

[0074] Reference Figure 5A and Figure 5B If the initial interval Ti (refer to) Figure 4B When the emission interval Te ends, the luminescent region can occur.

[0075] When the j-th data signal DSj is used to represent white grayscale, the data voltage "Vd" can have a voltage level higher than the reference voltage Vref. In this case, the gate-source voltage "Vgs" of the first transistor T1 can be greater than the threshold voltage "Vth". Therefore, if the gate-source voltage "Vgs" of the first transistor T1 is greater than the threshold voltage "Vth", the first transistor T1 can be turned on, and the drive current can flow between the first power line VL1 and the second power line VL2 through the turned-on first transistor T1. The brightness of the light output by the light-emitting element ED can vary depending on the magnitude of the drive current.

[0076] When the j-th data signal DSj is used to represent black grayscale, the data voltage "Vd" can have a voltage level lower than the reference voltage Vref. In this case, the gate-source voltage "Vgs" of the first transistor T1 can be less than the threshold voltage "Vth". Therefore, the first transistor T1 can be turned off, and the drive current can be omitted from the light-emitting element ED. In this case, the light-emitting element ED can be turned off to represent black grayscale.

[0077] When the gate-source voltage "Vgs" of the first transistor T1 has "Vd-Vref", the light-emitting element ED can stably present black grayscale even if the data voltage "Vd" with black grayscale or the initialization voltage Vint is not set to a voltage lower than 0V.

[0078] Figure 6 This is a waveform diagram showing the i-th write scan signal GWi and the i-th initialization scan signal GIi in a variable frequency mode according to an embodiment of the present invention.

[0079] Reference Figure 1 and Figure 6 According to an embodiment of the present invention, the drive controller 100 can determine the drive frequency and control the operation of the data drive circuit 200 and the scan drive circuit 300 according to the determined drive frequency.

[0080] The driving frequency of the display device DD can vary in various ways. As an example of the present invention, the first driving frequency can be the highest driving frequency that the display device DD can operate at. For example, the first driving frequency can be 360Hz. The first driving frequency can be referred to as the reference frequency or the maximum frequency.

[0081] If the display device DD operates at a first driving frequency, an image can be displayed during the first driving frame F1. The first driving frame F1 may include a first write frame WF1. If the display device DD operates at a second driving frequency, an image can be displayed during the second driving frame F2. When the second driving frequency is lower than the first driving frequency, the second driving frame F2 may include a second write frame WF2 and at least one hold frame HF. The second write frame WF2 may have the same duration as the first write frame WF1. The number of hold frames HF may vary depending on the magnitude of the second driving frequency.

[0082] The i-th write scan signal (or first scan signal) GWi and the i-th initialization scan signal (or second scan signal) GIi can be activated during the first write frame WF1 and the second write frame WF2. The i-th write scan signal GWi can be deactivated during the hold frame HF, and the i-th initialization scan signal GIi can be activated during the hold frame HF. Therefore, the hold frame HF does not include the data write interval Tw, but may include the initialization interval Ti. During the initialization interval Ti of the hold frame HF, the second node N2 of pixel PX (refer to...) Figure 2 The first transistor T1 (refer to the initialization voltage Vint) can be initialized to the initialization voltage Vint. During the initialization interval Ti of the holding frame HF, even if the potential "Vs" of the second node N2 changes to the initialization voltage Vint, the first transistor T1 (refer to the initialization voltage Vint) can be initialized to the initialization voltage Vint. Figure 2 The gate-source voltage “Vgs” can also be maintained as “Vd-Vref”.

[0083] Figure 7 This is a block diagram of a display device DDA according to an embodiment of the present invention. However, for Figure 7 The constituent elements shown are related to Figure 1 The same constituent elements shown are marked with the same reference numerals, and their specific descriptions will be omitted.

[0084] Reference Figure 7 The display device DDa may include a display panel DP, a drive controller 100, and a panel driver. As an example of the present invention, the panel driver may include a data drive circuit 200, a scan drive circuit 300, a light-emitting drive circuit (or light-emitting driver) 350, and a voltage generator 400.

[0085] The display panel DP may include a display area DA and a non-display area NDA surrounding at least a portion of the display area DA. The display panel DP may include a plurality of pixels PX arranged in the display area DA. The display panel DP may include write scan lines GWL1 to GWLn, initialization scan lines GIL1 to GILn, and light emission control lines EML1 to EMLn.

[0086] The drive controller 100 can generate a first control signal DCS, a second control signal SCS, and a third control signal ECS based on the control signal CTRL.

[0087] The light-emitting driving circuit 350 can be arranged in the non-display area NDA of the display panel DP. As an example of the invention, the scan driving circuit 300 can be arranged adjacent to a first side (e.g., the left side) of the display area DA, and the light-emitting driving circuit 350 can be arranged adjacent to a second side (e.g., the right side) of the display area DA that is different from the first side. As an example of the invention, the second side can be the side opposite to the first side. Figure 7 In the example shown, the scan driving circuit 300 and the light-emitting driving circuit 350 are respectively arranged on both sides of the display area DA, but the present invention is not limited thereto. For example, the scan driving circuit 300 and the light-emitting driving circuit 350 may be arranged adjacent to one of the first and second sides of the display panel DP. In one embodiment, the scan driving circuit 300 and the light-emitting driving circuit 350 may be integrated into a single circuit.

[0088] The light-emitting driving circuit 350 receives a third control signal ECS from the driving controller 100 and outputs a light-emitting control signal to the light-emitting control lines EML1 to EMLn in response to the third control signal ECS.

[0089] Figure 8 This is a circuit diagram of pixel PXij according to an embodiment of the present invention.

[0090] Reference Figure 8 Pixel PXij and written scan lines GWL1 to GGLn (refer to) Figure 7 Write the i-th scan line GWLi and initialize scan lines GIL1 to GILn (refer to) Figure 7 The i-th initialization scan line GILi and data lines DL1 to DLm in (refer to) Figure 7 The j-th data line DLj in the diagram is connected. Pixel PXij is also connected to the i-th light emission control line EML1 to EMLn (refer to the diagram). Figure 7 )connect.

[0091] Pixel PXij may include a pixel circuit (or pixel circuit section) PXCa and a light-emitting element ED electrically connected to the pixel circuit PXCa. In this embodiment, the pixel circuit PXCa may include five transistors (referred to as first transistor T1 to fourth transistor T4 and first light-emitting control transistor ET1) and a capacitor (hereinafter referred to as storage capacitor Cst). In one embodiment of the present invention, one of the five transistors of the pixel circuit PXCa may be omitted, or the pixel circuit PXCa may also include additional transistors.

[0092] In this embodiment, each of the first transistor T1 to the fourth transistor T4 and the first light-emitting control transistor ET1 can be an N-type transistor. Each of the first transistor T1 to the fourth transistor T4 and the first light-emitting control transistor ET1 can include an oxide semiconductor as a semiconductor layer.

[0093] The first transistor T1 to the third transistor T3 and the storage capacitor Cst and Figure 2 The structures shown are identical, so their specific descriptions will be omitted.

[0094] The first light-emitting control transistor ET1 is connected between the second node N2 and the light-emitting element ED, and receives the i-th light-emitting control signal (or first light-emitting control signal) EMi. The first light-emitting control transistor ET1 may include a first electrode connected to the second node N2, a second electrode connected to the anode of the light-emitting element ED, and a gate electrode connected to the i-th light-emitting control line EMLi. In response to the i-th light-emitting control signal EMi received through the i-th light-emitting control line EMLi, the first light-emitting control transistor ET1 electrically connects or disconnects the second node N2 from the anode of the light-emitting element ED.

[0095] The second node N2 can be defined as a node connected to the second electrode of the first transistor T1, the second electrode of the storage capacitor Cst, the second electrode of the third transistor T3, and the first electrode of the first light-emitting control transistor ET1.

[0096] A fourth transistor T4 is connected between the initialization voltage line VIL and the anode of the light-emitting element ED, and receives the i-th initialization scan signal GIi. The fourth transistor T4 may include a first electrode connected to the initialization voltage line VIL, a second electrode connected to the anode of the light-emitting element ED, and a gate electrode connected to the i-th initialization scan line GILi. The fourth transistor T4 can be turned on by the i-th initialization scan signal GIi received through the i-th initialization scan line GILi, thereby transmitting the initialization voltage Vint to the anode of the light-emitting element ED.

[0097] Figure 9A and Figure 9B This is a diagram illustrating the operation of pixel PXij during the data writing interval Tw according to an embodiment of the present invention.

[0098] Reference Figure 9A and Figure 9BThe i-th emission control signal EMi has an inactive level during the inactivation interval NEP and an active level during the activation interval EP. The i-th write scan signal GWi may have an active level (e.g., high level) during the data write interval Tw, and the i-th initialization scan signal GIi may have an inactive level (e.g., low level) during the data write interval Tw. As an example of the present invention, the inactivation interval NEP of the i-th emission control signal EMi may overlap with the data write interval Tw.

[0099] During the data write interval Tw, the second transistor T2 and the third transistor T3 are turned on in response to the i-th write scan signal GWi, and the fourth transistor T4 is turned off in response to the i-th initialization scan signal GIi. Therefore, during the data write interval Tw, the j-th data signal DSj supplied from the j-th data line DLj is applied (or written) to the first node N1 through the turned-on second transistor T2. In this case, the first node N1 can have a voltage level corresponding to the j-th data signal DSj (referred to as the data voltage "Vd"). Furthermore, during the data write interval Tw, the second node N2 is initialized to the reference voltage Vref through the turned-on third transistor T3.

[0100] During the deactivation interval NEP, the first light-emitting control transistor ET1 is turned off in response to the i-th light-emitting control signal EMi. Therefore, the second node N2 can be electrically disconnected from the anode of the light-emitting element ED during the deactivation interval NEP. That is, during the data write interval Tw, when the second node N2 is initialized to the reference voltage Vref, the anode of the light-emitting element ED is not initialized.

[0101] During the data write interval Tw, the gate-source voltage “Vgs” of the first transistor T1 can be “Vd-Vref”.

[0102] The data writing interval Tw can end at the time point when the i-th write scan signal GWi is deactivated.

[0103] Figure 10A and Figure 10B This is a diagram illustrating the operation of pixel PXij during the initialization interval Ti according to an embodiment of the present invention.

[0104] Reference Figure 10A and Figure 10B If data is written to interval Tw (refer to...) Figure 9BWhen the initialization interval Ti ends, the data writing interval Tw occurs before the initialization interval Ti. That is, the data writing interval Tw precedes the initialization interval Ti. The activation interval EP of the i-th emission control signal EMi can begin at the start time of the initialization interval Ti. Therefore, the initialization interval Ti can not overlap with the deactivation interval NEP of the i-th emission control signal EMi, but can overlap with the activation interval EP of the i-th emission control signal EMi.

[0105] During the initialization interval Ti, the fourth transistor T4 can be turned on in response to the i-th initialization scan signal GIi, while the second transistor T2 and the third transistor T3 can be turned off in response to the i-th write scan signal GWi. Therefore, during the initialization interval Ti, the initialization voltage Vint is applied to the anode of the light-emitting element ED.

[0106] During the initialization interval Ti, the first light-emitting control transistor ET1 is turned on in response to the i-th light-emitting control signal EMi. Therefore, the initialization voltage Vint is transmitted to the second node N2 through the turned-on first light-emitting control transistor ET1. That is, during the initialization interval Ti, the anode of the light-emitting element ED and the second node N2 can be initialized to the initialization voltage Vint.

[0107] When the potential "Vs" of the second node N2 is changed to the initial voltage Vint, the change in potential ΔV of the second node N2 can be "Vref-Vint".

[0108] Here, the first node N1 can be coupled to the second node N2 via the storage capacitor Cst. Therefore, the potential "Vg" of the first node N1 can change according to the change in the potential of the second node N2 (ΔV = Vref - Vint). That is, during the initialization interval Ti, the potential "Vg" of the first node N1 changes to "Vd - Vref + Vint". Therefore, during the initialization interval Ti, the gate-source voltage "Vgs" of the first transistor T1 can be "(Vd - Vref + Vint) - Vint = Vd - Vref". That is, even if the potential "Vs" of the second node N2 changes due to the change from the data write interval Tw to the initialization interval Ti, the gate-source voltage Vgs of the first transistor T1 can remain at "Vd - Vref".

[0109] Furthermore, regardless of the voltage level of the initialization voltage Vint, the gate-source voltage “Vgs” of the first transistor T1 can be maintained as “Vd-Vref”.

[0110] Figure 11A and Figure 11B This is a diagram illustrating the operation of pixel PXij during the light-emitting region Te according to an embodiment of the present invention.

[0111] Reference Figure 11A and Figure 11B If the initial interval Ti (refer to) Figure 10B When the emission control signal EMi ends, the emission interval Te can occur. As an example of the present invention, the emission interval Te can overlap with the activation interval EP of the i-th emission control signal EMi.

[0112] If the gate-source voltage "Vgs" of the first transistor T1 is greater than the threshold voltage "Vth", then the first transistor T1 can be turned on, and the driving current can flow between the turned-on first transistor T1 and the first light-emitting control transistor ET1 between the first power line VL1 and the second power line VL2. The brightness of the light output by the light-emitting element ED can be changed according to the magnitude of the driving current.

[0113] Figure 12 This is a waveform diagram showing the i-th write scan signal, the i-th initialization scan signal, and the i-th light emission control signal in a variable frequency mode according to an embodiment of the present invention.

[0114] Reference Figure 8 and Figure 12 The i-th write scan signal GWi, the i-th initialization scan signal GIi, and the i-th emission control signal EMi can be activated during the first write frame WF1 and the second write frame WF2. The i-th write scan signal GWi can be deactivated during the hold frame HF, and the i-th initialization scan signal GIi can be activated during the hold frame HF. Therefore, the hold frame HF does not include the data write interval Tw, but may include the initialization interval Ti. Furthermore, the i-th emission control signal EMi may not be deactivated during the hold frame HF, but may remain active. Therefore, during the hold frame HF, the first emission control transistor ET1 can remain on, and during the initialization interval Ti, the second node N2 of the pixel can be initialized to the initialization voltage Vint applied by the fourth transistor T4 and the first emission control transistor ET1. Even if the potential "Vs" of the second node N2 changes to the initialization voltage Vint during the initialization interval Ti of the hold frame HF, the gate-source voltage "Vgs" of the first transistor T1 can remain "Vd-Vref".

[0115] Figure 13 This is a circuit diagram of pixel PXij according to an embodiment of the present invention.

[0116] Reference Figure 13Pixel PXij may include a pixel circuit (or pixel circuit section) PXCb and a light-emitting element ED electrically connected to the pixel circuit PXCb. In this embodiment, the pixel circuit PXCb may include five transistors (referred to as first transistor T1 to fourth transistor T4 and first light-emitting control transistor ET1a) and a capacitor (hereinafter referred to as storage capacitor Cst). The first transistor T1 to fourth transistor T4 and storage capacitor Cst are connected to... Figure 2 The structures shown are identical, so their specific descriptions will be omitted.

[0117] A first light-emitting control transistor ET1a is connected between the second node N2 and the light-emitting element ED, and receives the i-th light-emitting control signal EMi. The first light-emitting control transistor ET1a may include a first electrode connected to the second node N2, a second electrode connected to the anode of the light-emitting element ED, and a gate electrode connected to the i-th light-emitting control line EMLi. In response to the i-th light-emitting control signal EMi received through the i-th light-emitting control line EMLi, the first light-emitting control transistor ET1a electrically connects or disconnects the second node N2 from the anode of the light-emitting element ED.

[0118] The second node N2 can be defined as a node connected to the second electrode of the first transistor T1, the second electrode of the storage capacitor Cst, the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the first light-emitting control transistor ET1a.

[0119] Figure 14A and Figure 14B This is a diagram illustrating the operation of pixel PXij during the data writing interval Tw according to an embodiment of the present invention.

[0120] Reference Figure 14A and Figure 14B The i-th emission control signal EMi has an inactive level during the inactivation interval NEP and an active level during the activation interval EP. The i-th write scan signal GWi may have an active level (e.g., high level) during the data write interval Tw, and the i-th initialization scan signal GIi may have an inactive level (e.g., low level) during the data write interval Tw. As an example of the present invention, the inactivation interval NEP of the i-th emission control signal EMi may overlap with the data write interval Tw.

[0121] During the data write interval Tw, the second transistor T2 and the third transistor T3 are turned on in response to the i-th write scan signal GWi, and the fourth transistor T4 is turned off in response to the i-th initialization scan signal GIi. Therefore, during the data write interval Tw, the j-th data signal DSj supplied from the j-th data line DLj is applied (or written) to the first node N1 through the turned-on second transistor T2. In this case, the first node N1 can have a voltage level corresponding to the j-th data signal DSj (i.e., referred to as the data voltage "Vd"). Furthermore, during the data write interval Tw, the second node N2 is initialized to the reference voltage Vref through the turned-on third transistor T3.

[0122] During the deactivation interval NEP, the first light-emitting control transistor ET1a is turned off in response to the i-th light-emitting control signal EMi. Therefore, the second node N2 can be electrically disconnected from the anode of the light-emitting element ED during the deactivation interval NEP. That is, during the data write interval Tw, when the second node N2 is initialized to the reference voltage Vref, the anode of the light-emitting element ED is not initialized.

[0123] During the data write interval Tw, the gate-source voltage “Vgs” of the first transistor T1 can be “Vd-Vref”.

[0124] The data writing interval Tw can end at the time point when the i-th write scan signal GWi is deactivated.

[0125] Figure 15A and Figure 15B This is a diagram illustrating the operation of pixel PXij during the initialization interval Ti according to an embodiment of the present invention.

[0126] Reference Figure 15A and Figure 15B If data is written to interval Tw (refer to...) Figure 14B When the data writing interval Tw ends, the initialization interval Ti occurs. That is, the data writing interval Tw precedes the initialization interval Ti. The initialization interval Ti may partially overlap with the deactivation interval NEP of the i-th light emission control signal EMi. As an example of the present invention, the initialization interval Ti may include a first initialization interval Ti1 and a second initialization interval Ti2. The first initialization interval Ti1 may overlap with the deactivation interval NEP of the i-th light emission control signal EMi, and the second initialization interval Ti2 may not overlap with the deactivation interval NEP of the i-th light emission control signal EMi. That is, the second initialization interval Ti2 may overlap with the activation interval EP of the i-th light emission control signal EMi.

[0127] During the initialization interval Ti, the fourth transistor T4 can be turned on in response to the i-th initialization scan signal GIi, while the second transistor T2 and the third transistor T3 can be turned off in response to the i-th write scan signal GWi. Therefore, during the initialization interval Ti, the initialization voltage Vint is applied to the second node N2.

[0128] During the first initialization interval Ti1, the first light-emitting control transistor ET1a is turned off in response to the i-th light-emitting control signal EMi. Therefore, during the first initialization interval Ti1, the initialization voltage Vint cannot be transmitted to the anode of the light-emitting element ED through the turned-off first light-emitting control transistor ET1a. That is, during the first initialization interval Ti1, only the second node N2 can be initialized. During the first initialization interval Ti1, the first light-emitting control transistor ET1a is in the off state, so even if the initialization voltage Vint has the same voltage level as the second driving voltage ELVSS, abnormal light emission of the light-emitting element ED will not occur.

[0129] When the potential "Vs" of the second node N2 is changed to the initial voltage Vint, the change in potential ΔV of the second node N2 can be "Vref-Vint".

[0130] Here, the first node N1 is coupled to the second node N2 via the storage capacitor Cst. Therefore, the potential "Vg" of the first node N1 can change according to the change in the potential of the second node N2 (ΔV = Vref - Vint). That is, during the initialization interval Ti, the potential "Vg" of the first node N1 changes to "Vd - Vref + Vint". Therefore, during the initialization interval Ti, the gate-source voltage "Vgs" of the first transistor T1 can be "(Vd - Vref + Vint) - Vint = Vd - Vref". That is, even if the potential "Vs" of the second node N2 changes, the gate-source voltage "Vgs" of the first transistor T1 can remain at "Vd - Vref".

[0131] Furthermore, regardless of the voltage level of the initialization voltage Vint, the gate-source voltage “Vgs” of the first transistor T1 can be maintained as “Vd-Vref”.

[0132] Subsequently, during the second initialization interval Ti2, the first light-emitting control transistor ET1a is turned on in response to the i-th light-emitting control signal EMi. Therefore, during the second initialization interval Ti2, the anode of the light-emitting element ED can be initialized to the initialization voltage Vint. As an example of the present invention, the duration of the second initialization interval Ti2 can be less than or equal to the duration of the first initialization interval Ti1.

[0133] Figure 16A and Figure 16B This is a diagram illustrating the operation of pixel PXij during the light-emitting region Te according to an embodiment of the present invention.

[0134] Reference Figure 16A and Figure 16B If the initial interval Ti (refer to) Figure 15B When the signal ends, the emission interval Te can occur. The emission interval Te can overlap with the activation interval EP of the i-th emission control signal EMi.

[0135] If the gate-source voltage "Vgs" of the first transistor T1 is greater than the threshold voltage "Vth", then the first transistor T1 can be turned on, and the driving current can flow between the turned-on first transistor T1 and the first light-emitting control transistor ET1a, between the first power line VL1 and the second power line VL2. The brightness of the light output by the light-emitting element ED can be changed according to the magnitude of the driving current.

[0136] Figure 17 This is a circuit diagram of pixel PXij according to an embodiment of the present invention.

[0137] Reference Figure 17 Pixel PXij may include a pixel circuit (or pixel circuit section) PXCc and a light-emitting element ED electrically connected to the pixel circuit PXCc. In this embodiment, the pixel circuit PXCc may include six transistors (referred to as first transistor T1 to fourth transistor T4, first light-emitting control transistor ET1a, and second light-emitting control transistor ET2) and two capacitors (hereinafter referred to as storage capacitor Cst and holding capacitor Chold). The first transistor T1 to fourth transistor T4, the first light-emitting control transistor ET1a, and the storage capacitor Cst and... Figure 13 The structures shown are identical, so their specific descriptions will be omitted.

[0138] The second light-emitting control transistor ET2 is connected between the first power line VL1 and the first transistor T1, and receives the i-th light-emitting control signal EMi. The second light-emitting control transistor ET2 may include a first electrode connected to the first power line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the i-th light-emitting control line EMi. In response to the i-th light-emitting control signal EMi received through the i-th light-emitting control line EMi, the second light-emitting control transistor ET2 electrically connects or disconnects the first power line VL1 from the first transistor T1.

[0139] The second light-emitting control transistor ET2 is turned off during the deactivation interval NEP of the i-th light-emitting control signal EMi, and turned on during the activation interval EP of the i-th light-emitting control signal EMi. That is, the second light-emitting control transistor ET2 can be turned on during the data write interval Tw (refer to...). Figure 14B ) and the first initialization interval Ti1 (refer to Figure 15B It is terminated during the period and in the second initialization interval Ti2 (refer to) Figure 15B ) and the luminescent region Te (refer to Figure 16B It was activated during the period.

[0140] A holding capacitor Chold can be connected between the first power line VL1 and the second node N2. The holding capacitor Chold can include a first electrode connected to the first power line VL1 and a second electrode connected to the second node N2. The holding capacitor Chold can store the voltage difference between the first power line VL1 and the second node N2. Here, the potential "Vs" of the second node N2 can be changed according to the ratio of the holding capacitor Chold to the storage capacitor Cst.

[0141] Figure 17 The illustration shows an embodiment in which the second light-emitting control transistor ET2 receives the same signal as the i-th light-emitting control signal EMi and is simultaneously turned on with the first light-emitting control transistor ET1a, but the invention is not limited thereto. Alternatively, the second light-emitting control transistor ET2 may receive a light-emitting control signal (or a second light-emitting control signal) different from the i-th light-emitting control signal EMi.

[0142] Figure 18 This is a block diagram of an electronic device 601 according to an embodiment of the present invention.

[0143] Reference Figure 18 The electronic device 601 displays various information through the display module 640 within the operating system. If the processor 610 runs an application stored in the memory 620, the display module 640 provides application information to the user through the display panel 641.

[0144] The processor 610 receives external input via the input module 630 or the sensor module 661 and runs the application corresponding to the external input. For example, if the user selects the camera icon displayed on the display panel 641, the processor 610 receives user input via the input sensor 661-2 and activates the camera module 671. The processor 610 transmits the image data corresponding to the captured image obtained by the camera module 671 to the display module 640. The display module 640 displays the image corresponding to the captured image via the display panel 641.

[0145] As another example, when the display module 640 performs personal information authentication, the fingerprint sensor 661-1 obtains the input fingerprint information as input data. The processor 610 compares the input data obtained by the fingerprint sensor 661-1 with the authentication data stored in the memory 620 and runs the application based on the comparison result. The display module 640 can display the information executed according to the application logic via the display panel 641.

[0146] As another example, when the music stream icon displayed on display module 640 is selected, processor 610 obtains user input through input sensor 661-2 and activates the music stream application stored in memory 620. If a music run command is entered in the music stream application, processor 610 activates sound output module 663 to provide the user with sound information consistent with the music run command.

[0147] The operation of electronic device 601 has been briefly described above. The configuration of electronic device 601 will now be described in detail. A portion of the configuration of electronic device 601 described below may be provided as a single integrated configuration, or a single configuration may be provided as two or more separate configurations.

[0148] Reference Figure 18 Electronic device 601 can communicate with external electronic device 602 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, electronic device 601 may include a processor 610, a memory 620, an input module 630, a display module 640, a power module 650, a built-in module 660, and an external module 670. According to one embodiment, electronic device 601 may omit at least one of the above-mentioned components, or may add one or more other components. According to one embodiment, some of the above-mentioned components (e.g., sensor module 661, antenna module 662, or voice output module 663) may be integrated into another component (e.g., display module 640).

[0149] The processor 610 can run software to control at least one other component (e.g., hardware or software component) of the electronic device 601 connected to the processor 610, and can perform various data processing or calculations. According to one embodiment, as at least part of the data processing or calculation, the processor 610 can store commands or data received from other components (e.g., input module 630, sensor module 661, or communication module 673) in volatile memory 621, process the commands or data stored in volatile memory 621, and store the result data in non-volatile memory 622.

[0150] Processor 610 may include a main processor 611 and an auxiliary processor 612. Main processor 611 may include one or more of a central processing unit (CPU) 611-1 and an application processor (AP). Main processor 611 may also include one or more of a graphics processing unit (GPU) 611-2, a communication processor (CP), and an image signal processor (ISP). Main processor 611 may also include a neural network processing unit (NPU) 611-3. Neural network processing unit 611-3 is a processor dedicated to processing artificial intelligence models, and these models can be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. Artificial neural networks can be one of the following: deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), restricted Boltzmann machines (RBM), deep belief networks (DBN), bidirectional recurrent deep neural networks (BRDNN), deep Q-networks, or combinations of two or more of the above, but are not limited to the examples above. In addition to hardware architecture, artificial intelligence models may additionally or alternatively include software architecture. At least two of the above-described processing units and processors can be implemented in an integrated configuration (e.g., a single chip), or each can be implemented in an independent configuration (e.g., multiple chips).

[0151] The auxiliary processor 612 may include a drive controller 612-1. The drive controller 612-1 may include an interface conversion circuit and a timing control circuit. The drive controller 612-1 receives image signals from the main processor 611, converts the data format of the image signals to an interface specification suitable for the display module 640, and outputs the image data. The drive controller 612-1 can output various control signals required for driving the display module 640. The configuration of the drive controller 612-1 is similar to... Figure 1The drive controller 100 shown is substantially similar, so its specific description will be omitted.

[0152] The auxiliary processor 612 may also include a data conversion circuit 612-2, a gamma correction circuit 612-3, a rendering circuit 612-4, etc. The data conversion circuit 612-2 receives image data from the drive controller 612-1 and compensates the image data so that the image is displayed with the desired brightness according to the characteristics of the electronic device 601 or user settings, or converts the image data to reduce power consumption or compensate for image retention. The gamma correction circuit 612-3 can convert image data or gamma reference voltage, etc., so that the image displayed on the electronic device 601 has the desired gamma characteristics. The rendering circuit 612-4 receives image data from the drive controller 612-1 and renders the image data by taking into account the pixel arrangement of the display panel 641 applied to the electronic device 601. At least one of the data conversion circuit 612-2, gamma correction circuit 612-3, and rendering circuit 612-4 can be integrated into another component (e.g., the main processor 611 or the drive controller 612-1). At least one of the data conversion circuit 612-2, the gamma correction circuit 612-3, and the rendering circuit 612-4 may also be integrated into the data driver 643 described later.

[0153] The memory 620 may store various types of data used by at least one component of the electronic device 601 (e.g., processor 610 or sensor module 661) and input or output data for commands related to said various types of data. The memory 620 may include at least one of volatile memory 621 and non-volatile memory 122.

[0154] The input module 630 can receive commands or data from outside the electronic device 601 (e.g., from a user or an external electronic device 602) that will be used by the components of the electronic device 601 (e.g., processor 610, sensor module 661, or voice output module 663).

[0155] Input module 630 may include a first input module 631 for receiving commands or data from a user and a second input module 632 for receiving commands or data from an external electronic device 602. The first input module 631 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 632 may support a specified protocol enabling wired or wireless connection to the external electronic device 602. According to one embodiment, the second input module 632 may include a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface. The second input module 632 may include a connector enabling physical connection to the external electronic device 602, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0156] Display module 640 provides visual information to the user. Display module 640 may include display panel 641, scan driver 642, and data driver 643. Display module 640 may also include a window, base, and support for protecting display panel 641. Display module 640 may also include a light-emitting driver and a voltage generator, etc. The voltage generator can output various voltages required for driving display panel 641 (e.g., first driving voltage ELVDD and second driving voltage ELVSS, see reference). Figure 1 The configuration of the display panel 641, scan driver 642, data driver 643, and voltage generator is similar to... Figure 1 The display panel DP, scan drive circuit 300, data drive circuit 200 and voltage generator 400 shown are substantially similar, so their specific descriptions will be omitted.

[0157] Power module 650 supplies power to the components of electronic device 601. Power module 650 may include a battery that charges to a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 650 may include a power management integrated circuit (PMIC). The PMIC provides optimized power to each of the modules described above and later. Power module 650 may include a wireless power transceiver electrically connected to the battery. The wireless power transceiver may include multiple antenna radiators in the form of coils.

[0158] The electronic device 601 may also include a built-in module 660 and an external module 670. The built-in module 660 may include a sensor module 661, an antenna module 662, and a sound output module 663. The external module 670 may include a camera module 671, an optical module 672, and a communication module 673.

[0159] Sensor module 661 can sense input via the user's body or via a pen in the first input module 631, and can generate an electrical signal or data value corresponding to the input. Sensor module 661 may include at least one of fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3.

[0160] The fingerprint sensor 661-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 661-1 may include one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0161] Input sensor 661-2 can generate data values ​​corresponding to coordinate information of input via the user's body or via a pen. Input sensor 661-2 generates data values ​​from the amount of capacitance change caused by the input. Input sensor 661-2 can sense input via a passive pen, or can transmit and receive data with an active pen.

[0162] The input sensor 661-2 can also measure biosignals such as blood pressure, water content, or body fat. For example, if a user places a part of their body in contact with the sensor layer or sensing panel and does not move it for a predetermined time, the input sensor 661-2 can sense the biosignal based on the change in the electric field caused by the part of the body and output the information desired by the user to the display module 640.

[0163] The digitizer 661-3 can generate data values ​​corresponding to the coordinate information input by a pen. The digitizer 661-3 generates data values ​​from the electromagnetic changes caused by the input. The digitizer 661-3 can sense input via a passive pen, or it can transmit and receive data with an active pen.

[0164] At least one of the fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3 can also be implemented as a sensor layer formed on the display panel 641 by a continuous process. The fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3 can be arranged on the upper side of the display panel 641, or one of the fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3 (e.g., digitizer 661-3) can be arranged on the lower side of the display panel 641.

[0165] At least two of the fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3 can be formed into a single integrated sensing panel using the same process. When integrated into a single sensing panel, the sensing panel can be positioned between the display panel 641 and a window positioned above the display panel 641. According to one embodiment, the sensing panel can also be positioned on the window; the position of the sensing panel is not particularly limited.

[0166] At least one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 can be integrated into the display panel 641. That is, at least one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 641.

[0167] Furthermore, sensor module 661 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 601. Sensor module 661 may also include, for example, gesture sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biosensors, temperature sensors, humidity sensors, or illuminance sensors.

[0168] Antenna module 662 may include one or more antennas for transmitting or receiving signals or power to or from an external source. According to one embodiment, communication module 673 may transmit or receive signals from external electronic device 602 via an antenna suitable for a communication method. The antenna pattern of antenna module 662 may also be integrated with a component of display module 640 (e.g., display panel 641) or input sensors 661-2, etc.

[0169] The sound output module 663 is a device for outputting sound signals to the outside of the electronic device 601. For example, it may include a speaker for general purposes such as multimedia playback or recording playback and a receiver specifically for telephone reception. According to one embodiment, the receiver may be integrally formed with or separate from the speaker. The sound output pattern of the sound output module 663 may also be integrated with the display module 640.

[0170] Camera module 671 can capture still images and moving images. According to one embodiment, camera module 671 may include one or more lenses, image sensors, or image signal processors. Camera module 671 may also include an infrared camera capable of measuring the presence of a user, the user's position, the user's line of sight, etc.

[0171] The optical module 672 can provide light. The optical module 672 may include a light-emitting diode or a xenon lamp. The optical module 672 can operate in conjunction with the camera module 671 or operate independently.

[0172] Communication module 673 can support the establishment of wired or wireless communication channels between electronic device 601 and external electronic device 602, and the execution of communication through the established communication channels. Communication module 673 may include one or all of the following: wireless communication modules (such as cellular communication modules, short-range wireless communication modules, or Global Navigation Satellite System (GNSS) communication modules) and wired communication modules (such as local area network (LAN) communication modules or power line communication modules). Communication module 673 can communicate with external electronic device 602 through short-range communication networks (such as Bluetooth, WiFi Direct, or Infrared Data Association (IrDA)) or long-range communication networks (such as cellular networks, the Internet, or computer networks (e.g., LAN or WAN)). The various types of communication modules 673 described above can be implemented as a single chip or as separate, independent chips.

[0173] The input module 630, sensor module 661, camera module 671, etc. can be linked with the processor 610 to control the operation of the display module 640.

[0174] The processor 610 outputs commands or data to the display module 640, sound output module 663, camera module 671, or optical module 672 based on the input data received from the input module 630. For example, the processor 610 can generate image data corresponding to input data applied via a mouse or active pen and output it to the display module 640, or it can generate command data corresponding to input data and output it to the camera module 671 or optical module 672. If the processor 610 does not receive input data from the input module 630 for a predetermined period of time, it can switch the operating mode of the electronic device 601 to a low-power mode or sleep mode to reduce the power consumption of the electronic device 601.

[0175] The processor 610 outputs commands or data to the display module 640, the sound output module 663, the camera module 671, or the optical module 672 based on the sensing data received from the sensor module 661. For example, the processor 610 can compare the input data obtained by the fingerprint sensor 661-1 with the authentication data stored in the memory 620, and then run the application based on the comparison result. The processor 610 can run commands or output corresponding image data to the display module 640 based on the sensing data sensed by the input sensor 661-2 or the digitizer 661-3. If the sensor module 661 includes a temperature sensor, the processor 610 can receive temperature data about the measured temperature from the sensor module 661, and can also perform brightness correction, etc., on the image data based on the temperature data.

[0176] The processor 610 can receive measurement data from the camera module 671 regarding the presence of a user, the user's position, and the user's gaze. The processor 610 can also perform brightness correction on the image data based on the measurement data. For example, the processor 610, which determines the presence of a user based on input from the camera module 671, can output image data with brightness corrected by the data conversion circuit 612-2 or the gamma correction circuit 612-3 to the display module 640.

[0177] Some of the constituent elements can be connected to each other and exchange signals (e.g., commands or data) through peripheral device communication methods (e.g., bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industry processor interface (MIPI), or ultra-path interconnect (UPI) links). The processor 610 can communicate with the display module 640 through an agreed-upon interface, for example, using one of the aforementioned communication methods, but not limited to those methods.

[0178] The electronic device 601 according to various embodiments disclosed in this document can be of various forms. The electronic device 601 may include at least one of, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance. The electronic device 601 according to embodiments of this document is not limited to the devices described above.

[0179] The above description refers to preferred embodiments of the present invention. However, it will be understood by those skilled in the art or those with ordinary knowledge in the art that the present invention pertains to, that the present invention can be modified and altered in various ways without departing from the concept and technical scope of the present invention as set forth in the claims.

[0180] Therefore, the technical scope of this invention is not limited to the contents described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display device, comprising: Display panel, including pixels, The pixels include: Light-emitting elements, including an anode and a cathode; The first transistor is connected between the first power line and the second node and operates according to the potential of the first node; The second transistor is connected between the first node and the data line and has a gate electrode for receiving the first scan signal. A third transistor is connected between the second node and the reference voltage line and has a gate electrode for receiving the first scan signal; A fourth transistor, connected between the second node and the initialization voltage line, and having a gate electrode for receiving a second scan signal; and A storage capacitor is connected between the first node and the second node.

2. The display device according to claim 1, wherein, During the data writing interval, the first scan signal has an active level, and the second scan signal has an inactive level. During the initialization interval, the first scan signal has the deactivation level, and the second scan signal has the activation level. The data writing interval precedes the initialization interval.

3. The display device according to claim 2, wherein, During the data writing interval, The first node is subjected to a data voltage. The second node is initialized to the reference voltage applied through the reference voltage line.

4. The display device according to claim 2, wherein, During the initialization interval, The second node is initialized to the initialization voltage applied through the initialization voltage line. The gate-source voltage of the first transistor in the initialization interval is the same as the gate-source voltage of the first transistor in the data writing interval.

5. The display device according to claim 2, wherein, The cathode of the light-emitting element is connected to a second power supply line to which a second driving voltage is applied. A reference voltage is applied to the reference voltage line. The reference voltage has a voltage level higher than the second driving voltage.

6. The display device according to claim 5, wherein, An initialization voltage is applied to the initialization voltage line. The initialization voltage has a voltage level that is lower than or equal to the second driving voltage.

7. The display device according to claim 2, wherein, The pixels also include: A first light-emitting control transistor is connected between the second node and the anode of the light-emitting element, and has a gate electrode for receiving a first light-emitting control signal.

8. The display device according to claim 7, wherein, The first emission control signal has the deactivation level during the deactivation interval and the activation level during the activation interval. The inactivation interval overlaps with the data writing interval. The initialization interval includes a first initialization interval that overlaps with the deactivation interval and a second initialization interval that overlaps with the activation interval.

9. The display device according to claim 8, wherein, During the data writing interval, The first node is subjected to a data voltage. The second node is initialized to the reference voltage applied through the reference voltage line.

10. The display device according to claim 8, wherein, During the initialization interval, The second node is initialized to the initialization voltage applied through the initialization voltage line. The gate-source voltage of the first transistor in the initialization interval is the same as the gate-source voltage of the first transistor in the data writing interval.

11. The display device according to claim 7, wherein, The pixels also include: A second light-emitting control transistor is connected between the first power line and the first transistor, and has a gate electrode for receiving a second light-emitting control signal; and The capacitor is held in place between the second node and the first power line.

12. The display device according to claim 2, wherein, The display panel displays an image during multiple drive frames, at least one of which includes a write frame and at least one hold frame. The write frame includes the data write interval and the initialization interval. The hold frame does not include the data write interval, but includes the initialization interval.

13. The display device according to claim 1, wherein, Each of the first to the fourth transistors comprises an oxide semiconductor.

14. A display device, comprising: Display panel, including pixels, The pixels include: Light-emitting elements, including an anode and a cathode; The first transistor is connected between the first power line and the second node and operates according to the potential of the first node; The second transistor is connected between the first node and the data line and has a gate electrode for receiving the first scan signal. A third transistor is connected between the second node and the reference voltage line and has a gate electrode for receiving the first scan signal; A light-emitting control transistor is connected between the second node and the anode of the light-emitting element, and has a gate electrode for receiving light-emitting control signals; A fourth transistor, connected between the anode of the light-emitting element and the initialization voltage line, and having a gate electrode for receiving a second scan signal; and A storage capacitor is connected between the first node and the second node.

15. The display device according to claim 14, wherein, During the data writing interval, the first scan signal has an active level, and the second scan signal has an inactive level. During the initialization interval, the first scan signal has the deactivation level, and the second scan signal has the activation level. The data writing interval precedes the initialization interval.

16. The display device according to claim 15, wherein, The light emission control signal has the deactivation level during the deactivation interval and the activation level during the activation interval. The inactivation interval overlaps with the data writing interval but does not overlap with the initialization interval.

17. The display device according to claim 16, wherein, During the data writing interval, The first node is subjected to a data voltage. The second node is initialized to the reference voltage applied through the reference voltage line.

18. The display device according to claim 16, wherein, During the initialization interval, The second node is initialized to the initialization voltage applied through the initialization voltage line. The gate-source voltage of the first transistor in the initialization interval is the same as the gate-source voltage of the first transistor in the data writing interval.

19. The display device according to claim 15, wherein, The display panel displays images during multiple driving frames, at least one of which includes a write frame and at least one hold frame. The write frame includes the data write interval and the initialization interval. The hold frame does not include the data write interval, but includes the initialization interval.

20. An electronic device comprising: Display module, including pixels; as well as The processor drives the display module. The display module is a display device according to any one of claims 1 to 19.

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