Shift register and driving method thereof, gate driving circuit, and display device

Abstract

A shift register and a driving method thereof, a gate driving circuit, and a display device. The shift register includes: an input circuit configured to input an input voltage to a first node under the control of a first clock signal; a first control circuit configured to output a first control signal to a first output node under the control of the first clock signal, the voltage of the first node, and a second clock signal; a second control circuit configured to output a second control signal to a second output node under the control of the voltage of the first node; and an output circuit configured to write a first voltage signal or a second voltage signal to a first output terminal as a first output signal under the control of the first control signal and the second control signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] With the rapid development of display technology, display panels are increasingly developing towards high integration and low cost. The gate-driver on array (GOA) technology is to directly integrate the gate drive circuit on the array substrate of the display device through a photolithography process. The GOA circuit usually includes a plurality of cascaded shift registers, each of which corresponds to a gate line corresponding to a row of pixels (for example, each shift register provides a scan drive signal to the gate line connected to a row of pixels) to achieve scan drive of the display panel. GOA technology can save space in the bonding area and fan-out area of ​​the gate integrated circuit (IC), thereby achieving a narrow frame of the display panel, while reducing product costs and improving product yields. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a shift register, including: an input circuit, a first control circuit, a second control circuit and an output circuit, wherein the input circuit is electrically connected to an input voltage terminal, a first clock signal terminal and a first node, respectively, and is configured to input an input voltage provided by the input voltage terminal to the first node under the control of a first clock signal provided by the first clock signal terminal; the first control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first node and a first output node, respectively, and is configured to output a first control signal to the first output node under the control of the first clock signal, the voltage of the first node and the second clock signal provided by the second clock signal terminal; the second control circuit is electrically connected to the first node, the second clock signal terminal and the second output node, respectively, and is configured to output a second control signal to the second output node under the control of the voltage of the first node; the output circuit is electrically connected to the first voltage terminal, the second voltage terminal, the first output node, the second output node and the first output terminal, respectively, and is configured to write the first voltage signal provided by the first voltage terminal or the second voltage signal provided by the second voltage terminal into the first output terminal as the first output signal under the control of the first control signal and the second control signal.

[0004] For example, in the shift register provided in at least one embodiment of the present disclosure, the first control circuit is configured to control the output circuit to output the first voltage signal in the first stage; the second control circuit is configured to control the output circuit to output the second voltage signal in the second stage, and the first output signal includes the first voltage signal in the first stage and the second voltage signal in the second stage.

[0005] For example, in the shift register provided in at least one embodiment of the present disclosure, the output circuit is further configured to, under the control of the first control signal and the second control signal, write a third voltage signal to the first output terminal in the second stage, wherein the first output signal also includes a third voltage signal, and an absolute value of a voltage of the third voltage signal is smaller than an absolute value of a voltage of the second voltage signal.

[0006] For example, in the shift register provided in at least one embodiment of the present disclosure, the first control circuit includes a first control input sub-circuit, which is electrically connected to the first clock signal terminal and the second node, respectively, and is configured to write a third control signal to the second node under the control of the first clock signal.

[0007] For example, in the shift register provided in at least one embodiment of the present disclosure, the first control circuit is also electrically connected to the first voltage terminal and the input circuit, and the second control input sub-circuit is electrically connected to the input circuit, the second clock signal terminal, the first voltage terminal and the second node, respectively, and is configured to write the first voltage signal to the second node under the control of the input voltage and the second clock signal.

[0008] For example, in the shift register provided in at least one embodiment of the present disclosure, the first control circuit includes a first bootstrap subcircuit, a first control output subcircuit and a second control output subcircuit, the first bootstrap subcircuit is electrically connected to the second node, the third node and the second clock signal terminal, respectively, and is configured to write the first intermediate signal to the third node under the control of the voltage of the second node; the first control output subcircuit is electrically connected to the second clock signal terminal, the third node and the first output node, respectively, and is configured to write the second intermediate signal determined based on the first intermediate signal to the first output node under the control of the second clock signal; the second control output subcircuit is electrically connected to the first node, the first voltage terminal and the first output node, respectively, and is configured to write the first voltage signal to the first output node under the control of the voltage of the first node, wherein the first control signal includes the second intermediate signal and the first voltage signal.

[0009] For example, in the shift register provided in at least one embodiment of the present disclosure, the input circuit includes an input terminal connected to the input voltage terminal and an output terminal connected to the first node, and the second control input sub-circuit is electrically connected to the output terminal of the input circuit, or the second control input sub-circuit is electrically connected to the input terminal of the input circuit.

[0010] For example, in the shift register provided in at least one embodiment of the present disclosure, the first control input subcircuit includes a first pull-down transistor, a first electrode of the first pull-down transistor is electrically connected to the first clock signal terminal, a second electrode of the first pull-down transistor is electrically connected to the second node, and a gate of the first pull-down transistor is electrically connected to the first clock signal terminal.

[0011] For example, in the shift register provided in at least one embodiment of the present disclosure, the second control input subcircuit includes a first pull-up transistor and a second pull-up transistor, the first electrode of the first pull-up transistor is electrically connected to the second electrode of the second pull-up transistor, the second electrode of the first pull-up transistor is electrically connected to the second node, the gate of the first pull-up transistor is electrically connected to the second clock signal terminal, the gate of the second pull-up transistor is electrically connected to the input terminal of the input circuit or the output terminal of the input circuit, and the first electrode of the second pull-up transistor is electrically connected to the first voltage terminal.

[0012] For example, in the shift register provided in at least one embodiment of the present disclosure, the first bootstrap sub-circuit includes a first capacitor and a first bootstrap transistor, the gate of the first bootstrap transistor is electrically connected to the second node and the first end of the first capacitor, the second electrode of the first bootstrap transistor is electrically connected to the second end of the first capacitor and the third node, and the first electrode of the first bootstrap transistor is electrically connected to the second clock signal end; the first control output sub-circuit includes a first control output transistor, the gate of the first control output transistor is electrically connected to the second clock signal end, the first electrode of the first control output transistor is electrically connected to the third node, and the second electrode of the first control output transistor is electrically connected to the first output node; the second control output sub-circuit includes a second control output transistor, the gate of the second control output transistor is electrically connected to the first node, the first electrode of the second control output transistor is electrically connected to the first voltage end, and the second electrode of the second control output transistor is electrically connected to the first output node.

[0013] For example, in the shift register provided in at least one embodiment of the present disclosure, the first control circuit also includes a holding subcircuit, which is electrically connected to the first voltage terminal, the first node and the first output node, respectively, and is configured to maintain the level of the first node in the first stage.

[0014] For example, in the shift register provided in at least one embodiment of the present disclosure, the holding subcircuit includes a holding transistor, a first electrode of the holding transistor is electrically connected to the first voltage terminal, a second electrode of the holding transistor is electrically connected to the first node, and a gate of the holding transistor is electrically connected to the first output node.

[0015] For example, in the shift register provided in at least one embodiment of the present disclosure, the first control circuit is also electrically connected to the second voltage terminal, the first control circuit also includes a first isolation sub-circuit, the input terminal of the first isolation sub-circuit is electrically connected to the second node, the output terminal of the first isolation sub-circuit is electrically connected to the first bootstrap sub-circuit, and the control terminal of the first isolation sub-circuit is electrically connected to the second voltage terminal.

[0016] For example, in the shift register provided in at least one embodiment of the present disclosure, the first isolation sub-circuit includes a first isolation transistor, a first electrode of the first isolation transistor is electrically connected to the second node, a second electrode of the first isolation transistor is electrically connected to the first bootstrap sub-circuit, and a gate of the first isolation transistor is electrically connected to the second voltage terminal.

[0017] For example, in the shift register provided in at least one embodiment of the present disclosure, the first control circuit further includes a storage subcircuit, which is electrically connected to the first voltage terminal and the first output node, respectively, and is configured to store the voltage of the first output node.

[0018] For example, in the shift register provided in at least one embodiment of the present disclosure, the storage subcircuit includes a storage capacitor, a first end of the storage capacitor is electrically connected to the first voltage end, and a second end of the storage capacitor is electrically connected to the first output node.

[0019] For example, in the shift register provided in at least one embodiment of the present disclosure, the second control circuit includes a second bootstrap sub-circuit, and the second bootstrap sub-circuit is electrically connected to the first node, the second clock signal terminal and the second output node respectively.

[0020] For example, in the shift register provided in at least one embodiment of the present disclosure, the second bootstrap sub-circuit includes a second capacitor and a second bootstrap transistor, the first electrode of the second bootstrap transistor is electrically connected to the second clock signal terminal, the first end of the second capacitor is electrically connected to the gate of the second bootstrap transistor and the second output node, and the second end of the second capacitor is electrically connected to the second electrode of the second bootstrap transistor.

[0021] For example, in the shift register provided in at least one embodiment of the present disclosure, the second control circuit also includes a second isolation sub-circuit, the input end of the second isolation sub-circuit is electrically connected to the first node, the output end of the second isolation sub-circuit is electrically connected to the second output node, and the control end of the second isolation sub-circuit is electrically connected to the second voltage end.

[0022] For example, in the shift register provided in at least one embodiment of the present disclosure, the second isolation sub-circuit includes a second isolation transistor, a first electrode of the second isolation transistor is electrically connected to the first node, a second electrode of the second isolation transistor is electrically connected to the second output node, and a gate of the second isolation transistor is electrically connected to the second voltage terminal.

[0023] For example, in the shift register provided in at least one embodiment of the present disclosure, the output circuit includes a first output sub-circuit and a second output sub-circuit, the first output sub-circuit is electrically connected to the first output node, the first voltage terminal and the first output terminal, respectively, and is configured to write the first voltage signal to the first output terminal in the first stage under the control of the first control signal; the second output sub-circuit is electrically connected to the second output node, the second voltage terminal and the first output terminal, respectively, and is configured to write the second voltage signal to the first output terminal in the second stage under the control of the second control signal.

[0024] For example, in the shift register provided in at least one embodiment of the present disclosure, the first output sub-circuit includes a first output transistor, the gate of the first output transistor is electrically connected to the first output node, the first electrode of the first output transistor is electrically connected to the first voltage terminal, and the second electrode of the first output transistor is electrically connected to the first output terminal; the second output sub-circuit includes a second output transistor, the gate of the second output transistor is electrically connected to the second output node, the first electrode of the second output transistor is electrically connected to the second voltage terminal, and the second electrode of the second output transistor is electrically connected to the first output terminal.

[0025] For example, in the shift register provided in at least one embodiment of the present disclosure, the shift register also includes an output inversion circuit, which is electrically connected to the first output node, the first voltage terminal, the second voltage terminal, the first output terminal and the second output terminal, respectively, and is configured to invert the first output signal to obtain a second output signal, and output the second output signal to the second output terminal.

[0026] For example, in the shift register provided in at least one embodiment of the present disclosure, the output inversion circuit includes a first output inversion sub-circuit, a second output inversion sub-circuit and an output inversion control sub-circuit, the output inversion control sub-circuit is electrically connected to the first voltage terminal, the first output node, the second voltage terminal and the fourth node, respectively, and is configured to output a fourth control signal to the fourth node under the control of the first control signal and the first output signal; the first output inversion sub-circuit is electrically connected to the first voltage terminal, the first output terminal and the second output terminal, respectively, and is configured to write the first voltage signal to the second output terminal in the second stage under the control of the first output signal; the second output inversion sub-circuit is electrically connected to the second voltage terminal, the fourth node and the second output terminal, respectively, and is configured to write the second voltage signal to the second output terminal in the first stage under the control of the fourth control signal, and the second output signal includes the second voltage signal located in the first stage and the first voltage signal located in the second stage.

[0027] For example, in the shift register provided in at least one embodiment of the present disclosure, the output inversion control subcircuit includes a pull-up subcircuit, a pull-down subcircuit and a third bootstrap subcircuit, the pull-up subcircuit is electrically connected to the first voltage terminal, the first output terminal and the fourth node, respectively, and is configured to write the first voltage signal to the fourth node under the control of the first output signal; the pull-down subcircuit is electrically connected to the first output node, the second voltage terminal and the fourth node, respectively, and is configured to write a third intermediate signal determined based on the second voltage signal to the fourth node under the control of the first control signal; the third bootstrap subcircuit is electrically connected to the fourth node and the first clock signal terminal, respectively, and is configured to write a fourth intermediate signal determined based on the third intermediate signal and the first clock signal to the fourth node under the control of the voltage of the fourth node, wherein the fourth control signal includes the first voltage signal, the third intermediate signal and the fourth intermediate signal.

[0028] For example, in the shift register provided in at least one embodiment of the present disclosure, the first output inversion sub-circuit includes a first output inversion transistor, and the second output inversion sub-circuit includes a second output inversion transistor, the gate of the first output inversion transistor is electrically connected to the first output terminal, the first pole of the first output inversion transistor is electrically connected to the first voltage terminal, and the second pole of the first output inversion transistor is electrically connected to the second output terminal; the gate of the second output inversion transistor is electrically connected to the fourth node, the first pole of the second output inversion transistor is electrically connected to the second voltage terminal, and the second pole of the second output inversion transistor is electrically connected to the second output terminal.

[0029] For example, in the shift register provided in at least one embodiment of the present disclosure, the pull-up sub-circuit includes a third pull-up transistor, the gate of the third pull-up transistor is electrically connected to the first output terminal, the first electrode of the third pull-up transistor is electrically connected to the first voltage terminal, and the second electrode of the third pull-up transistor is electrically connected to the fourth node; the pull-down sub-circuit includes a second pull-down transistor, the gate of the second pull-down transistor is electrically connected to the first output node, the first electrode of the second pull-down transistor is electrically connected to the second voltage terminal, and the second electrode of the second pull-down transistor is electrically connected to the fourth node; the third bootstrap sub-circuit includes a third capacitor and a third bootstrap transistor, the first end of the third capacitor and the gate of the third bootstrap transistor are both electrically connected to the fourth node, the second electrode of the third bootstrap transistor is electrically connected to the second end of the third capacitor, and the first electrode of the third bootstrap transistor is electrically connected to the first clock signal terminal.

[0030] For example, in the shift register provided in at least one embodiment of the present disclosure, the input circuit includes an input transistor, a first electrode of the input transistor is electrically connected to the input voltage terminal, a second electrode of the input transistor is electrically connected to the first node, and a gate of the input transistor is electrically connected to the first clock signal terminal.

[0031] At least one embodiment of the present disclosure further provides a gate driving circuit, comprising the shift register described in any embodiment of the present disclosure.

[0032] For example, in the gate driving circuit provided in at least one embodiment of the present disclosure, the gate driving circuit includes a plurality of cascaded shift registers, wherein, except for the first-stage shift register, the first output terminal of the M-th-stage shift register serves as the input voltage terminal connected to the M+1-th-stage shift register, wherein M is a positive integer and M is greater than 1.

[0033] For example, the gate driving circuit provided in at least one embodiment of the present disclosure also includes a signal generating circuit, wherein the signal generating circuit is configured to generate a first signal and a second signal, the first signal is applied to a first clock signal terminal connected to the 2N-1th stage shift register and a second clock signal terminal connected to the 2Nth stage shift register; the second signal is applied to the second clock signal terminal connected to the 2N-1th stage shift register and the first clock signal terminal connected to the 2Nth stage shift register; wherein N is a positive integer, and N is greater than or equal to 1.

[0034] At least one embodiment of the present disclosure further provides a display device, comprising the gate driving circuit as described in any embodiment of the present disclosure.

[0035] At least one embodiment of the present disclosure further provides a driving method of a shift register, which is used to drive the shift register as described in any embodiment of the present disclosure, wherein the output circuit outputs the first voltage signal in a first stage, and outputs the second voltage signal in a second stage, and the second stage includes an input stage and a stable stage, and the driving method includes: in the input stage, inputting the input voltage to the first node; in the first stage, under the control of the first control signal, outputting the first voltage signal to the first output terminal; in the stable stage, under the control of the second control signal, outputting the second voltage signal to the first output terminal.

[0036] For example, in the driving method provided in at least one embodiment of the present disclosure, the second stage also includes a buffer stage, and the driving method also includes: in the buffer stage, under the control of the second control signal, outputting a third voltage signal to the first output terminal, wherein the first output signal also includes the third voltage signal, and the absolute value of the voltage of the third voltage signal is smaller than the absolute value of the voltage of the second voltage signal.

[0037] For example, in the driving method provided in at least one embodiment of the present disclosure, when the first control circuit is electrically connected to the input voltage terminal, the pulse width of the input voltage at the first level is greater than the period of the first clock signal and the second clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0039] Figure 1A It is a structural schematic diagram of a shift register circuit;

[0040] Figure 1B for Figure 1A The driving timing diagram corresponding to the shift register circuit shown;

[0041] Figure 2A A schematic block diagram of a shift register provided for at least one embodiment of the present disclosure;

[0042] Figure 2B A schematic block diagram of another shift register provided for at least one embodiment of the present disclosure;

[0043] Figure 3A A schematic diagram of the structure of a shift register provided by at least one embodiment of the present disclosure;

[0044] Figure 3BA structural diagram of another shift register provided for at least one embodiment of the present disclosure

[0045] Figure 3C A schematic diagram of the structure of another shift register provided in at least one embodiment of the present disclosure;

[0046] Figure 3D A schematic diagram of the structure of another shift register provided in at least one embodiment of the present disclosure;

[0047] Figure 4A is a driving timing diagram of a shift register provided by at least one embodiment of the present disclosure;

[0048] Figure 4B is a driving timing diagram of another shift register provided by at least one embodiment of the present disclosure;

[0049] Figure 5A A schematic block diagram of another shift register provided for at least one embodiment of the present disclosure;

[0050] Figure 5B A schematic diagram of the structure of another shift register provided in at least one embodiment of the present disclosure;

[0051] Figure 5C is a driving timing diagram of another shift register provided by at least one embodiment of the present disclosure;

[0052] Figure 5D A schematic block diagram of another shift register provided for at least one embodiment of the present disclosure;

[0053] Figure 6 A schematic block diagram of a gate driving circuit provided in at least one embodiment of the present disclosure;

[0054] Fig. 7A A schematic diagram of the structure of a gate driving circuit provided by at least one embodiment of the present disclosure;

[0055] Figure 7B A schematic diagram of the structure of another gate driving circuit provided by at least one embodiment of the present disclosure;

[0056] Figure 8 A schematic diagram of a display device provided by at least one embodiment of the present disclosure;

[0057] Fig. 9 At least one embodiment of the present disclosure provides a flowchart of a driving method. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0059] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components.

[0060] The existing shift register circuit integrated on the display panel can generally realize the following functions: realize the shift output of high-level pulse signals by using N-type transistors, and realize the shift output of low-level pulse signals by using P-type transistors.

[0061] Figure 1A It is a structural diagram of a shift register circuit constructed based on P-type transistors. Figure 1B for Figure 1A The driving timing diagram corresponding to the shift register circuit shown.

[0062] like Figure 1A and Figure 1B As shown, the shift register circuit can output a low level signal. Figure 1BIn the stage t1 shown, the first signal terminal GCK is a low-level signal, the second signal terminal GCB is a high-level signal, the transistor T1 is turned on, and the input signal terminal GSTV inputs a low-level signal through the transistor T1 and stores it in the capacitor C2, thereby turning on the transistor T7. In the stage t2, the second signal terminal GCB is a low-level signal, the first signal terminal GCK is a high-level signal, and the low-level signal of the second signal terminal GCB (for example, it can be equal to the low-level signal VL) is output to the output terminal Output through the transistor T7 in the turned-on state, that is, the output terminal Output outputs a low-level signal. In the time period when the low-level signal does not need to be output, the signal at the input signal terminal GSTV is at a high level, the first signal terminal GCK turns on the transistor T3 every half cycle, and the low-level signal VL is written into the capacitor C1 through the transistor T3, so that the transistors T6 and T8 remain in a normally open state. When the transistor T5 is turned on under the control of the signal provided by the second signal terminal GCB, the high-level signal VGH is written into the capacitor C2 through the transistors T6 and T5, thereby controlling the transistor T7 to be turned off. At this time, the high-level signal VGH is output to the output terminal Output through the transistor T8, that is, the output terminal Output outputs the high-level signal VGH.

[0063] At present, in organic light-emitting diode display panels (OLED), P-type transistor technology is generally used to implement all backplane circuits, and gate drive circuits (such as GOA circuits) often need to output high-level pulse signals. In other words, P-type transistors are needed to construct shift register circuits that output high-level pulse signals. However, the key difficulty is that the starting signal at the input signal end is a high level, and this high level cannot be Figure 1A The shift register in the circuit makes transistor T7 turned on in advance, and the transistors used to build the circuit are all P-type transistors, which require a low level to turn on. This makes it impossible to use existing ideas to realize the shift function of the level opposite to the transistor turn-on level.

[0064] At least one embodiment of the present disclosure provides a shift register and a driving method thereof, a gate driving circuit, and a display device. The shift register includes an input circuit, a first control circuit, a second control circuit and an output circuit, wherein the input circuit is electrically connected to an input voltage terminal, a first clock signal terminal and a first node, respectively, and is configured to input an input voltage provided by the input voltage terminal to the first node under the control of a first clock signal provided by the first clock signal terminal; the first control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first node and the first output node, respectively, and is configured to output a first control signal to the first output node under the control of the first clock signal, the voltage of the first node and the second clock signal provided by the second clock signal terminal; the second control circuit is electrically connected to the first node, the second clock signal terminal and the second output node, respectively, and is configured to output a second control signal to the second output node under the control of the voltage of the first node; the output circuit is electrically connected to the first voltage terminal, the second voltage terminal, the first output node, the second output node and the first output terminal, respectively, and is configured to write a first voltage signal provided by the first voltage terminal or a second voltage signal provided by the second voltage terminal into the first output terminal as a first output signal under the control of the first control signal and the second control signal.

[0065] The shift register controls the output circuit to output a level opposite to the turn-on level of the transistor through the first control circuit and the second control circuit. For example, when the transistor is a P-type transistor, a high-level signal is output. In addition, the shift register circuit can realize the P-type transistor outputting a low-level signal without threshold loss, thereby improving the display quality of the display panel. On the other hand, the shift register has a simple structure and a low production cost.

[0066] In the embodiments of the present disclosure, a transistor refers to a component including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel, and the source electrode. It should be noted that in the present disclosure, the channel refers to the portion of the active layer corresponding to the positive projection of the gate of the transistor on the active layer, that is, the area where the current mainly flows.

[0067] It should be noted that the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole is the second pole, so the first pole and the second pole of all or part of the transistors in the embodiments of the present disclosure are interchangeable as needed. For example, the first pole of the transistor described in the embodiments of the present disclosure may be the source, and the second pole may be the drain; or, the first pole of the transistor may be the drain, and the second pole may be the source. In addition, transistors may be divided into N-type and P-type transistors according to the characteristics of the transistor. When the transistor is a P-type transistor, the turn-on level is a low level, that is, the turn-on voltage is a low level voltage (for example, 0V, -5V or other values), and the turn-off level is a high level, that is, the turn-off voltage is a high level voltage (for example, 5V, 10V or other values); when the transistor is an N-type transistor, the turn-on level is a high level, that is, the turn-on voltage is a high level voltage (for example, 5V, 10V or other values), and the turn-off level is a low level, that is, the turn-off voltage is a low level voltage (for example, 0V, -5V or other values).

[0068] It should be noted that, since the P-type transistor (for example, a thin film transistor) has a threshold loss when transmitting a low-level signal, when a signal at a low level is transmitted from the first pole of the P-type transistor to the second pole of the P-type transistor, there is a voltage difference between the voltage of the second pole of the P-type transistor and the voltage of the first pole of the P-type transistor, and the voltage difference is the threshold voltage of the P-type transistor. Since there is no threshold loss when the P-type transistor transmits a high-level signal, when a signal at a high level is transmitted from the first pole of the P-type transistor to the second pole of the P-type transistor, there is no voltage difference between the voltage of the second pole of the P-type transistor and the voltage of the first pole of the P-type transistor. That is to say, in the present disclosure, after a low-level signal is "transmitted" through a P-type transistor, a threshold voltage loss will occur, and after a high-level signal is "transmitted" through a P-type transistor, the voltage remains unchanged.

[0069] Similarly, when the transistor is an N-type transistor, similarly, the N-type transistor has a threshold loss when transmitting a high-level signal, which will not be described in detail here.

[0070] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0071] Figure 2A A schematic block diagram of a shift register provided for at least one embodiment of the present disclosure.

[0072] The embodiment of the present disclosure provides a shift register. For example, Figure 2A As shown, the shift register includes an input circuit 100 , a first control circuit 200 , a second control circuit 300 and an output circuit 400 .

[0073] For example, Figure 2A As shown, the input circuit 100 is electrically connected to the input voltage terminal ESTV, the first clock signal terminal ECK and the first node n1 respectively, and is configured to receive the first clock signal V provided at the first clock signal terminal ECK. ECK Under the control of the first clock signal V ECK Under the control of , when the input circuit 100 is turned on, that is, when one end of the input circuit 100 connected to the input voltage terminal ESTV and the other end connected to the first node n1 are turned on, the input voltage Vin can be transmitted to the first node n1.

[0074] The first control circuit 200 is electrically connected to the first clock signal terminal ECK, the second clock signal terminal ECB, the first node n1 and the first output node OP1, and is configured to ECK , the voltage of the first node n1 and the second clock signal V provided by the second clock signal terminal ECB ECB Under the control of ctr1 To the first output node OP1, the first control signal V ctr1 The device is configured to realize conduction and cutoff between the first voltage terminal VGH and the first output terminal Eout.

[0075] The second control circuit 300 is electrically connected to the first node n1, the second clock signal terminal ECB and the second output node OP2, and is configured to output a second control signal V under the control of the voltage of the first node n1. ctr2 To the second output node OP2, the second control signal V ctr2 It is configured to realize conduction and cutoff between the second voltage terminal VGL and the first output terminal Eout.

[0076] The output circuit is electrically connected to the first voltage terminal VGH, the second voltage terminal VGL, the first output node OP1, the second output node OP2 and the first output terminal Eout, and is configured to ctr1 And the second control signal V ctr2 Under the control of , the first voltage signal VH provided by the first voltage terminal VGH or the second voltage signal VL provided by the second voltage terminal VGL is written into the first output terminal Eout as the first output signal Vout.

[0077] For example, the first control circuit 200 is configured to control the output circuit 400 to output the first voltage signal VH as the first output signal Vout in the first stage. For example, the second control circuit 300 is configured to control the output circuit 400 to output the second voltage signal VL as the first output signal Vout in the second stage. That is, the first output signal Vout includes the first voltage signal VH in the first stage and the second voltage signal VL in the second stage.

[0078] For example, Figure 2A As shown, the first control circuit 200 is also electrically connected to the first voltage terminal VGH and the input circuit 100. For example, the first control circuit 200 includes a first control input subcircuit 201, a second control input subcircuit 202, a first bootstrap subcircuit 203, a first control output subcircuit 204, a second control output subcircuit 205 and a holding subcircuit 206.

[0079] For example, the first control input sub-circuit 201 is electrically connected to the first clock signal terminal ECK and the second node n2, and is configured to ECK Under the control of the third control signal V ctr3 For example, when the first control input subcircuit 201 is turned on, that is, when one end of the first control input subcircuit 201 connected to the first signal terminal ECK and the other end of the first control input subcircuit 201 connected to the second node n2 are turned on, the first clock signal V ECK is used as the third control signal V ctr3 The second node n2 is written so that the voltage of the second node n2 is at a second level.

[0080] The second control input sub-circuit 202 is electrically connected to the input circuit 100, the second clock signal terminal ECB, the first voltage terminal VGH and the second node n2, and is configured to ECB Under the control of , the first voltage signal VH is written into the second node n2. For example, when the second control input subcircuit 202 is turned on, that is, when one end of the second control input subcircuit 202 connected to the first voltage terminal VGH and the other end of the second control input subcircuit 202 connected to the second node n2 are turned on, the first voltage signal VH is written into the second node n2, so that the voltage of the second node n2 is at the first level.

[0081] For example, the first level and the second level are different, for example, opposite to each other. In some examples, the first level is a high level and the second level is a low level. However, the present disclosure is not limited thereto. According to actual application requirements, the first level may be a low level and the second level may be a high level. In the description of the present disclosure, the first level is a high level and the second level is a low level as an example.

[0082] For example, the first voltage terminal VGH can be a high voltage terminal to output a first voltage signal VH having a first level, and the second voltage terminal VGL can be a low voltage terminal to output a second voltage signal VL having a second level. That is, the first voltage signal VH is a high level signal (e.g., 5V, 10V or other voltages), and the second voltage signal VL is a low level signal (e.g., 0V, -1V or other voltages). For example, in some embodiments, the second voltage terminal VGL can be grounded. For example, the first voltage signal VH and the second voltage signal VL are both DC signals. It should be noted that the low level signal and the high level signal are relative, and the voltage value of the low level signal is less than the voltage value of the high level signal. In different implementations, the voltage value of the high level signal may be different, and the voltage value of the low level signal may also be different.

[0083] It should be noted that the first control circuit 200 may not be connected to the first voltage terminal VGH, but connected to another voltage terminal provided, as long as the other voltage terminal provided outputs a high voltage signal. In addition, the high voltage signal output by the other voltage terminal provided and the high voltage signal output by the first voltage terminal VGH may be the same or different. It should be noted that the first control circuit 200 may not be connected to the first voltage terminal VGH, but connected to another voltage terminal provided, as long as the other voltage terminal provided outputs a high voltage signal. In addition, the high voltage signal output by the other voltage terminal provided and the high voltage signal output by the first voltage terminal VGH may be the same or different.

[0084] For example, the input circuit 100 includes an input terminal connected to the input voltage terminal ESTV and an output terminal connected to the first node n1, the second control input sub-circuit 202 can be electrically connected to the output terminal of the input circuit 100, that is, electrically connected to the first node n1, or the second control input sub-circuit 202 can be electrically connected to the input terminal of the input circuit 100, that is, electrically connected to the input voltage terminal ESVT.

[0085] The first bootstrap sub-circuit 203 is electrically connected to the second node n2, the third node n3 and the second clock signal terminal ECB respectively, and is configured to ctr3 Under the control of , the first intermediate signal is written into the third node n3.

[0086] For example, when the voltage of the second node n2 is at the first level, under the control of the voltage of the second node n2, the first bootstrap sub-circuit 203 is in a cut-off state, and the voltage of the third node n3 remains unchanged.

[0087] For example, when the voltage of the second node n2 is at the second level, that is, when the third control signal V ctr3When writing into the second node n2, under the control of the voltage of the second node n2, the first bootstrap sub-circuit 203 is in a conducting state, that is, when one end of the first bootstrap sub-circuit 203 connected to the second clock signal terminal ECB and the other end of the first bootstrap sub-circuit 203 connected to the third node n3 are turned on, the second clock signal V ECB is transmitted to the third node n3. When the second clock signal V ECB When a jump from the first level to the second level occurs, and the voltage of the third node n3 also jumps from the first level to the second level, the first bootstrap sub-circuit 203 generates a bootstrap effect, so that the level of the second node n2 changes with the change of the level of the third node n3, that is, the level of the second node n2 also jumps, and the level of the second node n2 is lower than the second level (for example, at this time, the level of the second node n2 is (2*first level-second level)), thereby, the second clock signal V ECB The first intermediate signal can be outputted by the first bootstrap sub-circuit 203 and written into the third node n3 as the first intermediate signal. That is, the first intermediate signal is the second clock signal V at the second level. ECB .

[0088] The first control output sub-circuit 204 is electrically connected to the second clock signal terminal ECB, the third node n3 and the first output node OP1 respectively, and is configured to ECB , writes the second intermediate signal Vmid2 determined based on the first intermediate signal to the first output node OP1. ECB When the first intermediate signal Vmid2 is turned on under the control of the first control output sub-circuit 204, that is, when one end connected to the third node n3 and the other end connected to the first output node OP1 are turned on, the second intermediate signal Vmid2 determined based on the first intermediate signal is written into the first output node OP1, and the second intermediate signal Vmid2 is also at the second level. For example, the absolute value of the voltage of the second intermediate signal Vmid2 is less than the absolute value of the voltage of the first intermediate signal, and the absolute value of the signal difference between the first intermediate signal and the second intermediate signal Vmid2 is equal to the absolute value of the threshold voltage of the transistor in the first control output sub-circuit 204 (for example, the first control output transistor T7 to be described later).

[0089] The second control output subcircuit 205 is electrically connected to the first node n1, the first voltage terminal VGH and the first output node OP1, respectively, and is configured to write the first voltage signal VH into the first output node OP1 under the control of the voltage of the first node n1. For example, when the second control output subcircuit 205 is turned on under the control of the voltage of the first node n1, that is, when one end of the second control output subcircuit 205 connected to the first voltage terminal VGH and the other end connected to the first output node OP1 are turned on, the first voltage signal VH is written into the first output node OP1.

[0090] For example, the first control signal includes a second intermediate signal Vmid2 and a first voltage signal VH. For example, in the first stage, the first control signal is the second intermediate signal Vmid2, that is, it is at the second level, and the output circuit 400, under the control of the second intermediate signal Vmid2, realizes the connection between the first voltage terminal VGH and the first output terminal Eout, so as to output the first voltage signal VH to the first output terminal Eout; in the second stage, the first control signal is the first voltage signal VH, that is, it is at the first level, and the output circuit 400, under the control of the first voltage signal VH, realizes the connection between the first voltage terminal VGH and the first output terminal Eout is disconnected, thereby avoiding outputting the first voltage signal VH to the first output terminal Eout in the second stage.

[0091] For example, the holding subcircuit 206 is electrically connected to the first voltage terminal VGH, the first node n1 and the first output node OP1, and is configured to maintain the level of the first node in the first stage. ctr2 is a first level signal, the second output sub-circuit 402 is at the second control signal V ctr2 At this time, the holding sub-circuit 206 is turned on under the control of the voltage of the first output node OP1, that is, one end of the holding sub-circuit 206 connected to the first voltage terminal VGH and the other end of the holding sub-circuit 206 connected to the first node n1 are turned on, and the first voltage signal VH is written into the first node n1 to control the voltage of the first node n1 to always be at the first level in the first stage, thereby maintaining the second control signal V ctr2 In the first stage, it is at the first level to avoid circuit fluctuations and maintain output stability.

[0092] For example, Figure 2A As shown, the second control circuit 300 includes a second bootstrap subcircuit 301, which is electrically connected to the first node n1, the second clock signal terminal ECB and the second output node n2, and is configured to control the voltage of the second output node OP2 under the control of the voltage of the first node n1. For example, due to the bootstrap effect of the second bootstrap subcircuit 301, the voltage of the second output node OP2 can be lower than the second clock signal VECB The voltage at the second level.

[0093] For example, the second control signal V ctr2 The first level signal, the second level signal and the second clock signal V at the second level are included. ECB The obtained third level signal. For example, the first level signal is an input voltage Vin at a first level, for example, the voltage value of the first level signal is the same as the voltage value of the first voltage signal VH, the voltage value of the first level signal is greater than the voltage value of the second level signal, the second level signal is obtained based on the input voltage Vin at a second level, for example, the voltage value of the input voltage Vin at the second level is the same as the voltage value of the second voltage signal VL, and the voltage absolute value of the second level signal is less than the voltage absolute value of the third level signal.

[0094] For example, Figure 2A As shown, the output circuit 400 includes a first output sub-circuit 401 and a second output sub-circuit 402 .

[0095] For example, the first output sub-circuit 401 is electrically connected to the first output node n1, the first voltage terminal VGH and the first output terminal Eout, and is configured to ctr1 Under the control of the first control signal V , the first voltage signal VH is written into the first output terminal Eout in the first stage. For example, in the first stage, the first output sub-circuit 401 writes the first voltage signal VH to the first output terminal Eout under the control of the first control signal V ctr1 , that is, one end of the first output sub-circuit 401 connected to the first voltage terminal VGH and the other end of the first output sub-circuit 401 connected to the first output terminal Eout are turned on, the first voltage signal VH is written into the first output terminal Eout, and at this time, the second output sub-circuit 402 is turned on under the second control signal V ctr2 cut off under control.

[0096] The second output sub-circuit 402 is electrically connected to the second output node OP2, the second voltage terminal VGL and the first output terminal Eou, and is configured to ctr2 , the second output sub-circuit 402 writes the second voltage signal VL to the first output terminal Eout in the second stage. ctr2 , that is, one end of the second output sub-circuit 402 connected to the second voltage terminal VGL and the other end of the second output sub-circuit 402 connected to the first output terminal Eout are turned on, and the second voltage signal VL is written into the first output terminal Eout. At this time, the first output sub-circuit 401 is turned on under the first control signal V ctr1 cut off under control.

[0097] For example, the first output signal also includes a third voltage signal, and the output circuit 400 is further configured to ctr1 And the second control signal V ctr2 Under the control of , in the second stage, the third voltage signal VL1 obtained based on the second voltage signal VL is written to the first output terminal Eout, for example, the absolute value of the voltage of the third voltage signal VL1 is less than the absolute value of the voltage of the second voltage signal VL. Since there is a threshold loss in the low-level signal output by the P-type transistor, the second output sub-circuit 402 may write the third voltage signal VL1 obtained based on the second voltage signal VL into the first output terminal Eout. The absolute value of the signal difference between the second voltage signal VL and the third voltage signal VL1 is equal to the absolute value of the threshold voltage of the transistor in the second output sub-circuit 402 (for example, the second output transistor T10 to be described later).

[0098] For example, the second control signal V ctr2 The voltage absolute value of the included third level signal is greater than the voltage absolute value of the second voltage signal VL, so that the second output sub-circuit 402 can output the second voltage signal VL without threshold voltage loss to the first output terminal Eout. In the second stage, the first output signal Vout includes the third voltage signal VL1 and the second voltage signal VL, and finally the first output signal Vout remains in the state of the second voltage signal VL.

[0099] Figure 2B A schematic block diagram of another shift register provided for at least one embodiment of the present disclosure.

[0100] like Figure 2B As shown, the shift register includes an input circuit 100, a first control circuit 200, a second control circuit 300 and an output circuit 400, and, compared to Figure 2A In the shift register shown in FIG. 1 , the first control circuit 200 of the shift register further includes a storage subcircuit 207 and a first isolation subcircuit 208 , and the second control circuit 200 further includes a second isolation subcircuit 302 . Figure 2B The remaining subcircuits of the shift register shown are similar to Figure 2A The shift registers shown are the same and the repeated parts are not repeated here.

[0101] For example, the storage sub-circuit 207 is electrically connected to the first voltage terminal VGH and the first output node OP1 , respectively, and is configured to store the voltage of the first output node OP1 .

[0102] For example, the first control circuit 200 is also electrically connected to the second voltage terminal VGL, the input terminal of the first isolation subcircuit 208 is electrically connected to the second node n2, the output terminal of the first isolation subcircuit 208 is electrically connected to the first bootstrap subcircuit 203, and the control terminal of the first isolation subcircuit 208 is electrically connected to the second voltage terminal VGL. For example, in general, the first isolation subcircuit 208 is in a conducting state, that is, one end of the first isolation subcircuit 208 connected to the second node n2 and the other end of the first isolation subcircuit 208 connected to the first bootstrap subcircuit 203 are conducting. When the voltage of the first bootstrap subcircuit 203 fluctuates, for example, when the voltage of one end of the first isolation subcircuit 208 connected to the first bootstrap subcircuit 203 suddenly drops, the first isolation subcircuit 208 is converted from the conducting state to the off state, thereby preventing the voltage of the second node n2 from fluctuating and affecting the performance of the transistor (for example, the first pull-up transistor T2 described below) in the second control input subcircuit 202.

[0103] It should be noted that the first control circuit 200 may be connected to another voltage terminal instead of the second voltage terminal VGL, as long as the other voltage terminal outputs a low voltage signal. In addition, the low voltage signal output by the other voltage terminal may be the same as or different from the low voltage signal output by the second voltage terminal VGL.

[0104] For example, the second control circuit further includes a second isolation subcircuit 302, the input end of the second isolation subcircuit 302 is electrically connected to the first node n1, the output end of the second isolation subcircuit 302 is electrically connected to the second bootstrap subcircuit 301 and the second output node OP2, and the control end of the second isolation subcircuit 302 is electrically connected to the second voltage end VGL. For example, in general, the second isolation subcircuit 302 is in a conducting state, that is, one end of the second isolation subcircuit 302 connected to the first node n1 and the other end of the second isolation subcircuit 302 connected to the second bootstrap subcircuit 301 are conducting, when the voltage of the second bootstrap subcircuit 301 fluctuates, for example, due to the bootstrap effect of the second bootstrap subcircuit 301, the voltage of one end of the second isolation subcircuit 302 connected to the second bootstrap subcircuit 301 will suddenly drop, at which time the second isolation subcircuit 302 is converted from the conducting state to the off state, thereby preventing the voltage of the first node n1 from fluctuating and avoiding output abnormality. For example, when the second control input subcircuit 202 is connected to the first node n1, if the voltage of the first node n1 decreases following the voltage change of the second output node OP2, the second control input subcircuit 202 may be turned on, causing output abnormality.

[0105] For example, in the present disclosure, all transistors (transistors T1 to T18 to be described below) are P-type transistors.

[0106] Figure 3A A schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure. Figure 3A The circuit structure diagram shown is Figure 2A A specific example of a schematic block diagram of a shift register is shown.

[0107] like Figure 3A As shown, the first control input subcircuit 201 includes a first pull-down transistor T3, a first electrode of the first pull-down transistor T3 is electrically connected to the first clock signal terminal ECK, a second electrode of the first pull-down transistor T3 is electrically connected to the second node n2, and a gate of the first pull-down transistor T3 is electrically connected to the first clock signal terminal ECK.

[0108] The second control input sub-circuit 202 includes a first pull-up transistor T2 and a second pull-up transistor T5, the first electrode of the first pull-up transistor T2 is electrically connected to the second electrode of the second pull-up transistor T5, the second electrode of the first pull-up transistor T2 is electrically connected to the second node n2, the gate of the first pull-up transistor T2 is electrically connected to the second clock signal terminal ECB, the first electrode of the second pull-up transistor T5 is electrically connected to the first voltage terminal VGH, and the gate of the second pull-up transistor T5 is electrically connected to the output terminal of the input circuit 100, that is, electrically connected to the first node n1.

[0109] The first bootstrap sub-circuit 203 includes a first capacitor C1 and a first bootstrap transistor T6, wherein the gate of the first bootstrap transistor T6 is electrically connected to the second node n2 and the first end of the first capacitor C1, the second electrode of the first bootstrap transistor T6 is electrically connected to the second end of the first capacitor C1 and the third node n3, and the first electrode of the first bootstrap transistor T6 is electrically connected to the second clock signal terminal ECB.

[0110] The first control output subcircuit 204 includes a first control output transistor T7, a gate of which is electrically connected to the second clock signal terminal ECB, a first electrode of which is electrically connected to the third node n3, and a second electrode of which is electrically connected to the first output node OP1.

[0111] The second control output subcircuit 205 includes a second control output transistor T8, a gate of the second control output transistor T8 is electrically connected to the first node n1, a first electrode of the second control output transistor T8 is electrically connected to the first voltage terminal VGH, and a second electrode of the second control output transistor T8 is electrically connected to the first output node OP1.

[0112] The holding sub-circuit 206 includes a holding transistor T4 , a first electrode of the holding transistor T4 is electrically connected to the first voltage terminal VGH, a second electrode of the holding transistor T4 is electrically connected to the first node n1 , and a gate of the holding transistor T4 is electrically connected to the first output node OP1 .

[0113] The storage sub-circuit 207 includes a storage capacitor C3 , a first end of the storage capacitor C3 is electrically connected to the first voltage terminal VGH, and a second end of the storage capacitor C3 is electrically connected to the first output node OP1 .

[0114] The second bootstrap sub-circuit 301 includes a second capacitor C2 and a second bootstrap transistor T13, a first electrode of the second bootstrap transistor T13 is electrically connected to the second clock signal terminal ECB, a first end of the second capacitor C2 is electrically connected to the gate of the second bootstrap transistor T13 and the second output node OP2, and a second end of the second capacitor C2 is electrically connected to the second electrode of the second bootstrap transistor T13.

[0115] The first output sub-circuit 401 includes a first output transistor T9, a gate of the first output transistor T9 is electrically connected to the first output node OP1, a first electrode of the first output transistor T9 is electrically connected to the first voltage terminal VGH, and a second electrode of the first output transistor T9 is electrically connected to the first output terminal Eout.

[0116] The second output sub-circuit 402 includes a second output transistor T10, a gate of the second output transistor T10 is electrically connected to the second output node OP2, a first electrode of the second output transistor T10 is electrically connected to the second voltage terminal VGL, and a second electrode of the second output transistor T10 is electrically connected to the first output terminal Eout.

[0117] For example, the input circuit 100 is used to transmit an input voltage Vin to the first node n1 to trigger the shift register to work. Figure 3A As shown, the input circuit 100 includes an input transistor T1. A first electrode of the input transistor T1 is electrically connected to the input voltage terminal ESTV, a second electrode of the input transistor T1 is electrically connected to the first node n1, and a gate of the input transistor T1 is electrically connected to the first clock signal terminal ECK.

[0118] Figure 3B A schematic diagram of the structure of another shift register provided by an embodiment of the present disclosure. Figure 3B The circuit structure diagram shown is Figure 2B A specific example of a schematic block diagram of a shift register is shown. Figure 2B The shift register shown also includes a first isolation subcircuit 208 and a second isolation subcircuit 302 .

[0119] For example, Figure 3B As shown, the first isolation sub-circuit 208 includes a first isolation transistor T12, a first electrode of the first isolation transistor T12 is electrically connected to the second node n2, a gate of the first isolation transistor T12 is electrically connected to the second voltage terminal VGL, and a second electrode of the first isolation transistor T12 is electrically connected to the first bootstrap sub-circuit 203, for example, Figure 3BAs shown, the second electrode of the first isolation transistor T12 is electrically connected to the gate of the first bootstrap transistor T6.

[0120] The second isolation sub-circuit 302 includes a second isolation transistor T11, a first electrode of the second isolation transistor T11 is electrically connected to the first node n1, a second electrode of the second isolation transistor T11 is electrically connected to the second output node OP2, and a gate of the second isolation transistor T11 is electrically connected to the second voltage terminal VGL.

[0121] Figure 3C A schematic diagram of the structure of another shift register provided by an embodiment of the present disclosure. Figure 3C The circuit structure diagram shown is Figure 2B Another specific example of a schematic block diagram of a shift register is shown.

[0122] For example, Figure 3B and Figure 3C The difference between the circuit diagrams shown is: Figure 3B The gate of the second pull-up transistor T5 of the shift register shown is electrically connected to the first node n1. Figure 3C The gate of the second pull-up transistor T5 of the shift register shown is electrically connected to the input voltage terminal ESTV. The connection relationship between other circuit structures can be found in Figure 3A and Figure 3B The description of the structure of the shift register shown is not repeated here.

[0123] For example, when the second pull-up transistor T5 is electrically connected to the input voltage terminal ESTV, the input voltage Vin can directly control the on and off of the second pull-up transistor T5, so that the second pull-up transistor T5 can be turned off early before the input stage under the control of the high level of the input voltage Vin.

[0124] In addition, it should be noted that Figure 3A , Figure 3B and Figure 3C The input circuit 100, the first control circuit 200, the second control circuit 300 and the output circuit 400 shown are only an example of the embodiment of the present disclosure. The embodiments of the present disclosure include but are not limited to Figure 3A , Figure 3B and Figure 3C The situation shown.

[0125] For example, the first clock signal V ECK And the second clock signal V ECB The high level of the first clock signal V ECK And the second clock signal V ECB The low level of is the same as the level of the second voltage signal VL.

[0126] It should be noted that the first clock signal V ECK and the second clock signal V ECB The high level of the first clock signal V ECK and the second clock signal V ECB The low level of the first clock signal V ECK and the second clock signal V ECB It is sufficient that the first clock signal V ECK and the second clock signal V ECB The high level of the first clock signal V ECK and the second clock signal V ECB The shift register provided by the present disclosure is described by taking the low level of the second voltage signal VL as an example.

[0127] Figure 3D A schematic diagram of the structure of another shift register provided in at least one embodiment of the present disclosure. Figure 3D The circuit structure diagram shown is Figure 2A Another specific example of a schematic block diagram of a shift register is shown.

[0128] For example, Figure 3D and Figure 3A The difference between the circuit diagrams shown is: Figure 3A The gate of the second pull-up transistor T5 of the shift register shown is electrically connected to the first node n1. Figure 3D The gate of the second pull-up transistor T5 of the shift register shown is electrically connected to the input voltage terminal ESTV. The connection relationship between other circuit structures can be found in Figure 3A The description of the structure of the shift register shown is not repeated here.

[0129] Figure 4A is a driving timing diagram of a shift register provided by an embodiment of the present disclosure. Figure 3B The shift register shown and Figure 4A The driving timing sequence shown is taken as an example to introduce the working principle of the shift register provided in the embodiment of the present disclosure.

[0130] For example, Figure 4A As shown, the working process of the shift register provided by the embodiment of the present disclosure includes an input stage A, a first stage B, a buffer stage C and a stabilization stage D, wherein the input stage A, the buffer stage C and the stabilization stage D belong to the second stage.

[0131] For example, Figure 4AAs shown, the high-level input voltage Vin, the high-level first clock signal V ECK and the high level second clock signal V ECB are equal to the first voltage signal VH, the low-level input voltage Vin, the low-level first clock signal V ECK and the low level second clock signal V ECB are equal to the second voltage signal VL.

[0132] For example, Figure 4A As shown, Vout represents the first output signal, Vn3 represents the voltage of the third node n3, Vctr1 represents the first control signal, and Vctr2 represents the second control signal.

[0133] For example, the first isolation transistor T12 is in a normally-on state under the control of the second voltage signal VL, and the second isolation transistor T11 is also in a normally-on state under the control of the second voltage signal VL.

[0134] In the input phase A, the input voltage Vin is input to the first node n1. Figure 4A and Figure 3B As shown, in the input phase A, the first clock signal V output by the first clock signal terminal ECK ECK is a low level signal, and the second clock signal V output by the second clock signal terminal ECB ECB It is a high level signal, and the input voltage Vin output by the input voltage terminal ESTV is a high level signal.

[0135] Since the first clock signal V ECK The second control signal V is a low level signal, the input transistor T1 is turned on, the input voltage Vin (high level signal) is transmitted to the first node n1 via the input transistor T1, and the second isolation transistor T11 is also turned on, so that the input voltage Vin is also transmitted to the second output node OP2 via the second isolation transistor T11, so that the first node n1 and the second output node OP2 are both at a high level. ctr2 It includes a first level signal, which is the voltage of the second output node OP2 in the input stage A, that is, the input voltage Vin. Since the input voltage Vin is equal to the voltage of the first voltage signal VH at this time, the first level signal is the first voltage signal VH, that is, the second control signal Vctr2 is the first voltage signal VH.

[0136] Under the high level control of the first node n1 and the second output node OP2, the second pull-up transistor T5, the second control output transistor T8, the second output transistor T10, and the second bootstrap transistor T13 are all in the cut-off state. ECBis a high level signal, the first pull-up transistor T2 and the first output control transistor T7 are ECB They are also in the cut-off state under the high level control.

[0137] Since the first pull-up transistor T2 and the second pull-up transistor T5 are both in the cut-off state, the voltage of the second node n2 will not be affected by the first voltage terminal VGH. ECK The first clock signal V ECK The low level is transmitted to the second node n2 via the first pull-down transistor T3, so that the second node n2 is at a low level. Since the first pull-down transistor T3 has a threshold loss when transmitting a low level signal, the voltage of the second node n2 is V ECK1 -Vth3, where Vth3 represents the threshold voltage of the first pull-down transistor T3, V ECK1 is the first clock signal V at a low level ECK , V ECK1 =VL, that is, the voltage of the second node n2 is VL-Vth3. Since the first isolation transistor T12 is turned on, the voltage of the second node n2 is transmitted to the gate of the first bootstrap transistor T6 via the first isolation transistor T12, so that the gate of the first bootstrap transistor T6 is also at a low level. For example, the threshold voltage of the first isolation transistor T12 is expressed as Vth12. Similarly, since the first isolation transistor T12 has a threshold loss when transmitting a low-level signal, the voltage of the gate of the first bootstrap transistor T6 is VL-VthN, where VthN is the smaller threshold voltage of Vth3 and Vth12.

[0138] The voltage VL-VthN received by the gate of the first bootstrap transistor T6 can control the first bootstrap transistor T6 to be turned on. The second clock signal V ECB The high level signal of is written into the third node n3 via the first bootstrap transistor T6, so that the third node n3 is at a high level. For example, the voltage Vn3 of the third node n3 is the second clock signal V at a high level in the input phase A. ECB , that is, the first voltage signal VH.

[0139] Since the first control output transistor T7 and the second control output transistor T8 are both in the cut-off state, the voltage of the first output node OP1 remains unchanged, and the first control signal Vctr1 is a high-level signal, that is, the gate voltage of the first output transistor T9 maintains the state of the previous stage unchanged and is still at a high level, so the first output terminal Eout still maintains the state of the previous stage unchanged, and the first output signal Vout is still a low-level signal.

[0140] In the first phase B, at the first control signal V ctr1Under the control of , the first voltage signal VH is output to the first output terminal Eout. Figure 4A and Figure 3B As shown, in the first phase B, the first clock signal V output by the first clock signal terminal ECK ECK is a high level signal, the second clock signal V output by the second clock signal terminal ECB ECB It is a low level signal, and the input voltage Vin output by the input voltage terminal ESTV is a low level signal.

[0141] Since the first clock signal V ECK is a high level signal, the input transistor T1 is turned off, and the voltage of the first node n1 and the second output node OP2 remain unchanged, that is, the voltage of the first node n1 and the voltage of the second output node OP2 are still the first voltage signal VH. ctr2 Still being the first level signal, the second pull-up transistor T5, the second control output transistor T8, the second output transistor T10, and the second bootstrap transistor T13 are all still in the cut-off state under the high level control of the first node n1 and the second output node OP2.

[0142] Since the first clock signal V ECK is a high level signal, the first pull-down transistor T3 is in the off state, although the first pull-up transistor T2 is in the second clock signal V ECB However, since the second pull-up transistor T5 is in the cut-off state, the voltage of the second node n2 remains unchanged, that is, the voltage of the second node n2 is still VL-Vth3.

[0143] The first bootstrap transistor T6 is still in the on state, and the second clock signal V ECB The low-level signal (i.e., the second voltage signal VL) is written into the third node n3 via the first bootstrap transistor T6, so that the voltage Vn3 of the third node n3 jumps from a high level to a low level. Due to the coupling effect of the first capacitor C1, when the voltage Vn3 of the third node n3 jumps from a high level to a low level, the voltage of the gate of the first bootstrap transistor T6 also jumps, and the voltage of the gate of the first bootstrap transistor T6 jumps to VL-VthN-ΔV, where ΔV represents the potential difference from a high level to a low level, and VL-VthN-ΔV is less than VL-VthN, so that the voltage of the gate of the first bootstrap transistor T6 becomes lower, so that the first bootstrap transistor T6 can be better opened, so that the low-level second clock signal V ECB can be transmitted to the third node n3 without threshold loss, that is, at this time, the voltage of the third node n3 is the second clock signal V at a low level ECB , that is, the second voltage signal VL, the low level second clock signal V ECBThat is, the first intermediate signal is the second voltage signal VL.

[0144] The first control output transistor T7 is in the second clock signal V ECB The first control output transistor T7 is turned on under the control of the low-level signal, and the second intermediate signal Vmid2 determined based on the first intermediate signal is written into the first output node OP1. Since the first control output transistor T7 has a threshold loss when transmitting a low-level signal, the voltage of the second intermediate signal Vmid2 is VL-Vth7, where Vth7 represents the threshold voltage of the first control output transistor T7, that is, in the first stage B, the voltage of the first output node OP1 is VL-Vth7, and the first control signal V ctr1 is the second intermediate signal Vmid2, that is, VL-Vth7.

[0145] The first control signal V ctr1 is the second intermediate signal Vmid2, the second intermediate signal Vmid2 is a low level signal, so that in the first stage B, the first control signal V ctr1 (i.e., the second intermediate signal Vmid2), the first output transistor T9 and the holding transistor T4 are turned on, and the first voltage signal VH is written into the first output terminal Eout through the first output transistor T9 to complete the high-level output. At this time, the first output signal Vout is the first voltage signal VH; the first voltage signal VH is written into the first node n1 through the holding transistor T4 to maintain the high level of the first node, thereby avoiding the second pull-up transistor T5 from being mistakenly turned on in the first stage B.

[0146] In the buffering stage C, under the control of the voltage of the second output node OP2, the third voltage signal VL1 obtained based on the second voltage signal VL is output to the first output terminal Eout.

[0147] For example, Figure 4A and Figure 3B As shown, in the buffering stage C, the first clock signal V output by the first clock signal terminal ECK ECK is a low level signal, and the second clock signal V output by the second clock signal terminal ECB ECB is a high level signal, and the input voltage Vin output by the input voltage terminal ESTV is a low level signal.

[0148] The first pull-down transistor T3 has a first clock signal V ECK The low level control is in the on state, and the low level first clock signal V ECKThe voltage of the second node n2 is transmitted to the second node n2 through the first pull-down transistor T3, so that the second node n2 is maintained at a low level. At the same time, since the first isolation transistor T12 is turned on, the voltage of the second node n2 is transmitted to the gate of the first bootstrap transistor T6 through the first isolation transistor T12, so that the gate of the first bootstrap transistor T6 is also at a low level, so that the first bootstrap transistor T6 is in an on state, and the second clock signal V ECB The high level of the second clock signal V is written into the third node n3, so that the third node n3 is at a high level, that is, the voltage Vn3 of the third node n3 is the high level of the second clock signal V ECB .

[0149] The first control output transistor T7 is in the second clock signal V ECB Under the control of the high level of the first clock signal V ECK The low-level input voltage Vin is turned on under the control of the low level, and the low-level input voltage Vin is transmitted to the first node n1 via the input transistor T1, so that the first node n1 is at a low level. The second control output transistor T8 is turned on under the control of the voltage of the first node n1, and the first voltage signal VH is transmitted to the first output node OP1 via the second control output transistor T8, and the storage capacitor C3 is charged to make the first output node OP1 at a high level, that is, at this time, the first control signal V ctr1 is the first voltage signal VH, the first output transistor T9 and the holding transistor T4 are in the first control signal V ctr1 are all in the cut-off state under the control of.

[0150] Since the first clock signal V ECK The second control signal V is a low level signal, the input transistor T1 is turned on, and the low level VL of the input voltage Vin is transmitted to the first node n1 via the input transistor T1, and the second isolation transistor T11 is also turned on, so that the input voltage Vin is also transmitted to the second output node OP2 via the second isolation transistor T11, so that the first node n1 and the second output node OP2 are both at a low level. Since the input transistor T1 has a threshold loss when transmitting a low level signal, the voltage of the first node n1 is Vin-Vth1, that is, VL-Vth1, where Vth1 represents the threshold voltage of the input transistor T1. For example, the threshold voltage of the second isolation transistor T11 is expressed as Vth11. Similarly, since the second isolation transistor T11 has a threshold loss when transmitting a low level signal, the voltage of the second output node OP2 is VL-VthM, where VthM is the smaller threshold voltage of Vth1 and Vth11. The second control signal V ctr2 Including the second level signal (such as Figure 4A The second level signal VL2 is the voltage of the second output node OP2 in the input phase C, that is, VL-VthM, that is, Figure 4A The level of VL2 is shown to be VL-VthM.

[0151] Under the low level control of the first node n1 and the second output node OP2, the second pull-up transistor T5, the second control output transistor T8, the second output transistor T10, and the second bootstrap transistor T13 are all in the on state. The first pull-up transistor T2 and the first output control transistor T7 are in the on state when the second clock signal V ECB Under the high level control, they are in the cut-off state.

[0152] In the buffering stage C, the second output transistor T10 is at the second control signal V ctr2 The second output transistor T10 is in the on state under the control of the low level (i.e., the second level signal VL2), and the second voltage signal VL is transmitted to the first output terminal Eout via the second output transistor T10. Since the second output transistor T10 has a threshold loss when transmitting the low level signal, the second voltage signal VL cannot be completely output to the first output terminal Eout. At this time, the first output terminal Eout is the third voltage signal VL1, and the voltage of the third voltage signal VL1 is VL-Vth10-VthM, wherein Vth10 represents the threshold voltage of the second output transistor T10.

[0153] In the stable phase D, under the control of the voltage of the second output node OP2 , the second voltage signal VL is output to the first output terminal Eout, so that the first output signal Vout is finally reduced from the third voltage signal VL1 to the second voltage signal VL.

[0154] For example, Figure 4A and Figure 3B As shown, in the stable phase D, the first clock signal V output by the first clock signal terminal ECK ECK is a high level signal, the second clock signal V output by the second clock signal terminal ECB ECB It is a low level signal, and the input voltage Vin output by the input voltage terminal ESTV is a low level signal.

[0155] Since the first clock signal V ECK It is a high level signal, the input transistor T1 is turned off, the voltages of the first node n1 and the second output node OP2 maintain the low level of the buffer stage C, the second pull-up transistor T5 and the second control output transistor T8 are in the on state under the low level control of the first node n1, and the second output transistor T10 and the second bootstrap transistor T13 are in the on state under the low level control of the second output node OP2.

[0156] The first pull-up transistor T2 receives the second clock signal V ECBThe first voltage signal VH is also in the on state under the low level control of the first pull-up transistor T2 and the second pull-up transistor T5, so that the second node n2 is in a high level, and the voltage of the second node n2 is transmitted to the gate of the first bootstrap transistor T6 via the first isolation transistor T12, so that the first bootstrap transistor T6 is in the off state, and the first control output transistor T7 is in the second clock signal V ECB It is also in the on state under the low level control.

[0157] The first voltage signal VH is transmitted to the first output node OP1 via the second control output transistor T8, and charges the storage capacitor C3 so that the first output node OP1 maintains a high level. ctr1 is the first voltage signal VH, the first output transistor T9 and the holding transistor T4 are in the first control signal V ctr1 are all in the cut-off state under the control of.

[0158] Since the second bootstrap transistor T13 is in the on state, the input transistor T1 and the holding transistor T4 are in the off state, and the voltage of the second output node OP2 is only affected by the second capacitor C2. ECB A voltage jump from a high level to a low level is generated. Since the second bootstrap transistor T13 is turned on, the voltage at the second end of the second capacitor C2 also jumps from a high level to a low level. Under the coupling effect of the second capacitor C2, the voltage at the first end of the second capacitor C2, that is, the second output node OP2, jumps, so that the voltage of the second output node OP2 drops further. Under the control of the voltage of the second output node OP2, the second bootstrap transistor T13 is fully turned on, so that the low-level second clock signal V ECB can be transmitted to the second end of the second capacitor C2 via the second bootstrap transistor T13 without threshold loss. Therefore, it can be seen that at this time, the voltage at the second end of the second capacitor C2 changes from the high-level second clock signal V ECB (i.e., the first voltage signal VH) jumps to the second clock signal V at a low level ECB (second voltage signal VL), the voltage difference of the voltage jump is VH-VL. At this time, the second control signal V ctr2 is the third level signal (i.e. Figure 4A The voltage of the second output node OP2 jumps from the second level signal VL2 to the third level signal VL3. The voltage of the third level signal VL3 is (VL-VthM-ΔV), that is, Figure 4A The level of VL3 is shown as (VL-VthM-ΔV), and the voltage absolute value difference between the third level signal VL3 and the second level signal VL2 is the voltage difference of the voltage jump.

[0159] At this time, since the third level signal is lower than the second level signal, the second output transistor T10 can be better opened, so that the second voltage signal VL can be output to the first output terminal Eout without threshold loss. At this time, the first output signal Vout can reach the second voltage signal VL.

[0160] Afterwards, before the next high level of the input voltage Vin arrives, the voltage of the first node n1 maintains a low level, so the second pull-up transistor T8 is always in the on state, thereby maintaining the high level of the first output node OP1, and the first output transistor T9 is always in the off state; in addition, in the second clock signal V ECB Under the control of , the voltage of the second output node OP2 is periodically pulled down, that is, the second control signal Vctr2 periodically changes between the second voltage signal VL2 and the third voltage signal VL3, thereby ensuring that the first output signal Vout remains at the second voltage signal VL of the low level, and the entire circuit continues to maintain the output state of the stable stage D, and the subsequent stages will not be repeated.

[0161] It should be noted that, in the embodiment of the present disclosure, the first control signal V ctr1 The voltage of the first output node OP1 in each phase (i.e., input phase A, first phase B, buffer phase C, and stable phase D), the second control signal V ctr2 Including the voltage of the second output node OP2 in each stage.

[0162] Figure 4B is a driving timing diagram of a shift register provided by another embodiment of the present disclosure, and the driving timing diagram is used to drive Figure 3C That is to say, when the second control input subcircuit 202 is electrically connected to the input terminal of the input circuit 100, that is, electrically connected to the input voltage terminal ESTV, it is necessary to use Figure 4B At this time, the pulse width of the input voltage Vin at the first level (for example, a high level) is required to be greater than the first clock signal V ECK The period of the second clock signal V ECB cycle.

[0163] like Figure 4B As shown, the first clock signal V ECK The period of the second clock signal V ECB The pulse width of the input voltage Vin at a high level is greater than the first clock signal V ECK The period of the second clock signal V ECB cycle.

[0164] Figure 4BThe circuit function of the shift register corresponding to the driving timing diagram shown in Figure 3A and Figure 3B The shift registers shown are identical, as Figure 4B As shown, the working process of the shift register also includes an input stage A, a first stage B, a buffer stage C and a stabilization stage D. Regarding the input stage A, the buffer stage C and the stabilization stage D, the circuit operation is exactly the same as the above process and will not be repeated here. Regarding the first stage B, the first control signal V generated in the first stage B ctr1 Still a low level signal, the second control signal V ctr1 It is still a high level signal, so that the first output terminal can be controlled to output the first voltage signal VH. The specific circuit operation process is similar to the above content and will not be repeated here.

[0165] Figure 5A A schematic block diagram of a shift register provided in at least one embodiment of the present disclosure. Figure 5A As shown, in Figure 2B Based on the shift register shown, the shift register also includes an output inversion circuit 500, which is electrically connected to the first output node OP1, the first voltage terminal VGH, the second voltage terminal VGL, the first output terminal Eout and the second output terminal REout, respectively, and is configured to invert the first output signal Vout to obtain the second output signal Rout, and output the second output signal Rout to the second output terminal REout.

[0166] It should be noted that it is also possible to Figure 2A An output inverting circuit 500 is added to the shift register shown to obtain a second output signal Rout which is inverted to the first output signal Vout. The specific connection relationship will not be described in detail here.

[0167] like Figure 5A As shown, the output inversion circuit includes a first output inversion sub-circuit 501 , a second output inversion sub-circuit 502 and an output inversion control sub-circuit 503 .

[0168] The output inversion control subcircuit 503 is electrically connected to the first voltage terminal VGH, the first output node OP1, the second voltage terminal VGL and the fourth node n4 respectively, and is configured to ctr1 , under the control of the first output signal Vout, outputs a fourth control signal V ctr4 To the fourth node n4, using the fourth control signal V ctr4 Control the conduction and cutoff between the second voltage terminal VGL and the second output terminal REout.

[0169] The first output inverting subcircuit 501 is electrically connected to the first voltage terminal VGH, the first output terminal Eout, and the second output terminal REout, respectively, and is configured to write the first voltage signal VH into the second output terminal REout in the second stage under the control of the first output signal Vout. For example, in the second stage, the first output inverting subcircuit 501 is turned on under the control of the first output signal Vout, that is, one end of the first output inverting subcircuit 501 connected to the first voltage terminal VGH and the other end of the first output inverting subcircuit 501 connected to the second output terminal REout are turned on, the first voltage signal VH is written into the second output terminal REout, and at this time, the second output inverting subcircuit 502 is turned on under the control of the fourth control signal V ctr4 cut off under control.

[0170] The second output inverting sub-circuit 502 is electrically connected to the second voltage terminal VGL, the fourth node n4 and the second output terminal REout respectively, and is configured to ctr4 , the second voltage signal VL is written into the second output terminal REout in the first stage. For example, in the first stage, the second output inversion sub-circuit 502 is controlled by the fourth control signal V ctr4 That is, one end of the second output inverting sub-circuit 502 connected to the second voltage terminal VGL and the other end of the second output inverting sub-circuit 502 connected to the second output terminal REout are turned on, and the second voltage signal VL is written into the second output terminal REout. At this time, the first output inverting sub-circuit 501 is turned off under the control of the first output signal Vout.

[0171] For example, the second output signal Rout includes the second voltage signal VL in the first stage and the first voltage signal VH in the second stage.

[0172] For example, the output inversion control sub-circuit 503 includes a pull-up sub-circuit 5031 , a second pull-down sub-circuit 5032 , and a third bootstrap sub-circuit 5033 .

[0173] The pull-up sub-circuit 5031 is electrically connected to the first voltage terminal VGH, the first output terminal Eout, and the fourth node n4, respectively, and is configured to write the first voltage signal VH into the fourth node n4 under the control of the first output signal Vout. For example, when the pull-up sub-circuit 5031 is turned on under the control of the first output signal Vout, that is, when one end of the pull-up sub-circuit 5031 connected to the first voltage terminal VGH and the other end of the pull-up sub-circuit 5031 connected to the fourth node n4 are turned on, the first voltage signal VH is written into the fourth node n4, so that the fourth node n4 is at a high level.

[0174] The pull-down sub-circuit 5032 is electrically connected to the first output node OP1, the second voltage terminal VGL and the fourth node n4, and is configured to ctr1 , writes the third intermediate signal Vmid3 determined based on the second voltage signal VL into the fourth node n4. ctr1 , that is, when one end of the pull-down sub-circuit 5032 connected to the second voltage terminal VGL and the other end of the pull-down sub-circuit 5032 connected to the fourth node n4 are turned on, the third intermediate signal Vmid3 determined based on the second voltage signal VL is written into the fourth node n4, so that the fourth node n4 is at a low level.

[0175] The third bootstrap sub-circuit 5033 is electrically connected to the fourth node n4 and the first clock signal terminal ECK, respectively, and is configured to, under the control of the voltage of the fourth node, generate a voltage based on the third intermediate signal Vmid3 and the first clock signal V ECK The determined fourth intermediate signal Vmid4 is written into the fourth node n4. For example, under the bootstrap effect of the third bootstrap sub-circuit 5033, the voltage Vn4 of the fourth node n4 can be lower than the second clock signal V ECK The voltage of the fourth intermediate signal Vmid4 is at a low level, and the absolute value of the voltage of the fourth intermediate signal Vmid4 obtained based on the bootstrap effect is greater than the absolute value of the voltage of the third intermediate signal Vmid3.

[0176] The fourth control signal includes the first voltage signal, a third intermediate signal Vmid3 and a fourth intermediate signal Vmid4.

[0177] Figure 5B A schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure. The shift register is based on Figure 3C The output inverting circuit 500 is added to the shift register shown in FIG. 1 , so the structural description of the input circuit 100, the first control circuit 200, the second control circuit 300 and the output circuit 400 is referred to in the FIG. 3A to FIG. 3C The relevant structural description of the structural schematic diagram shown will not be repeated here.

[0178] It should be noted that the shift register including the output inverting circuit 500 is not limited to Figure 5B The structure shown in FIG. 1 , the input circuit 100, the first control circuit 200, the second control circuit 300 and the output circuit 400 can be modified and combined with reference to any embodiment of the present disclosure, and the present disclosure does not limit this. Figure 3A as well as Figure 3B The shift register shown is based on which an output inverting circuit 500 is added, but the present disclosure does not limit this.

[0179] Below Figure 5B As an example, the structural relationship of the shift register including the output inverting circuit 500 is specifically described.

[0180] The first output inverting sub-circuit 501 includes a first output inverting transistor T17 , and the second output inverting sub-circuit 502 includes a second output inverting transistor T16 .

[0181] A gate of the first output inverting transistor T17 is electrically connected to the first output terminal Eout, a first electrode of the first output inverting transistor T17 is electrically connected to the first voltage terminal VGH, and a second electrode of the first output inverting transistor T17 is electrically connected to the second output terminal REout.

[0182] A gate of the second output inverting transistor T16 is electrically connected to the fourth node n4 , a first electrode of the second output inverting transistor T16 is electrically connected to the second voltage terminal VGL, and a second electrode of the second output inverting transistor T16 is electrically connected to the second output terminal REout.

[0183] The pull-up sub-circuit 5031 includes a third pull-up transistor T15, a gate of the third pull-up transistor T15 is electrically connected to the first output terminal Eout, a first electrode of the third pull-up transistor T15 is electrically connected to the first voltage terminal VGH, and a second electrode of the third pull-up transistor T15 is electrically connected to the fourth node n4.

[0184] The pull-down sub-circuit 5032 includes a second pull-down transistor T14, a gate of which is electrically connected to the first output node OP1, a first electrode of which is electrically connected to the second voltage terminal VGL, and a second electrode of which is electrically connected to the fourth node n4.

[0185] The third bootstrap sub-circuit 5033 includes a third capacitor C4 and a third bootstrap transistor T18, the first end of the third capacitor C4 and the gate of the third bootstrap transistor T18 are both electrically connected to the fourth node n4, the second electrode of the third bootstrap transistor T18 is electrically connected to the second end of the third capacitor C4, and the first electrode of the third bootstrap transistor T18 is electrically connected to the first clock signal terminal ECK.

[0186] Figure 5C is another driving timing diagram of a shift register provided by an embodiment of the present disclosure. Figure 5B The shift register shown and Figure 5C The driving timing sequence shown is taken as an example to introduce the working principle of the shift register provided in the embodiment of the present disclosure.

[0187] For example, Figure 5CAs shown, the working process of the shift register provided by the embodiment of the present disclosure includes an input stage A, a first output stage B1, a second output stage B2, a buffer stage C and a stabilization stage D, wherein the first stage includes the first output stage B1 and the second output stage B2, and the second stage includes the input stage A, the buffer stage C and the stabilization stage D.

[0188] For the input circuit 100, the first control circuit 200, the second control circuit 300 and the output circuit 400, the working process in the input stage A, the buffer stage C and the stable stage D can refer to the description of the aforementioned content, which will not be repeated here. The first stage B in the aforementioned working process is divided into the first output stage B1 and the second output stage B2, and the working process is exactly the same. Therefore, the description of the working process of the input circuit 100, the first control circuit 200, the second control circuit 300 and the output circuit 400 in the first output stage B1 and the second output stage B2 can refer to the aforementioned description of the first stage B, which will not be repeated here.

[0189] The working process of the output inverting circuit 500 is described below.

[0190] For example, in the input phase A, the first clock signal V output by the first clock signal terminal ECK ECK is a low level signal, and the second clock signal V output by the second clock signal terminal ECB ECB is a high level signal, the input voltage Vin output by the input voltage terminal ESTV is a high level signal, and the first output signal Vout is a low level signal.

[0191] According to the above description about the input stage A, since the first control output transistor T7 and the second control output transistor T8 are both in the off state, the voltage of the first output node OP1 remains unchanged and is still at a high level, so the second pull-down transistor T14 is in the off state under the control of the voltage of the first output node OP1. The first output terminal Eout maintains the state of the previous stage in the input stage A. At this time, the first output signal Vout is a low-level signal. Therefore, under the control of the first output signal Vout, the third pull-up transistor T15 and the first output inverting transistor T17 are in the on state, and the first voltage signal VH is written into the fourth node n4 via the third pull-up transistor T15, so that the fourth node n4 is at a high level, that is, the voltage Vn4 of the fourth node is a high level VH, thereby controlling the second output inverting transistor T16 to be in the off state; the first voltage signal VH is written into the second output terminal REout via the first output inverting transistor T17, that is, at this time, the second output signal Rout is the first voltage signal VH.

[0192] In the first output stage B1, the first clock signal V output by the first clock signal terminal ECKECK is a high level signal, the second clock signal V output by the second clock signal terminal ECB ECB is a low level signal, the input voltage Vin output by the input voltage terminal ESTV is a high level signal, and the first output signal Vout is a high level signal.

[0193] According to the above description of the first stage B, at this time, the first output signal Vout is the first voltage signal VH, so the third pull-up transistor T15 and the first output inverter transistor T17 are in the cut-off state, and the voltage Vn4 of the fourth node n4 is no longer affected by the first voltage terminal VGH. The voltage of the first output node OP1 is VL-Vth7, that is, at this time, the first control signal V ctrl1 is low level, the first control signal V ctrl1 Under the control of , the second pull-down transistor T14 is in the on state, and the third intermediate signal Vmid3 determined based on the second voltage signal VL is written into the fourth node n4. Since the second pull-down transistor T14 has a threshold loss when transmitting a low-level signal, the voltage of the third intermediate signal Vmid3 is VL-Vth7-Vth14, wherein Vth7 represents the threshold voltage of the first control output transistor T7, and Vth14 represents the threshold voltage of the second pull-down transistor T14, that is, the voltage Vn4 of the fourth node n4 is VL-Vth7-Vth14 at this time, and when the voltage Vn4 of the fourth node n4 reaches VL-Vth7-Vth14, the second pull-down transistor T14 is turned off.

[0194] The third bootstrap transistor T18 is turned on under the control of the voltage Vn4 at the fourth node n4, and the first clock signal V ECK The high level is transmitted to the second end of the third capacitor C4, so that the second end of the third capacitor C4 is at a high level.

[0195] Since the voltage Vn4 of the fourth node n4 is VL-Vth7-Vth14, the second output inverting transistor T16 is in a certain degree of on state, and the second output inverting transistor T16 has a threshold loss when transmitting a low-level signal. When the voltage of the second output signal Rout output by the second output terminal REout reaches VL-Vth14-Vth16, the second output inverting transistor T16 is turned off, and the voltage of the second output signal Rout no longer decreases. Therefore, in the first output stage B1, the voltage of the second output signal Rout is VL-Vth14-Vth16, and the low level output by the second output terminal REout cannot reach the potential of the second voltage signal VL.

[0196] In the second output stage B2, when the input voltage Vin is at a high level, the first clock signal V output by the first clock signal terminal ECK ECKis a low level signal, and the second clock signal V output by the second clock signal terminal ECB ECB is a high level signal; when the input voltage Vin is at a low level, the first clock signal V output by the first clock signal terminal ECK ECK is a high level signal, the second clock signal V output by the second clock signal terminal ECB ECB is a low level signal; the first output signal Vout is a high level signal in the second output stage B2.

[0197] When the input voltage Vin is at a high level, the first control signal V ctrl1 is a low level signal, and the first output signal Vout is a high level signal, so the third pull-up transistor T15 and the first output inverting transistor T17 are still in the off state, and the second pull-down transistor T14 and the second output inverting transistor T16 are also in the off state.

[0198] From the first output stage B1 to the second output stage B2, the first clock signal V ECK From high level to low level, due to the coupling effect of the third capacitor C4, the voltage Vn4 of the fourth node n4 drops to Vmid3-ΔV, that is, the voltage of the fourth intermediate signal Vmid4 is Vmid3-ΔV, ΔV represents the potential difference from high level to low level. Since the voltage Vn4 of the fourth node n4 drops to a voltage value much lower than VL, the second output inverting transistor T16 is better turned on, so that the second voltage signal VL can be output to the second output terminal REout without threshold loss, that is, the second output signal Rout reaches the voltage of the second voltage signal VL.

[0199] When the input voltage Vin is at a low level, due to the first control signal V ctrl1 , the first output signal Vout and the voltage Vn4 of the fourth node n4 remain unchanged, so the second output signal Rout is still the second voltage signal VL.

[0200] In the buffering stage C, the first clock signal V output by the first clock signal terminal ECK ECK is a low level signal, and the second clock signal V output by the second clock signal terminal ECB ECB is a high level signal, the input voltage Vin output by the input voltage terminal ESTV is a low level signal, and the first output signal Vout is a low level signal, that is, a third voltage signal.

[0201] According to the description of the buffer stage C, the first control signal V ctr1is the first voltage signal VH, that is, at this time, the first output node OP1 is at a high level, so the second pull-down transistor T14 is in a cut-off state. The first output signal Vout is the third voltage signal VL1, and the voltage absolute value of the third voltage signal VL1 is less than the second voltage signal VL. Under the control of the third voltage signal VL1, the third pull-up transistor T15 and the first output inverting transistor T17 are both turned on. The first voltage signal VH is written into the fourth node n4 via the third pull-up transistor T15, so that the fourth node n4 is at a high level. At this time, the voltage Vn4 of the fourth node n4 is the first voltage signal VH, and the second output inverting transistor T16 is in a cut-off state; the first voltage signal VH is written into the second output terminal REout via the first output inverting transistor T17, and the second output terminal REout outputs a high level signal, that is, at this time, the second output signal Rout is the first voltage signal VH.

[0202] In the stable phase D, the first clock signal V output by the first clock signal terminal ECK ECK is a high level signal, the second clock signal V output by the second clock signal terminal ECB ECB is a low level signal, the input voltage Vin output by the input voltage terminal ESTV is a low level signal, and the first output signal Vout is a low level signal, that is, the second voltage signal VL.

[0203] Similar to the buffering stage C, under the high level control of the first output node OP1, the second pull-down transistor T14 is in the cut-off state, and under the control of the second voltage signal VL, the third pull-up transistor T15 and the first output inverting transistor T17 are both turned on, so that the second output inverting transistor T16 is also in the cut-off state; the first voltage signal VH is written to the second output terminal REout via the first output inverting transistor T17, and the second output terminal REout still outputs a high level signal, that is, at this time, the second output signal Rout is the first voltage signal VH.

[0204] Figure 5D A schematic block diagram of another shift register provided in at least one embodiment of the present disclosure. Figure 5D As shown, in Figure 2A Based on the shift register shown, the shift register also includes an output inversion circuit 500, which is electrically connected to the first output node OP1, the first voltage terminal VGH, the second voltage terminal VGL, the first output terminal Eout and the second output terminal REout, respectively, and is configured to invert the first output signal Vout to obtain the second output signal Rout, and output the second output signal Rout to the second output terminal REout.

[0205] about Figure 5DThe structural relationship of the shift register of the output inverting circuit 500 and the driving timing diagram can refer to the above content, and the repeated parts will not be repeated.

[0206] Figure 6 A schematic block diagram of a gate driving circuit provided in an embodiment of the present disclosure is shown in FIG. Fig. 7A A schematic diagram of the structure of a gate driving circuit provided by an embodiment of the present disclosure.

[0207] At least one embodiment of the present disclosure further provides a gate driving circuit, such as Figure 6 As shown, the gate drive circuit 1 includes the shift register 10 described in any one of the above embodiments of the present disclosure. The gate drive circuit provided by the present disclosure can output a level opposite to the turn-on level of the transistor through the shift register 10, for example, when the transistor is a P-type transistor, a high level pulse is output.

[0208] For example, Fig. 7A As shown, the gate drive circuit 1 includes a plurality of cascaded shift registers SR1, SR2, SR3...SRn. These shift registers SR1, SR2, SR3...SRn can be any of the shift registers described in the above embodiments of the present disclosure. The first output terminals Eout of these shift registers SR1, SR2, SR3...SRn are respectively connected to a plurality of gate lines G1, G2, G3...Gn (not shown) in one-to-one correspondence.

[0209] For example, in addition to the first-stage shift register, the first output terminal of the M-stage shift register is used as the input voltage terminal connected to the M+1-stage shift register, where M is a positive integer and M is greater than 1. Thus, the working state of the next-stage shift register is controlled by the first output signal of the previous-stage shift register to realize the sequential output of the pulse scanning signal.

[0210] For example, the input voltage terminal ESTV of the first-stage shift register SR1 is connected to the trigger signal terminal STV0 (which is configured to provide a trigger signal to control the gate driving circuit to start working) to receive the trigger signal as the input voltage Vin.

[0211] For example, Figure 6 As shown, the gate drive circuit 1 further includes a signal generating circuit 20. Fig. 7A As shown, the signal generating circuit 20 is configured to generate a first signal CK and a second signal CB. For example, for the 2N-1 stage shift register, the first signal CK is the first clock signal V in the embodiment of the above shift register. ECK The second signal CB is the second clock signal V in the embodiment of the shift register. ECB For the 2N-stage shift register, the first signal CK is the second clock signal V in the above-mentioned shift register embodiment.ECB The second signal CB is the first clock signal V in the embodiment of the above shift register. ECK The first signal CK and the second signal CB alternately control the shift registers of odd-numbered stages and even-numbered stages, thereby reducing the number of signals and lowering the production cost.

[0212] For example, Fig. 7A As shown, the first signal CK is applied to the first clock signal terminal ECK connected to the 2N-1 stage shift register and the second clock signal terminal ECB connected to the 2N stage shift register; the second signal CB is applied to the second clock signal terminal ECB connected to the 2N-1 stage shift register and the first clock signal terminal ECK connected to the 2N stage shift register, wherein N is a positive integer, and N is greater than or equal to 1, and less than n / 2. It should be noted that n can be an even number or an odd number, and the present disclosure does not limit this. Fig. 7A In the example shown, n is an even number.

[0213] It should be noted that the above-mentioned “previous level” and “next level” do not refer to the previous level and next level in terms of scanning sequence, but refer to the previous level and next level in terms of physical connection.

[0214] For example, taking the first-stage shift register SR1 and the second-stage shift register SR2 as examples, the trigger signal terminal STV0 provides the trigger signal STV0 as the input voltage Vin to the first-stage shift register SR1, thereby controlling the first-stage shift register SR1 to start working. Under the control of the first signal CK and the second signal CB, the first-stage shift register SR1 outputs the first output signal Vout(1) as the scanning signal to the gate line G1, and transmits the first output signal Vout(1) output by the first-stage shift register SR1 to the second-stage shift register SR2 as the input voltage of the second-stage shift register SR2, thereby controlling the second-stage shift register SR2 to start working. Under the control of the first signal CK and the second signal CB, the second-stage shift register SR2 outputs the second output signal Vout(2) as the scanning signal to the gate line G2, and transmits the first output signal Vout(2) output by the second-stage shift register SR2 to the next-stage shift register as the input voltage of the next-stage shift register, and so on. Finally, the gate drive circuit completes the scanning work of one frame.

[0215] Figure 7B A schematic diagram of the structure of another gate drive circuit provided in an embodiment of the present disclosure.

[0216] The gate drive circuit 1 includes a shift register including an output inverting circuit in the above embodiment of the present disclosure, for example, Figure 5A and Figure 5B The shift register shown.

[0217] like Figure 7B As shown, these shift registers SR1, SR2, SR3, ... SRn have a second output terminal REout in addition to the first output terminal Eout. The second output terminal REout outputs a second output signal Rout which is inverted to the first output signal Vout. For example, the second output signal Rout(1) is a signal which is inverted to the first output signal Vout(1), the second output signal Rout(2) is a signal which is inverted to the first output signal Vout(2), and so on.

[0218] The connection relationship and scanning process of the shift registers SR1, SR2, SR3, ... SRn in the gate driving circuit 1 are as described above and will not be repeated here.

[0219] Figure 8 A schematic diagram of a display device provided in accordance with an embodiment of the present disclosure.

[0220] The embodiment of the present disclosure also provides a display device 50. Figure 8 As shown, the display device 50 includes the gate driving circuit 1 provided by any embodiment of the present disclosure.

[0221] For example, Figure 8 As shown, the display device 50 provided by the embodiment of the present disclosure further includes a gate line 2 , a data line 3 , and a plurality of pixel units 4 defined by the intersection of the gate line 2 and the data line 3 , and the gate driving circuit 1 is configured to provide a gate driving signal to the gate line 2 .

[0222] For example, each stage of the shift registers SR1, SR2, SR3, ... SRn is used to output a row of gate driving signals to the corresponding gate lines G1, G2, G3, ... Gn.

[0223] For example, the display device 50 may be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0224] At least one embodiment of the present disclosure further provides a shift register driving method, which is used to drive the shift register provided according to at least one embodiment of the present disclosure.

[0225] Fig. 9 A flowchart of a driving method provided by an embodiment of the present disclosure.

[0226] The embodiment of the present disclosure also provides a shift register driving method, such as Fig. 9 As shown, the driving method includes the following steps:

[0227] Step S10: In the input stage, input voltage is input to the first node.

[0228] Step S20: In the first stage, under the control of the first control signal, the first voltage signal is output to the first output terminal.

[0229] Step S30: In the stable phase, under the control of the second control signal, the second voltage signal is output to the first output terminal.

[0230] The shift register driving method provided by the embodiments of the present disclosure can enable the P-type transistor to output a level opposite to the turn-on level of the P-type transistor, for example, a high-level pulse.

[0231] It should be noted that the specific operation process of the driving method provided in the embodiment of the present disclosure can refer to the relevant descriptions of the input stage A, the first stage B, the buffer stage C and the stabilization stage D in the above-mentioned shift register embodiment, and the repeated parts will not be repeated here.

[0232] There are a few points to note about this disclosure:

[0233] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0234] (2) For the sake of clarity, the thickness and size of layers or structures are exaggerated in the drawings used to describe the embodiments of the present invention. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intervening elements.

[0235] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0236] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A shift register, comprising: An input circuit, a first control circuit, a second control circuit and an output circuit, wherein: The input circuit is electrically connected to the input voltage terminal, the first clock signal terminal and the first node respectively, and is configured to input the input voltage provided by the input voltage terminal to the first node under the control of the first clock signal provided by the first clock signal terminal; The first control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first voltage terminal, the first node and the first output node respectively, and is configured to output a first control signal to the first output node under the control of the first clock signal, the voltage of the first node and the second clock signal provided by the second clock signal terminal; The second control circuit is electrically connected to the first node, the second clock signal terminal and the second output node respectively, and is configured to output a second control signal to the second output node under the control of the voltage of the first node; The output circuit is electrically connected to the first voltage terminal, the second voltage terminal, the first output node, the second output node and the first output terminal respectively, and is configured to write the first voltage signal provided by the first voltage terminal or the second voltage signal provided by the second voltage terminal into the first output terminal as the first output signal under the control of the first control signal and the second control signal; Wherein, the first control circuit is also electrically connected to the input circuit, The first control circuit comprises a second control input subcircuit, The second control input subcircuit is electrically connected to the input circuit, the second clock signal terminal, the first voltage terminal and the second node, respectively, and is configured to write the first voltage signal into the second node under the control of the input voltage and the second clock signal.

2. The shift register according to claim 1, wherein: The first control circuit is configured to control the output circuit to output the first voltage signal in a first stage; The second control circuit is configured to control the output circuit to output the second voltage signal in the second stage. The first output signal includes the first voltage signal in the first stage and the second voltage signal in the second stage.

3. The shift register according to claim 2, wherein: The output circuit is also configured to, under the control of the first control signal and the second control signal, write a third voltage signal to the first output terminal in the second stage, wherein the first output signal also includes the third voltage signal, and the absolute value of the voltage of the third voltage signal is smaller than the absolute value of the voltage of the second voltage signal.

4. The shift register according to claim 1, wherein: The first control circuit comprises a first control input subcircuit, The first control input subcircuit is electrically connected to the first clock signal terminal and the second node, respectively, and is configured to write a third control signal into the second node under the control of the first clock signal.

5. The shift register according to claim 1, wherein: The first control circuit includes a first bootstrap subcircuit, a first control output subcircuit and a second control output subcircuit, The first bootstrap subcircuit is electrically connected to the second node, the third node and the second clock signal terminal respectively, and is configured to write the first intermediate signal to the third node under the control of the voltage of the second node; The first control output subcircuit is electrically connected to the second clock signal terminal, the third node and the first output node respectively, and is configured to write the second intermediate signal into the first output node under the control of the second clock signal; The second control output subcircuit is electrically connected to the first node, the first voltage terminal and the first output node respectively, and is configured to write the first voltage signal into the first output node under the control of the voltage of the first node, The first control signal includes the second intermediate signal and the first voltage signal.

6. The shift register according to claim 1, wherein: The input circuit includes an input terminal connected to the input voltage terminal and an output terminal connected to the first node, The second control input subcircuit is electrically connected to the output end of the input circuit, or the second control input subcircuit is electrically connected to the input end of the input circuit.

7. The shift register according to claim 4, wherein: The first control input subcircuit includes a first pull-down transistor, a first electrode of the first pull-down transistor is electrically connected to the first clock signal terminal, a second electrode of the first pull-down transistor is electrically connected to the second node, and a gate of the first pull-down transistor is electrically connected to the first clock signal terminal.

8. The shift register according to claim 1, wherein: The second control input subcircuit includes a first pull-up transistor and a second pull-up transistor, the first electrode of the first pull-up transistor is electrically connected to the second electrode of the second pull-up transistor, the second electrode of the first pull-up transistor is electrically connected to the second node, the gate of the first pull-up transistor is electrically connected to the second clock signal terminal, the gate of the second pull-up transistor is electrically connected to the input terminal of the input circuit or the output terminal of the input circuit, and the first electrode of the second pull-up transistor is electrically connected to the first voltage terminal.

9. The shift register according to claim 5, wherein: The first bootstrap subcircuit comprises a first capacitor and a first bootstrap transistor, wherein a gate of the first bootstrap transistor is electrically connected to the second node and a first end of the first capacitor, a second electrode of the first bootstrap transistor is electrically connected to a second end of the first capacitor and the third node, and a first electrode of the first bootstrap transistor is electrically connected to the second clock signal end; The first control output subcircuit comprises a first control output transistor, a gate of the first control output transistor is electrically connected to the second clock signal terminal, a first electrode of the first control output transistor is electrically connected to the third node, and a second electrode of the first control output transistor is electrically connected to the first output node; The second control output subcircuit includes a second control output transistor, a gate of the second control output transistor is electrically connected to the first node, a first electrode of the second control output transistor is electrically connected to the first voltage terminal, and a second electrode of the second control output transistor is electrically connected to the first output node.

10. The shift register according to any one of claims 4 to 9, wherein: The first control circuit further includes a holding subcircuit, The holding sub-circuit is electrically connected to the first voltage terminal, the first node, and the first output node, respectively, and is configured to maintain a level of the first node in a first stage.

11. The shift register according to claim 10, wherein: The holding subcircuit includes a holding transistor, a first electrode of the holding transistor is electrically connected to the first voltage terminal, a second electrode of the holding transistor is electrically connected to the first node, and a gate of the holding transistor is electrically connected to the first output node.

12. The shift register according to any one of claims 4 to 9, wherein: The first control circuit is also electrically connected to the second voltage terminal. The first control circuit also includes a first isolation subcircuit, an input end of the first isolation subcircuit is electrically connected to the second node, an output end of the first isolation subcircuit is electrically connected to the first bootstrap subcircuit, and a control end of the first isolation subcircuit is electrically connected to the second voltage end.

13. The shift register according to claim 12, wherein: The first isolation subcircuit includes a first isolation transistor, a first electrode of the first isolation transistor is electrically connected to the second node, a second electrode of the first isolation transistor is electrically connected to the first bootstrap subcircuit, and a gate of the first isolation transistor is electrically connected to the second voltage terminal.

14. The shift register according to any one of claims 4 to 9, wherein: The first control circuit further includes a storage sub-circuit, which is electrically connected to the first voltage terminal and the first output node, respectively, and is configured to store the voltage of the first output node.

15. The shift register according to claim 14, wherein: The storage subcircuit includes a storage capacitor, a first end of the storage capacitor is electrically connected to the first voltage end, and a second end of the storage capacitor is electrically connected to the first output node.

16. The shift register according to any one of claims 1 to 9, wherein: The second control circuit includes a second bootstrap sub-circuit, and the second bootstrap sub-circuit is electrically connected to the first node, the second clock signal terminal and the second output node respectively.

17. The shift register according to claim 16, wherein: The second bootstrap sub-circuit includes a second capacitor and a second bootstrap transistor, a first electrode of the second bootstrap transistor is electrically connected to the second clock signal terminal, a first end of the second capacitor is electrically connected to the gate of the second bootstrap transistor and the second output node, and a second end of the second capacitor is electrically connected to the second electrode of the second bootstrap transistor.

18. The shift register according to any one of claims 1 to 9, wherein: The second control circuit also includes a second isolation subcircuit, an input end of the second isolation subcircuit is electrically connected to the first node, an output end of the second isolation subcircuit is electrically connected to the second output node, and a control end of the second isolation subcircuit is electrically connected to the second voltage end.

19. The shift register according to claim 18, wherein: The second isolation subcircuit includes a second isolation transistor, a first electrode of the second isolation transistor is electrically connected to the first node, a second electrode of the second isolation transistor is electrically connected to the second output node, and a gate of the second isolation transistor is electrically connected to the second voltage terminal.

20. The shift register according to any one of claims 1 to 9, wherein: The output circuit includes a first output subcircuit and a second output subcircuit, The first output subcircuit is electrically connected to the first output node, the first voltage terminal and the first output terminal respectively, and is configured to write the first voltage signal to the first output terminal in a first stage under the control of the first control signal; The second output subcircuit is electrically connected to the second output node, the second voltage terminal and the first output terminal respectively, and is configured to write the second voltage signal to the first output terminal in a second phase under the control of the second control signal.

21. The shift register according to claim 20, wherein: The first output subcircuit comprises a first output transistor, a gate of the first output transistor is electrically connected to the first output node, a first electrode of the first output transistor is electrically connected to the first voltage terminal, and a second electrode of the first output transistor is electrically connected to the first output terminal; The second output subcircuit includes a second output transistor, a gate of the second output transistor is electrically connected to the second output node, a first electrode of the second output transistor is electrically connected to the second voltage terminal, and a second electrode of the second output transistor is electrically connected to the first output terminal.

22. The shift register according to claim 1, further comprising an output inversion circuit, wherein: The output inversion circuit is electrically connected to the first output node, the first voltage terminal, the second voltage terminal, the first output terminal and the second output terminal respectively, and is configured to invert the first output signal to obtain a second output signal, and output the second output signal to the second output terminal.

23. The shift register according to claim 22, wherein: The output inversion circuit includes a first output inversion subcircuit, a second output inversion subcircuit and an output inversion control subcircuit. The output inversion control subcircuit is electrically connected to the first voltage terminal, the first output node, the second voltage terminal and the fourth node respectively, and is configured to output a fourth control signal to the fourth node under the control of the first control signal and the first output signal; The first output inversion subcircuit is electrically connected to the first voltage terminal, the first output terminal and the second output terminal respectively, and is configured to write the first voltage signal into the second output terminal in the second stage under the control of the first output signal; The second output inversion subcircuit is electrically connected to the second voltage terminal, the fourth node and the second output terminal respectively, and is configured to write the second voltage signal to the second output terminal in the first stage under the control of the fourth control signal. The second output signal includes a second voltage signal in the first stage and the first voltage signal in the second stage.

24. The shift register according to claim 23, wherein: The output inversion control subcircuit includes a pull-up subcircuit, a pull-down subcircuit and a third bootstrap subcircuit, The pull-up subcircuit is electrically connected to the first voltage terminal, the first output terminal and the fourth node respectively, and is configured to write the first voltage signal into the fourth node under the control of the first output signal; The pull-down subcircuit is electrically connected to the first output node, the second voltage terminal and the fourth node respectively, and is configured to write a third intermediate signal determined based on the second voltage signal into the fourth node under the control of the first control signal; The third bootstrap subcircuit is electrically connected to the fourth node and the first clock signal terminal respectively, and is configured to write a fourth intermediate signal determined based on the third intermediate signal and the first clock signal into the fourth node under the control of the voltage of the fourth node, The fourth control signal includes the first voltage signal, the third intermediate signal and the fourth intermediate signal.

25. The shift register according to claim 23 or 24, wherein: The first output inversion subcircuit includes a first output inversion transistor, the second output inversion subcircuit includes a second output inversion transistor, The gate of the first output inverting transistor is electrically connected to the first output terminal, the first electrode of the first output inverting transistor is electrically connected to the first voltage terminal, and the second electrode of the first output inverting transistor is electrically connected to the second output terminal; A gate of the second output inverting transistor is electrically connected to the fourth node, a first electrode of the second output inverting transistor is electrically connected to the second voltage terminal, and a second electrode of the second output inverting transistor is electrically connected to the second output terminal.

26. The shift register according to claim 24, wherein: The pull-up sub-circuit comprises a third pull-up transistor, a gate of the third pull-up transistor is electrically connected to the first output terminal, a first electrode of the third pull-up transistor is electrically connected to the first voltage terminal, and a second electrode of the third pull-up transistor is electrically connected to the fourth node; The pull-down sub-circuit includes a second pull-down transistor, a gate of the second pull-down transistor is electrically connected to the first output node, a first electrode of the second pull-down transistor is electrically connected to the second voltage terminal, and a second electrode of the second pull-down transistor is electrically connected to the fourth node; The third bootstrap sub-circuit includes a third capacitor and a third bootstrap transistor, the first end of the third capacitor and the gate of the third bootstrap transistor are both electrically connected to the fourth node, the second electrode of the third bootstrap transistor is electrically connected to the second end of the third capacitor, and the first electrode of the third bootstrap transistor is electrically connected to the first clock signal end.

27. The shift register according to any one of claims 1 to 9, wherein: The input circuit includes an input transistor, a first electrode of the input transistor is electrically connected to the input voltage terminal, a second electrode of the input transistor is electrically connected to the first node, and a gate of the input transistor is electrically connected to the first clock signal terminal.

28. A gate driving circuit, comprising the shift register according to any one of claims 1 to 27.

29. The gate driving circuit according to claim 28, wherein: The gate driving circuit includes a plurality of the shift registers connected in cascade. Among them, except for the first stage shift register, the first output terminal of the Mth stage shift register is used as the input voltage terminal connected to the M+1th stage shift register, Wherein, M is a positive integer, and M is greater than 1.

30. The gate driving circuit according to claim 28 or 29, further comprising a signal generating circuit, in, The signal generating circuit is configured to generate a first signal and a second signal, The first signal is applied to a first clock signal terminal connected to the 2N-1th stage shift register and a second clock signal terminal connected to the 2Nth stage shift register; The second signal is applied to the second clock signal terminal connected to the 2N-1th stage shift register and the first clock signal terminal connected to the 2Nth stage shift register; Wherein, N is a positive integer, and N is greater than or equal to 1.

31. A display device, comprising the gate driving circuit according to any one of claims 28 to 30.

32. A shift register driving method, used to drive the shift register according to any one of claims 1 to 27, The output circuit outputs the first voltage signal in a first stage, and outputs the second voltage signal in a second stage, wherein the second stage includes an input stage and a stable stage, The driving method comprises: In the input stage, the input voltage is input to the first node; In the first stage, under the control of the first control signal, the first voltage signal is output to the first output terminal; In the stable phase, under the control of the second control signal, the second voltage signal is output to the first output terminal.

33. The driving method according to claim 32, wherein: The second stage also includes a buffer stage, The driving method further comprises: In the buffering stage, under the control of the second control signal, the third voltage signal is output to the first output terminal, The first output signal further includes the third voltage signal, and the absolute value of the voltage of the third voltage signal is smaller than the absolute value of the voltage of the second voltage signal.

34. The driving method according to claim 32 or 33, wherein: When the first control circuit is electrically connected to the input voltage terminal, A pulse width of the input voltage at the first level is greater than periods of the first clock signal and the second clock signal.

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