Production test system for i3c devices

Abstract

The application provides a mass production test system of an I3C device, the I3C device is a MEMS device with an I3C interface, the mass production test system of the I3C device comprises a mass production tester and an FPGA test board card, the FPGA test board card comprises: a tester interface connected between the FPGA master control unit and the mass production tester; an FPGA master control unit used for receiving a test starting instruction sent by the mass production tester through the tester interface, performing tests on multiple items of the I3C device to obtain test data of each item, and sending the test data of each item to the mass production tester through the tester interface; a cache connected with the FPGA master control unit and used for improving distortion of a through signal; and an I3C device carrier connected with the cache and used for placing the I3C device to be tested. Compared with the prior art, the application can be compatible with the existing mass production test equipment with a slow communication timing, and can test the high-speed I3C communication function of the MEMS device in the mass production stage.

Description

[Technical Field]

[0001] This invention relates to the field of testing technology for microelectromechanical systems (MEMS) devices, and more particularly to a mass production testing system for I3C devices. [Background Technology]

[0002] MEMS devices refer to high-tech electromechanical devices with micro-electro-mechanical systems (MEMS) and a size of only a few millimeters or even smaller. Their processing technology integrates photolithography, etching, thin film, LIGA, silicon micromachining, non-silicon micromachining and precision machining technologies.

[0003] When MEMS devices with I3C (Improved Inter-Integrated Circuit) interfaces are deployed in practical applications, many scenarios require high-speed communication. Traditional mass production test boards like the PXIE-6570 encounter issues with incomplete I3C communication timing, such as overshoot and ringing, resulting in high failure rates and poor reliability. This makes it impossible to fully verify the high-speed I3C communication function of devices in a mass production environment (FT testing), significantly impacting product yield.

[0004] Therefore, there is an urgent need to propose an improved technical solution to address the above problems. [Summary of the Invention]

[0005] One of the objectives of this invention is to provide a mass production testing system for I3C devices that is compatible with existing mass production testing equipment with slow communication timing, and to test the high-speed I3C communication function of MEMS devices during the mass production stage.

[0006] According to one aspect of the present invention, a mass production testing system for an I3C device is provided. The I3C device is a MEMS device with an I3C interface. The mass production testing system for the I3C device includes a mass production testing machine and an FPGA test board. The FPGA test board includes: a test machine interface connected between the FPGA main control unit and the mass production testing machine; an FPGA main control unit for receiving a test start command sent by the mass production testing machine through the test machine interface, executing multiple tests of the I3C device to obtain test data for each item, and sending the test data of each item to the mass production testing machine through the test machine interface; a high-speed buffer connected to the FPGA main control unit for improving signal distortion; and an I3C device carrier connected to the high-speed buffer for placing the I3C device under test.

[0007] Furthermore, the FPGA main control unit includes: a PLL unit for providing a reference frequency; an FSM state machine control unit for executing state control of the internal hardware circuits of the FPGA main control unit; an I3C communication unit for performing I3C communication; and an SPI communication unit for performing SPI communication. The PLL unit is connected to the FSM state machine control unit, the I3C communication unit, and the SPI communication unit. The FSM state machine control unit is connected to the I3C communication unit and the SPI communication unit. The I3C communication unit is connected to the high-speed buffer. The SPI communication unit is connected to the test machine interface.

[0008] Furthermore, the mass production testing system for the I3C device also includes: a host computer connected to the mass production testing machine; and a loading and sorting machine connected to the host computer for loading and sorting the I3C devices to be tested.

[0009] Furthermore, the PLL unit provides a reference frequency to the I3C communication unit, the FSM state machine control unit, and the SPI communication unit; the loading and sorting machine places the I3C device under test onto the I3C device carrier, and notifies the host computer after loading; the host computer sends a test start command to the FPGA main control unit through the mass production test machine to begin testing the I3C device under test; the mass production test machine sends one or more commands to the FSM state machine control unit through the test machine interface and the SPI communication unit. The FSM state machine control unit parses the I3C test command sent by the mass production test machine and forwards it to the I3C communication unit. The I3C communication unit communicates with the I3C device under test through the high-speed buffer and the I3C device carrier based on the I3C test command to realize the I3C test of the I3C device under test and obtain I3C test data based on the I3C test command. The FSM state machine control unit sends the I3C test data to the mass production test machine through the SPI communication unit.

[0010] Furthermore, the FPGA main control unit also includes an I2C communication unit, a high-impedance I / O port, and a gating switch. The high-impedance I / O port is connected to the FSM state machine control unit, and the high-impedance I / O port is connected to the high-speed buffer via the gating switch. The I2C communication unit is connected to the FSM state machine control unit, and the I2C communication unit is connected to the high-speed buffer via the gating switch. The I2C communication unit is also connected to the PLL unit. The I3C communication unit is connected to the high-speed buffer via the gating switch. The FSM state machine control unit is connected to the gating switch and controls the gating switch to select one of the high-impedance I / O port, the I2C communication unit, and the I3C communication unit to connect to the high-speed buffer.

[0011] Furthermore, when performing I3C testing on an I3C device, the FSM state machine control unit controls the gating switch to connect the I3C communication unit and the high-speed buffer; when performing I2C testing on an I3C device, the FSM state machine controls the gating switch to connect the I2C communication unit and the high-speed buffer. At this time, the mass production test machine sends one or more I2C test commands to the FSM state machine control unit through the test machine interface and the SPI communication unit. The FSM state machine control unit parses the I2C test commands sent by the mass production test machine and forwards them to the I2C communication unit. The I2C communication unit communicates with the I3C device under test through the high-speed buffer and the I3C device carrier based on the I2C test commands to realize the I2C testing of the I3C device under test and obtain I2C test data based on the I2C test commands. The FSM state machine control unit sends the I2C test data to the mass production test machine via the SPI communication unit. When performing other tests on the I3C device, the FSM state machine control unit controls the gating switch to connect the high-impedance I / O port and the high-speed buffer. At this time, the mass production test machine sends one or more electrical test commands to the FSM state machine control unit through the test machine interface and the SPI communication unit. The FSM state machine control unit parses the electrical test commands sent by the mass production test machine and forwards them to the high-impedance I / O port. The high-impedance I / O port performs electrical tests on the I3C device under test through the high-speed buffer and the I3C device carrier based on the electrical test commands, and obtains electrical test data based on the feedback of the electrical test commands. The FSM state machine control unit sends the electrical test data to the mass production test machine via the SPI communication unit.

[0012] Furthermore, the mass production testing machine aggregates the various test data transmitted from the FPGA test board into test data for the currently tested I3C device and uploads it to the host computer. Based on a predetermined algorithm and the test data of the currently tested I3C device, the host computer automatically analyzes and judges the pass / fail status of each test item of the currently tested I3C device. The host computer then notifies the loading and sorting machine of the pass / fail status of each test item of the currently tested I3C device. The loading and sorting machine removes the currently tested I3C device from the I3C device carrier and classifies it accordingly based on the pass / fail judgment of the currently tested I3C device by the host computer.

[0013] Furthermore, the FPGA main control unit also includes: a first FIFO buffer connected between the FSM state machine control unit and the I3C communication unit, wherein the first FIFO buffer is used to buffer the I3C test data fed back from the I3C communication unit to the FSM state machine control unit; and a second FIFO buffer connected between the FSM state machine control unit and the I3C communication unit, wherein the second FIFO buffer is used to buffer the I3C test instructions sent from the FSM state machine control unit to the I3C communication unit.

[0014] Furthermore, the FPGA main control unit also includes an LDO regulator, which is used to provide regulated power to the FPGA main control unit.

[0015] Furthermore, the I3C device is a MEMS magnetic sensor or a MEMS optical image stabilization device.

[0016] Compared with existing technologies, this invention is used for I3C functional testing of MEMS devices in the mass production stage (FT stage). It is compatible with existing mass production test equipment with slow communication timing and can reliably test the high-speed I3C communication function of MEMS devices in a mass production environment, thereby improving the product yield of I3C devices. The system structure is developed and upgraded based on existing old mass production test equipment, with low hardware cost. While improving the yield, it saves enterprises a lot of mass production testing costs. [Attached Image Description]

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0018] Figure 1This is a schematic diagram of the mass production testing system for the I3C device in one embodiment of the present invention.

Detailed Implementation Methods

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments. Unless otherwise specified, the terms "connected," "linked," and "connected" used herein to indicate electrical connection refer to direct or indirect electrical connection.

[0021] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0022] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," and "coupling" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0023] To address the problems existing in the prior art, this invention provides a mass production testing system for I3C devices, which is mainly used for I3C functional testing of MEMS devices in the mass production stage (FT stage). It should be noted that "I3C device" in this invention refers to MEMS (Micro-Electro-Mechanical System) devices with I3C interfaces, and is referred to as I3C device throughout the text.

[0024] Please refer to Figure 1 As shown, it is a schematic diagram of the mass production testing system for the I3C device in one embodiment of the present invention. Figure 1The mass production test system for the I3C (Improved Inter Integrated Circuit, i.e., the improved I2C standard) device shown includes an FPGA (Field Programmable Gate Array) test board 1, a mass production test machine 2, a host computer 3, and a loading and sorting machine 4.

[0025] The FPGA test board 1 includes an FPGA main control unit 11, an I3C device carrier 12, a high-speed buffer 13, and a test machine interface 14. The test machine interface 14 connects the FPGA main control unit 11 and the mass production test machine 2. The FPGA main control unit 11 receives test start commands from the mass production test machine 2 via the test machine interface 14 and executes multiple tests on the I3C device to obtain test data for each test. This test data is then transmitted to the mass production test machine 2 via the test machine interface 14. The high-speed buffer 13, connected to the FPGA main control unit 11, is used to reduce signal distortion. The I3C device carrier 12, connected to the high-speed buffer 13, is used to hold the I3C device under test.

[0026] The FPGA main control unit 11 includes a PLL (Phase Locked Loop) unit 111, an FSM (Finite State Machine) state machine control unit 112, an I3C communication unit 113, and an SPI (Serial Peripheral Interface) communication unit 114.

[0027] PLL unit 111 is used to provide a reference frequency; FSM state machine control unit 112 is used to execute state control of the internal hardware circuit of FPGA main control unit 11; I3C communication unit 113 is used to perform I3C communication (or to simulate I3C communication timing); SPI communication unit 114 is used to perform SPI communication (or to simulate SPI communication).

[0028] PLL unit 111 is connected to FSM state machine control unit 112, I3C communication unit 113 and SPI communication unit 114; FSM state machine control unit 112 is connected to I3C communication unit 113 and SPI communication unit 114; I3C communication unit 113 is connected to high-speed buffer 13 (i.e. I3C communication unit 113 is connected to the I3C device under test in I3C device carrier 12 through high-speed buffer 13); SPI communication unit 114 is connected to test machine interface 14 (i.e. SPI communication unit 114 is connected to mass production test machine 2 through test machine interface 14).

[0029] The host computer 3 is connected to the mass production testing machine 2; the loading and sorting machine 4 is connected to the host computer 3 and is used for loading and sorting the I3C devices to be tested.

[0030] The following is a detailed introduction Figure 1 The working principle of the mass production testing system for the I3C device shown.

[0031] Upon system power-on initialization, PLL unit 111 provides a reference frequency to I3C communication unit 113, FSM state machine control unit 112, and SPI communication unit 114. The loading and sorting machine (also known as handler) 4 automatically feeds (or places) the I3C device under test from the reel onto the I3C device carrier (also known as socket) 12. Once the I3C device under test is placed in the I3C device carrier 12, its signals are electrically connected to the FPGA test board 1. After loading, the loading and sorting machine 4 notifies the host computer 3. The host computer 3 sends a test start command to the FPGA main control unit 11 through the mass production test machine 2 to begin testing the I3C device under test.

[0032] The mass production test machine 2 sends one or more I3C test commands to the FSM state machine control unit 112 through the test machine interface 14 and the SPI communication unit 114. The FSM state machine control unit 112 parses the I3C test commands sent by the mass production test machine 2 and forwards them to the I3C communication unit 113. Based on the received I3C test commands, the I3C communication unit 113 communicates with the I3C device under test through the high-speed buffer 13 and the I3C device carrier 12 to realize the I3C test of the I3C device under test and obtain the I3C test data based on the feedback of the I3C test commands. The FSM state machine control unit 112 sends the I3C test data to the mass production test machine 2 through the SPI communication unit 114. Specifically, the FSM state machine control unit 112 parses the I3C test command sent by the mass production test machine 2 and forwards it to the I3C communication unit 113. It drives the I3C communication unit 113 to simulate the I3C communication timing. Through a high-speed buffer 13, it strongly pulls up the simulated I3C communication timing to improve the distortion signal in the simulated I3C communication timing. After stabilizing the I3C communication timing, it transmits the stable I3C communication timing to the I3C device under test in the I3C device carrier 12. The I3C device under test acts as a slave device and receives the I3C test command. The system returns the corresponding I3C test data. After the signal is kept undistorted by the high-speed buffer 13, the data is returned to the I3C communication unit 113. The I3C communication unit 113 further transmits the returned I3C communication timing (i.e., I3C test data) to the FSM state machine control unit 112. The FSM state machine control unit 112 drives the SPI communication unit 114 to perform high-speed SPI protocol communication, converting the returned I3C test data into SPI communication signals and sending them to the mass production test machine 2 through the test machine interface 14.

[0033] exist Figure 1 In the specific embodiment shown, the FPGA main control unit 11 further includes a first FIFO (First Input First Output) buffer 115 and a second FIFO buffer 116. The first FIFO buffer 115 is connected between the FSM state machine control unit 112 and the I3C communication unit 113, and is used to buffer I3C test data fed back from the I3C communication unit to the FSM state machine control unit 112. The second FIFO buffer 116 is connected between the FSM state machine control unit 112 and the I3C communication unit 113, and is used to buffer I3C test commands sent from the FSM state machine control unit 112 to the I3C communication unit 113. This reduces the problem of lost I3C test data or I3C test commands, improving the stability and reliability of the test system.

[0034] exist Figure 1 In the specific embodiment shown, the FPGA main control unit 11 further includes an I2C communication unit 117, a high-impedance I / O port 118, and a gating switch 119. The high-impedance I / O port 118 is connected to the FSM state machine control unit 112, and is connected to the high-speed buffer 13 via the gating switch 119. The I2C communication unit 117 is connected to the FSM state machine control unit 112, and is connected to the high-speed buffer 13 via the gating switch 119. The I2C communication unit 117 is also connected to the PLL unit 111. The I3C communication unit 113 is connected to the high-speed buffer 13 via the gating switch 119. The FSM state machine control unit 112 is connected to the gating switch 119, controlling the gating switch 119 to select one of the high-impedance I / O port 118, the I2C communication unit 117, and the I3C communication unit 113 to connect to the high-speed buffer 13.

[0035] Correspondingly, Figure 1 The working principle of the mass production testing system for the I3C device shown also includes the following.

[0036] When performing I3C testing on an I3C device (see above for details), the FSM state machine control unit 112 controls the gating switch 119 to connect the I3C communication unit 113 and the high-speed buffer 13.

[0037] When performing I2C testing on an I3C device, the FSM state machine control unit 112 controls the gating switch 119 to connect the I2C communication unit 117 and the high-speed buffer 13. At this time, the mass production test machine 2 sends one or more I2C test commands to the FSM state machine control unit 112 through the test machine interface 14 and the SPI communication unit 114. The FSM state machine control unit 112 parses the I2C test commands sent by the mass production test machine and forwards them to the I2C communication unit 117. The I2C communication unit 117 communicates with the I3C device under test through the high-speed buffer 13 and the I3C device carrier 12 based on the I2C test commands to realize the I2C test of the I3C device under test and obtain the I2C test data based on the feedback of the I2C test commands. The FSM state machine control unit 112 sends the I2C test data to the mass production test machine 2 through the SPI communication unit 114. Both I2C and I3C communication reuse the SDA / SCL (SDA is a bidirectional data line, SCL is a clock line) communication bus.

[0038] When performing tests on I3C devices other than I3C and I2C tests (e.g., leakage current testing), the FSM state machine control unit 112 controls the gating switch 119 to connect the high-impedance I / O port 118 and the high-speed buffer 13. At this time, the mass production test machine 2 sends one or more electrical test commands to the FSM state machine control unit 112 through the test machine interface 14 and the SPI communication unit 114. The FSM state machine control unit 112 parses the electrical test commands sent by the mass production test machine 2 and forwards them to the high-impedance I / O port 118. Based on the electrical test commands, the high-impedance I / O port 118 performs electrical tests on the I3C device under test through the high-speed buffer 13 and the I3C device carrier 12, and obtains electrical test data based on the feedback of the electrical test commands. The FSM state machine control unit 112 sends the electrical test data to the mass production test machine 2 through the SPI communication unit 114. The FSM state machine control unit 112 controls the gating switch 119 to connect the high-impedance I / O port 118 and the high-speed buffer 13. This enables the SDA and SCL communication buses to be in a high-impedance state, preventing leakage current from flowing back into the electrical signal circuit of the FPGA test board 1, which would lead to inaccurate leakage current test results. Reducing current backflow also extends the service life of the FPGA test board 1 and the system to some extent.

[0039] The mass production testing machine 2 aggregates the various test data (e.g., I2C test data, I3C test data, electrical test data) transmitted from the FPGA test board 1 into test data for the currently tested I3C device, and uploads it to the host computer 3. Based on a predetermined algorithm and the test data of the currently tested I3C device, the host computer 3 automatically analyzes and judges the PASS or Fail (i.e., pass / fail) status of each test item for the currently tested I3C device (or the I3C device under test). The host computer 3 notifies the loading and sorting machine 4 of the PASS or Fail status of the currently tested I3C device. The loading and sorting machine 4 removes the currently tested I3C device from the I3C device carrier 12 and processes it, classifying it accordingly based on the host computer 3's judgment. For example, if the host computer 3 judges it as Fail, the loading and sorting machine 4 places the currently tested I3C device into different failure bins according to the failed item. Once the current I3C device under test has been processed, the loading and sorting machine 4 automatically takes a new material from the tape, places it into the I3C test carrier 12, and notifies the host computer 3 to start the test.

[0040] In the mass production testing system for I3C devices provided by this invention, the structure and model of the mass production tester 2 are not limited. For ease of understanding, the mass production tester 2 model used can be a PXIE-6570 Jetek tester. By simulating timing, it can only achieve slow I3C communication of about 400KHz, and cannot stably test the I3C function in high-speed mode (e.g., 12.5MHz). By setting up the FPGA test board 1 and using the FPGA to edit and set the logic array module, the operating frequency can be configured up to 500MHz. The internal PLL unit 111 provides a 50MHz reference frequency to the FSM state machine control unit 112; the PLL unit 111 provides a 52MHz reference frequency to the I3C communication unit 113, and an 8MHz reference frequency to the SPI communication unit 113, providing a basic frequency guarantee for simulating high-speed I3C communication. Combined with the high-speed TTL of the FPGA main control unit 11 on the FPGA test board 1... The I / O model (a unique attribute of FPGA) enables high-speed signal communication and returns I3C test data via SPI communication, providing a high-speed interface for returning I3C test data to the mass production test machine 2. On the other hand, a high-speed buffer 13, such as a 74AVC1T245 high-speed buffer, is set between the I3C communication unit 113 and the I3C device carrier 12. However, the type of high-speed buffer 13 is not limited to this. It improves the timing distortion of the signal waveform through strong pull-up, thereby enhancing the stability and accuracy of communication data under high-speed I3C communication.

[0041] Furthermore, in the mass production testing system for I3C devices provided by this invention, the power supply on the FPGA test board 1 is not limited to a specific form, but is preferably an LDO (low dropout regulator) regulated power supply 16. For example, an LMS117 is selected to provide a stable power supply for the FPGA main control unit 11, thereby reducing system test errors caused by power supply noise.

[0042] The mass production testing system for I3C devices provided by this invention can be used to test MEMS magnetic sensors, MEMS OIS optical image stabilization devices, etc. For example, when verifying the I3C communication of a MEMS magnetic sensor, the host computer 3 sends an I3C command for TMM (Take Magnetic Measurement), or when verifying the I3C communication of an OIS optical image stabilization device, the host computer 3 sends an I3C command for Read OIS status. The system judges whether the I3C test result passes by feeding back test data to the host computer 5. This system is compatible with older mass production testing equipment with slow communication timing and has a wide range of applicable products. When performing high-speed I3C communication function testing in a mass production environment, it has strong reliability and test stability, solving the problem that older mass production testing machines cannot fully verify the high-speed I3C communication function of devices in a mass production environment (FT testing). This improves the product yield of I3C devices. The system structure is developed and upgraded based on existing older mass production testing machines, with low hardware costs, saving enterprises a lot of mass production testing costs while improving the yield.

[0043] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0044] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications and variations to the above embodiments within the scope of the present invention.

Claims

1. A mass production testing system for an I3C device, wherein the I3C device is a MEMS device with an I3C interface, characterized in that, It includes a mass production testing machine and an FPGA test board, wherein the FPGA test board includes: A test machine interface, which connects the FPGA main control unit and the mass production test machine; The FPGA main control unit is used to receive the test start command sent by the mass production test machine through the test machine interface, and execute multiple tests of the I3C device to obtain test data for each item, and send the test data of each item to the mass production test machine through the test machine interface; A high-speed buffer, which is connected to the FPGA main control unit, is used to improve the distortion of the passed signal; An I3C device carrier, connected to the high-speed buffer, is used to hold the I3C device under test. The FPGA main control unit includes: The PLL unit is used to provide a reference frequency; The FSM state machine control unit is used to perform state control of the internal hardware circuits of the FPGA main control unit. I3C communication unit, which is used for I3C communication; SPI communication unit, which is used for SPI communication; Specifically, the PLL unit is connected to the FSM state machine control unit, the I3C communication unit, and the SPI communication unit; the FSM state machine control unit is connected to the I3C communication unit and the SPI communication unit; the I3C communication unit is connected to the high-speed buffer; and the SPI communication unit is connected to the test machine interface. It also includes: A host computer, which is connected to the mass production testing machine; A loading and sorting machine, which is communicatively connected to the host computer, is used for loading and sorting the I3C devices to be tested. The PLL unit provides a reference frequency to the I3C communication unit, the FSM state machine control unit, and the SPI communication unit; The loading and sorting machine places the I3C device to be tested onto the I3C device carrier, and notifies the host computer after loading the device. The host computer sends a test start command to the FPGA main control unit through the mass production test machine to start the test of the I3C device under test; The mass production test machine sends one or more I3C test commands to the FSM state machine control unit through the test machine interface and the SPI communication unit. The FSM state machine control unit parses the I3C test commands sent by the mass production test machine and forwards them to the I3C communication unit. The I3C communication unit communicates with the I3C device under test through the high-speed buffer and the I3C device carrier based on the I3C test commands to realize the I3C test of the I3C device under test and obtain I3C test data based on the I3C test commands. The FSM state machine control unit sends the I3C test data to the mass production test machine through the SPI communication unit.

2. The mass production testing system for I3C devices according to claim 1, characterized in that, The FPGA main control unit also includes an I2C communication unit, a high-impedance I / O port, and a selection switch. The high-impedance I / O port is connected to the FSM state machine control unit, and the high-impedance I / O port is connected to the high-speed buffer via the gating switch; The I2C communication unit is connected to the FSM state machine control unit, and the I2C communication unit is connected to the high-speed buffer via the gating switch. The I2C communication unit is also connected to the PLL unit. The I3C communication unit is connected to the high-speed buffer via the gating switch; The FSM state machine control unit is connected to the gating switch and controls the gating switch to select one of the high-impedance I / O port, the I2C communication unit, and the I3C communication unit to connect to the high-speed buffer.

3. The mass production testing system for I3C devices according to claim 2, characterized in that, When performing I3C testing on an I3C device, the FSM state machine control unit controls the gating switch to connect the I3C communication unit and the high-speed buffer; When performing I2C testing on an I3C device, the FSM state machine controls the gating switch to connect the I2C communication unit and the high-speed buffer. At this time, the mass production test machine sends one or more I2C test commands to the FSM state machine control unit through the test machine interface and the SPI communication unit. The FSM state machine control unit parses the I2C test commands sent by the mass production test machine and forwards them to the I2C communication unit. The I2C communication unit communicates with the I3C device under test through the high-speed buffer and the I3C device carrier based on the I2C test commands to realize the I2C test of the I3C device under test and obtain I2C test data based on the I2C test commands. The FSM state machine control unit sends the I2C test data to the mass production test machine through the SPI communication unit. When performing other tests on the I3C device, the FSM state machine control unit controls the gating switch to connect the high-impedance I / O port and the high-speed buffer. At this time, the mass production test machine sends one or more electrical test commands to the FSM state machine control unit through the test machine interface and the SPI communication unit. The FSM state machine control unit parses the electrical test commands sent by the mass production test machine and forwards them to the high-impedance I / O port. The high-impedance I / O port performs electrical tests on the I3C device under test through the high-speed buffer and the I3C device carrier based on the electrical test commands, and obtains electrical test data based on the feedback of the electrical test commands. The FSM state machine control unit sends the electrical test data to the mass production test machine through the SPI communication unit.

4. The mass production testing system for I3C devices according to claim 3, characterized in that, The mass production test machine summarizes the various test data transmitted from the FPGA test board into the test data of the I3C device currently being tested, and uploads it to the host computer. The host computer automatically analyzes and judges the pass / fail status of each test item of the currently tested I3C device based on a predetermined algorithm and the test data of the currently tested I3C device. The host computer notifies the loading and sorting machine of the pass / fail status of each test item of the currently tested I3C device. The loading and sorting machine removes the currently tested I3C device from the I3C device carrier and classifies it accordingly based on the host computer's judgment of whether the currently tested I3C device is qualified or unqualified.

5. The mass production testing system for I3C devices according to any one of claims 1-4, characterized in that, The FPGA main control unit also includes; A first FIFO buffer is connected between the FSM state machine control unit and the I3C communication unit. The first FIFO buffer is used to buffer the I3C test data fed back from the I3C communication unit to the FSM state machine control unit. A second FIFO buffer is connected between the FSM state machine control unit and the I3C communication unit. The second FIFO buffer is used to buffer the I3C test commands sent by the FSM state machine control unit to the I3C communication unit.

6. The mass production testing system for I3C devices according to claim 1, characterized in that, The FPGA main control unit also includes an LDO regulator. The LDO regulator is used to provide regulated power to the FPGA main control unit.

7. The mass production testing system for I3C devices according to claim 1, characterized in that, The I3C device is a MEMS magnetic sensor or a MEMS optical image stabilization device.

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