Testing method, device, equipment, medium and system for testing structure on wafer
By using image acquisition equipment and an automated process framework, the problem of coordinate deviation of the test structure on the wafer was solved, high-precision detection was achieved, wafer shipment yield and inspection efficiency were improved, and the accuracy of test results was ensured.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGZHOU ZENGXIN TECH CO LTD
- Filing Date
- 2026-02-12
- Publication Date
- 2026-05-08
AI Technical Summary
In existing technologies, manual intervention during the coordinate transfer process of the Test Structure on Wafer (TSK) leads to coordinate deviations, resulting in problems such as die kneeling and wafer scratches, which affect wafer shipment yield and test data accuracy. Furthermore, manual calibration is inefficient and cannot meet the needs of large-scale semiconductor manufacturing.
The system automatically acquires images of the test structure using image acquisition equipment, and achieves high-precision detection of the test structure coordinates through border and character recognition technology. This establishes an automated process framework, reduces manual intervention, and improves detection efficiency and accuracy.
It achieves high-precision detection of the test structure coordinates, avoids wafer damage and test data abnormalities caused by coordinate deviations, improves wafer shipment yield, and enhances detection efficiency and result reliability.
Smart Images
Figure CN122003136A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor testing technology, and more specifically, to a testing method, apparatus, device, medium, and system for testing structures on a wafer. Background Technology
[0002] In the semiconductor manufacturing process, electrical performance testing of wafers is a critical step in ensuring product quality and yield. Among these, the test key (TSK), as the core pin insertion point of the electrical test pin card, directly determines the reliability of the test results due to its coordinate accuracy. The TSK is typically placed within the dicing grooves of the wafer, avoiding the effective chip area, thus not affecting the normal function of the chip while enabling comprehensive monitoring of the wafer manufacturing process.
[0003] After the etching process is completed, the PIE (Process Integration Engineer) or TDPIE (Research and Development Process Integration Engineer) provides TSK coordinate data for the WAT (Wafer Acceptance Testing) equipment to identify and execute the testing process. However, due to the human intervention in the coordinate transfer process, deviations can easily occur between the given TSK coordinates and the actual TSK coordinates on the wafer. When this deviation exceeds a reasonable range, it can lead to a series of irreversible adverse consequences. For example, during pin jamming, physical damage such as pin failure or wafer scratches can easily occur, directly increasing the wafer defect rate and seriously affecting the wafer shipment yield. At the same time, coordinate deviations or disordered TSK coordinates can also cause abnormal test data, triggering WAT equipment test errors and interfering with the judgment of wafer process stability.
[0004] To address these issues, WAT engineers (Wafer Test Engineers) must meticulously calibrate the TSK coordinates one by one when setting up prober programs. Currently, the mainstream calibration method in the industry is manual inspection. WAT engineers manually input the coordinates one by one on the prober equipment and visually assess the match between the actual TSK position and the input coordinates. However, with the advancement of semiconductor technology, the number of TSKs on a single wafer has increased dramatically, while the efficiency of manual inspection is only about 200 TSKs per hour. For wafers with a large number of TSKs, this method consumes a significant amount of WAT engineers' time, significantly reducing the overall efficiency of the testing process. Furthermore, the subjectivity and fatigue inherent in manual operation further increase the risk of errors in coordinate calibration, failing to fundamentally guarantee the accuracy of TSK coordinates and hindering the large-scale production and yield improvement of semiconductor manufacturing. Summary of the Invention
[0005] This application addresses the shortcomings of the prior art by providing a testing method, apparatus, equipment, medium, and system for testing structures on a wafer, in order to solve the problems existing in the prior art.
[0006] The technical solution adopted in the embodiments of this application is as follows: In a first aspect, embodiments of this application provide a testing method for a test structure on a wafer, including: Obtain the test structure coordinate file of the wafer to be tested; the test structure coordinate file includes: the identification characters and identification positions of multiple test structures on the wafer to be tested, wherein the identification position is the position of the identification character on the corresponding test structure; Based on the identification positions of the multiple test structures, detection images of the multiple test structures are acquired using an image acquisition device; The test structure is tested based on the detection image of the test structure.
[0007] In one embodiment, acquiring detection images of the multiple test structures using an image acquisition device based on the identification positions of the multiple test structures includes: Based on the identification position of the first test structure among the plurality of test structures, the image acquisition device is controlled to move to the identification position of the first test structure in order to obtain the detection image of the first test structure; The image acquisition device is sequentially moved to the marked positions of other test structures to acquire the detection images of the other test structures in turn.
[0008] In one embodiment, each test structure includes multiple test keys, and the identifier position is the position of the identifier character on the first test key of the corresponding test structure; The step of acquiring detection images of multiple test structures using an image acquisition device based on the identification positions of the multiple test structures includes: Based on the identification position of each test structure, the image acquisition device is used to acquire the image of the first test key on each test structure as the detection image of each test structure.
[0009] In one embodiment, testing the test structure based on the detected image of the test structure includes: Perform border recognition on the image of the first test key to determine the detection border of the first test key; The test structure is tested based on the detection border of the first test key.
[0010] In one embodiment, testing the test structure based on the detection border of the first test key includes: Perform character recognition on the image of the first test key to obtain the detection position of the identifier character on the corresponding test structure; Based on the detection position of the identified character, determine the expected border of the first test key; Determine whether each edge in the detection border and the expected border of the first test key meets the preset deviation condition; If all the edges meet the preset deviation conditions, then the test structure is determined to have passed the test. If at least one edge does not meet the preset deviation condition, then the test structure test is determined to be unsuccessful.
[0011] In one embodiment, before determining whether each edge in the detection border and the desired border of the first test key meets the preset deviation condition, the method further includes: Based on the pad size corresponding to the test key, the preset deviation condition and the shooting range of the image acquisition device are determined.
[0012] Secondly, embodiments of this application provide a test apparatus for a test structure on a wafer, comprising: The acquisition module is used to acquire the test structure coordinate file of the wafer to be tested; the test structure coordinate file includes: the identification characters and identification positions of multiple test structures on the wafer to be tested, wherein the identification position is the position of the identification character on the corresponding test structure; The acquisition module is used to acquire detection images of the multiple test structures using an image acquisition device based on the identification positions of the multiple test structures; The testing module is used to test the test structure based on the detection image of the test structure.
[0013] Thirdly, embodiments of this application provide a control device, including: a processor, a storage medium, and a bus. The storage medium stores program instructions executable by the processor. When the control device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the test method for the on-wafer test structure described in any of the above embodiments.
[0014] Fourthly, embodiments of this application provide a readable storage medium storing program instructions, which, when executed by a processor, implement the test method for the on-wafer test structure described in any of the above embodiments.
[0015] Fifthly, embodiments of this application provide a testing system, including: a control device, a probe machine, a testing machine, and an image acquisition device; The probe machine, the test machine, and the image acquisition device are respectively connected to the control device; The control device is used to perform the test method for the on-wafer test structure described in any of the above embodiments.
[0016] The beneficial effects of this application are as follows: This application provides a testing method for test structures on a wafer, comprising: obtaining a test structure coordinate file of the wafer to be tested; the test structure coordinate file includes: identification characters and identification positions of multiple test structures on the wafer to be tested, wherein the identification position is the position of the identification character on the corresponding test structure; acquiring detection images of the multiple test structures using an image acquisition device based on the identification positions of the multiple test structures; and testing the test structures based on the detection images of the test structures.
[0017] This application establishes a test automation process framework, which reduces manual intervention and test time, while achieving high-precision detection of the Test Structure (TSK) coordinates. This avoids problems such as pin drop, wafer scratches, and abnormal test data caused by coordinate deviations, thereby improving wafer shipment yield. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is one of the flowcharts illustrating the testing method for the on-wafer test structure provided in the embodiments of this application; Figure 2 A schematic diagram of the test structure provided in this application; Figure 3 A second schematic flowchart illustrating the testing method for the on-wafer test structure provided in this application embodiment; Figure 4 The third schematic flowchart of the test method for the test structure on the wafer provided in the embodiments of this application; Figure 5 The fourth schematic flowchart of the test method for the on-wafer test structure provided in the embodiments of this application; Figure 6 This is a schematic diagram of the test apparatus for the on-wafer test structure provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the control device provided in an embodiment of this application. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.
[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0022] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0023] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.
[0024] First, this application provides a testing system, including a control device, a probe station, a tester, and an image acquisition device.
[0025] The probe station, testing station, and image acquisition device are all connected to the control equipment. The probe station includes a stage and probes. The stage is used to support the wafer to be tested, and the probes are used to achieve precise positioning of the wafer and physical alignment of the test structure (TSK). The testing station provides the coordinate file of the test structure, generates test instructions and transmits them to the control equipment, and receives the test data fed back by the control equipment. The image acquisition device is integrated into the probe station and has high-resolution imaging capability below 5μm. It is used to capture images of the test structure on the wafer to be tested supported on the probe station and transmit them to the control equipment.
[0026] The control device is used to perform the test method for the wafer-on-a-chip test structure according to any of the following embodiments. The control device may be, for example, a terminal-facing computer device or a back-end server.
[0027] Based on this, embodiments of this application provide a test method for a test structure on a wafer. The following examples, in conjunction with the accompanying drawings, provide specific illustrations of the test method for a test structure on a wafer provided in this application.
[0028] Figure 1This is one of the flowcharts illustrating the test method for the on-wafer test structure provided in the embodiments of this application, such as... Figure 1 As shown, the method may include: S101. Obtain the test structure coordinate file of the wafer to be tested.
[0029] The test structure coordinate file may include identification characters and their positions for multiple test structures on the wafer under test. The identification position is the location of the identification character on the corresponding test structure.
[0030] In this embodiment, the test structure coordinate file is a die file, provided by the tester, which contains the identification characters (such as P01, P02, P03, etc.) and identification positions of multiple test structures (TSKs) on the wafer to be tested.
[0031] The identifier position is the position of the identifier character on the corresponding test structure, and each test structure can include multiple test keys. Specifically, the identifier position can be the position of the identifier character on the first test key on the corresponding test structure.
[0032] In this embodiment, the test structure coordinate file also includes coordinate data of each test structure, character order information, pad size data of each test key on the test structure, and the relative positional relationship between the pads of the test key and the identification characters.
[0033] Figure 2 A schematic diagram of the test structure provided in this application, such as Figure 2 As shown, the test structure (TSK) is an overall structure on the wafer dicing groove used for process monitoring and electrical testing. A TSK contains multiple test keys, and the pads are the core metal contact components on each test key for pins to be secured.
[0034] Specifically, a test structure is an independent test unit located within a wafer dicing slot. It is an overall structure used to monitor the stability of wafer manufacturing processes and perform electrical tests. Each test structure corresponds to a set of specific process parameter test requirements (such as metal layer resistance and dielectric layer insulation tests). Test keys are the constituent units of a test structure. A test structure contains multiple test keys, each corresponding to a specific electrical parameter test function. They are sub-components of the test structure that enable process monitoring. Pads are the metal contact areas (aluminum / copper material) on the surface of each test key. They are the areas where the probes of the probe machine directly insert their pins and are used to transmit test signals (voltage / current). They are the core interface connecting the test keys to the test machine.
[0035] S102. Based on the identification positions of multiple test structures, use an image acquisition device to acquire detection images of multiple test structures.
[0036] In this embodiment, based on the identification position of each test structure, the probe station can be precisely positioned and the image acquisition device can work together to obtain detection images of multiple test structures. Specifically, the detection image is the image of the first test key on each test structure.
[0037] S103. Test the test structure based on the detection image of the test structure.
[0038] In this embodiment, the test structure can be tested based on the detection image of the test structure, and an automated test process framework is built. While reducing manual intervention and detection time, it achieves high-precision detection of the coordinates of the test structure (TSK), avoiding problems such as pin failure, wafer scratches, and abnormal test data caused by coordinate deviation, and ensuring wafer shipment yield.
[0039] Figure 3 This is a second schematic flowchart of the test method for the on-wafer test structure provided in the embodiments of this application, as shown below. Figure 3 As shown, step S102, which involves acquiring detection images of multiple test structures using an image acquisition device based on the identification positions of these test structures, may include: S201. Based on the identification position of the first test structure among multiple test structures, control the image acquisition device to move to the identification position of the first test structure in order to obtain the detection image of the first test structure.
[0040] Among them, after receiving the test structure coordinate file transmitted by the test machine, the control equipment first parses the position of the first test structure identifier in the file (i.e., Figure 2 In the P01 section, the stage of the driving probe unit moves the wafer under test, so that the image acquisition device is precisely aligned with the marked position (which corresponds to the first test key position of the first test structure). The image acquisition device is then activated to capture the detection image of the first test structure, and the marked position of the first test structure is defined as the origin of the coordinate system, providing a reference for the positioning of subsequent test structures.
[0041] S202. Sequentially control the image acquisition device to move to the marked positions of other test structures in order to acquire the detection images of other test structures in sequence.
[0042] In this embodiment, the stage can be automatically moved to the identification position of the next test structure (corresponding to the first test key position of the next test structure) according to the coordinate data and character order of each test structure recorded in the test structure coordinate file. After the position is stable, the image acquisition device automatically captures and collects the detection image of the test structure. The above steps are repeated until the detection image acquisition of all test structures on the wafer is completed.
[0043] This embodiment establishes a positioning reference with the marker position of the first test structure as the origin, ensuring the consistency and accuracy of positioning for all subsequent test structures. Furthermore, it automatically moves and acquires images based on the marker position, replacing the manual input of coordinates and visual search for the test structure positions, thus improving detection efficiency. The use of image acquisition equipment also enables the standardization and consistency of image acquisition, avoiding recognition errors caused by manual detection, and providing high-quality data support for border recognition and character recognition in the following embodiments.
[0044] Figure 4 This is the third schematic flowchart of the test method for the on-wafer test structure provided in the embodiments of this application, as shown below. Figure 4 As shown, step S103, testing the test structure based on the detected image of the test structure, may include: S301. Perform border recognition on the image of the first test key to determine the detection border of the first test key.
[0045] In this embodiment, the image of the first test key is subjected to border recognition, the actual border of the pad corresponding to the first test key is extracted, and the actual border is used as the detection border of the first test key.
[0046] S302. Test the test structure based on the detection border of the first test key.
[0047] In this embodiment, the deviation between the detected border and the preset expected border is compared, and the consistency of the test structure's identifier is verified by character recognition to comprehensively determine whether the coordinates of the test structure are accurate. The expected border is used to represent the theoretical design position and theoretical design size of the pads.
[0048] It should be noted that the acceptable threshold for the deviation between the detected border and the expected border can be set by the engineer according to the actual application scenario. In other words, it supports custom configuration of the acceptable threshold for the deviation between the detected border and the expected border.
[0049] Figure 5 This is the fourth flowchart illustrating the test method for the on-wafer test structure provided in the embodiments of this application. Figure 5 As shown, S302 may specifically include: S401. Perform character recognition on the image of the first test key to obtain the detection position of the character on the corresponding test structure.
[0050] In this embodiment, the control device performs optical character recognition (OCR) on the detection image of the first test key, extracts the identifier characters (P01, P02, P03, etc.) of the test structure in the image, and determines the actual position of the identifier character in the image as the detection position of the identifier character.
[0051] S402. Determine the expected border of the first test key based on the detection position of the identifier character.
[0052] Specifically, based on the pad size data of the test key recorded in the test structure coordinate file, and taking the detection position (actual position) of the identification character in the image determined by S401 as a reference, combined with the relative positional relationship between the pad of the test key and the identification character recorded in the test structure coordinate file, the theoretical design border that the first test key should have, i.e. the expected border, can be calculated and determined. The size of the expected border matches the actual size of the PAD and reserves a reasonable safety margin to ensure that qualified PADs can be completely selected.
[0053] Specifically, firstly, based on the detection position of the identifier character obtained by S401, the theoretical design position of the pad in the image is calculated according to the design relative position of the identifier character and the test key pad in the test structure coordinate file (including the relative distance and orientation between the identifier character and the test key pad). Then, based on the pad size data recorded in the file, the actual size of the pad is matched with the theoretical position as the center and a safety margin is reserved, and finally the expected border of the first test key is formed.
[0054] S403. Determine whether each edge in the detection border and the expected border of the first test key meets the preset deviation conditions.
[0055] In this embodiment, based on the testing requirements of the test structure and the probe positioning accuracy of the probe machine, a preset deviation condition is set. For example, the preset deviation condition can be that the deviation between each edge of the detection frame and the expected frame is ≤3μm.
[0056] The preset deviation conditions and the shooting range of the image acquisition device are determined based on the preset pad size corresponding to the test key, ensuring that the shooting range can completely cover the pad and identification characters corresponding to the test key, meeting the requirements of border recognition and character recognition. For example Figure 2 In the image acquisition device, the shooting range includes the identification characters and the pad corresponding to the first test key.
[0057] S404. If all edges meet the preset deviation conditions, the test structure is deemed to have passed the test.
[0058] In this embodiment, when the deviation of all corresponding edges between the detected border and the expected border is ≤3μm, and the identification characters obtained by OCR are consistent with the order of the identification characters of the test structure recorded in the test structure coordinate file, it is determined that the actual position of the first test key matches the theoretical design position, the coordinates of the test structure are accurate, the test passes, the test machine records the qualified information of the test structure, and continues to execute the test process of the next test structure.
[0059] S405. If at least one edge does not meet the preset deviation condition, the test structure test is determined to be unsuccessful.
[0060] In this embodiment, when the deviation of any edge between the detected border and the expected border is greater than 3μm, or when the order of the identifier characters obtained by OCR recognition is inconsistent with the order of the identifier characters of the test structure recorded in the test structure coordinate file, it is considered that the actual position of the first test key deviates from the theoretical design position, the coordinates of the test structure are determined to be abnormal, and the test fails. The test machine records the test information of the test structure (including the coordinates, deviation value, and character mismatch) and pauses the test process, waiting for manual review and verification, to avoid irreversible damage such as pin failure and wafer scratches caused by coordinate errors.
[0061] This embodiment uses graphic features and character features as a dual verification mechanism to improve the reliability of test results. Furthermore, it quantifies the coordinate deviation judgment criteria, avoids the subjectivity and fatigue errors of manual judgment, and achieves the standardization and reproducibility of test results.
[0062] The apparatus, equipment, and storage medium for performing the test method for the wafer-on-a-chip structure provided in any of the above embodiments of this application will be explained below. The specific implementation process and the resulting technical effects are the same as those in the corresponding method embodiments. For the sake of brevity, the parts not mentioned in the following embodiments can be referred to the corresponding content in the method embodiments.
[0063] Figure 6 This is a schematic diagram of the test apparatus for the on-wafer test structure provided in the embodiments of this application, as shown below. Figure 6 As shown, this application provides a test apparatus for a test structure on a wafer, which may include: The acquisition module 10 is used to acquire the test structure coordinate file of the wafer to be tested. The test structure coordinate file includes: the identification characters and identification positions of multiple test structures on the wafer to be tested, where the identification position is the position of the identification character on the corresponding test structure.
[0064] The acquisition module 20 is used to acquire detection images of multiple test structures using an image acquisition device based on the identification positions of multiple test structures.
[0065] The test module 30 is used to test the test structure based on the detection image of the test structure.
[0066] Optionally, the acquisition module 20 is further configured to control the image acquisition device to move to the identification position of the first test structure among the plurality of test structures, so as to acquire the detection image of the first test structure; and sequentially control the image acquisition device to move to the identification positions of other test structures, so as to acquire the detection images of the other test structures sequentially.
[0067] Optionally, each test structure includes multiple test keys, and the identification position is the position of the first test key of the identification character on the corresponding test structure; the acquisition module 20 is further configured to acquire the image of the first test key on each test structure as the detection image of each test structure based on the identification position of each test structure using the image acquisition device.
[0068] Optionally, the testing module 30 is further configured to perform border recognition on the image of the first test key to determine the detection border of the first test key; and to test the test structure based on the detection border of the first test key.
[0069] Optionally, the testing module 30 is further configured to perform character recognition on the image of the first test key to obtain the detection position of the identifier character on the corresponding test structure; determine the expected border of the first test key based on the detection position of the identifier character; determine whether each edge in the detection border and the expected border of the first test key meets a preset deviation condition; if each edge meets the preset deviation condition, the test structure is determined to pass the test; if at least one edge does not meet the preset deviation condition, the test structure is determined to fail the test.
[0070] Optionally, the apparatus of this application further includes a determining module, used to determine the preset deviation condition and the shooting range of the image acquisition device based on the pad size corresponding to the test key.
[0071] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.
[0072] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).
[0073] Figure 7 This is a schematic diagram of the structure of the control device provided in the embodiments of this application, such as... Figure 7 As shown, this application also provides a control device, including a processor 100, a storage medium 200 and a bus 300. The storage medium stores program instructions that can be executed by the processor. When the control device is running, the processor communicates with the storage medium through the bus, and the processor executes the program instructions to implement the test method for the on-wafer test structure provided in any of the above embodiments.
[0074] This application also provides a readable storage medium storing program instructions, which, when executed by a processor, implement the test method for the on-wafer test structure provided in any of the above embodiments.
[0075] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0076] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0077] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.
[0078] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0079] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A test method for a test structure on a wafer, characterized in that, include: Obtain the test structure coordinate file of the wafer to be tested; The test structure coordinate file includes: identification characters and identification positions of multiple test structures on the wafer to be tested, wherein the identification position is the position of the identification character on the corresponding test structure; Based on the identification positions of the multiple test structures, detection images of the multiple test structures are acquired using an image acquisition device; The test structure is tested based on the detection image of the test structure.
2. The method according to claim 1, characterized in that, The step of acquiring detection images of multiple test structures using an image acquisition device based on the identification positions of the multiple test structures includes: Based on the identification position of the first test structure among the plurality of test structures, the image acquisition device is controlled to move to the identification position of the first test structure in order to obtain the detection image of the first test structure; The image acquisition device is sequentially moved to the marked positions of other test structures to acquire the detection images of the other test structures in turn.
3. The method according to claim 1, characterized in that, Each of the test structures includes multiple test keys, and the identifier position is the position of the identifier character on the first test key of the corresponding test structure; The step of acquiring detection images of multiple test structures using an image acquisition device based on the identification positions of the multiple test structures includes: Based on the identification position of each test structure, the image acquisition device is used to acquire the image of the first test key on each test structure as the detection image of each test structure.
4. The method according to claim 3, characterized in that, The step of testing the test structure based on the detected image of the test structure includes: Perform border recognition on the image of the first test key to determine the detection border of the first test key; The test structure is tested based on the detection border of the first test key.
5. The method according to claim 4, characterized in that, The step of testing the test structure based on the detection border of the first test key includes: Perform character recognition on the image of the first test key to obtain the detection position of the identifier character on the corresponding test structure; Based on the detection position of the identified character, determine the expected border of the first test key; Determine whether each edge in the detection border and the expected border of the first test key meets the preset deviation condition; If all the edges meet the preset deviation conditions, then the test structure is determined to have passed the test. If at least one edge does not meet the preset deviation condition, then the test structure test is determined to be unsuccessful.
6. The method according to claim 5, characterized in that, Before determining whether each edge in the detection border and the expected border of the first test key meets the preset deviation condition, the method further includes: Based on the pad size corresponding to the test key, the preset deviation condition and the shooting range of the image acquisition device are determined.
7. A test apparatus for testing structures on a wafer, characterized in that, include: The acquisition module is used to acquire the test structure coordinate file of the wafer to be tested; The test structure coordinate file includes: identification characters and identification positions of multiple test structures on the wafer to be tested, wherein the identification position is the position of the identification character on the corresponding test structure; The acquisition module is used to acquire detection images of the multiple test structures using an image acquisition device based on the identification positions of the multiple test structures; The testing module is used to test the test structure based on the detection image of the test structure.
8. A control device, characterized in that, include: The device includes a processor, a storage medium, and a bus. The storage medium stores program instructions executable by the processor. When the control device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the test method for the on-wafer test structure according to any one of claims 1 to 6.
9. A readable storage medium, characterized in that, The readable storage medium stores program instructions that, when executed by a processor, implement the test method for the on-wafer test structure as described in any one of claims 1 to 6.
10. A testing system, characterized in that, include: Control equipment, probe machine, testing machine, and image acquisition equipment; The probe machine, the test machine, and the image acquisition device are respectively connected to the control device; The control device is used to perform the test method for the wafer-on-a-chip test structure according to any one of claims 1 to 6.