Chip surface intelligent detection method and system based on machine vision

Abstract

The application discloses a kind of chip surface intelligent detection method and system based on machine vision, it is related to chip surface defect detection technical field, the present application includes submicron level defect fusion detection and mixed defect hierarchical analysis, realizes super-resolution reconstruction and defect detection integration by end-to-end fusion network model, improves submicron level defect detection sensitivity;Utilize feature decoupling-correlation reasoning model to generate the hierarchical analysis report of main defect type, correlation defect type and cause probability.In addition, it also includes defect distribution thermodynamic diagram generation and process parameter intelligent feedback step, optimizes process adjustment strategy.The present application can significantly improve defect detection precision and efficiency, provides technical support for semiconductor manufacturing quality control.

Description

Technical Field

[0001] This invention relates to the field of chip surface defect detection technology, and specifically to a chip surface intelligent detection method and system based on machine vision. Background Technology

[0002] Chip surface inspection is a crucial step in semiconductor manufacturing. Its goal is to identify and locate minute defects on the chip surface, such as pinholes, microcracks, and foreign particles, in order to ensure product quality.

[0003] In existing technologies, common detection methods include traditional image processing algorithms such as edge detection and grayscale analysis, deep learning-based defect classification models, and detection methods based on optical or infrared imaging. Traditional detection methods lack sensitivity for submicron-level defects and are prone to missed detections due to resolution or feature blurring. While deep learning models can detect multiple types of defects, their classification accuracy for mixed defects or irregularly shaped defects is low, easily leading to misclassification as a single defect, making it difficult to meet the detection requirements of submicron-level defects. Therefore, this invention proposes a technical solution of an "end-to-end fusion network model" and a "feature decoupling-association reasoning model" to address the detection requirements of submicron-level defects.

[0004] Existing technologies, such as the invention patent application CN114813783B, provide a method for detecting chip surface defects. This method improves detection accuracy by adjusting light source conditions and acquiring images from multiple angles, but it does not involve super-resolution reconstruction or defect feature decoupling techniques. For example, CN113218945A and CN114130695B disclose chip surface detection devices and equipment, respectively, using automated detection schemes to replace manual operation, but they lack the ability to enhance local features and perform multi-level analysis of submicron-level defects. CN111220621B provides a method for detecting tilted chip surfaces, detecting defects based on the relationship between image intensity ratio and tilt, but its technical principle is not directly related to the submicron-level defect detection and mixed defect analysis of this invention. CN119991558A proposes a method based on super-resolution reconstruction and an improved Faster R-CNN, which is somewhat similar to this invention in terms of super-resolution reconstruction, but it does not involve a defect feature decoupling-association inference model, and the technical path and application scenarios are different.

[0005] In summary, existing technologies mainly focus on improving detection efficiency, optimizing light source conditions, or achieving automated detection, but none of them have proposed a technical solution similar to the end-to-end fusion network model and feature decoupling-association reasoning model of this invention. Summary of the Invention

[0006] The purpose of this invention is to provide a machine vision-based intelligent detection method and system for chip surfaces, which solves the problems existing in the background art.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The first aspect of the present invention provides a chip surface intelligent detection method based on machine vision.

[0008] S1. Acquire a low-resolution image of the surface of the chip to be inspected, and input the low-resolution image into an end-to-end fusion network model. The end-to-end fusion network model integrates a super-resolution reconstruction module and a defect detection module.

[0009] S2. The super-resolution reconstruction module enhances the local features of the candidate defect regions in the low-resolution image to generate high-resolution defect features. Based on these high-resolution defect features, the defect detection module directly outputs preliminary detection results for submicron-level defects.

[0010] S3. For the mixed defect regions identified in the preliminary detection results, start the feature decoupling-association reasoning model.

[0011] S4. The image data of the mixed defect region is subjected to basic feature extraction through the convolutional neural network in the feature decoupling-association inference model to obtain a set of decoupled basic feature vectors.

[0012] S5. Use graph neural networks to perform reasoning analysis on the topological correlation between the basic feature vectors, and generate a hierarchical analysis report containing the main defect type, related defect types, and causal probabilities.

[0013] S6. Based on the preliminary detection results and the hierarchical analysis report, generate a visual heatmap of defect distribution that can characterize the spatial distribution pattern of defects at the chip level.

[0014] S7. Automatically generate parameter adjustment suggestions for specific process steps.

[0015] A second aspect of the present invention provides a system for executing the machine vision-based intelligent chip surface inspection method of the present invention, comprising: a submicron-level defect fusion detection module, used to acquire a low-resolution image of the chip surface to be inspected, and through an end-to-end fusion network model embedded with a super-resolution reconstruction unit and a defect detection unit, to perform local feature enhancement on candidate defect regions in the low-resolution image to generate high-resolution defect features, and to directly output preliminary detection results for submicron-level defects based on the high-resolution defect features.

[0016] The hybrid defect hierarchical analysis module is used to identify hybrid defect regions in the preliminary detection results and then activate the feature decoupling-association reasoning model. This model includes a convolutional neural network for extracting basic feature vectors for decoupling, and a graph neural network for reasoning and analyzing the topological correlation between the basic feature vectors. Finally, it generates a hierarchical analysis report containing the main defect type, associated defect types, and causal probabilities.

[0017] The data processing and storage module is connected to the submicron level defect fusion detection module and the hybrid defect hierarchical analysis module, and is used to store the end-to-end fusion network model, the feature decoupling-association reasoning model, and the generated preliminary detection results and hierarchical analysis report.

[0018] The beneficial effects of this invention are as follows: This invention combines super-resolution reconstruction with defect detection for the first time, and introduces a feature decoupling-association reasoning model, which solves the technical bottleneck of traditional methods in submicron level defect detection and mixed defect analysis.

[0019] This invention not only achieves high-precision detection of submicron-level defects, but also provides a scientific basis for subsequent process optimization through hierarchical analysis of mixed defects. For example, through defect distribution heatmaps and intelligent feedback functions for process parameters, it can guide the adjustment of parameters for specific process steps, thereby reducing production costs and improving yield.

[0020] This invention utilizes a super-resolution reconstruction module to generate high-definition defect features while preserving submicron-level details, thereby significantly improving the detection rate of submicron-level defects. Simultaneously, by generating defect distribution heatmaps and providing intelligent feedback on process parameters, it helps manufacturers quickly locate critical failure areas and adjust process parameters, reducing resource waste and environmental pollution. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the implementation steps of the method of the present invention.

[0023] Figure 2 This is a schematic diagram of the system structure connection of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Reference Figure 1 As shown, this invention provides a machine vision-based intelligent chip surface inspection method, comprising: S1, acquiring a low-resolution image of the chip surface to be inspected, and inputting the low-resolution image into an end-to-end fusion network model. The end-to-end fusion network model integrates a super-resolution reconstruction module and a defect detection module.

[0026] This invention is the first to combine super-resolution reconstruction with defect detection and introduces a feature decoupling-association reasoning model, which solves the technical bottleneck of traditional methods in submicron level defect detection and mixed defect analysis.

[0027] S2. The super-resolution reconstruction module enhances the local features of the candidate defect regions in the low-resolution image to generate high-resolution defect features. Based on these high-resolution defect features, the defect detection module directly outputs preliminary detection results for submicron-level defects.

[0028] In a specific embodiment of the present invention, the end-to-end fusion network model is a Transformer-based multi-scale feature alignment network.

[0029] The specific process of enhancing the local features of the candidate defect regions in the low-resolution image through the super-resolution reconstruction module includes: in the multi-scale feature alignment network, using its self-attention mechanism to identify regions in the low-resolution image that are highly correlated with the preset defect template as the candidate defect regions.

[0030] The preset defect template includes, but is not limited to, feature templates of typical defects such as pinholes and microcracks. The self-attention mechanism can calculate the correlation between each pixel region in the image and the preset defect template, and mark regions with correlation exceeding a preset correlation threshold as candidate defect regions. The correlation is specifically such as the similarity of grayscale distribution and edge shape.

[0031] The image of the candidate defect region is upsampled and aligned at multiple scales to reconstruct the high-resolution defect features while preserving submicron-level details. The high-resolution defect features are then passed to the defect detection module, where they are used to directly learn the end-to-end mapping from low-resolution input to high-resolution defect classification results.

[0032] The multi-scale sampling specifically involves magnifying low-resolution candidate defect regions to higher resolutions, such as from 20*20 pixels to 80*80 pixels, while taking into account defect details at different scales during the magnification process, such as the overall direction of microcracks and local burrs.

[0033] The feature alignment specifically involves using algorithms to correct edge offsets and detail blurring caused by sampling, such as ensuring that the circular outline of the pinhole is not distorted after the method.

[0034] It should be noted that the self-attention mechanism is used to identify candidate defect regions. This process avoids the waste of computing power and noise amplification caused by the indiscriminate enhancement of the entire image in traditional methods, and improves the targeting of feature enhancement. The model directly learns the mapping relationship between low-resolution input and high-resolution defect classification results, avoiding the error accumulation caused by the separation of super-resolution reconstruction and defect detection in traditional methods, such as the noise after reconstruction being brought into the detection stage.

[0035] In a specific embodiment of the present invention, the specific process by which the defect detection module directly outputs preliminary detection results for submicron level defects includes: receiving high-definition defect features generated by the super-resolution reconstruction module and subjected to multi-scale upsampling and feature alignment.

[0036] The high-definition defect features are input into the classifier and locator built into the defect detection module. The classifier is responsible for identifying the defect category corresponding to the high-definition defect features, which includes pinholes, microcracks, foreign particles, etc.

[0037] The locator is responsible for outputting the precise location bounding box of the defect in the chip surface coordinate system. The defect category and the location bounding box are integrated to form the preliminary detection result, which includes category labels and coordinate information.

[0038] It should be noted that traditional methods have a low recognition rate for minute defects and a large positioning error. This invention improves the recognition accuracy of submicron level defects and reduces positioning error by using precise input of high-definition defect features and combining the collaborative processing of classifiers and locators. This meets the high-precision detection requirements of chips, provides basic data for mixed defect analysis, and supports defect distribution heatmaps and process feedback.

[0039] S3. For the mixed defect regions identified in the preliminary detection results, start the feature decoupling-association reasoning model.

[0040] S4. The image data of the mixed defect region is subjected to basic feature extraction through the convolutional neural network in the feature decoupling-association inference model to obtain a set of decoupled basic feature vectors.

[0041] In a specific embodiment of the present invention, the specific process of extracting basic features through the convolutional neural network in the feature decoupling-association inference model includes: feeding the image data of the identified mixed defect region into multiple pre-trained convolutional neural network branches in parallel, wherein the mixed defect region contains at least two different defect categories.

[0042] The first branch network is used to extract the grayscale distribution features of the mixed defect region.

[0043] The grayscale distribution features include, but are not limited to, the average grayscale value of the region, the standard deviation of grayscale, and the maximum value of the grayscale gradient at the edge.

[0044] The second branch network is used to extract the edge contour features of the mixed defect region.

[0045] The edge contour features include, but are not limited to, edge length, edge direction angle, and edge continuity value, wherein the edge continuity value specifically refers to the ratio of the number of edge breaks to the total length.

[0046] The third branch network is used to extract the surface texture features of the mixed defect region.

[0047] The surface texture features include, but are not limited to, texture roughness and texture entropy.

[0048] The grayscale distribution features, edge contour features, and surface texture features are combined together to form the decoupled basic feature vector set, with each basic feature vector corresponding to a specific visual dimension.

[0049] It should be noted that the present invention provides computable units for the analysis of hybrid defects by extracting basic features. The quantified feature vectors can be used to calculate the correlation through mathematical methods, providing a data foundation for the correlation reasoning of graph neural networks. Moreover, quantified features are more stable than fuzzy visual descriptions, improving the accuracy of subsequent determination of main defects and related defects. They can also be directly matched with the defect combination-cause mapping library, providing a quantitative basis for generating cause probabilities.

[0050] S5. Use graph neural networks to perform reasoning analysis on the topological correlation between the basic feature vectors, and generate a hierarchical analysis report containing the main defect type, related defect types, and causal probabilities.

[0051] In a specific embodiment of the present invention, the specific process of using a graph neural network to reason about and analyze the topological correlations between the basic feature vectors includes: S51, Defect map construction: Each basic feature vector is defined as a node in the graph neural network, and the node attribute is the specific numerical value of the vector. Based on the spatial proximity and feature similarity of the basic features in the original mixed defect region image, connecting edges are established between the nodes. The weight of the edge is determined by the weighted sum of the spatial proximity and feature similarity, thereby constructing a defect map representing the internal structural relationships of the defects.

[0052] S52. Execution of association reasoning: Perform graph convolution operation on the defect graph, update the representation of each node by aggregating the information of neighboring nodes, so that the final representation of each node integrates its own features and contextual features, and perform full graph pooling based on the updated node representation to obtain a global defect representation vector.

[0053] It should be noted that the principle of graph convolution is that each node absorbs the feature information of its neighboring nodes according to the weight of the edges and updates its own attributes. For example, if node B is an edge contour feature vector, node A is a gray-level distribution feature vector, and node C is a surface texture feature vector, and the neighboring nodes of node B are nodes A and C, then node B will absorb the gray-level distribution feature of node A through the weight with node A, and absorb the surface texture feature of node C through the weight with node C. After the update, the attributes of node B not only include its own edge contour features, but also the gray-level distribution features of node A and the surface texture features of node C. This technology is relatively mature in the current technology, so it will only be briefly described here.

[0054] It should also be noted that the essence of full-image pooling is to globally condense the fused features. Full-image pooling methods include max pooling, average pooling, and attention pooling. The specific method can be flexibly selected according to the defect features of pinholes, microcracks, and foreign particles, adapting to the feature differences of pinholes, microcracks, and foreign particles, ensuring that the global defect representation vector can accurately reflect the overall characteristics of various defects, and providing reliable input for subsequent hierarchical analysis.

[0055] In a specific embodiment of the present invention, the specific process of establishing connecting edges between the nodes includes: calculating any two basic feature vectors. and Euclidean distance between them is used as a measure of feature similarity. .

[0056] Calculate the spatial distance between the center points of the corresponding pixels of the two basic feature vectors in the image of the mixed defect region. .

[0057] Set feature distance threshold and spatial distance threshold If and only if < and < At the node and nodes Establish connecting edges between them.

[0058] The weight of the edge The calculation formula is: ,in These are preset weighting factors.

[0059] In a specific embodiment of the present invention, the specific process of generating a hierarchical analytical report containing the main defect type, associated defect types, and causal probabilities includes: inputting the global defect representation vector into a multi-task output layer.

[0060] The first task branch of the multi-task output layer outputs a main defect classification result, which corresponds to the defect type with the highest confidence.

[0061] The above-mentioned output of a main defect classification result is specifically achieved by analyzing the confidence of each defect feature in the global defect representation vector through a classification model. The classification model records the defect representation of each defect type. For example, the classification model is a trained CNN classifier.

[0062] The second task branch of the multi-task output layer outputs one or more associated defect classification results, which correspond to other defect types that coexist with the main defect.

[0063] It should be noted that the output of one or more associated defect classification results satisfies that the spatial distance from the main defect type is less than or equal to a preset spatial distance threshold.

[0064] The third task branch of the multi-task output layer, based on the combination of the main defect classification result and the associated defect classification result, matches and outputs one or more causes and their corresponding probability values ​​from the preset defect combination-cause mapping library, and finally forms the hierarchical parsing report.

[0065] For example, the hierarchical analysis report might look like this: Main defect type: microcrack, confidence level 92%. Related defect type: foreign particles, confidence level 85%. Causes and probabilities: tool contamination, probability 80%; incomplete cleaning, probability 20%.

[0066] It should be added that the preset defect combination-cause mapping library is specifically a defect combination-cause mapping library built based on chip production historical data and process knowledge. Specifically, it can be established through data collection, mapping relationship extraction, expert verification and annotation, and dynamic updates. The establishment method is relatively mature and will not be elaborated here.

[0067] In a specific embodiment of the present invention, the method further includes: S6, generating a defect distribution heatmap: based on the preliminary detection results and the hierarchical analysis report, statistically analyzing the defect types, locations, and severity levels of all chips in the current batch, wherein the severity level is specifically divided according to the defect size, and the defect size is specifically calculated based on the location bounding box output by the defect detection module.

[0068] It should be noted that the larger the size coverage of the same type of defect, the higher the severity level.

[0069] On the preset chip coordinate system, each defect is marked as a data point. The color of the data point corresponds to the defect type or severity level, and the brightness of the data point corresponds to the probability of defect formation.

[0070] By using a kernel density estimation algorithm to perform spatial density interpolation on all data points, a visual heatmap of defect distribution that can characterize the spatial distribution pattern of defects at the chip level is generated.

[0071] It should be noted that the kernel density estimation algorithm is the core tool for transforming discrete data points into a continuous heatmap. Its principle is as follows: each data point is considered a heat source, releasing heat of a certain intensity to its surroundings. The intensity is positively correlated with the number and severity of defects. The total heat at each location on the chip is calculated, and the heat level is represented by a color gradient to form a heatmap.

[0072] For example, if the color gradient from blue to red indicates that the heat is from low to high, and if a large number of red high-brightness points are concentrated in the edge area of ​​the chip, the red corresponds to microcrack defects. After kernel density interpolation, the area will show a red high-temperature zone, which intuitively reflects that the microcracks at the edge of the chip are dense and mostly caused by high probability.

[0073] In a specific embodiment of the present invention, the method further includes: S7, intelligent feedback of process parameters: defining the area with the highest defect density in the defect distribution heat map as the critical failure area, wherein the defect density is specifically the number of defects per unit area.

[0074] Extract hierarchical analysis reports of all defects within the critical failure area, and statistically analyze the most frequent defect type combinations and their associated highest probability causes.

[0075] The highest probability cause is associated with and matched with the process steps in the process database to automatically generate parameter adjustment suggestions for specific process steps. These suggestions include adjusting the etching time, optimizing the cleaning solution concentration, or replacing the photomask.

[0076] It should be noted that the process database pre-stores the process steps and corresponding key parameters of the entire chip manufacturing process, and marks the defect type corresponding to each process step. It also records the key parameter adjustment rules corresponding to each cause. The process steps include cutting, etching, cleaning, photolithography, etc., and the key parameters include cutting speed, etching time, cleaning solution concentration, mask model, etc.

[0077] The logic of the above-mentioned correlation matching is to first locate the specific process steps that lead to the combination of defect types, and then output key parameter adjustment suggestions based on the most probable cause.

[0078] It should be added that the process of establishing the process database is as follows: structured storage of the entire process information: classified by chip manufacturing steps, with each step associated with its key parameters, forming a step-parameter basic framework.

[0079] Mapping the causes of defects to process parameters: By analyzing experimental data and production records, clarify the correspondence between abnormal process parameters and specific defect causes. For example: excessive etching time → over-etching → leading to pinhole defects.

[0080] Insufficient cleaning solution concentration → incomplete cleaning → resulting in foreign matter residue.

[0081] The impact of parameter adjustment on defects: Based on historical data or experimental records, the quantitative relationship between the adjustment range of key parameters and the change in defect rate is as follows: For example, for every 5 seconds reduction in etching time, the pinhole defect rate decreases by about 15%.

[0082] Increasing the cleaning solution concentration from 5% to 7% reduced the foreign particle residue rate by approximately 20%.

[0083] Recommendations for adjusting related parameters and feasibility boundaries: For each cause, match the adjustment direction and safety range of key parameters to ensure that the recommendations are feasible.

[0084] Based on structured storage, quantitative correlation, and executable suggestions, and given that existing data acquisition and analysis technologies and industry process knowledge can support its implementation, it is feasible and will not be elaborated upon here.

[0085] This invention not only achieves high-precision detection of submicron-level defects, but also provides a scientific basis for subsequent process optimization through hierarchical analysis of mixed defects. For example, through defect distribution heatmaps and intelligent feedback functions for process parameters, it can guide the adjustment of parameters for specific process steps, thereby reducing production costs and improving yield.

[0086] This invention utilizes a super-resolution reconstruction module to generate high-definition defect features while preserving submicron-level details, thereby significantly improving the detection rate of submicron-level defects. Simultaneously, by generating defect distribution heatmaps and providing intelligent feedback on process parameters, it helps manufacturers quickly locate critical failure areas and adjust process parameters, reducing resource waste and environmental pollution.

[0087] Reference Figure 2 As shown, a second aspect of the present invention provides a system for executing the intelligent chip surface inspection method based on machine vision described in the present invention, comprising: a submicron-level defect fusion detection module, used to acquire a low-resolution image of the chip surface to be inspected, and through an end-to-end fusion network model embedded with a super-resolution reconstruction unit and a defect detection unit, to perform local feature enhancement on candidate defect regions in the low-resolution image to generate high-resolution defect features, and to directly output preliminary detection results for submicron-level defects based on the high-resolution defect features.

[0088] The hybrid defect hierarchical analysis module is used to identify hybrid defect regions in the preliminary detection results and then activate the feature decoupling-association reasoning model. This model includes a convolutional neural network for extracting basic feature vectors for decoupling, and a graph neural network for reasoning and analyzing the topological correlation between the basic feature vectors. Finally, it generates a hierarchical analysis report containing the main defect type, associated defect types, and causal probabilities.

[0089] The data processing and storage module is connected to the submicron level defect fusion detection module and the hybrid defect hierarchical analysis module, and is used to store the end-to-end fusion network model, the feature decoupling-association reasoning model, and the generated preliminary detection results and hierarchical analysis report.

[0090] The various thresholds involved in this invention, such as feature similarity thresholds, spatial distance thresholds, defect density thresholds, and severity level classification thresholds, are all set based on statistical analysis of a large amount of historical defect data, combined with the physical characteristics of defects such as pinholes, microcracks, and foreign particles and their impact on chip performance, while also referencing semiconductor industry standards and engineering practices. These thresholds are not fixed values ​​and can be dynamically adjusted according to changes in production processes, materials, or defect types. This ensures both the scientific validity of the judgment criteria and the rationality of practical applications, providing a reliable basis for judgment throughout the entire process of defect detection, correlation reasoning, and process optimization.

[0091] The above content is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described, or use similar methods to replace them, as long as they do not deviate from the concept of the invention or exceed the scope defined by the present invention, and all such modifications and additions should fall within the protection scope of the present invention.

Claims

1. A machine vision-based intelligent inspection method for chip surfaces, characterized in that, include: S1. Acquire a low-resolution image of the surface of the chip to be inspected, and input the low-resolution image into an end-to-end fusion network model; the end-to-end fusion network model integrates a super-resolution reconstruction module and a defect detection module; The end-to-end fusion network model is a Transformer-based multi-scale feature alignment network. S2. The super-resolution reconstruction module performs local feature enhancement on the candidate defect region in the low-resolution image to generate high-resolution defect features. Based on the high-definition defect characteristics, the defect detection module directly outputs preliminary detection results for submicron-level defects; The specific process of performing local feature enhancement on the candidate defect region in the low-resolution image through the super-resolution reconstruction module includes: in the multi-scale feature alignment network, using its self-attention mechanism to identify regions in the low-resolution image that are highly correlated with the preset defect template as the candidate defect regions; The image of the candidate defect region is upsampled and aligned at multiple scales to reconstruct the high-resolution defect features while preserving submicron-level details. The high-resolution defect features are then passed to the defect detection module, where they are used to directly learn the end-to-end mapping from low-resolution input to high-resolution defect classification results. The specific process by which the defect detection module directly outputs preliminary detection results for submicron-level defects includes: Receive high-resolution defect features generated by the super-resolution reconstruction module, which have undergone multi-scale upsampling and feature alignment; The high-definition defect features are input into the classifier and locator built into the defect detection module; the classifier is responsible for identifying the defect category corresponding to the high-definition defect features. The locator is responsible for outputting the precise location bounding box of the defect in the chip surface coordinate system; integrating the defect category with the location bounding box, a preliminary detection result containing category label and coordinate information is formed. S3. For the mixed defect regions identified in the preliminary detection results, the feature decoupling-association reasoning model is activated; S4. Extract basic features from the image data of the mixed defect region using the convolutional neural network in the feature decoupling-association inference model to obtain a set of decoupled basic feature vectors; The specific process of extracting basic features through the convolutional neural network in the feature decoupling-association inference model includes: The image data of the identified mixed defect regions are fed in parallel into multiple pre-trained convolutional neural network branches, wherein the mixed defect regions contain at least two different defect categories; The first branch network is used to extract the grayscale distribution features of the mixed defect region; The second branch network is used to extract the edge contour features of the mixed defect region; The third branch network is used to extract the surface texture features of the mixed defect region; The grayscale distribution features, edge contour features, and surface texture features are combined together to form the decoupled basic feature vector set, and each basic feature vector corresponds to a specific visual dimension. S5. Use graph neural networks to perform reasoning analysis on the topological correlation between the basic feature vectors, and generate a hierarchical analysis report containing the main defect type, related defect types and causal probabilities. The specific process for generating a hierarchical analysis report that includes the main defect type, associated defect types, and cause probabilities includes: The global defect representation vector is input into a multi-task output layer; The first task branch of the multi-task output layer outputs a main defect classification result, which corresponds to the defect type with the highest confidence. The second task branch of the multi-task output layer outputs one or more associated defect classification results, which correspond to other defect types that coexist with the main defect. The third task branch of the multi-task output layer, based on the combination of the main defect classification result and the associated defect classification result, matches and outputs one or more causes and their corresponding probability values ​​from the preset defect combination-cause mapping library, and finally forms the hierarchical parsing report. The method further includes: S7. Intelligent feedback of process parameters: The area with the highest defect density in the defect distribution heat map is defined as the critical failure area, and the defect density is specifically the number of defects per unit area. Extract hierarchical analysis reports of all defects within the critical failure area, and statistically analyze the most frequent defect type combinations and their associated highest probability causes. The highest probability cause is associated with and matched with the process steps in the process database to automatically generate parameter adjustment suggestions for specific process steps. These suggestions include adjusting the etching time, optimizing the cleaning solution concentration, or replacing the photomask.

2. The intelligent chip surface detection method based on machine vision according to claim 1, characterized in that, The specific process of using graph neural networks to reason and analyze the topological correlations between the basic feature vectors includes: S51, Defect Map Construction: Each basic feature vector is defined as a node in a graph neural network, and the node attribute is the specific numerical value of the vector; based on the spatial proximity and feature similarity of the basic features in the original mixed defect region image, connecting edges are established between the nodes, and the weight of the edges is determined by the weighted sum of the spatial proximity and feature similarity, thereby constructing a defect map that represents the internal structural relationship of the defects. S52. Execution of association reasoning: Perform graph convolution operation on the defect graph, update the representation of each node by aggregating the information of neighboring nodes, so that the final representation of each node integrates its own features and contextual features, and perform full graph pooling based on the updated node representation to obtain a global defect representation vector.

3. The intelligent chip surface detection method based on machine vision according to claim 1, characterized in that, The method further includes: S6. Defect Distribution Heatmap Generation: Based on the preliminary detection results and the hierarchical analysis report, the defect types, locations, and severity levels of all chips in the current batch are statistically analyzed. The severity level is specifically classified according to the defect size, and the defect size is specifically calculated based on the location bounding box output by the defect detection module. On the preset chip coordinate system, each defect is marked as a data point. The color of the data point corresponds to the defect type or severity level, and the brightness of the data point corresponds to the probability of defect formation. By using a kernel density estimation algorithm to perform spatial density interpolation on all data points, a visual heatmap of defect distribution that can characterize the spatial distribution pattern of defects at the chip level is generated.

4. The intelligent chip surface detection method based on machine vision according to claim 2, characterized in that, The specific process of establishing connecting edges between the nodes includes: Calculate any two fundamental eigenvectors and Euclidean distance between them is used as a measure of feature similarity. ; Calculate the spatial distance between the center points of the corresponding pixels of the two basic feature vectors in the image of the mixed defect region. ; Set feature distance threshold and spatial distance threshold If and only if < and < At the node and nodes Establish connecting edges between them; The weight of the edge The calculation formula is: ,in These are preset weighting factors.

5. A system for performing the machine vision-based intelligent chip surface inspection method according to any one of claims 1-4, characterized in that, include: The submicron-level defect fusion detection module is used to acquire a low-resolution image of the surface of the chip to be inspected, and to perform local feature enhancement on the candidate defect region in the low-resolution image through an end-to-end fusion network model with an embedded super-resolution reconstruction unit and a defect detection unit to generate high-resolution defect features, and to directly output the preliminary detection results for submicron-level defects based on the high-resolution defect features. The mixed defect hierarchical analysis module is used to identify mixed defect regions in the preliminary detection results and then start the feature decoupling-association reasoning model. This model includes a convolutional neural network for extracting the basic feature vectors for decoupling, and a graph neural network for reasoning and analyzing the topological correlation between the basic feature vectors. Finally, it generates a hierarchical analysis report containing the main defect type, associated defect type, and causal probability. The data processing and storage module is connected to the submicron level defect fusion detection module and the hybrid defect hierarchical analysis module, and is used to store the end-to-end fusion network model, the feature decoupling-association reasoning model, and the generated preliminary detection results and hierarchical analysis report.

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