Effective node management method, storage device and memory control circuit unit

Abstract

The present application provides an effective node management method, a memory storage device and a memory control circuit unit. The method comprises: establishing an effective node management table corresponding to a first physical management unit; storing effective node management data in the effective node management table, wherein the effective node management data reflects the distribution of effective nodes in the first physical management unit; receiving an operation instruction from a host system, which is used to change the data storage state of the first physical management unit; and updating the effective node management data in the effective node management table in response to the operation instruction. In this way, the management efficiency of the effective nodes in the physical management unit can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory management technique, and more particularly, to an efficient node management method, a memory storage device, and a memory control circuit unit. BACKGROUND

[0002] Smart phones, tablet computers, and personal computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memories) are very suitable for being built into various portable multimedia devices exemplified above due to their data non-volatility, power saving, small size, and lack of mechanical structure.

[0003] Generally, when a data compaction operation such as garbage collection is to be performed, a memory controller scans at least part of physical blocks in a rewritable non-volatile memory module to determine the distribution of efficient nodes in each physical block according to physical to logical (P2L) mapping information stored in the physical blocks in combination with logical to physical (L2P) mapping information stored in a logical to physical mapping table, and then performs the data compaction operation according to the distribution. However, the scanning of the physical blocks consumes a lot of time and system resources, resulting in a low efficiency of performing the data compaction operation. SUMMARY

[0004] The present application provides an efficient node management method, a memory storage device, and a memory control circuit unit, which can improve the management efficiency of efficient nodes in a physical management unit.

[0005] An example embodiment of the present application provides an efficient node management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical management units. The efficient node management method includes: establishing an efficient node management table corresponding to a first physical management unit of the plurality of physical management units; storing efficient node management data in the efficient node management table, wherein the efficient node management data reflects the distribution of efficient nodes in the first physical management unit; receiving an operation instruction from a host system, wherein the operation instruction is used to change the data storage state of the first physical management unit; and updating the efficient node management data in the efficient node management table in response to the operation instruction.

[0006] An exemplary embodiment of the present application further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to connect to a host system. The rewritable non-volatile memory module includes a plurality of physical management units. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: establish a valid node management table corresponding to a first physical management unit of the plurality of physical management units; store valid node management data in the valid node management table, wherein the valid node management data reflects a distribution of valid nodes in the first physical management unit; receive an operation instruction from the host system, wherein the operation instruction is configured to change a data storage state of the first physical management unit; and update the valid node management data in the valid node management table in response to the operation instruction.

[0007] An exemplary embodiment of the present application further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical management units. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is configured to: establish a valid node management table corresponding to a first physical management unit of the plurality of physical management units; store valid node management data in the valid node management table, wherein the valid node management data reflects a distribution of valid nodes in the first physical management unit; receive an operation instruction from the host system, wherein the operation instruction is configured to change a data storage state of the first physical management unit; and update the valid node management data in the valid node management table in response to the operation instruction.

[0008] Based on the above, after establishing a valid node management table corresponding to a first physical management unit, valid node management data can be stored in the valid node management table to reflect a distribution of valid nodes in the first physical management unit. Then, in response to receiving an operation instruction from a host system to change a data storage state of the first physical management unit, the valid node management data in the valid node management table can be updated. In this way, the management efficiency of valid nodes in a physical management unit can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application;

[0010] Figure 2 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application;

[0011] Figure 3 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application;

[0012] Figure 4 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application;

[0013] Figure 5 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application;

[0014] Figure 6 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application;

[0015] Figure 7 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application;

[0016] Figure 8 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application;

[0017] Figures 9A to 9C FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application;

[0018] Figure 10 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application;

[0019] Figure 11 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present application; DETAILED DESCRIPTION

[0020] Reference will now be made in detail to exemplary embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0021] Generally speaking, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0022] Figure 1 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device, according to an example embodiment of the present disclosure. Figure 2 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device, according to an example embodiment of the present disclosure.

[0023] Please refer to Figure 1 and Figure 2 The host system 11 can include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be connected to a system bus 110.

[0024] In an example embodiment, the host system 11 can be connected to the memory storage device 10 through the data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 can be connected to the I / O device 12 through the system bus 110. For example, the host system 11 can transmit an output signal to or receive an input signal from the I / O device 12 via the system bus 110.

[0025] In an example embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be disposed on a host board 20 of the host system 11. The number of the data transfer interface 114 can be one or more. Through the data transfer interface 114, the host board 20 can be connected to the memory storage device 10 via a wired or wireless manner.

[0026] In an example embodiment, the memory storage device 10 can be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy memory storage device (e.g., iBeacon), among other memory storage devices based on various wireless communication technologies. In addition, the host board 20 can also be connected to various I / O devices, such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like, through the system bus 110. For example, in an example embodiment, the host board 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

[0027] In an example embodiment, the host system 11 is a computer system. In an example embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 can each include a memory storage device 30 and a host system 31, respectively, as shown in Figure 3

[0028] Figure 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the present disclosure. Please refer to Figure 3 The memory storage device 30 can be used in cooperation with the host system 31 to store data. For example, the host system 31 can be a digital camera, a camcorder, a communication device, an audio player, a video player, or a tablet computer, among other systems. For example, the memory storage device 30 can be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34, among other non-volatile memory storage devices used by the host system 31. The embedded storage device 34 includes an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342, among other embedded storage devices that directly connect a memory module to a substrate of the host system.

[0029] Figure 4 is a schematic diagram of a memory storage device according to an example embodiment of the present disclosure. Please refer to​Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

[0030] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present application is not limited thereto, and the connection interface unit 41 can also be compatible with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip that includes the memory control circuit unit 42.

[0031] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable nonvolatile memory module 43 according to instructions of the host system 11.

[0032] The rewritable nonvolatile memory module 43 stores data written by the host system 11. The rewritable nonvolatile memory module 43 can include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one bit can be stored in one memory cell), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which two bits can be stored in one memory cell), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module in which three bits can be stored in one memory cell), a quad level cell (QLC) NAND type flash memory module (i.e., a flash memory module in which four bits can be stored in one memory cell), another flash memory module, or another memory module having the same characteristics.

[0033] Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between a control gate and a channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons of the charge trapping layer is changed, and thus the threshold voltage of the memory cell is changed. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage is changed, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, and thus it is possible to acquire one or more bits stored in the memory cell.

[0034] In an example embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute a plurality of physical program units, and the physical program units can constitute a plurality of physical erase units. Specifically, the memory cells on the same word line can form one or more physical program units. If each memory cell can store more than two bits, the physical program units on the same word line can be classified into at least lower physical program units and upper physical program units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical program unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical program unit. Generally, in an MLC NAND type flash memory, the write speed of a lower physical program unit is greater than that of an upper physical program unit, and / or the reliability of a lower physical program unit is higher than that of an upper physical program unit.

[0035] In an example embodiment, a physical program unit is the smallest unit of programming. That is, a physical program unit is the smallest unit of writing data. For example, a physical program unit can be a physical page or a physical sector. If a physical program unit is a physical page, the physical program units can include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is for storing system data (e.g., management data such as error correction codes). In an example embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit area can include 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can be greater or smaller. On the other hand, a physical erase unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased together. For example, a physical erase unit is a physical block.

[0036] Figure 5 FIG. 1 is a schematic diagram of a memory control circuit unit according to an example embodiment of the present application. Referring to FIG. 1, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. Figure 5

[0037] ​The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and these control instructions are executed to perform data write, read and erase operations, etc. when the memory storage device 10 is in operation. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0038] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform data write, read and erase operations, etc.

[0039] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code form in a specific area (e.g., a system area in the memory module for storing system data) of the rewritable non-volatile memory module 43. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform data write, read and erase operations, etc.

[0040] In an example embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or the groups of memory cells of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations, etc. In an example embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct to perform corresponding operations.

[0041] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In the present example embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present application is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0042] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written into the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 transmits a corresponding instruction sequence. For example, the instruction sequence can include a write instruction sequence indicating write data, a read instruction sequence indicating read data, an erase instruction sequence indicating erase data, and corresponding instruction sequences to indicate various memory operations (e.g., change the read voltage level or perform a garbage collection operation, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on a bus. These signals or data can include instruction codes or program codes. For example, in a read instruction sequence, the identification code of the read, the memory address, etc. information are included.

[0043] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0044] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 writes the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the corresponding error correcting code and / or error detecting code corresponding to this data is also read, and the error checking and correction circuit 54 performs error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0045] The buffer memory 55 is connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0046] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0047] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 6 The memory management circuit 51 can logically group the physical management units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602.

[0048] In one exemplary embodiment, an entity management unit includes one or more entity blocks. An entity management unit may include multiple entity nodes. In one exemplary embodiment, each entity node may store 4KB of data. In another exemplary embodiment, each entity node may store more or less data; this invention is not limited thereto.

[0049] The entity management units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 The host system 11 contains user data. For example, entity management units 610(0) to 610(A) in storage area 601 can store valid and invalid data. Entity management units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity management unit does not store valid data, this entity management unit can be associated (or added) to free area 602. In addition, entity management units (or entity management units that do not store valid data) in free area 602 can be erased. When new data is written, one or more entity management units can be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0050] The memory management circuit 51 can configure the logical units 612(0)~612(C) to map the physical management units 610(0)~610(A) in the storage area 601. In an example embodiment, each logical unit corresponds to a logical address. For example, a logical address can include one or more logical block addresses (LBAs) or other logical management units. In an example embodiment, a logical unit can also correspond to a logical programming unit or be composed of multiple contiguous or non-contiguous logical addresses.

[0051] It should be noted that one logical unit can be mapped to one or more physical management units. If a physical management unit is currently mapped by a logical unit, it means that the data currently stored in the physical management unit includes valid data. Conversely, if a physical management unit is not currently mapped by any logical unit, it means that the data currently stored in the physical management unit is invalid data.

[0052] Similarly, if the data currently stored in a physical node belongs to a logical unit, it means that the physical node currently stores valid data. Conversely, if the data currently stored in a physical node does not belong to any logical unit, it means that the physical node currently does not store valid data. In an example embodiment, a physical node that currently stores valid data is also referred to as a valid node, and / or a physical node that currently does not store valid data is also referred to as an invalid node.

[0053] The memory management circuit 51 can record mapping information (also referred to as logical-to-physical mapping information) describing the mapping relationship between the logical units and the physical management units in at least one mapping table (also referred to as a logical-to-physical mapping table). When the host system 11 wants to read data from or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information (i.e., the mapping information) in the mapping table.

[0054] In an example embodiment, the memory management circuit 51 can establish a valid node management table (also referred to as a first valid node management table) corresponding to one physical management unit (also referred to as a first physical management unit). For example, the first physical management unit can be any one of the physical management units 610(0)~610(B) in the storage area 601. Figure 6 The memory management circuit 51 can store the first valid node management table in the rewritable non-volatile memory module 43.

[0055] In an example embodiment, the memory management circuit 51 can store the first valid node management table in a system area in the rewritable non-volatile memory module 43. The system area can be dedicated for storing system data. For example, the user or the host system 11 cannot access the data in the system area. Thus, the user or the host system 11 can be prevented from accidentally modifying or deleting the data in the system area, thereby causing the memory storage device 10 to malfunction.

[0056] In an example embodiment, the memory management circuit 51 can store valid node management data (also referred to as first valid node management data) in the first valid node management table. In particular, the first valid node management data can reflect the distribution of valid nodes in the first physical management unit. For example, the first valid node management data can reflect whether the first physical management unit contains any valid nodes. In the case that the first physical management unit contains at least one valid node, the first valid node management data can further reflect the distribution of valid nodes in the first physical management unit (e.g., which physical nodes in the first physical management unit are valid nodes or invalid nodes) and / or the total number of valid nodes in the first physical management unit.

[0057] Figure 7 FIG. 1 is a schematic diagram of a valid data management table according to an example embodiment of the present application. Please refer to FIG. 1, in which a valid data management table 100 is shown. The valid data management table 100 can be established by the memory management circuit 51 of the memory storage device 10. The valid data management table 100 can be used to record the distribution of valid nodes in the first physical management unit 101. In particular, the valid data management table 100 can record a plurality of identification bits B(0)~B(7) corresponding to a plurality of physical nodes N(0)~N(7) in the first physical management unit 101. For example, the identification bit B(i) in the identification bits B(0)~B(7) can be used to represent whether the physical node N(i) is a valid node. In the example shown in FIG. 1, the identification bits B(2), B(4), B(5) and B(6) are bits "1" and the identification bits B(0), B(l), B(3) and B(7) are bits "0", indicating that the physical nodes N(2), N(4), N(5) and N(6) in the first physical management unit 101 are valid nodes (i.e., physical nodes currently storing valid data), and the physical nodes N(0), N(l), N(3) and N(7) are invalid nodes (i.e., physical nodes currently not storing valid data). Figure 7 In an example embodiment, the memory management circuit 51 can establish a valid node management table 702 (i.e., a first valid node management table) corresponding to the physical management unit 701 (i.e., a first physical management unit). The memory management circuit 51 can store valid node management data (i.e., first valid node management data) corresponding to the physical management unit 701 in the valid node management table 702.

[0058] In an example embodiment, the valid node management table 702 can record a plurality of identification bits B(0)~B(7) and the physical management unit 701 includes a plurality of physical nodes N(0)~N(7). In particular, the identification bit B(i) in the identification bits B(0)~B(7) can be used to represent whether the physical node N(i) is a valid node. For example, in the valid node management table 702, assume that the identification bits B(2), B(4), B(5) and B(6) are bits "1" and the identification bits B(0), B(l), B(3) and B(7) are bits "0", indicating that the physical nodes N(2), N(4), N(5) and N(6) in the physical management unit 701 are valid nodes (i.e., physical nodes currently storing valid data), and the physical nodes N(0), N(l), N(3) and N(7) are invalid nodes (i.e., physical nodes currently not storing valid data).

[0059] In an example embodiment, the memory management circuit 51 can obtain the distribution of valid nodes in the physical management unit 701 according to the information recorded in the valid node management table 702 (i.e., the first valid node management data). For example, according to the identification bits B(0)-B(7), the memory management circuit 51 can determine that the physical nodes N(2), N(4), N(5), and N(6) belong to valid nodes and / or the physical nodes N(0), N(l), N(3), and N(7) belong to invalid nodes. In addition, the valid node management table 702 can record more identification bits to reflect the status (e.g., whether valid nodes) of the remaining physical nodes in the physical management unit 701.

[0060] In an example embodiment, after the first valid node management table is established, the memory management circuit 51 can continuously update, maintain, and manage the first valid node management table to reflect the latest distribution of valid nodes in the first physical management unit. In an example embodiment, in response to the absence of valid nodes in the first physical management unit, the memory management circuit 51 can delete the first valid node management table. Alternatively, in an example embodiment, even if there are no valid nodes in the first physical management unit, the memory management circuit 51 can not delete (i.e., retain) the first valid node management table.

[0061] In an example embodiment, the memory management circuit 51 can establish an index table and store the address information of one or more valid node management tables (including the first valid node management table) in the index table. When the first valid node management table is to be queried, the memory management circuit 51 can read the index table to obtain the address information of the first valid node management table. According to the address information, the memory management circuit 51 can read the first valid node management table from the rewritable non-volatile memory module 43.

[0062] Figure 8 is a schematic diagram of an index table according to an example embodiment of the present application. Please refer to Figure 8 The memory management circuit 51 can establish an index table 81. The memory management circuit 51 can store the address information PA(0)-PA(2) corresponding to the valid node management tables TB(l)-TB(2) in the index table 81. For example, the address information PA(i) can correspond to the valid node management table TB(i) and reflect the storage address of the valid node management table TB(i) in the physical management unit 82. In an example embodiment, the physical management unit 82 can be a physical management unit in the rewritable non-volatile memory module 43 that is specifically used to store system data (i.e., a physical management unit belonging to the system area). In an example embodiment, the physical management unit 82 can be any physical management unit in the rewritable non-volatile memory module 43.

[0063] In an example embodiment, when the valid node management table TB(i) (i.e., the first valid node management table) is to be read, the memory management circuit 51 can obtain the storage address of the valid node management table TB(i) in the physical management unit 82 according to the address information PA(i) recorded in the index table 81. Then, the memory management circuit 51 can read the valid node management table TB(i) from the storage address according to the address information PA(i).

[0064] In an example embodiment, in response to the absence of a valid node in the first physical management unit, the memory management circuit 51 can remove the address information of the first valid node management table corresponding to the first physical management unit from the index table. For example, assuming that the physical management unit corresponding to the valid node management table TB(0) does not have any valid node, the memory management circuit 51 can remove the address information PA(0) of the valid node management table TB(0) from the index table 81. Meanwhile, the memory management circuit 51 can delete the valid node management table TB(0). In this way, the storage space can be used more efficiently.

[0065] In an example embodiment, the memory management circuit 51 can receive one or more operation instructions from the host system 11. The operation instructions can be used to change the data storage state of the first physical management unit. For example, the operation instructions can include a write instruction and / or a delete instruction. The write instruction is used to indicate writing or updating data belonging to a specific logical unit. The delete instruction can be used to indicate deleting or erasing data belonging to a specific logical unit. The specific logical unit is mapped to the first physical management unit. In an example embodiment, the operation instructions can also include other types of instructions as long as they can be used to change the data storage state of the first physical management unit.

[0066] In an example embodiment, in response to the operation instructions, the memory management circuit 51 can update the data in the first valid node management table (i.e., the first valid node management data). For example, the updated first valid node management data can reflect the latest distribution of valid nodes in the first physical management unit.

[0067] Figures 9A to 9C is a schematic diagram showing the updating of valid node management data according to an example embodiment of the present application. Please refer to Figure 9A , assuming that the valid node management table 911 is used to record the valid node management data corresponding to the physical management unit 901, and the valid node management table 912 is used to record the valid node management data corresponding to the physical management unit 902. In addition, in Figure 9AIn the exemplary embodiment, entity nodes marked with slashes represent entity nodes that have been written with data (i.e., have stored data), while entity nodes not marked with slashes represent entity nodes that have not yet been written with data (i.e., have not yet stored data).

[0068] It should be noted that, in Figure 9A In the exemplary embodiment, it is assumed that the entity nodes marked with slashes in entity management units 901 and 902 are currently storing valid data. Therefore, the identification bits corresponding to these valid nodes in the valid node management tables 911 and 912 are all bit "1", while the identification bits corresponding to the remaining invalid nodes are bit "0".

[0069] Please refer to Figure 9B , continuing Figure 9A In an exemplary embodiment, it is assumed that the data belonging to logic units L(0) to L(3) are currently stored in physical nodes 931(0) to 931(3), respectively. In one exemplary embodiment, the memory management circuit 51 may receive at least one operation instruction (also referred to as a first operation instruction) from the host system 11. The first operation instruction indicates that the data belonging to logic units L(0) to L(7) be updated. In response to the first operation instruction, the memory management circuit 51 may mark the data currently stored in physical nodes 931(0) to 931(3) as invalid data and store the new data (i.e., valid data) belonging to logic units L(0) to L(7) into physical nodes 941(0) to 941(7). In other words, in response to the first operation instruction, the data storage state of physical management units 901 and 902 changes.

[0070] exist Figure 9B In an exemplary embodiment, in response to a change in the data storage state of entity management units 901 and 902, memory management circuit 51 can update the valid node management data in valid node management tables 911 and 912. For example, in response to data stored in entity nodes 931(0) to 931(3) becoming invalid data, memory management circuit 51 can update multiple identification bits in valid node management tables 911 and 912 corresponding to entity nodes 931(0) to 931(3) from bit "1" to bit "0". Furthermore, in response to valid data being stored in entity nodes 941(0) to 941(7), memory management circuit 51 can update multiple identification bits in valid node management table 912 corresponding to entity nodes 941(0) to 941(7) from bit "0" to bit "1".

[0071] Please refer to Figure 9C , continuing Figure 9BIn an exemplary embodiment, it is assumed that the memory management circuit 51 continues to receive at least one operation instruction (also referred to as a second operation instruction) from the host system 11. The second operation instruction instructs the deletion of data belonging to logic units L(2) to L(5). In response to the second operation instruction, the memory management circuit 51 may mark the data stored in physical nodes 941(2) to 941(5) as invalid data. In other words, in response to the second operation instruction, the data storage state of physical management units 901 and 902 changes again.

[0072] exist Figure 9C In an exemplary embodiment, in response to a change in the data storage status of entity management units 901 and 902, memory management circuit 51 may update the valid node management data in valid node management tables 911 and 912 again. For example, in response to data stored in entity nodes 941(2) to 941(5) becoming invalid data, memory management circuit 51 may update multiple identification bits in valid node management table 912 corresponding to entity nodes 941(2) to 941(5) from bit "1" to bit "0".

[0073] In other words, in Figures 9A to 9C In the exemplary embodiment, by continuously updating, maintaining and managing the valid node management tables 911 and 912, the valid node management data in the valid node management tables 911 and 912 can continuously reflect the latest data storage status of the entity management units 901 and 902 and / or the latest distribution of valid nodes in the entity management units 901 and 902.

[0074] In one exemplary embodiment, the memory management circuit 51 may also create a compression table. The memory management circuit 51 may store compressed data corresponding to the first valid node management data in this compression table. This compressed data may be generated based on the first valid node management data. For example, the memory management circuit 51 may perform compression processing on the first valid node management data to generate this compressed data. Furthermore, the compression table may also be stored in the system area of ​​the rewritable non-volatile memory module 43.

[0075] In one exemplary embodiment, compared to the first valid node management data which uses a single identification bit to indicate whether a single entity node is a valid node (e.g., ...), ... Figure 7 , Figures 9A to 9C As shown, the compressed data is modified to use fewer identification bits to represent whether the same number of entity nodes are all valid nodes (for example, using a single identification bit to represent whether multiple entity nodes are all valid nodes). By compressing the management data of the first valid node, the amount of storage space used can be effectively reduced.

[0076] In one exemplary embodiment, the compressed data includes first compressed data. The memory management circuit 51 can generate the first compressed data based on valid node management data within a specific data range (also referred to as a target range) from the first valid node management data. In one exemplary embodiment, at least one identification bit in the first compressed data can reflect the numerical distribution of valid node management data within the target range from the first valid node management data based on a smaller amount of data.

[0077] In one exemplary embodiment, at least one identification bit in the first compressed data may reflect the offset of the target range relative to a first valid node management table based on a smaller amount of data. This offset can be used to locate the target range in the first valid node management table. Subsequently, the memory management circuit 51 may use this offset to determine the valid node management data belonging to the target range in the first valid node management table.

[0078] In one exemplary embodiment, the first compressed data may include a flag bit and an identification bit corresponding to the flag bit. If the flag bit is a first value, the identification bit may reflect the numerical distribution of multiple identification bits belonging to the target range in the first valid node management data. Furthermore, if the flag bit is a second value, the identification bit may reflect the offset value of the target range relative to the first valid node management table.

[0079] Figure 10 This is a schematic diagram of a compressed table according to an exemplary embodiment of the present invention. Please refer to... Figure 10 The compressed table 1001 can store multiple compressed data entries. These compressed data entries can be generated based on the first valid node management data. For example, these compressed data entries include content (A) to content (C) corresponding to ranges (A) to (C), respectively. Here, range (i) corresponds to a target range in the first valid node management data, and content (i) is the compressed data corresponding to this target range.

[0080] For example, if the flag bit in content (C) is the first value (e.g., bit "1"), the identification bits in content (C) can reflect the value distribution state of the identification bits in the first valid node management data corresponding to range (C). For example, if the flag bit in content (C) is the first value (e.g., bit "1") and the identification bits in content (C) are bit "1", it means that the identification bits in the first valid node management data corresponding to range (C) are all bit "1". In addition, if the flag bit in content (C) is the first value (e.g., bit "1") and the identification bits in content (C) are bit "0", it means that the identification bits in the first valid node management data corresponding to range (C) are all bit "0". However, in another example embodiment, the identification bits in the compressed data can also present the value distribution state of the identification bits in the original first valid node management data in other ways, which are not limited in the present application. On the other hand, if the flag bit in content (C) is the second value (e.g., bit "0"), the identification bits in content (C) can reflect the offset value of range (C) compared to the first valid node management table.

[0081] In an example embodiment, the memory management circuit 51 can obtain the distribution state of the valid nodes in the first physical management unit according to the compressed data in the compressed table. For example, if the flag bit in content (A) is bit "1", the memory management circuit 51 can obtain the state (e.g., all valid nodes or invalid nodes) of the physical nodes in the first physical management unit corresponding to range (A) according to the identification bits in content (A). In addition, if the flag bit in content (B) is bit "0", the memory management circuit 51 can obtain the offset value of range (B) compared to the first valid node management table according to the identification bits in content (B). Then, the memory management circuit 51 can read the identification bits of the physical nodes from the first valid node management table according to the offset value. Then, the memory management circuit 51 can obtain the state of the physical nodes according to the identification bits.

[0082] It should be noted that, Figure 10 The description of the compressed data in the compressed table 1001 in the example embodiment of the present application is only an example. In other example embodiments, the description of the compressed data can also be adjusted according to practical needs, which are not limited in the present application.

[0083] Figure 11 is a flowchart of the valid node management method according to an example embodiment of the present application. Please refer to Figure 11In step S1101, an active node management table corresponding to the first entity management unit is established. In step S1102, active node management data reflecting the distribution of active nodes in the first entity management unit is stored in the active node management table. In step S1103, an operation instruction is received from the host system, wherein the operation instruction is used to change the data storage state of the first entity management unit. In step S1104, in response to the operation instruction, the active node management data in the active node management table is updated.

[0084] However, Figure 11 The above steps have been described in detail, and thus will not be repeated here. It is worth noting that, Figure 11 The steps in the above embodiments can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. In addition, Figure 11 The method of the present application can be used in combination with the above embodiments, or can be used alone, and the present application is not limited thereto.

[0085] In summary, the active node management method, memory storage device and memory control circuit unit of the embodiments of the present application can use an active node management table to reflect the current data storage state of a specific entity management unit and / or the distribution of active nodes in the specific entity management unit. In addition, by dynamically updating, maintaining and managing the active node management table, the data in the active node management table can immediately reflect the latest data storage state of the specific entity management unit and / or the latest distribution of active nodes in the specific entity management unit. Thus, the execution efficiency of any data processing program (such as a garbage collection program or a wear leveling program) that needs to refer to the current data storage state of the entity management unit can be effectively improved.

[0086] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions described in the above embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An effective node management method, characterized by, A method for managing valid nodes in a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical management units, and the method comprises: establishing a valid node management table corresponding to a first physical management unit of the plurality of physical management units; storing valid node management data in the valid node management table, wherein the valid node management data reflects a distribution of valid nodes in the first physical management unit; receiving an operation instruction from a host system, wherein the operation instruction is used to change a data storage state of the first physical management unit; updating the valid node management data in the valid node management table in response to the operation instruction; establishing a compression table; and storing compression data corresponding to the valid node management data in the compression table, wherein the compression data represents a same number of physical nodes in the first physical management unit with less identification bits than the valid node management data.

2. The method of claim 1, wherein one identification bit in the valid node management data is used to represent whether a single physical node in the first physical management unit is the valid node.

3. The method of claim 1, further comprising: deleting the valid node management table in response to an absence of the valid node in the first physical management unit.

4. The method of claim 1, further comprising: establishing an index table; storing address information of the valid node management table in the index table; reading the index table to obtain the address information of the valid node management table; and reading the valid node management table from the rewritable non-volatile memory module according to the address information.

5. The method of claim 4, further comprising: removing the address information of the valid node management table from the index table in response to an absence of the valid node in the first physical management unit.

6. The method of claim 1, wherein the compression data comprises a flag bit and identification bits corresponding to the flag bit, if the flag bit is a first value, the identification bits reflect a value distribution of a plurality of identification bits in the valid node management data that belong to a target range, and if the flag bit is a second value, the identification bits reflect an offset value of the target range compared to the valid node management table. comprising:

7. A memory storage device, characterized by, a connection interface unit connected to a host system; a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical management units; and a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is used to: establish a valid node management table corresponding to a first physical management unit of the plurality of physical management units; storing valid node management data in the valid node management table, wherein the valid node management data reflects a distribution of valid nodes in the first physical management unit; receive an operation instruction from a host system, wherein the operation instruction is used to change a data storage state of the first physical management unit; update the valid node management data in the valid node management table in response to the operation instruction; establish a compression table; and store compression data corresponding to the valid node management data in the compression table, wherein the compression data represents a same number of physical nodes in the first physical management unit with less identification bits than the valid node management data. storing valid node management data in the valid node management table, wherein the valid node management data reflects a distribution of valid nodes in the first physical management unit; receiving an operation instruction from the host system, wherein the operation instruction is used to change a data storage state of the first physical management unit; updating the valid node management data in the valid node management table in response to the operation instruction; establishing a compression table; and storing compression data corresponding to the valid node management data in the compression table, wherein the compression data represents a same number of physical nodes in the first physical management unit with less identification bits than the valid node management data.

8. The memory storage device of claim 7, wherein one identification bit in the valid node management data is used to represent whether a single physical node in the first physical management unit is the valid node.

9. The memory storage device of claim 7, wherein the memory control circuit is further operative to: delete the valid node management table in response to an absence of the valid node in the first physical management unit.

10. The memory storage device of claim 7, wherein the memory control circuit is further operative to: establish an index table; store address information of the valid node management table in the index table; read the index table to obtain the address information of the valid node management table; and read the valid node management table from the rewritable non-volatile memory module according to the address information.

11. The memory storage device of claim 10, wherein the memory control circuit is further operative to: remove the address information of the valid node management table from the index table in response to an absence of the valid node in the first physical management unit.

12. The memory storage device of claim 7, wherein the compression data comprises a flag bit and identification bits corresponding to the flag bit, if the flag bit is a first value, the identification bits reflect a value distribution state of a plurality of identification bits in the valid node management data that belong to a target range, and if the flag bit is a second value, the identification bits reflect an offset value of the target range compared to the valid node management table. A memory storage device for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical management units, and the memory control circuit comprises:

13. A memory control circuit unit, characterized by a host interface connected to a host system; a memory interface connected to the rewritable non-volatile memory module; and a memory management circuit connected to the host interface and the memory interface, wherein the memory management circuit is operative to: establish a valid node management table corresponding to a first physical management unit in the plurality of physical management units; ​ storing valid node management data in the valid node management table, wherein the valid node management data reflects a distribution of valid nodes in the first physical management unit; receiving an operation instruction from the host system, wherein the operation instruction is used to change a data storage state of the first physical management unit; updating the valid node management data in the valid node management table in response to the operation instruction; establishing a compression table; and storing compression data corresponding to the valid node management data in the compression table, wherein the compression data represents a same number of physical nodes in the first physical management unit with less identification bits than the valid node management data.

14. The memory control circuit unit of claim 13, wherein one identification bit in the valid node management data is used to represent whether a single physical node in the first physical management unit is the valid node.

15. The memory control circuit unit of claim 13, wherein the memory management circuit is further used to: delete the valid node management table in response to an absence of the valid node in the first physical management unit.

16. The memory control circuit unit of claim 13, wherein the memory management circuit is further used to: establish an index table; store address information of the valid node management table in the index table; read the index table to obtain the address information of the valid node management table; and read the valid node management table from the rewritable non-volatile memory module according to the address information.

17. The memory control circuit unit of claim 16, wherein the memory management circuit is further used to: remove the address information of the valid node management table from the index table in response to an absence of the valid node in the first physical management unit.

18. The memory control circuit unit of claim 13, wherein the compression data comprises a flag bit and identification bits corresponding to the flag bit, if the flag bit is a first value, the identification bits reflect a value distribution state of a plurality of identification bits in the valid node management data that belong to a target range, and if the flag bit is a second value, the identification bits reflect an offset value of the target range compared to the valid node management table.

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