An arbitrary-remainder-based forward conversion device

Abstract

The application discloses a forward conversion device based on an arbitrary remainder base and belongs to the technical field of wireless communication. The application comprises a data segmentation module, an intra-segment processing module and an extra-segment processing module, and realizes forward conversion of a binary number with a large bit width into an RNS number with a small bit width based on an arbitrary remainder base. The application utilizes the parallel computation and non-carry features of the remainder system, provides a conversion mode for the data input end of the RNS number in a digital signal processing system, reduces the hardware complexity of the DSP device and improves the data processing speed.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, and specifically refers to a forward conversion device based on an arbitrary remainder base, which is suitable for the real-time determination of phase generation process of long-period spreading codes in spread spectrum communication systems and long-period frequency hopping sequences in frequency hopping communication systems. Background Technology

[0002] The numerical representation system of binary numbers, formed by the set of remainders obtained through modulo operations on the remainder base, is called the remainder system. Because the remainder bases are pairwise coprime and each remainder has a completely independent structure, the remainder system exhibits excellent characteristics of parallelism, no weighting, and no carry propagation. Using the remainder system, large-bit-width operations can be decomposed into multiple smaller-bit-width operations for parallel implementation. Given a fixed dynamic range of data processed by a DSP, appropriately increasing the number of remainder base channels can correspondingly shorten the critical path length, reduce system latency and area, and thus reduce the complexity, resource consumption, and power consumption of the DSP implementation. Traditional binary adders and multipliers are affected by carry propagation delay; in contrast, the characteristics of the remainder system can significantly improve the operational efficiency of arithmetic units, thus making it widely used in multiplicative digital signal processing systems, such as FIR digital filters. Nowadays, the requirements for signal processing capabilities, speed, real-time performance, and power consumption are increasing. Remainder systems introduce parallel advantages at the forefront of data or signal processing systems, reducing computational complexity, reducing the resources and power consumption required for implementation, and improving system efficiency. Therefore, remainder systems are numerical representation systems that meet the expectations of DSPs, and DSP technology based on remainder systems has become one of the hot topics in data channel design.

[0003] In forward conversion methods for binary to RNS numbers, some methods restrict the size of the remainder base, such as requiring the remainder base to be a small number like 11, 17, or 19; other methods restrict the form of the remainder base, such as 2... n ±1,2 n ±3, or a fixed form of the remainder base formed by its variants or extensions, such as r n ±1, r n ±2, etc. This forces developers to consider the numerical transformation and representation of the algorithm front-end when designing and optimizing the algorithm, or to carry out design and optimization based on specific numerical representation forms, which greatly limits the flexibility and versatility of the remainder system application.

[0004] The forward conversion method with arbitrary remainder base can convert binary numbers into RNS numbers with arbitrary remainder base. It has no special requirements on the size and structure of the data to be converted and the remainder base, which increases the range of numerical representation and effectively avoids the limitations of forward conversion. It is helpful for the parallel implementation of more general signal processing systems and is of great significance for the design of systems with low complexity, high speed, low power consumption and large dynamic range. Summary of the Invention

[0005] This invention proposes a forward conversion device based on arbitrary remainder base, which can realize the forward conversion of binary numbers to RNS numbers with arbitrary remainder base, and can represent binary numbers as RNS numbers.

[0006] The technical solution adopted in this invention is as follows:

[0007] A forward conversion device based on an arbitrary remainder base includes a data segmentation module, an intra-segment processing module, and an extra-segment processing module;

[0008] The data segmentation module divides the binary representation of the data to be processed into s segments and calculates the corresponding value K for each segment. j j = 0, 1, 2, ..., s-1, and store K in the corresponding register. j ; calculate and store in the corresponding registers q is m i The minimum number of bits required for binary representation Indicates about m i Modulo operation; calculated using a 2-input 1-output multiplier unit. Store X in the corresponding register. j ;

[0009] The intra-segment processing module will process each X j The values ​​j = 0, 1, 2, ..., s-1 are represented bit by bit and converted to binary representation (b 2q-1 b 2q-2 ...b1b0)2; calculate and store in the corresponding register. Using a 2-to-1 selector unit, based on X j The value of the bit is determined by the output: a bit that is 0 outputs 0, and a bit that is 1 outputs the corresponding value. Through 2 inputs - modulo m i The adder unit outputs all bits that are 1. The modulo sum is obtained by using a modulo adder to calculate the sum of each pair of modulo pairs. The value;

[0010] The segment external processing module uses a 2-input modulo-m approach. i Adder unit, all The modulo sum is obtained by using a modulo adder to calculate the sum of each pair of modulo pairs. The value of, i.e. The value of .

[0011] The beneficial effects of this invention are as follows:

[0012] 1. This invention can decompose data processing into multiple independent channels and implement it in parallel, thereby reducing the complexity of the signal processing system, effectively improving the system operating speed, and reducing system power consumption.

[0013] 2. This invention can realize the forward conversion of binary numbers to RNS numbers with arbitrary remainder bases, and can represent binary numbers as RNS (Residue Number System) numbers. That is, based on arbitrary remainder bases, it can realize the forward conversion of binary numbers with larger bit widths to RNS numbers with smaller bit widths.

[0014] 3. This invention utilizes the parallel computation and carry-free characteristics of the remainder system to provide a conversion method for RNS numbers at the data input end of a digital signal processing (DSP) system, reducing the hardware complexity of the DSP device and improving data processing speed. The size and structure of the remainder base are unrestricted (e.g., it does not need to be 2). n The size of the data to be converted is not limited (±1 or other forms); the remainder base can be a specific integer value or a range of values. Attached Figure Description

[0015] Figure 1 This is a schematic diagram illustrating the principle of the present invention.

[0016] Figure 2 This is a schematic diagram of the structure of the present invention.

[0017] Figure 3 In this invention, the 2-input modulus m i A schematic diagram of an adder. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0019] like Figure 2 As shown, a forward conversion device based on an arbitrary remainder basis includes a data segmentation module, an intra-segment processing module, and an extra-segment processing module. The functions of each module are as follows:

[0020] (1) Data segmentation module

[0021] 1) Convert the data to be processed into a binary representation (when the data to be processed is in another form);

[0022] 2) Padding with zeros (when the number of bits in the binary representation of the data to be processed is less than an integer multiple of the number of bits in the remainder base);

[0023] 3) Divide the data into s segments and calculate the value K for each segment. j j = 0, 1, 2, ..., s-1, i.e., K0, K1, K2, ..., K s-1 and store K in the corresponding register. j ;

[0024] 4) Calculate and store in the corresponding registers.

[0025] 5) A 2-input, 1-output multiplier unit calculates based on 3) and 4). Store X in the corresponding register. j .

[0026] (2) Intra-segment processing module

[0027] 1) Transfer each X j The values ​​j = 0, 1, 2, ..., s-1 are represented bit-by-bit, i.e., converted to binary representation, i.e. (b 2q- 1b 2q-2 ...b1b0)2;

[0028] 2) Calculate and store in the corresponding registers.

[0029] 3) 2-to-1 selector unit, based on X j The value of the bit is determined by the output: a bit that is 0 outputs 0, and a bit that is 1 outputs the corresponding value.

[0030] 4) 2 inputs - modulo m i The adder unit outputs all bits that are 1. By using a modulo adder to calculate the modulo sum pairwise, the result is obtained. The value of .

[0031] (3) External processing module

[0032] like Figure 3 As shown, 2 inputs - modulo m i Adder unit, all By using a modulo adder to calculate the modulo sum pairwise, the result is obtained. The value, that is The value of .

[0033] The principle of the device is as follows: Figure 1 As shown, the details are as follows:

[0034] Step 1: If the remainder base value m is known... i ,2 q-1 <m i <2 q q is mi The minimum number of bits required for binary representation;

[0035] Step 2: Given the data to be processed, X, 2 n-1 <X<2 n Let n be the minimum number of bits required to represent X in binary. The binary representation of X is X = (x n-1 ...x1x0)2=x n-1 2 n-1 +...+x12 1 +x020, where x i ∈{0,1}, i=0,1,...,n,(·)2 represents the binary form of the number;

[0036] Step 3: Calculate the total number of segments s that X can represent with each segment having q bits, i.e. If X has insufficient digits, zeros are padded at the highest digits to obtain X′. Therefore, the number of digits in X′ is n′ = sq, and X′ = x. n′-1 ...x1x0=x n′-1 2 n′-1 +...+x n 2 n +...+x12 1 +x020, Indicates rounding up;

[0037] Step 4: Extract the corresponding values ​​K0, K1, K2, ..., K from X′ for each segment of q bits. s-1 K j The numerical range is [0, 2]. q -1],j=0,1,2,...,s-1,Let X′=K s-1 *2 (s-1)q +...+K1*2 q +K0*2 0 Then X′ (that is, X) is based on the remainder basis m i The number of RNS is shown in equation (1-1).

[0038]

[0039] in Indicates about m i Find the remainder;

[0040] Step 5: As can be seen from Step 4, the sum... of In, each item The numerical range is [0, 2]. 2q -1], then each X item j It is represented as a 2q-bit binary number, as shown in equation (1-2).

[0041]

[0042] Among them, b h ∈{0,1},h=0,1,...,2q-1;

[0043] Step Six: Then, in Step Five, b... h =1 corresponds to As the input to a 2-input modular adder, all are obtained according to equation (1-2).

[0044] Step 7: Put all X j j = 0, 1, 2, ..., s-1 are used as the inputs of a 2-input modular adder, and the result is obtained according to equation (1-3).

[0045]

[0046] Step 8: Specifically, for Step 5, it is not necessary to expand all powers of 2, but to find the modulus m of the powers of 2 corresponding to the (n-1)th to (2q-1)th positions. i That is, as shown in equation (1-4),

[0047]

[0048] b h ∈{0,1},h=n-1,n,...,2q-2,2q-1;

[0049] Step 9: If the range of the remainder base values ​​is known (m) min ,m max ), 2a < m min ,m max <2b, where a and b are the number of bits corresponding to the binary representation of the remainder base value range, and the value range can be any of the open interval, closed interval, or half-open / half-closed interval; therefore, for step five, it is not necessary to expand all powers of 2, but to find the modulus m of the powers of 2 corresponding to the a-th to 2q-1-th bits. i That is, as shown in equation (1-5),

[0050]

[0051] b h ∈{0,1},h=a,...,2q-2,2q-1.

[0052] In summary, this invention utilizes the parallel computation and carry-free characteristics of the remainder system to provide a conversion method for RNS numbers at the data input end of a digital signal processing (DSP) system. It can achieve forward conversion of binary numbers with arbitrary remainder bases to RNS numbers, that is, represent binary numbers as RNS numbers. This invention reduces the hardware complexity of DSP devices and improves data processing speed.

Claims

1. A forward conversion device based on an arbitrary remainder basis, characterized in that, It includes a data segmentation module, an intra-segment processing module, and an inter-segment processing module; The data segmentation module divides the binary representation of the data to be processed into s segments and calculates the corresponding value K for each segment. j j = 0, 1, 2, ..., s-1, and store K in the corresponding register. j ; calculate and store in the corresponding registers q is m i The minimum number of bits required for binary representation Indicates about m i Modulo operation; calculated using a 2-input 1-output multiplier unit. Store X in the corresponding register. j ; The intra-segment processing module will process each X j The values ​​j = 0, 1, 2, ..., s-1 are represented bit by bit and converted to binary representation (b 2q- 1b 2q-2 ...b1b0)2; calculate and store in the corresponding register. Using a 2-to-1 selector unit, based on X j The value of the bit is determined by the output: a bit that is 0 outputs 0, and a bit that is 1 outputs the corresponding value. Through 2 inputs - modulo m i The adder unit outputs all bits that are 1. The modulo sum is obtained by using a modulo adder to calculate the sum of each pair of modulo pairs. The value; The segment external processing module uses a 2-input modulo-m approach. i Adder unit, all The modulo sum is obtained by using a modulo adder to calculate the sum of each pair of modulo pairs. The value of, i.e. The value of .

Images