A test method for vehicle-mounted TSN clock synchronization error

Abstract

The present invention provides a method for testing the clock synchronization error of a vehicle-mounted TSN, comprising the following steps: starting an application; configuring the node type, determining the main test node and the node under test; the main test node sending a clock synchronization error test notification; the node under test generating a random factor, sending a reverse synchronization message at a random time in each test cycle and carrying the message sending time to the main test node; the main test node receiving each reverse synchronization message, recording the message arrival time, calculating the time difference between the node under test and the main test node; determining the time difference between all slave clocks and the master clock, and judging whether the error exceeds a threshold. The present invention has the following beneficial effects: through the host computer application of each node in the TSN network, the clock synchronization error test can be performed without an external device, which is simple and convenient to implement; randomness is introduced in the test time, and the test time is completely unrelated to the clock synchronization time, making the clock synchronization error test more real and objective.

Description

Technical Field

[0001] The present invention belongs to the technical field of vehicle-mounted communication, and in particular relates to a method for testing a vehicle-mounted TSN clock synchronization error. Background Art

[0002] With the advancement of autonomous driving technology, cars are developing towards intelligence, unmanned driving, and automation. At the same time, there are high requirements for the real-time and synchronization of data transmission in the vehicle network. The clock synchronization performance of each node in the vehicle network has a great impact on vehicle safety driving, user experience, etc. The data of perception sensors such as cameras and radars can provide a basis for autonomous driving decisions. Sensor data fusion requires that each sensor be synchronized with the master clock time. Excessive synchronization error will directly affect the accuracy of fusion and may lead to wrong decisions. In addition, the clock synchronization performance of each node during the transmission of control instructions will affect the delay time of instruction execution, which is crucial for vehicle control and even affects driving safety.

[0003] Time Sensitive Networking (TSN) is a new network technology that can provide deterministic and real-time data transmission based on automotive Ethernet, and the deterministic transmission of TSN is based on precise clock synchronization. IEEE 802.1AS is the protocol used to achieve precise clock synchronization in time-sensitive networks, that is, the Generalized Precision Time Protocol (gPTP), which can achieve precise time measurement for the network and meet the demanding synchronization requirements of some applications. The clock synchronization mechanism defined by the gPTP protocol includes algorithms such as the best master clock selection, clock synchronization tree generation, link delay measurement, and clock frequency difference correction.

[0004] Theoretically, after the clocks of all nodes in the TSN network are synchronized, the clock synchronization accuracy of all nodes will be limited to a very small threshold. The gPTP protocol requires that the clock synchronization error does not exceed 1 microsecond in a network with a maximum of 7 hops. However, in practice, due to hardware equipment and other reasons, the slave clock cannot follow the master clock very well, and the time of each slave clock is not completely consistent with the master clock. Therefore, it is necessary to study the test method of clock synchronization error to promptly discover abnormal situations where the synchronization error is too large.

[0005] The existing clock synchronization error test methods are mainly divided into two categories: the second pulse method and the network message method. The second pulse method requires the master node and the slave node to output a pulse signal every full second of the synchronization time. The rising edge time difference of the pulses output by different nodes is the synchronization error. The network message method calculates the synchronization error by sending a message with synchronization time through the node in the network. Because the second pulse method generally requires the use of an oscilloscope for measurement, it is only suitable for laboratories or small networks. In the vehicle environment, the number of nodes is large and it is difficult to implement due to space constraints. Therefore, the vehicle-mounted TSN clock synchronization error is more considered through network message testing.

[0006] The test results of clock synchronization error are closely related to the selection of test time. In the clock synchronization process, the slave clock time is periodically corrected mainly through the synchronization message sent by the master clock node. After each time synchronization of the slave clock, the error approaches 0; and in each synchronization cycle, as time goes by, due to factors such as clock drift, the synchronization error value of the slave clock relative to the master clock will increase. Since the clock synchronization error fluctuates with the synchronization cycle, if the offset of the test time in each synchronization cycle is the same, the real clock synchronization error cannot be reflected. Therefore, the clock synchronization error test method needs to take measures to decouple the test time from the synchronization time to objectively reflect the real error size. Summary of the invention

[0007] In view of this, the present invention aims to propose a method for testing the clock synchronization error of a vehicle-mounted TSN to solve the above problem. The clock synchronization error of each node in the vehicle network can be tested after the clock is synchronized, and the situation where the clock synchronization error does not meet the standard can be discovered in time to ensure the communication performance of the TSN network.

[0008] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0009] A method for testing a vehicle-mounted TSN clock synchronization error comprises the following steps:

[0010] S1. Start TSN network clock synchronization;

[0011] S2. Configure the node type, determine the main test node and the node under test, and configure the clock synchronization error test period and the clock synchronization error threshold in the main test node application;

[0012] S3, start the clock synchronization error test, the main test node sends a clock synchronization error test notification to all nodes under test along the clock tree, and the clock synchronization error test notification carries the clock synchronization error test period value;

[0013] S4. After receiving the clock synchronization error test notification, each node under test reads the clock synchronization error test period, adds a random factor to the clock synchronization error test period, and sends a reverse synchronization message and a Reverse Follow_up message at a random time in each clock synchronization error test period; the reverse synchronization message and the Reverse Follow_up message are transmitted to the main test node along the reverse clock tree in the test clock domain;

[0014] S5, link delay measurement, synchronization message forwarding and residence time recording, master-slave clock frequency ratio calculation and correction mechanism and related messages of multiplexing IEEE 802.1AS protocol;

[0015] Specifically, the master port on each link of the clock tree in the test clock domain periodically initiates link delay measurement and calculates the adjacent clock frequency ratio; after receiving the reverse synchronization message, the bridge device forwards it within a certain period of time, calculates the master-slave clock frequency ratio of the current node based on the master-slave clock frequency ratio of the previous node carried in the ReverseFollow_up message and the neighbor clock frequency ratio saved by the current node, accumulates the link delay after frequency difference correction and the residence time of the current node into the correction domain of the ReverseFollow_up message, and writes the master-slave clock frequency ratio of the current node into the corresponding field of the Reverse Follow_up message;

[0016] S6. After receiving the reverse synchronization message from each node under test, the main test node records the message arrival time and calculates the time difference between the node under test and the main test node;

[0017] S7. For all reverse synchronization messages from the same clock synchronization error test cycle, the master clock time is used as the reference time to determine the time difference between all slave clocks and the master clock; if the synchronization error value of a slave clock is greater than the clock synchronization error threshold, an abnormal notification of excessive clock synchronization error of the slave clock node is generated.

[0018] Furthermore, starting TSN network clock synchronization in step S1 includes the following steps:

[0019] S11, obtaining the master clock by the best master clock algorithm election or static configuration method, dividing the clock synchronization domain and generating a clock synchronization tree;

[0020] S12: The master clock and the slave clock continue to perform periodic clock synchronization operations.

[0021] Further, the value of the clock synchronization error test period in step S2 is greater than the clock synchronization period.

[0022] Furthermore, the Reverse Follow_up message in step S4 is a message carrying the sending time of the reverse synchronization message.

[0023] Furthermore, the time difference formula between the tested node and the main test node in step S6 is:

[0024] Δt=t1+Correction+Pdelayj'-t2

[0025] Among them, Pdelayj' is the link delay measurement on the last link segment relative to the time base of the tested node, t2 is the message arrival time recorded after the main test node receives the reverse synchronization message from each test node; t1 is the sending time read from the Reverse Follow_up message; Correction is the correction domain field value; Δt is the time difference between the tested node and the main test node.

[0026] Furthermore, the clock synchronization error test period value in step S7 is set to 1 ms.

[0027] Furthermore, the clock synchronization error threshold in step S7 is 1 μs.

[0028] Compared with the prior art, the vehicle-mounted TSN clock synchronization error testing method described in the present invention has the following advantages:

[0029] The method for testing the vehicle-mounted TSN clock synchronization error described in the present invention reuses part of the mechanism and message format of the IEEE 802.1AS protocol through the host computer application of each node in the TSN network, and can perform the clock synchronization error test without the need for external equipment, which is simple and convenient to implement; and randomness is introduced in the test time, and the test time is completely unrelated to the clock synchronization time, making the clock synchronization error test more real and objective. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0031] Figure 1 A schematic diagram of the workflow of the clock synchronization error test application according to an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of message transmission for a clock synchronization error test in a TSN network according to an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the vehicle-mounted TSN network architecture described in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0035] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", and the like may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0036] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0037] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0038] like Figures 1 to 3 As shown, a method for testing a vehicle-mounted TSN clock synchronization error includes the following steps:

[0039] S1: First, start the TSN network clock synchronization, obtain the master clock through the Best Master Clock Algorithm (BMCA) election or static configuration method, divide the clock synchronization domain and generate a clock synchronization tree, and continue to perform periodic clock synchronization operations between the master and slave clocks.

[0040] S2: Before the test begins, ensure that all nodes have installed the preset clock synchronization error test application. Determine the main test node and the node under test, and configure them in the clock synchronization error test application. The main test node is generally selected from all nodes with stronger computing power. Configure the clock synchronization error test period and synchronization error threshold in the main test node application. The value of the clock synchronization error test period is generally greater than the clock synchronization period.

[0041] S3: Start the clock synchronization error test, generate a clock tree and a test clock domain (different from the clock domain for clock synchronization) with the main test node as the root node, and the main test node sends a clock synchronization error test notification to all nodes under test along the clock tree. The notification carries the clock synchronization error test period value.

[0042] S4: After receiving the clock synchronization error test notification, the node under test adds a random factor to the clock synchronization error test cycle and sends a reverse synchronization message (ReverseSync message) at a random time in each error test cycle. Similar to the clock synchronization mechanism of IEEE 802.1AS, the node under test sends a Reverse Follow_up message carrying the sending time of the Reverse Sync message after sending the Reverse Sync message. The Reverse Sync and Reverse Follow_up messages are transmitted to the main test node along the reverse clock tree in the test clock domain.

[0043] S5: Multiplex the link delay measurement, synchronization message forwarding and residence time recording, master-slave clock frequency ratio calculation correction mechanism and related messages of the IEEE 802.1AS protocol. Specifically: the master port on each link of the clock tree in the test clock domain periodically initiates link delay measurement and calculates the adjacent clock frequency ratio. After receiving the reverse synchronization message, the bridge device forwards it within a certain period of time, calculates the master-slave clock frequency ratio of this node based on the master-slave clock frequency ratio of the previous node carried in the Reverse Follow_up message and the neighbor clock frequency ratio saved by this node, and adds the link delay and the residence time of this node after the frequency difference correction to the correction field of the Reverse Follow_up message, and writes the master-slave clock frequency ratio of this node into the corresponding field of the Reverse Follow_up message.

[0044] S6: After receiving the reverse synchronization message from each node under test, the main test node records the message arrival time and calculates the time difference between the node under test and the main test node.

[0045] S7: For all reverse synchronization messages from the same clock synchronization error test cycle, the master clock time is used as the reference time to determine the time difference between all slave clocks and the master clock. If the synchronization error value of a slave clock is greater than the synchronization error threshold, an abnormal notification of excessive clock synchronization error of the slave clock node is generated.

[0046] The above steps are as follows Figure 1 With attached Figure 2 As shown. By using the above method and steps, it is possible to timely discover the situation where the clock synchronization error in the vehicle-mounted TSN network is too large and give a reminder. The present invention reuses part of the mechanism and message format of the IEEE 802.1AS protocol through the host computer application of each node in the TSN network, and can perform clock synchronization error testing without external equipment, which is simple and convenient to implement; and randomness is introduced in the test time, and the test time is completely unrelated to the clock synchronization time, making the clock synchronization error test more real and objective.

[0047] Example 1

[0048] Figure 1 This is the workflow diagram of the clock synchronization error test application. Before the test begins, the node type is configured, including the main test node and the node under test. The main test node is generally selected from all nodes with stronger computing power.

[0049] Configure the clock synchronization error test cycle and synchronization error threshold in the master test node. The value of the clock synchronization error test cycle is generally greater than the clock synchronization cycle and can be configured to 1ms. It is generally required that the on-board TSN network clock synchronization error is no more than 1μs, and the synchronization error threshold is configured to 1μs here.

[0050] Figure 2 This is a diagram of message transmission for clock synchronization error testing in a TSN network. After the clock synchronization error test starts, a clock tree and a test clock domain (different from the clock domain for clock synchronization) are generated with the master test node as the root node. The master test node sends a clock synchronization error test notification carrying a clock synchronization error test cycle value, which will be transmitted along the clock tree to all nodes under test. After that, it starts waiting to receive a reverse synchronization message from the node under test.

[0051] After receiving the clock synchronization error test notification, the node under test adds a random factor to the clock synchronization error test cycle. A reverse synchronization message (Reverse Sync message) is sent at a random time in each error test cycle, and then a Reverse Follow_up message carrying the sending time of the Reverse Sync message is sent. The Reverse Sync and Reverse Follow_up messages are transmitted to the main test node along the reverse clock tree in the test clock domain.

[0052] The clock synchronization error test can directly reuse the link delay measurement, synchronization message forwarding and residence time recording, master-slave clock frequency ratio calculation correction mechanism and related messages of the IEEE 802.1AS protocol.

[0053] The specific process of the above mechanism is as follows: the master port on each link of the clock tree in the test clock domain periodically initiates link delay measurement and calculates the adjacent clock frequency ratio. After receiving the Reverse Sync message, the bridge device forwards it within a certain period of time, and calculates the residence time residence_time from the message arrival time and forwarding time. The link delay from the previous node to the current node stored in the device is Pdelay i, and the correction field (Correction field) of the Reverse Follow_up message is updated as follows:

[0054] New Correction=Old Correction+Pdelay i'+residence_time'

[0055] The link delay Pdelay i' and the residence time residence_time' are measured values ​​relative to the time base of the measured node converted by the clock frequency ratio. The clock frequency ratio is calculated by the clock frequency ratio between the measured node and the previous node on the link recorded in the RateRatio field of the Reverse Follow_up message and the adjacent clock frequency ratio measured previously saved in the device, and the RateRatio field of the Reverse Follow_up message is updated.

[0056] After receiving the reverse synchronization message from each test node, the main test node records the message arrival time t2, reads the sending time t1 and the correction field value in the Reverse Follow_up message, and calculates the time difference Δt between the node under test and the main test node:

[0057] Δt=t1+Correction+Pdelayj'-t2

[0058] Where Pdelayj' is the link delay measure on the last link segment relative to the time base of the node under test.

[0059] For all reverse synchronization messages from the same clock synchronization error test cycle, the master clock time is used as the reference time to determine the time difference between all slave clocks and the master clock. For example, based on the reverse synchronization messages from the same test cycle, the time differences between the tested node 1 (slave clock node) and the tested node 2 (master clock node) and the master test node are calculated as Δt1 and Δt2 respectively. The clock synchronization error of the tested node 1 at this time is:

[0060] δ1=Δt1-Δt2

[0061] If the clock synchronization error value of the node is greater than the synchronization error threshold, δ1>1μs, an abnormal notification of excessive clock synchronization error of the node is generated.

[0062] Figure 3 This is a schematic diagram of the vehicle-mounted TSN network architecture. The T-box module can communicate with satellites for GNSS timing and is selected as the master clock node. The remaining switches, sensors, actuators, and central computing platforms are all slave clock nodes. Because the central computing platform has strong computing power, it is configured as the master test node in its clock synchronization error test application and as the tested node in other node test applications.

[0063] During the clock synchronization process of the vehicle TSN network, the synchronization message is sent from the T-box module to the central computing platform, and then to each sensor and actuator node via the switch. During the clock synchronization error test, each node except the central computing platform sends a reverse synchronization message, which arrives at the central computing platform via a transmission path different from the clock synchronization process. The test application of the central computing platform node calculates the time difference between each node under test and the synchronization clock of this node, and then calculates the clock synchronization error of each slave clock based on the master clock time, and issues an abnormal notification if the error is too large.

[0064] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for testing vehicle-mounted TSN clock synchronization error, characterized in that: The following steps are involved: S1. Start TSN network clock synchronization; S2. Configure the node type, determine the main test node and the node under test, and configure the clock synchronization error test period and the clock synchronization error threshold in the main test node application; S3, start the clock synchronization error test, the main test node sends a clock synchronization error test notification to all nodes under test along the clock tree, and the clock synchronization error test notification carries the clock synchronization error test period value; S4. After receiving the clock synchronization error test notification, each node under test reads the clock synchronization error test period, adds a random factor to the clock synchronization error test period, and sends a reverse synchronization message and a Reverse Follow_up message at a random time in each clock synchronization error test period; the reverse synchronization message and the Reverse Follow_up message are transmitted to the main test node along the reverse clock tree in the test clock domain; S5, link delay measurement, synchronization message forwarding and residence time recording, master-slave clock frequency ratio calculation and correction mechanism and related messages of multiplexing IEEE 802.1AS protocol; Specifically, the master port on each link of the clock tree in the test clock domain periodically initiates link delay measurement and calculates the adjacent clock frequency ratio; after receiving the reverse synchronization message, the bridge device forwards it within a certain period of time, calculates the master-slave clock frequency ratio of the current node based on the master-slave clock frequency ratio of the previous node carried in the ReverseFollow_up message and the neighbor clock frequency ratio saved by the current node, accumulates the link delay after frequency difference correction and the residence time of the current node into the correction domain of the ReverseFollow_up message, and writes the master-slave clock frequency ratio of the current node into the corresponding field of the Reverse Follow_up message; S6. After receiving the reverse synchronization message from each node under test, the main test node records the message arrival time and calculates the time difference between the node under test and the main test node; S7, for all reverse synchronization messages from the same clock synchronization error test cycle, using the master clock time as the reference time, determine the time difference between all slave clocks and the master clock; If the synchronization error value of a slave clock is greater than the clock synchronization error threshold, an abnormal notification of excessive clock synchronization error of the slave clock is generated.

2. The method for testing vehicle-mounted TSN clock synchronization error according to claim 1, characterized in that: Starting TSN network clock synchronization in step S1 includes the following steps: S11, obtaining the master clock by the best master clock algorithm election or static configuration method, dividing the clock synchronization domain and generating a clock synchronization tree; S12: The master clock and the slave clock continue to perform periodic clock synchronization operations.

3. The method for testing vehicle-mounted TSN clock synchronization error according to claim 1, characterized in that: The value of the clock synchronization error test period in step S2 is greater than the period of clock synchronization.

4. The method for testing vehicle-mounted TSN clock synchronization error according to claim 1, characterized in that: The Reverse Follow_up message in step S4 is a message carrying the sending time of the reverse synchronization message.

5. The method for testing vehicle-mounted TSN clock synchronization error according to claim 1, characterized in that: The time difference formula between the tested node and the main test node in step S6 is: Δt=t1+Correction+Pdelayj'-t2 Among them, Pdelayj' is the link delay measurement on the last link segment relative to the time base of the tested node, t2 is the message arrival time recorded after the main test node receives the reverse synchronization message from each test node; t1 is the sending time read from the Reverse Follow_up message; Correction is the correction domain field value; Δt is the time difference between the tested node and the main test node.

6. The method for testing vehicle-mounted TSN clock synchronization error according to claim 1, characterized in that: The clock synchronization error test period value in step S7 is set to 1 ms.

7. The method for testing vehicle-mounted TSN clock synchronization error according to claim 1, characterized in that: The clock synchronization error threshold in step S7 is 1 μs.

8. An electronic device, comprising a processor and a memory connected to the processor for storing instructions executable by the processor, characterized in that: The processor is used to execute a vehicle-mounted TSN clock synchronization error testing method as described in any one of claims 1-7.

9. A server, characterized in that: It includes at least one processor and a memory communicatively connected to the processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor so that the at least one processor executes a method for testing a vehicle-mounted TSN clock synchronization error as described in any one of claims 1-7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, a method for testing a vehicle-mounted TSN clock synchronization error as described in any one of claims 1 to 7 is implemented.

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