Video signal decoding circuit, method, electronic device and storage medium

Abstract

The present invention provides a decoding circuit, method, electronic device and storage medium for video signals. The decoding circuit includes an interface module, a phase-locked loop module and a control module; the control module is used to obtain a video signal and a data stream clock signal, determine the end flag of the first blanking area in each frame of the video signal, determine the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal according to the end flag of the first blanking area in each frame, and determine a timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal and the main data stream attribute parameters; wherein, the horizontal synchronization signal and the vertical synchronization signal in the timing format signal group for controlling the display of the picture are aligned with the end flag of the first blanking area appearing in each frame of the video signal. Through the above method, the present invention can correctly decode video signals with a dynamic refresh frequency and generate a timing format signal group required by the subsequent display system.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a decoding circuit, method, electronic device and storage medium for a video signal. Background Art

[0002] With the rapid development of the gaming industry in recent years, gamers are increasingly pursuing the consistency and delicacy of game screen details. Based on this demand, the technology for dynamically changing the frame refresh rate has emerged. For example, in a fierce shooting scene in the game, the game player needs to move the mouse aiming device in a very short time to track and aim at the enemy. At this time, the game rendering end (such as the graphics card) can use a very high frame refresh rate such as 165Hz to quickly update the game screen, so that the player does not feel the lag and tearing; when the game scene switches to a relatively quiet surrounding and the scenery does not change often, such as a gunman squatting in a corner to ambush the enemy, the game rendering end can use a very low graphics refresh rate such as 30Hz to update the screen, which can reduce the system power consumption by reducing the frequency of image rendering.

[0003] The width of the vertical blanking block in the video signal may change at any time, which results in that the existing decoding mechanism of the video signal is no longer applicable to the video signal whose vertical blanking block width changes at any time. For example, free-sync is a technology that can achieve dynamically variable refresh rate. The free-sync DP (DisplayPort) video signal, like the ordinary DP video signal, needs to be packaged in a specific format before transmission. The display device needs to decode the packaged data to generate a signal group that meets the display processing needs of the display device; however, since the width of the vertical blanking block in the free-sync DP video signal can change at any time, the existing decoding mechanism of the DP video signal is no longer applicable to free-sync. The display device using free-sync cannot rely on the information of the main data stream attributes to reconstruct the signal group like ordinary display devices, which ultimately makes the display device unable to display the refreshed picture normally. Therefore, it is necessary to find a new decoding mechanism that adapts to the video signal whose vertical blanking block width changes at any time. Summary of the invention

[0004] The invention provides a decoding circuit, method, electronic equipment and storage medium for a video signal, which are used to solve the defect of a video signal with a dynamic refresh frequency that cannot be correctly decoded in the prior art.

[0005] The present invention provides a decoding circuit for a video signal, comprising an interface module, a phase-locked loop module and a control module; wherein, the interface module is respectively connected to the phase-locked loop module and the control module; the phase-locked loop module is connected to the control module; the interface module is used to obtain the video signal and the link clock signal; the phase-locked loop module is used to obtain the link clock signal and generate a data stream clock signal according to the link clock signal; the control module is used to obtain the video signal and the data stream clock signal, determine the end flag of the first blanking area of each frame in the video signal, determine the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal according to the end flag of the first blanking area of each frame, and determine a timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal and the main data stream attribute parameters; wherein, the timing format signal group for controlling the display of the picture includes a horizontal synchronization signal, a vertical synchronization signal, a data valid signal, a pixel signal and a data stream clock signal; the horizontal synchronization signal and the vertical synchronization signal are aligned with the end flag of the first blanking area appearing in each frame of the video signal.

[0006] According to the decoding circuit for a video signal provided by the present invention, the control module includes a timing generation module and a buffer module; the timing generation module is connected to the buffer module; the timing generation module is used to obtain the video signal and the data stream clock signal, determine the end flag of the first blanking area of each frame in the video signal, determine the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal according to the end flag of the first blanking area of each frame, and determine the horizontal synchronization signal and the data valid signal according to the data stream clock signal and the main data stream attribute parameters; and finally output the horizontal synchronization signal, the vertical synchronization signal, the data valid signal and the data stream clock signal; the buffer module is used to write the picture data in the video signal when responding to the end flag of the first blanking area of each frame in the video signal; and read out the picture data as the pixel signal when responding to the data valid signal.

[0007] According to the decoding circuit for a video signal provided by the present invention, it further includes a measurement module, wherein the measurement module is respectively connected to the interface module and the control module; the measurement module is used to measure the period information of the video signal based on the link clock signal, wherein the period signal is used to determine the horizontal synchronization signal and the data valid signal.

[0008] According to the decoding circuit for a video signal provided by the present invention, it further includes a frequency tracking module, wherein the frequency tracking module is respectively connected to the interface module, the phase-locked loop module and the control module; the frequency tracking module includes a frequency discriminator and a modulator; the modulator is respectively connected to the frequency discriminator and the phase-locked loop module; the frequency discriminator is used to compare the positions of the end flag of the blanking area and the horizontal synchronization signal on the time axis, and the modulator is used to adjust the data stream clock signal according to the comparison result of the frequency discriminator so that the data stream clock signal is dynamically equal to the initial data stream clock signal of the source device sending the video signal.

[0009] A decoding circuit for a video signal provided by the present invention further includes an auxiliary data packet module, and the auxiliary data packet module is connected to the interface module; the auxiliary data packet module is used to receive and save the auxiliary data packet data that meets the preset conditions, and to monitor the change situation of the received auxiliary data packet data in real time.

[0010] The present invention also provides a method for decoding a video signal, including: obtaining a video signal and a link clock signal; determining a data stream clock signal based on the link clock signal; determining the end flag of the first blanking area of each frame in the video signal, and determining the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal according to the end flag of the first blanking area of each frame; determining a timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal, and the main data stream attribute parameters; wherein, the timing format signal group for controlling the display of the picture includes a horizontal synchronization signal, a vertical synchronization signal, a data valid signal, a pixel signal, and a data stream clock signal; the horizontal synchronization signal and the vertical synchronization signal are aligned with the end flag of the first blanking area that appears in each frame of the video signal.

[0011] A method for decoding a video signal provided by the present invention, determining a timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal, and the main data stream attribute parameters, includes: after determining the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal, repeating and initiating the horizontal synchronization signal with a first preset period and a first preset valid length until determining the end flag of the last blanking area in this frame of the video signal; when determining that the end flag of the first blanking area of each frame in the video signal arrives, determining the rising edge of the data valid signal after a first preset time, and repeating and initiating the data valid signal with a second preset period and a second preset valid length until determining the end flag of the last blanking area in this frame of the video signal; wherein, the first preset period, the first preset valid length, the second preset period, and the second preset valid length are determined according to the data stream clock signal and the main data stream attribute parameters.

[0012] A method for decoding a video signal provided by the present invention, when determining that the end flag of the first blanking area of each frame in the video signal arrives, determining the rising edge of the data valid signal after a first preset time, and repeating and initiating the data valid signal with a second preset period and a second preset valid length until determining the end flag of the last blanking area in this frame of the video signal, includes: when determining that the end flag of the first blanking area of each frame in the video signal arrives, storing the picture data in the video signal into the cache module, wherein the time-consuming for the cache module to cache the picture data is the first preset time; in response to the rising edge of the data valid signal, the picture data is read from the cache module.

[0013] A video signal decoding method provided by the present invention, wherein the buffer depth of the buffer module is greater than the picture data depth; wherein, the picture data depth is determined according to the picture data, the first preset time, and the data stream clock.

[0014] A video signal decoding method provided by the present invention, which determines a timing format signal group for controlling the display of a picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal, and the main data stream attribute parameters, and further includes: determining a first time period between two adjacent blanking area start flags within the same frame based on the first measurement period and the time coefficient; wherein, the first measurement period is a period for measuring the time length between two adjacent blanking area start flags within the same frame based on the link clock signal; determining a second time period between the blanking area end flag within the first time period and the blanking area start flag within the next first time period based on the second measurement period and the time coefficient; wherein, the second measurement period is a period for measuring the time length between the blanking area end flag within the first time period and the blanking area start flag within the next first time period based on the link clock signal; wherein, the first time period is equal to the sum of the second time period and the third time period, and the third time period is the time length between the blanking area start flag and the blanking area end flag within the same first time period; the second time period is equal to the second preset effective length of the data valid signal.

[0015] A video signal decoding method provided by the present invention, which determines the data stream clock signal based on the link clock signal, including: comparing the positions of the blanking area end flag and the horizontal synchronization signal on the time axis based on the tracking signal, and adjusting the data stream clock signal according to the comparison result.

[0016] A video signal decoding method provided by the present invention, which compares the positions of the blanking area end flag and the horizontal synchronization signal on the time axis based on the tracking signal, and adjusts the data stream clock signal according to the comparison result, including: if the occurrence time of the horizontal synchronization signal is later than the occurrence time of the blanking area end flag, increasing the frequency of the data stream clock signal; if the occurrence time of the horizontal synchronization signal is earlier than the occurrence time of the blanking area end flag, decreasing the frequency of the data stream clock signal.

[0017] The present invention further provides an electronic device, including the decoding circuit for the video signal described in any one of the above.

[0018] The present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the video signal decoding method described in any one of the above.

[0019] The decoding circuit, method, electronic device, and storage medium for video signals provided by the present invention determine the end flag of the first blanking area in each frame of the video signal through a control module, determine the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal according to the end flag of the first blanking area in each frame, and determine a timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal, and the main data stream attribute parameters; in the above manner, the rising edge of the vertical synchronization signal is synchronized with the end flag of the first blanking area in each frame, that is, the relative position of the vertical synchronization signal and the effective display area is fixed. Therefore, the video signal with the correct decoding dynamic refresh frequency can be determined according to this feature, and a timing format signal group required by the subsequent display system can be generated. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings.

[0021] Figure 1 It is a schematic connection diagram of an embodiment of the present invention from the source device to the display panel;

[0022] Figure 2 It is a schematic structural diagram of an embodiment of the decoding circuit of the video signal of the present invention;

[0023] Figure 3 It is a schematic diagram of an embodiment of the change of adjacent two-frame vertical blanking blocks of the present invention;

[0024] Figure 4 It is a schematic diagram of an embodiment of the frequency tracking module and the phase-locked loop module of the present invention;

[0025] Figure 5 It is a schematic structural diagram of another embodiment of the decoding circuit of the video signal of the present invention;

[0026] Figure 6 It is a schematic flowchart of an embodiment of the decoding method of the video signal of the present invention;

[0027] Figure 7 It is a schematic timing diagram of an embodiment of the decoding method of the video signal of the present invention;

[0028] Figure 8 is Figure 7 a schematic diagram of the timing details near the vertical synchronization signal in;

[0029] Figure 9It is a timing schematic diagram of an embodiment of the data stream clock signal of the present invention. Detailed implementation manners

[0030] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] The technology of dynamically changing the frame refresh rate includes the production of video content, the rendering of video pictures during operation, and the display of video pictures by a display device. This is an industrial chain, and all devices on the chain need to support the dynamically variable refresh rate technology under the same specifications.

[0032] Please refer to Figure 1 , Figure 1 It is a link schematic diagram of an embodiment of the present invention from a source device to a display panel. The source device identifies whether the display device supports the ability to dynamically change the frame refresh rate by reading the data of the display device, and shakes hands with the display device. After determining that both parties support it, the source device will transmit the signal format of the dynamically changing frame refresh rate.

[0033] The source device sends a video signal and a link clock signal to the receiving end of the display IC area. The receiving end generates a group of timing format signals for controlling the display of the picture according to the video signal and the link clock signal, and sends the group of timing format signals for controlling the display of the picture to the data processor, so that the data processor controls the display panel to display according to the group of timing format signals.

[0034] The improvement of the present invention mainly lies in the video signal decoding circuit in the receiving end. Please refer to Figure 2 , Figure 2 It is a structural schematic diagram of an embodiment of the decoding circuit of the video signal of the present invention. In this embodiment, the decoding circuit of the video signal may include an interface module 110, a phase-locked loop module 120, and a control module 130. Among them, the interface module 110 is respectively connected to the phase-locked loop module 120 and the control module 130; the phase-locked loop module 120 is connected to the control module 130.

[0035] The interface module 110 is used to obtain the video signal and the link clock signal. Optionally, the interface module 110 may include a physical interface module and a signal separation module.

[0036] Optionally, the interface in this embodiment may be a DP interface. The DP interface adds support for the transmission of high-definition audio signals while transmitting video signals, and also supports higher resolutions and refresh rates.

[0037] The phase-locked loop module 120 is used to obtain a link clock signal and generate a data stream clock signal based on the link clock signal.

[0038] The control module 130 is used to obtain a video signal and a data stream clock signal, determine the end flag BE of the first blanking area in each frame of the video signal, determine the rising edge of the horizontal synchronization signal HS and the rising edge of the vertical synchronization signal VS according to the end flag BE of the first blanking area in each frame, and determine a timing format signal group (Timing Format) for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal HS, the rising edge of the vertical synchronization signal VS, and the main data stream attribute (MSA) parameter.

[0039] Among them, the timing format signal group for controlling the display of the picture includes a horizontal synchronization signal HS, a vertical synchronization signal VS, a data enable signal (Data Enable, DEN), a pixel signal, and a data stream clock signal; the horizontal synchronization signal HS and the vertical synchronization signal VS are aligned with the end flag BE of the first blanking area that appears in each frame of the video signal. The pixel signal includes signals such as R (Vr), G (Yg), and B (Ub).

[0040] Free-sync is a technology that can achieve dynamic variable refresh rate using a DP interface. The following takes DP free-sync as an example to introduce the video signal decoding mechanism of this embodiment.

[0041] Similar to ordinary DP signals, the DP video signal of AMD free-sync uses 4 main link data channels to transmit data. There is no clock signal and direct timing signal on the transmission interface (its timing signal is transmitted through the main data stream attribute MSA parameter), and it packs the data content in a specific format and then transmits it. The display device needs to decode the packed data to restore the timing that conforms to the image restoration of the display device before it can play the picture on the panel. However, since the width of the vertical blanking block in the DP video signal may change at any time, the timing signal cannot directly depend on the main data stream attribute MSA parameter to obtain.

[0042] Please refer to Figure 3 , Figure 3 is a schematic diagram of an embodiment of the change of adjacent two-frame vertical blanking blocks of the present invention. It can be seen from Figure 3 that the width of the vertical blanking block of the nth frame is not equal to the width of the vertical blanking block of the n + 1th frame. For the convenience of subsequent processing, this embodiment selects to make the relative position of the rising edge of the vertical synchronization signal VS and the first data line of the effective display area fixed.

[0043] However, since the vertical blanking block is variable, it is necessary to go back and locate the rising edge of the vertical synchronization signal VS only after seeing the effective display area on the time axis. Therefore, in this embodiment, the design adopts tracking the end flag BE of the first blanking area of each frame, using the end flag BE of the first blanking area as a reference for pulling up the rising edge of the vertical synchronization signal VS, and simultaneously pulling up the rising edge of the horizontal synchronization signal HS to ensure that the rising edge of the horizontal synchronization signal HS is aligned with the rising edge of the vertical synchronization signal VS.

[0044] In some embodiments, the control module 130 may include a timing generation module 131 and a buffer module 132; the timing generation module 131 is connected to the buffer module 132.

[0045] The timing generation module 131 is used to obtain a video signal and a data stream clock signal, determine the end flag BE of the first blanking area of each frame in the video signal, determine the rising edge of the horizontal synchronization signal HS and the rising edge of the vertical synchronization signal VS according to the end flag BE of the first blanking area of each frame, and determine the horizontal synchronization signal HS and the data valid signal DEN according to the data stream clock signal and the main data stream attribute parameters; finally, output the horizontal synchronization signal HS, the vertical synchronization signal VS, the data valid signal DEN and the data stream clock signal;

[0046] The buffer module 132 is used to write the picture data in the video signal when responding to the end flag BE of the first blanking area of each frame in the video signal; when responding to the data valid signal DEN, read out the picture data as a pixel signal.

[0047] Among them, the buffer module 132 may be a FIFO (First Input First Output), that is, a first-in first-out queue.

[0048] Optionally, the buffer depth of the buffer module FIFO is greater than the picture data depth; among them, the picture data depth is determined according to the picture data, the first preset time and the data stream clock. Among them, the time taken for the buffer module FIFO to buffer the picture data is the first preset time.

[0049] In some embodiments, the decoding circuit of the video signal may further include a measurement module, where the measurement module is respectively connected to the interface module and the control module. The measurement module is used to measure the period information of the video signal based on the link clock signal, where the period signal is used to determine the horizontal synchronization signal HS and the data valid signal DEN.

[0050] Optionally, the measurement module can be used to measure a first measurement period and a second measurement period. The first measurement period is the period during which the measurement module measures the time length between two adjacent blanking area start flags BS within the same frame based on the link clock signal. The second measurement period is the period during which the measurement module measures the time length between the blanking area end flag BE within the first time period and the blanking area start flag BS within the next first time period based on the link clock signal.

[0051] The first measurement period and the second measurement period can be used to determine a first time period H-Total between two adjacent blanking area start flags BS within the same frame and a second time period H-Width between the blanking area end flag BE within the first time period and the blanking area start flag BS within the next first time period.

[0052] In some embodiments, the decoding circuit of the video signal may further include a frequency tracking module. The frequency tracking module is respectively connected to the interface module, the phase-locked loop module, and the control module.

[0053] Please refer to Figure 4 , Figure 4 FIG. is a schematic diagram of an embodiment of the frequency tracking module and the phase-locked loop module of the present invention. The phase-locked loop module is used to generate an initial data stream clock signal, and the frequency tracking module is used to perform subsequent frequency tracking on the data stream clock signal. The phase-locked loop module may include a voltage-controlled oscillator, a frequency discriminator and phase detector, an Nvid calculation module, and an Mvid calculation module.

[0054] The Nvid calculation module is connected to the frequency discriminator and phase detector of the phase-locked loop module. The Nvid calculation module is used to receive the link clock signal and the Nvid parameter, and input the calculation result of dividing the link clock signal by the Nvid parameter into the frequency discriminator and phase detector of the phase-locked loop module.

[0055] The output end of the frequency discriminator and phase detector of the phase-locked loop module is connected to the voltage-controlled oscillator, and the voltage-controlled oscillator outputs the data stream clock signal. And the data stream clock signal passes through the Mvid calculation module, and the Mvid calculation module inputs the calculation result of dividing the data stream clock signal by the Mvid parameter into the frequency discriminator and phase detector of the phase-locked loop module.

[0056] The frequency tracking module includes a frequency discriminator and phase detector and a modulator. The modulator in the frequency tracking module is connected to the Mvid calculation module in the phase-locked loop module. Optionally, the frequency discriminator and phase detector in the frequency tracking module can be a digital frequency discriminator and phase detector.

[0057] In the frequency tracking module, the modulator is respectively connected to the frequency discriminator and phase detector of the frequency tracking module and the Mvid calculation module of the phase-locked loop module; the frequency discriminator and phase detector of the frequency tracking module is used to compare the positions of the blanking interval end flag BE and the horizontal sync signal HS on the time axis, and the modulator is used to adjust the data stream clock signal according to the comparison result of the frequency discriminator and phase detector of the frequency tracking module, so that the data stream clock signal is dynamically equal to the initial data stream clock signal of the source device that sends the video signal.

[0058] The purpose of the frequency tracking module is to make the frequency of the data stream clock signal almost equal to the frequency of the original data stream clock signal of the source device to avoid data loss due to overflow or underflow in the buffer module. To achieve this purpose, it can be ensured that the time period between the original BEs is equal to the period between the HSs in the timing format signal group of the control picture reconstructed by the reference data stream clock signal, that is, the purpose is achieved. In fact, due to the sensitivity limitation of the voltage-controlled oscillator in the phase-locked loop module, it is impossible to truly achieve complete equality in the circuit, but a dynamic equality can be achieved, that is, the average period is equal within a period of time. Then, with the help of the buffer module to buffer the dynamic drift in frequency, the data buffered in the buffer module fluctuates up and down. As long as overflow or underflow does not occur, dynamic balance is achieved.

[0059] Specifically, if the occurrence time of the horizontal sync signal HS is later than the occurrence time of the blanking interval end flag BE, the frequency of the data stream clock signal is increased; if the occurrence time of the horizontal sync signal HS is earlier than the occurrence time of the blanking interval end flag BE, the frequency of the data stream clock signal is decreased.

[0060] It should be noted that the Mvid parameter and the Nvid parameter can be obtained through the MSA parameter.

[0061] In some embodiments, the decoding circuit of the video signal may further include an auxiliary data packet module, and the auxiliary data packet module is connected to the interface module. The auxiliary data packet (SDP) can be regarded as an optional secondary data packet. The auxiliary data packet module is used to receive and save the auxiliary data packet data that meets the preset conditions and monitor the change of the received auxiliary data packet data in real time.

[0062] Optionally, the auxiliary data packet module may include an SDP decoding module and an SDP caching module. Among them, the SDP decoding module is respectively connected to the signal separation module and the SDP caching module. The SDP decoding module can decode the received auxiliary data packet, determine the qualified SDP data, and save the qualified data into the SDP caching module. The SDP decoding module can also monitor the change of the SDP data received from the source device in real time. AMD free-sync needs to inform other auxiliary parameters for the continuous normal operation of the display system through specific auxiliary data packets.

[0063] The modules in the above embodiments can be freely combined without conflict. Those skilled in the art can set up a video signal decoding circuit with multiple modules according to the actual situation. As Figure 5 shown, Figure 5 is a schematic structural diagram of another embodiment of the decoding circuit of the video signal of the present invention. In this embodiment, the decoding circuit of the video signal includes an interface module 210, a phase-locked loop module 220, a control module 230, a measurement module 240, a frequency tracking module 250, and an auxiliary data packet module 260.

[0064] The control module 230 includes a timing generation module and a caching module. The interface module 210 includes a physical interface module and a signal separation module. The auxiliary data packet module includes an SDP decoding module and an SDP caching module.

[0065] The video signal decoding circuit of this embodiment can determine the rising edges of the horizontal synchronization signal HS and the vertical synchronization signal VS according to the end flag BE of the first blanking area of each frame. The data valid signal DEN is generated adjacent to the vertical synchronization signal VS to achieve extremely low latency of the picture; the frequency of the data stream clock signal is adjusted by comparing the cycle of the horizontal synchronization signal HS with the cycle of the end flag BE of the first blanking area of each frame to achieve dynamic equality between the actually output data stream clock signal and the original data stream clock signal of the source device.

[0066] It should be noted that whether it is a common DP signal or AMD free-sync, adaptive sync, G-sync, etc. with variable frame dynamic refresh rate, they all have the same encapsulation characteristics. Since the present invention aims only at the end flag BE of the first blanking area within the frame for generating the timing format signal group for controlling the display of the picture, a general solution can be achieved for generating the timing format signal group of all DP format signals.

[0067] Next, the video signal decoding method provided by the present invention will be described. The video signal decoding method described below can be mutually corresponded and referred to with the video signal decoding circuit described above.

[0068] Please refer to Figures 6 - 7 , Figure 6 which is a schematic flowchart of an embodiment of the decoding method for video signals of the present invention, Figure 7 and which is a schematic timing diagram of an embodiment of the decoding method for video signals of the present invention; in this embodiment, the decoding method for video signals may include steps S110 to S140, and the specific steps are as follows:

[0069] S110: Obtain a video signal and a link clock signal.

[0070] Obtain the video signal and the link clock signal through an interface module. Optionally, when connected through a DP interface, a DP video signal will be obtained.

[0071] S120: Determine a data stream clock signal based on the link clock signal.

[0072] Obtain the link clock signal through a phase-locked loop module, and generate a data stream clock signal according to the link clock signal.

[0073] S130: Determine the end flag of the first blanking area of each frame in the video signal, and determine the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal according to the end flag of the first blanking area of each frame.

[0074] For the convenience of subsequent processing, in this embodiment, it is selected that the relative position of the rising edge of the vertical synchronization signal VS with respect to the first line of the effective display area is fixed. However, since the vertical blanking block is variable, it is only possible to locate the rising edge of the vertical synchronization signal VS after seeing the effective display area on the time axis. Therefore, in this embodiment, it is designed to track the end flag BE of the first blanking area of each frame, use the end flag BE of the first blanking area as the reference for pulling up the rising edge of the vertical synchronization signal VS, and at the same time pull up the rising edge of the horizontal synchronization signal HS to ensure that the rising edge of the horizontal synchronization signal HS is aligned with the rising edge of the vertical synchronization signal VS, and its implementation method is as follows Figure 7 as shown.

[0075] From Figure 7 it can be seen that when the end flag BE of the first blanking area of the 0th frame arrives, after the reaction time (BE2VSDelay) of the hardware circuit of the second preset time, the rising edge of the vertical synchronization signal VS is pulled up and at the same time the rising edge of the horizontal synchronization signal HS is also pulled up synchronously. It should be noted that the second preset time is the reaction time of the hardware circuit and objectively exists, and its value can be set according to the actual situation.

[0076] S140: Determine a timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal, and the main data stream attribute parameters.

[0077] Among them, the timing format signal group for controlling the display of the screen includes a horizontal synchronization signal HS, a vertical synchronization signal VS, a data valid signal DEN, a pixel signal, and a data stream clock signal; the horizontal synchronization signal HS and the vertical synchronization signal VS are aligned with the end flag BE of the first blanking area in each frame of the video signal.

[0078] Optionally, after determining the rising edge of the horizontal synchronization signal HS and the rising edge of the vertical synchronization signal VS, the horizontal synchronization signal HS is repeatedly initiated with a first preset period and a first preset effective length until the end flag BE of the last blanking area in this frame of the video signal is determined; when it is determined that the end flag BE of the first blanking area in each frame of the video signal arrives, after a first preset time BE2VSdelay + H-Start, the rising edge of the data valid signal DEN is determined, and the data valid signal DEN is repeatedly initiated with a second preset period and a second preset effective length until the end flag BE of the last blanking area in this frame of the video signal is determined.

[0079] Among them, the first preset period, the first preset effective length, the second preset period, and the second preset effective length are determined according to the data stream clock signal and the MSA parameters.

[0080] It should be noted that the number of rows in the high-level area of the data valid signal in the timing format signal group for controlling the display of the screen is less than the number of rows in the high-level area of the horizontal synchronization signal HS.

[0081] Continue to refer to Figure 7 , when the rising edges of the vertical synchronization signal VS and the horizontal synchronization signal HS are pulled up synchronously, until before the end flag BE of the first blanking area of the next frame, the first frame, arrives, the horizontal synchronization signal HS and the data valid signal DEN are both initiated with a fixed length (determined based on the data stream clock signal and the MSA parameters). When the end flag BE of the first blanking area of the next frame, the first frame, appears, the rising edges of the vertical synchronization signal VS and the horizontal synchronization signal HS are synchronized to align with the position of the end flag BE of the first blanking area, and so on.

[0082] Furthermore, when it is determined that the end flag BE of the first blanking area in each frame of the video signal arrives, after a first preset time, the rising edge of the data valid signal DEN is determined, and the data valid signal DEN is repeatedly initiated with a second preset period and a second preset effective length until the end flag BE of the last blanking area in this frame of the video signal is determined, including:

[0083] When it is determined that the end flag BE of the first blanking area in each frame of the video signal arrives, the picture data in the video signal is stored in the cache module FIFO. Among them, the time-consuming for the cache module FIFO to cache the picture data is the first preset time BE2VSdelay + H-Start; in response to the rising edge of the data valid signal DEN, the picture data is read from the cache module FIFO.

[0084] In some embodiments, the cache depth of the cache module FIFO is greater than the picture data depth; wherein, the picture data depth is determined according to the picture data, the first preset time, and the data stream clock.

[0085] Please refer to Figure 8 , Figure 8 is Figure 7 a schematic diagram of the timing details near the vertical synchronization signal VS in. Zoom in on the area near the rising edge of the vertical synchronization signal VS. After the end flag BE of the first blanking area of the 0th frame arrives, it is followed by the first line of data of the picture. The picture data must not be lost. At this time, the picture data directly enters the cache module FIFO. After a time of BE2VSdelay + H-Start, when the data valid signal DEN is initiated, data starts to be read from the cache module FIFO and sent out. At this time, the data volume of the cache module FIFO is the filled column. The time required for the data depth it needs to cache is BS2VSdelay + H-start. This time is very short, only dozens to more than a hundred pixel levels. This time is also the delay amount of the data in this module. Calculated with a 600M data stream clock signal for BS2VS delay 1pixel and H-Start 100pixel, the delay is 0.168us. This delay time is already very small and can fully meet the requirement of low data latency. The size of the cache module FIFO should be at least larger than the cache data size, for example, set to 1.2 - 2.5 times the cache data size.

[0086] Preferably, the size of the cache module FIFO can be designed to be 2 times the cache data size, that is, in this embodiment, it can be selected to be greater than 200 pixels in depth.

[0087] In addition, the first time period H-Total and the second time period H-Width need to be set as fixed constants. Due to the characteristics of the AMD free-sync signal, since the MSA parameter cannot be used as a reference for reconstruction, therefore, based on the data stream clock signal, the rising edge of the horizontal synchronization signal HS, the rising edge of the vertical synchronization signal VS, and the main data stream attribute parameters, a timing format signal group for controlling the display of the picture is determined, and it further includes:

[0088] Determine the first time period H-Total between two adjacent blanking area start flags BS within the same frame based on the first measurement period x and the time coefficient Mvid / Nvid; its expression is:

[0089] H-total = x * Mvid / Nvid;

[0090] Among them, the first measurement period x is the period for measuring the time length between two adjacent blanking area start flags BS within the same frame based on the link clock signal.

[0091] Determine the second time period H-Width between the blanking area end flag BE within this first time period and the blanking area start flag BS within the next first time period based on the second measurement period y and the time coefficient Mvid / Nvid; its expression is:

[0092] H-width = y * Mvid / Nvid;

[0093] Among them, the second measurement period y is the period for measuring the time length between the blanking area end flag BE within this first time period and the blanking area start flag BS within the next first time period based on the link clock signal.

[0094] The first time period H-Total is equal to the sum of the second time period H-Width and the third time period H-Blank, that is:

[0095] H-Total = H-Width + H-Blank.

[0096] Among them, the third time period H-Blank is the time length between the blanking area start flag BS and the blanking area end flag BE within the same first time period; the second time period H-Width is equal to the second preset valid length of the data valid signal DEN.

[0097] In addition, it is also necessary to consider the calculation error and the timing characteristics. The first time period H-Total and the second time period H-Width are multiples of 4 (excluding 1366x768). Based on the difference between H-width in the MSA parameters and the measurement calculation result, the actual set first time period H-Total and second time period H-width parameters are comprehensively obtained.

[0098] In some embodiments, the steps of determining the data stream clock signal based on the link clock signal specifically include:

[0099] Compare the positions of the blanking area end flag BE and the horizontal sync signal HS on the time axis based on the tracking signal, and adjust the data stream clock signal according to the comparison result.

[0100] Further, the step of comparing the positions of the blanking area end flag BE and the horizontal synchronization signal HS on the time axis based on the tracking signal and adjusting the data stream clock signal according to the comparison result specifically includes:

[0101] If the occurrence time of the horizontal synchronization signal HS is later than the occurrence time of the blanking area end flag BE, the frequency of the data stream clock signal is increased; if the occurrence time of the horizontal synchronization signal HS is earlier than the occurrence time of the blanking area end flag BE, the frequency of the data stream clock signal is decreased. Please refer to Figure 9 , Figure 9 which is the timing schematic diagram of an embodiment of the data stream clock signal of the present invention.

[0102] As Figure 9 shown, if it can be ensured that the time period between the first blanking area end flag BE of each original frame and the first blanking area end flag BE of each frame is equal to the period between the horizontal synchronization signals HS in the timing format signal group for reconstructing the reference data stream clock signal for controlling the display of the picture, that is, the purpose is achieved.

[0103] In fact, due to the sensitivity limitation of the voltage-controlled oscillator in the phase-locked loop module, it is impossible to truly achieve complete equality in the circuit, but a dynamic equality can be achieved, that is, the average period within a period of time is equal. Then, with the help of the buffer module to buffer the dynamic drift in frequency, the data cached in the buffer module fluctuates up and down. As long as no overflow or underflow occurs, a dynamic balance is achieved.

[0104] Combined with Figure 4 and Figure 9 , in this embodiment, a blanking area end flag BE signal is generated at the position where the blanking area ends on the time axis. Since the rising edge of the horizontal synchronization signal HS is aligned with the blanking area end flag BE, that is, only the area where the blanking area end flag BE is located needs to be tracked. Therefore, a tracking signal needs to be framed in the area where the blanking area end flag BE is located. Within the effective area of the tracking signal, the positions of the blanking area end flag BE and the HS signal on the time axis are compared.

[0105] For example, if the horizontal synchronization signal pulse HE’ appears after the blanking area end flag pulse BE’, it means that the data stream clock signal is slow and needs to be accelerated. The frequency discriminator and phase discriminator of the frequency tracking module measure the deviation time between the two and count it with a δ value (delta value), and set up control signals of Up = 1 and down = 0 and send them to the modulator. The modulator calculates the parameter that affects the change in the frequency of the voltage-controlled oscillator in the phase-locked loop module based on this control signal and the δ value, and sends the new parameter to the phase-locked loop module to enable the phase-locked loop module to generate a new data stream clock signal frequency.

[0106] Among them, the horizontal synchronization signal pulse HS’ is obtained based on the horizontal synchronization signal HS and the DIV parameter; the blanking area end flag pulse BE’ is obtained based on the blanking area end flag number BE and the DIV parameter. Specifically, BE’ = BE / DIV; HS’ = HS / DIV.

[0107] When the next horizontal synchronization signal HS reconstructed by the newly generated frequency is compared with the next blanking area end flag BE, and the above-mentioned method is continuously used to obtain new parameters for whether the phase-locked loop module needs to speed up or slow down. By repeating this cycle, it is possible to maintain an average dynamic balance effect where the period of the actually output horizontal synchronization signal HS is the same as the period of the blanking area end flag BE, so that the reconstructed data stream clock signal is basically equal to the original frequency of the source device.

[0108] In addition, in terms of circuit implementation, the vertical synchronization signal VS and the horizontal synchronization signal HS will only start at the beginning of each frame (aligned with the first blanking area end flag BE within the tracked frame). Subsequently, H-Start, H-Total, and H-width are counted using fixed parameters with the data stream clock signal. This ensures that H-Start is fixed, that is, the data enable signal DEN is a fixed length relative to the rising edge of the horizontal synchronization signal HS, and at the same time, H-total is also a fixed length, so as to achieve no jitter phenomenon when H-Start and H-Total are counted with the data stream clock signal.

[0109] From Figure 8 it can be seen that the synchronization pulse of the vertical synchronization signal VS encloses the data enable signal DEN of the first row of picture data. The pulse width of the vertical synchronization signal VS can be set to one piece of picture data or multiple pieces of picture data, which requires the subsequent display system to support this timing format.

[0110] From Figure 7 it can be seen that the decoding circuit of the video signal can track the first blanking area end flag BE in each frame of the source device as the position where the vertical synchronization signal VS is generated. When the source device adjusts the size of the vertical blanking block, its essence is to adjust the position where the first blanking area end flag BE appears in the next frame. Therefore, the generation mechanism of this vertical synchronization signal VS naturally follows the change characteristics of the vertical blanking block of the source device, which also enables the vertical synchronization signal VS in the timing format signal group for controlling the display of the control screen generated by the control module to align with the signal changes of the source device.

[0111] The present invention also provides an electronic device. In this embodiment, the electronic device may include the decoding circuit of the video signal described in any one of the above. Its steps and principles have been introduced in detail in the above method and will not be elaborated here.

[0112] On the other hand, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the decoding method of the video signal provided by the above-mentioned various methods. The steps and principles have been introduced in detail in the above methods and will not be elaborated here.

[0113] The circuit embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0114] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A decoding circuit for a video signal, characterized in that, It includes an interface module, a phase-locked loop module and a control module; wherein, the interface module is respectively connected to the phase-locked loop module and the control module; the phase-locked loop module is connected to the control module; The interface module is used to obtain a video signal and a link clock signal; The phase-locked loop module is used to obtain the link clock signal and generate a data stream clock signal according to the link clock signal; The control module is used to obtain the video signal and the data stream clock signal, determine the end flag of the first blanking area of each frame in the video signal, determine the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal according to the end flag of the first blanking area of each frame, and determine a timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal and the main data stream attribute parameters; Wherein, the timing format signal group for controlling the display of the picture includes a horizontal synchronization signal, a vertical synchronization signal, a data valid signal, a pixel signal and a data stream clock signal; the horizontal synchronization signal and the vertical synchronization signal are aligned with the end flag of the first blanking area that appears in each frame of the video signal; Determining the timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal and the main data stream attribute parameters includes: After determining the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal, the horizontal synchronization signal is repeatedly initiated with a first preset period and a first preset effective length until the end flag of the first blanking area of the next frame in the video signal is determined; When it is determined that the end flag of the first blanking area of each frame in the video signal arrives, the rising edge of the data valid signal is determined after a first preset time, and the data valid signal is repeatedly initiated with a second preset period and a second preset effective length until the end flag of the last blanking area in the current frame of the video signal is determined; Wherein, the first preset period, the first preset effective length, the second preset period and the second preset effective length are determined according to the data stream clock signal and the main data stream attribute parameters.

2. The decoding circuit for a video signal according to claim 1, wherein, The control module includes a timing generation module and a cache module; the timing generation module is connected to the cache module; The timing generation module is used to obtain the video signal and the data stream clock signal, determine the end flag of the first blanking area of each frame in the video signal, determine the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal according to the end flag of the first blanking area of each frame, determine the horizontal synchronization signal and the data valid signal according to the data stream clock signal and the main data stream attribute parameters; and finally output the horizontal synchronization signal, the vertical synchronization signal, the data valid signal and the data stream clock signal; The cache module is used to write the picture data in the video signal when the end flag of the first blanking area of each frame in the video signal is responded to; When responding to the data valid signal, read out the picture data as the pixel signal.

3. The decoding circuit for a video signal according to claim 1, wherein, It further includes a measurement module, where the measurement module is respectively connected to the interface module and the control module; The measurement module is used to measure the period information of the video signal based on the link clock signal, where the period information is used to determine the horizontal synchronization signal and the data valid signal.

4. The decoding circuit for a video signal according to claim 1, characterized in that, It further includes a frequency tracking module, where the frequency tracking module is respectively connected to the interface module, the phase-locked loop module and the control module; The frequency tracking module includes a frequency discriminator and a modulator; The modulator is respectively connected to the frequency discriminator and the phase-locked loop module; the frequency discriminator is used to compare the positions of the end flag of the blanking area and the horizontal synchronization signal on the time axis, and the modulator is used to adjust the data stream clock signal according to the comparison result of the frequency discriminator, so that the data stream clock signal is dynamically equal to the initial data stream clock signal of the source device that sends the video signal.

5. The decoding circuit for a video signal according to claim 1, characterized in that, It further includes an auxiliary data packet module, and the auxiliary data packet module is connected to the interface module; The auxiliary data packet module is used to receive and save the auxiliary data packet data that meets the preset conditions, and monitor the change situation of the received auxiliary data packet data in real time.

6. A decoding method for a video signal, characterized in that, It includes: Obtain a video signal and a link clock signal; Determine a data stream clock signal based on the link clock signal; Determine the end flag of the first blanking area in each frame of the video signal, and determine the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal according to the end flag of the first blanking area in each frame; Determine a timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal and the main data stream attribute parameters; Among them, the timing format signal group for controlling the display of the picture includes a horizontal synchronization signal, a vertical synchronization signal, a data valid signal, a pixel signal and a data stream clock signal; the horizontal synchronization signal and the vertical synchronization signal are aligned with the end flag of the first blanking area that appears in each frame of the video signal; The determining the timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal and the main data stream attribute parameters includes: After determining the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal, initiate the horizontal synchronization signal repeatedly with a first preset period and a first preset effective length until the end flag of the first blanking area in the next frame of the video signal is determined; When it is determined that the end flag of the first blanking area in each frame of the video signal arrives, determine the rising edge of the data valid signal after a first preset time, and initiate the data valid signal repeatedly with a second preset period and a second preset effective length until the end flag of the last blanking area in the current frame of the video signal is determined; Wherein, the first preset period, the first preset effective length, the second preset period, and the second preset effective length are determined according to the data stream clock signal and the main data stream attribute parameters.

7. The decoding method of a video signal according to claim 6, characterized in that, When it is determined that the end flag of the first blanking area in each frame of the video signal arrives, after a first preset time, the rising edge of the data valid signal is determined, and the data valid signal is repeated and initiated with a second preset period and a second preset effective length until it is determined that the end flag of the last blanking area in this frame of the video signal, including: When it is determined that the end flag of the first blanking area in each frame of the video signal arrives, the picture data in the video signal is stored in the buffer module, wherein the time taken for the buffer module to cache the picture data is the first preset time; In response to the rising edge of the data valid signal, the picture data is read from the buffer module.

8. The decoding method of a video signal according to claim 7, characterized in that, The buffer depth of the buffer module is greater than the picture data depth; wherein, the picture data depth is determined according to the picture data, the first preset time, and the data stream clock.

9. The decoding method of a video signal according to claim 6, characterized in that, The determining the timing format signal group for controlling the display of the picture based on the data stream clock signal, the rising edge of the horizontal synchronization signal, the rising edge of the vertical synchronization signal, and the main data stream attribute parameters further includes: Determining a first time period between the start flags of two adjacent blanking areas within the same frame based on a first measurement period and a time coefficient; wherein, the first measurement period is a period for measuring the time length between the start flags of two adjacent blanking areas within the same frame based on the link clock signal; Determining a second time period between the end flag of the blanking area within the first time period and the start flag of the blanking area within the next first time period based on a second measurement period and a time coefficient; wherein, the second measurement period is a period for measuring the time length between the end flag of the blanking area within the first time period and the start flag of the blanking area within the next first time period based on the link clock signal; Wherein, the first time period is equal to the sum of the second time period and the third time period, and the third time period is the time length between the start flag and the end flag of the blanking area within the same first time period; the second time period is equal to the second preset effective length of the data valid signal.

10. The decoding method of a video signal according to claim 6, characterized in that, The determining the data stream clock signal based on the link clock signal includes: Comparing the positions of the end flag of the blanking area and the horizontal synchronization signal on the time axis based on the tracking signal, and adjusting the data stream clock signal according to the comparison result.

11. The decoding method of a video signal according to claim 10, wherein, The comparing the positions of the end flag of the blanking area and the horizontal synchronization signal on the time axis based on the tracking signal, and adjusting the data stream clock signal according to the comparison result includes: If the occurrence time of the horizontal synchronization signal is later than the occurrence time of the end flag of the blanking area, the frequency of the data stream clock signal is increased; If the occurrence time of the horizontal synchronization signal is earlier than the occurrence time of the end flag of the blanking area, the frequency of the data stream clock signal is decreased.

12. An electronic device, characterized in that, Including a decoding circuit for the video signal according to any one of claims 1 to 5.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the video signal decoding method according to any one of claims 6 to 11.

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