Array substrate, display device and driving method

Abstract

The embodiments of the present invention disclose an array substrate, a display device, and a driving method. In one embodiment, the array substrate includes a driving circuit board, N rows and 2M columns of sub-pixels arranged in an array, 2N gate lines, and M data lines, wherein the mth data line is connected to the 2m-1st and 2m-th columns of sub-pixels, respectively, the 8n+1th gate line is connected to the sub-pixels in the odd columns in the 4n+1th row, the 8n+2th gate line is connected to the sub-pixels in the even columns in the 4n+2th row, the 8n+3th gate line is connected to the sub-pixels in the even columns in the 4n+1th row, and the 8n+4th gate line is connected to the sub-pixels in the odd columns in the 4n+2th row. The 8n+5th gate line connects the sub-pixels in the odd columns in the 4n+2th row, the 8n+5th gate line connects the sub-pixels in the even columns in the 4n+3th row, the 8n+6th gate line connects the sub-pixels in the odd columns in the 4n+4th row, the 8n+7th gate line connects the sub-pixels in the odd columns in the 4n+3th row, and the 8n+8th gate line connects the sub-pixels in the even columns in the 4n+4th row, m is a positive integer, and n is a natural number; the driving circuit board is configured to drive the array of the sub-pixels in a dot inversion manner.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly to an array substrate, a display device, and a driving method. Background Art

[0002] TFT LCD panels require positive and negative voltage driving due to the characteristics of liquid crystal. Common liquid crystal driving inversion methods include Frame Inversion, Row Inversion, Column Inversion, and Dot Inversion. Figure 1 As shown in the figure, commonly used inversion methods are column inversion and dot inversion. Column inversion has the advantage of low power consumption, but poor performance in terms of low flicker and low crosstalk. Dot inversion, on the other hand, has good performance in terms of low flicker and low crosstalk, but high power consumption. Summary of the Invention

[0003] An object of the present invention is to provide an array substrate, a display device and a driving method to solve at least one of the problems existing in the prior art.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] The first aspect of the present invention provides an array substrate, comprising a driving circuit board, N rows and 2M columns of sub-pixels arranged in an array, 2N gate lines, and M data lines, wherein the mth data line is connected to the 2m-1st and 2mth columns of sub-pixels, the 8n+1th gate line is connected to the sub-pixels in the odd columns in the 4n+1th row, the 8n+2th gate line is connected to the sub-pixels in the even columns in the 4n+2th row, and the 8n+3th gate line is connected to the sub-pixels in the even columns in the 4n+1th row. The 8n+4th gate line connects the sub-pixels in the odd-numbered columns in the 4n+2th row, the 8n+5th gate line connects the sub-pixels in the even-numbered columns in the 4n+3th row, the 8n+6th gate line connects the sub-pixels in the odd-numbered columns in the 4n+4th row, the 8n+7th gate line connects the sub-pixels in the odd-numbered columns in the 4n+3th row, and the 8n+8th gate line connects the sub-pixels in the even-numbered columns in the 4n+4th row, where m is a positive integer and n is a natural number;

[0006] The driving circuit board is configured to drive the array of sub-pixels in a dot inversion manner.

[0007] In a specific embodiment, the driving circuit board is configured to scan the 2N gate lines row by row in the current frame period, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the first polarity through the mth data line, when scanning the 8n+2th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the first polarity through the mth data line, when scanning the 8n+3th gate line, the sub-pixel in the 2m-2nd column of the 4n+1th row is charged with a data signal of the second polarity through the mth data line, and when scanning the 8n+4th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line. The sub-pixel in the 2m-1th column is charged with a data signal of the second polarity, and when scanning the 8n+5th gate line, the sub-pixel in the 2m-1th column in the 4n+3th row is charged with a data signal of the second polarity through the m-th data line, and when scanning the 8n+6th gate line, the sub-pixel in the 2m-1th column in the 4n+4th row is charged with a data signal of the second polarity through the m-th data line, and when scanning the 8n+7th gate line, the sub-pixel in the 2m-1th column in the 4n+3th row is charged with a data signal of the first polarity through the m-th data line, and when scanning the 8n+8th gate line, the sub-pixel in the 2m-1th column in the 4n+4th row is charged with a data signal of the first polarity through the m-th data line.

[0008] In a specific embodiment, the driving circuit board is configured to scan the 2N gate lines row by row in the next frame period, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the second polarity through the mth data line, when scanning the 8n+2th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line, when scanning the 8n+3th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the first polarity through the mth data line, and when scanning the 8n+4th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line. The sub-pixel in the 2m-1th column is charged with a data signal of the first polarity, and when scanning the 8n+5th gate line, the sub-pixel in the 2m-1th column in the 4n+3th row is charged with a data signal of the first polarity through the mth data line, and when scanning the 8n+6th gate line, the sub-pixel in the 2m-1th column in the 4n+4th row is charged with a data signal of the first polarity through the mth data line, and when scanning the 8n+7th gate line, the sub-pixel in the 2m-1th column in the 4n+3th row is charged with a data signal of the second polarity through the mth data line, and when scanning the 8n+8th gate line, the sub-pixel in the 2m-1th column in the 4n+4th row is charged with a data signal of the second polarity through the mth data line.

[0009] In a specific embodiment, two gate lines are provided between two adjacent rows of sub-pixels and are respectively connected to some columns of sub-pixels in the two adjacent rows of sub-pixels.

[0010] In a specific embodiment, the data line is disposed between two adjacent columns of sub-pixels connected thereto.

[0011] In a specific embodiment, the sub-pixel includes a transistor and a pixel electrode, wherein the control electrode of the transistor is connected to the corresponding gate line, the first electrode is connected to the corresponding data line, and the second electrode is connected to the pixel electrode.

[0012] A second aspect of the present invention provides a display device comprising the array substrate described above.

[0013] A third aspect of the present invention provides a driving method for an array substrate, the array substrate comprising a driving circuit board, N rows and 2M columns of sub-pixels arranged in an array, 2N gate lines, and M data lines, wherein the mth data line is connected to the 2m-1st and 2mth columns of sub-pixels, the 8n+1th gate line is connected to the sub-pixels in the odd columns in the 4n+1th row, the 8n+2th gate line is connected to the sub-pixels in the even columns in the 4n+2th row, the 8n+3th gate line is connected to the sub-pixels in the 4nth The 8n+4th gate line connects the sub-pixels in the even-numbered columns of the 4n+2th row, the 8n+5th gate line connects the sub-pixels in the even-numbered columns of the 4n+3th row, the 8n+6th gate line connects the sub-pixels in the odd-numbered columns of the 4n+4th row, the 8n+7th gate line connects the sub-pixels in the odd-numbered columns of the 4n+3th row, and the 8n+8th gate line connects the sub-pixels in the even-numbered columns of the 4n+4th row, where m is a positive integer and n is a natural number;

[0014] The driving method includes: driving a circuit board to drive the array of sub-pixels in a dot inversion manner.

[0015] In a specific embodiment, the driving circuit board drives the array of sub-pixels in a dot inversion manner, comprising: scanning the 2N gate lines row by row in the current frame period, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 4n+1th row and the 2m-1th column is charged with a data signal of a first polarity through the mth data line; when scanning the 8n+2th gate line, the sub-pixel in the 4n+2th row and the 2mth column is charged with a data signal of a first polarity through the mth data line; when scanning the 8n+3th gate line, the sub-pixel in the 4n+1th row and the 2mth column is charged with a data signal of a second polarity through the mth data line; and when scanning the 8n+4th gate line, the sub-pixel in the 8n+5th row and the 2mth column is charged with a data signal of a second polarity through the mth data line. The sub-pixel in the 2m-1 column of the 4n+2th row is charged with a data signal of the second polarity, the sub-pixel in the 2m-2nd column of the 4n+3th row is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+5th gate line, the sub-pixel in the 2m-1st column of the 4n+4th row is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+6th gate line, the sub-pixel in the 2m-1st column of the 4n+3th row is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+7th gate line, and the sub-pixel in the 2m-2nd column of the 4n+4th row is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+8th gate line.

[0016] In a specific embodiment, the driving circuit board drives the array of sub-pixels in a dot inversion manner further comprising: in the next frame period, scanning the 2N gate lines row by row, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 4n+1th row and the 2m-1th column is charged with a data signal of the second polarity through the mth data line, when scanning the 8n+2th gate line, the sub-pixel in the 4n+2th row and the 2m-1th column is charged with a data signal of the second polarity through the mth data line, when scanning the 8n+3th gate line, the sub-pixel in the 4n+1th row and the 2m-1th column is charged with a data signal of the first polarity through the mth data line, and when scanning the 8n+4th gate line, the sub-pixel in the 8n+5th row and the 2m-5th column is charged with a data signal of the first polarity through the mth data line. The sub-pixel in the 4n+2 row and 2m-1 column is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+5-th gate line, the sub-pixel in the 4n+3 row and 2m-1 column is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+6-th gate line, the sub-pixel in the 4n+4 row and 2m-1 column is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+7-th gate line, and the sub-pixel in the 4n+3 row and 2m-1 column is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+8-th gate line.

[0017] The beneficial effects of the present invention are as follows:

[0018] The technical solution described in this invention reduces display power consumption by reducing the number of voltage polarity switching times on the data lines. It also employs a dot inversion method with excellent low flicker and low crosstalk performance while reducing display power consumption. Furthermore, the driver circuit eliminates the need for an additional charge pump circuit, saving electronic components and thus reducing product costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0020] Figure 1 Schematic diagrams of four existing liquid crystal drive inversion modes are shown.

[0021] Figure 2 A schematic diagram of a conventional driving architecture of a dual gate + (1+2 Dot Inversion) inversion method is shown.

[0022] Figure 3 The figure shows a driving timing diagram of the existing Dual gate+(1+2 Dot Inversion) inversion mode.

[0023] Figure 4 A schematic diagram of a driving architecture of an array substrate according to an embodiment of the present invention is shown.

[0024] Figure 5 A driving timing diagram of an array substrate according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0025] In order to more clearly illustrate the present invention, the present invention will be further described below in conjunction with the embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the following specific description is illustrative rather than restrictive and should not be used to limit the scope of protection of the present invention.

[0026] In the process of implementing the present invention, the inventors discovered that the prior art has at least the following problems:

[0027] TFT LCD panels require positive and negative voltage driving due to the characteristics of liquid crystal. Common liquid crystal driving inversion methods include Frame Inversion, Row Inversion, Column Inversion, and Dot Inversion. Figure 1 As shown in Table 1, the commonly used inversion methods are column inversion and dot inversion.

[0028] Table 1

[0029]

[0030] The column inversion method has the advantage of low power consumption, but its quality performance such as low flicker and low crosstalk is poor. Due to the feed-through effect of TFT, the optimal VCOM (LCD common voltage) is different at different positions of the displayed image. The dot inversion method disperses the voltage asymmetry to various positions of the TFT LCD liquid crystal panel, offsetting the voltage asymmetry to the greatest extent and making the optimal VCOM as uniform as possible. Therefore, the dot inversion method has good quality performance such as low flicker and low crosstalk, but it has the highest power consumption.

[0031] Taking the automotive TFT LCD panel as an example, currently, most automotive TFT LCD panels use the Dual gate + (1 + 2 Dot Inversion) inversion method. Figure 2 The driving structure of the array substrate using the Dual gate + (1 + 2 Dot Inversion) inversion method in the prior art is shown. It can be understood that Figure 2 Only part of the driving architecture is shown, including 6 rows and 8 columns of sub-pixels arranged in an array, 12 gate lines Gate1-Gate12 and 4 data lines Source1-Source4. The first gate line Gate1 is connected to the sub-pixels in the odd columns of the first row, the second gate line Gate2 is connected to the sub-pixels in the even columns of the first row, the third gate line Gate3 is connected to the sub-pixels in the odd columns of the second row, the fourth gate line Gate4 is connected to the sub-pixels in the even columns of the second row, the fifth gate line Gate5 is connected to the sub-pixels in the odd columns of the third row, the sixth gate line Gate6 is connected to the sub-pixels in the even columns of the third row, the seventh gate line Gate7 is connected to the sub-pixels in the odd columns of the fourth row, the eighth gate line Gate8 is connected to the sub-pixels in the even columns of the fourth row, and the ninth gate line Gate9 is connected to the sub-pixels in the odd columns of the third row. The 10th gate line Gate10 is connected to the sub-pixels in the odd columns of the 5th row, the 11th gate line Gate11 is connected to the sub-pixels in the odd columns of the 6th row, the 12th gate line Gate12 is connected to the sub-pixels in the even columns of the 6th row, the 1st data line Source1 is connected to the sub-pixels in the 1st and 2nd columns, the 2nd data line Source2 is connected to the sub-pixels in the 3rd and 4th columns, the 3rd data line Source3 is connected to the sub-pixels in the 5th and 6th columns, and the 4th data line Source4 is connected to the sub-pixels in the 7th and 8th columns. The sub-pixels include a thin film transistor (TFT) and a pixel electrode, wherein the control electrode (gate) of the thin film transistor is connected to the corresponding gate line, the source electrode is connected to the corresponding data line, and the drain electrode is connected to the pixel electrode.

[0032] One sub-pixel is connected to one data line and one gate line. Two gate lines are set between two adjacent rows of sub-pixels. One gate line is set on the side of the first and last rows of sub-pixels without adjacent sub-pixels. In combination with 1+2 Dot Inversion, the voltage polarity is switched once after each pair of two sub-pixels on the data line is charged, which is +5V to -5V or -5V to +5V (except Figure 2 In the embodiment, the fixed amplitude of 5 is used as an example just for the convenience of explanation, because the embodiment mainly focuses on the number of switching times. Figure 3 As shown, the specific driving method of the existing array substrate using the Dual gate + (1 + 2 Dot Inversion) inversion method is:

[0033] In the current frame period, the 12 gate lines are scanned row by row, wherein when scanning the first gate line Gate1, the sub-pixels in the first row, the first column, and the fifth column are charged with a +5V data signal through the first and third data lines Source1 and Source3, respectively, and the sub-pixels in the first row, the third column, and the seventh column are charged with a -5V data signal through the second and fourth data lines Source2 and Source4, respectively.

[0034] When scanning the second gate line Gate2, the sub-pixels in the first row, second column, and sixth column are charged with -5V data signals through the first and third data lines Source1 and Source3, respectively, and the sub-pixels in the first row, fourth column, and eighth column are charged with +5V data signals through the second and fourth data lines Source2 and Source4, respectively.

[0035] When scanning the third gate line Gate3, the sub-pixels in the second row, first column, and fifth column are charged with -5V data signals through the first and third data lines Source1 and Source3, respectively, and the sub-pixels in the second row, third column, and seventh column are charged with +5V data signals through the second and fourth data lines Source2 and Source4, respectively.

[0036] When scanning the 4th gate line Gate4, the 2nd row, 2nd column, and 6th column sub-pixels are charged with +5V data signals through the 1st and 3rd data lines Source1 and Source3 respectively, and the 2nd row, 4th, and 8th column sub-pixels are charged with -5V data signals through the 2nd and 4th data lines Source2 and Source4 respectively.

[0037] When scanning the fifth gate line Gate5, the sub-pixels in the third row, first column and fifth column are charged with +5V data signals through the first and third data lines Source1 and Source3 respectively, and the sub-pixels in the third row, third column and seventh column are charged with -5V data signals through the second and fourth data lines Source2 and Source4 respectively.

[0038] When scanning the 6th gate line Gate6, the sub-pixels in the 3rd row, 2nd column and 6th column are charged with -5V data signals through the 1st and 3rd data lines Source1 and Source3 respectively, and the sub-pixels in the 3rd row, 4th column and 8th column are charged with +5V data signals through the 2nd and 4th data lines Source2 and Source4 respectively.

[0039] When scanning the 7th gate line Gate7, the 1st and 5th sub-pixels in the 4th row are charged with -5V data signals through the 1st and 3rd data lines Source1 and Source3 respectively, and the 3rd and 7th sub-pixels in the 4th row are charged with +5V data signals through the 2nd and 4th data lines Source2 and Source4 respectively.

[0040] When scanning the 8th gate line Gate8, the 2nd and 6th sub-pixels in the 4th row are charged with +5V data signals through the 1st and 3rd data lines Source1 and Source3 respectively, and the 4th sub-pixels in the 4th row are charged with -5V data signals through the 2nd and 4th data lines Source2 and Source4 respectively.

[0041] When scanning the 9th gate line Gate9, the 1st and 5th column sub-pixels in the 5th row are charged with +5V data signals through the 1st and 3rd data lines Source1 and Source3 respectively, and the 3rd and 7th column sub-pixels in the 5th row are charged with -5V data signals through the 2nd and 4th data lines Source2 and Source4 respectively.

[0042] When scanning the 10th gate line Gate10, the sub-pixels in the 5th row, 2nd column and 6th column are charged with -5V data signals through the 1st and 3rd data lines Source1 and Source3 respectively, and the sub-pixels in the 5th row, 4th column and 8th column are charged with +5V data signals through the 2nd and 4th data lines Source2 and Source4 respectively.

[0043] When scanning the 11th gate line Gate11, the sub-pixels in the 1st and 5th columns of the 6th row are charged with -5V data signals through the 1st and 3rd data lines Source1 and Source3 respectively, and the sub-pixels in the 3rd and 7th columns of the 6th row are charged with +5V data signals through the 2nd and 4th data lines Source2 and Source4 respectively.

[0044] When scanning the 12th gate line Gate12, the sub-pixels in the 6th row, 2nd column and 6th column are charged with +5V data signals through the 1st and 3rd data lines Source1 and Source3 respectively, and the sub-pixels in the 6th row, 4th column and 8th column are charged with -5V data signals through the 2nd and 4th data lines Source2 and Source4 respectively.

[0045] In the next frame period, the 12 gate lines are scanned row by row, and the driving method is the same as that of the current frame period mentioned above, except that the +5V data signal of the current frame period is converted into a -5V data signal, and the -5V data signal of the current frame period is converted into a +5V data signal, which will not be repeated here.

[0046] The power consumption of automotive TFT LCD panels is positively correlated with the number of voltage switching times and the switching amplitude on the data line. That is, the more times the voltage on the data line switches, the greater the power consumption; the greater the amplitude of the voltage switching on the data line, the greater the power consumption. For example, the power consumption of switching from +5V to -5V (absolute voltage value 10V) is greater than that of switching from +5V to 0V (absolute voltage value 5V). Therefore, according to the specific driving method of the array substrate of the above-mentioned Dual gate+(1+2DotInversion) inversion method, it can be known that when the 1+2DotInversion inversion method is applied, the voltage polarity of the data line is switched once after each pair of two sub-pixels are charged. Taking the first data line Source1 as an example, when scanning the second gate line Gate2 and the third gate line Gate3, the first data line Source1 provides a -5V data signal. When scanning the fourth gate line Gate4 and the fifth gate line Gate5, the first data line Source1 switches to provide a +5V data signal. When scanning the sixth gate line Gate6 and the seventh gate line Gate7, the first data line Source1 switches back to providing a -5V data signal, and so on. The power consumption is very high. In addition, under the Dual gate+(1+2DotInversion) inversion method, the sub-pixels are still switched alternately in two columns / two columns, that is, the quality performance such as low flicker and low crosstalk is still not as good as that of the conventional method. Figure 1 The true point reversal method shown.

[0047] Currently, major panel manufacturers are targeting high resolution, high display quality, low power consumption, and low cost for automotive TFT LCD panels. In view of this, an embodiment of the present invention provides an array substrate that maintains the advantages of low power consumption, high display quality, and low cost while maintaining high resolution.

[0048] The array substrate comprises: a driving circuit board, N rows and 2M columns of sub-pixels arranged in an array, 2N gate lines and M data lines, wherein the mth data line is connected to the 2m-1st and 2mth columns of sub-pixels respectively, the 8n+1th gate line is connected to the sub-pixels in the odd columns in the 4n+1th row, the 8n+2th gate line is connected to the sub-pixels in the even columns in the 4n+2th row, and the 8n+3th gate line is connected to the sub-pixels in the even columns in the 4n+1th row. Pixels, the 8n+4th gate line connects the sub-pixels in the odd-numbered columns of the 4n+2th row, the 8n+5th gate line connects the sub-pixels in the even-numbered columns of the 4n+3th row, the 8n+6th gate line connects the sub-pixels in the odd-numbered columns of the 4n+4th row, the 8n+7th gate line connects the sub-pixels in the odd-numbered columns of the 4n+3th row, and the 8n+8th gate line connects the sub-pixels in the even-numbered columns of the 4n+4th row, m is a positive integer, n is a natural number, and N and M are both positive integers and may be the same or different.

[0049] In one possible implementation, two gate lines are provided between two adjacent rows of sub-pixels, each connected to a portion of the columns of sub-pixels in the two adjacent rows. The data line is provided between the two adjacent columns of sub-pixels connected thereto. Exemplarily, the sub-pixel includes a transistor and a pixel electrode, wherein a control electrode (gate) of the transistor is connected to the corresponding gate line, a first electrode (e.g., source electrode) is connected to the corresponding data line, and a second electrode (e.g., drain electrode) is connected to the pixel electrode.

[0050] The driving circuit board is configured to drive the array of sub-pixels in a dot inversion manner.

[0051] In a possible implementation, the driving circuit board is configured as follows:

[0052] In the current frame period, the 2N gate lines are scanned row by row, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the first polarity through the mth data line, when scanning the 8n+2th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the first polarity through the mth data line, when scanning the 8n+3th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the second polarity through the mth data line, and when scanning the 8n+4th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line. The sub-pixel in the 4n+3 row and the 2m-1 column is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+5-th gate line; the sub-pixel in the 4n+4 row and the 2m-1 column is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+6-th gate line; the sub-pixel in the 4n+3 row and the 2m-1 column is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+7-th gate line; and the sub-pixel in the 4n+4 row and the 2m-1 column is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+8-th gate line.

[0053] Furthermore, the driving circuit board is configured as follows:

[0054] In the next frame period, the 2N gate lines are scanned row by row, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the second polarity through the mth data line, when scanning the 8n+2th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line, when scanning the 8n+3th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the first polarity through the mth data line, and when scanning the 8n+4th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line. The sub-pixel in the 4n+3 row and the 2m-1 column is charged with a data signal of one polarity through the m-th data line when scanning the 8n+5-th gate line, the sub-pixel in the 4n+4 row and the 2m-1 column is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+6-th gate line, the sub-pixel in the 4n+3 row and the 2m-1 column is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+7-th gate line, and the sub-pixel in the 4n+4 row and the 2m-1 column is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+8-th gate line.

[0055] It is understandable that the connection method of "the 8n+1th gate line is connected to the sub-pixels of the even columns in the 4n+1th row, the 8n+2th gate line is connected to the sub-pixels of the odd columns in the 4n+2th row, the 8n+3th gate line is connected to the sub-pixels of the odd columns in the 4n+1th row, the 8n+4th gate line is connected to the sub-pixels of the even columns in the 4n+2th row, the 8n+5th gate line is connected to the sub-pixels of the odd columns in the 4n+3th row, the 8n+6th gate line is connected to the sub-pixels of the even columns in the 4n+4th row, the 8n+7th gate line is connected to the sub-pixels of the even columns in the 4n+3th row, and the 8n+8th gate line is connected to the sub-pixels of the odd columns in the 4n+4th row" can also be adopted, which can also achieve the same low power consumption, low flicker and low crosstalk effects.

[0056] In a specific example, Figure 4 As shown, Figure 4 The driving structure of an array substrate provided by this embodiment is shown. It can be understood that: Figure 4 Only a partial drive architecture is shown.

[0057] The array substrate includes a driving circuit board (not shown in the figure), 6 rows and 8 columns of sub-pixels arranged in an array, 12 gate lines Gate1-Gate12 and 4 data lines Source1-Source4.

[0058] Among them, the first data line Source1 is connected to the first and second columns of sub-pixels respectively, the second data line Source2 is connected to the third and fourth columns of sub-pixels respectively, the third data line Source3 is connected to the fifth and sixth columns of sub-pixels respectively, and the fourth data line Source4 is connected to the seventh and eighth columns of sub-pixels respectively.

[0059] The first gate line Gate1 connects the sub-pixels in the odd-numbered columns in the first row, the second gate line Gate2 connects the sub-pixels in the even-numbered columns in the second row, the third gate line Gate3 connects the sub-pixels in the even-numbered columns in the first row, the fourth gate line Gate4 connects the sub-pixels in the odd-numbered columns in the second row, the fifth gate line Gate5 connects the sub-pixels in the even-numbered columns in the third row, the sixth gate line Gate6 connects the sub-pixels in the odd-numbered columns in the fourth row, the seventh gate line Gate7 connects the sub-pixels in the odd-numbered columns in the third row, the eighth gate line Gate8 connects the sub-pixels in the even-numbered columns in the fourth row, the ninth gate line Gate9 connects the sub-pixels in the odd-numbered columns in the fifth row, the tenth gate line Gate10 connects the sub-pixels in the even-numbered columns in the sixth row, the eleventh gate line Gate11 connects the sub-pixels in the even-numbered columns in the fifth row, and the twelfth gate line Gate12 connects the sub-pixels in the odd-numbered columns in the sixth row.

[0060] Wherein, the sub-pixel includes a thin film transistor (TFT) and a pixel electrode, the gate of the thin film transistor is connected to the corresponding gate line, the first electrode is connected to the corresponding data line and the second electrode is connected to the pixel electrode, the first electrode and the second electrode are respectively the source and the drain; or, the drain and the source. Figure 4 Taking the sub-pixel in the second row and second column as an example, the gate of its thin film transistor needs to cross the third gate line Gate3 and connect to the second gate line Gate2. Here, only a via hole needs to be added, which is technically simple and does not increase the cost.

[0061] Among them, the first gate line Gate1 is set on the side of the first row of sub-pixels away from the second row of sub-pixels; the second gate line Gate2 and the third gate line Gate3 are set between the first and second rows of sub-pixels; the fourth gate line Gate4 and the fifth gate line Gate5 are set between the second and third rows of sub-pixels; the sixth gate line Gate6 and the seventh gate line Gate7 are set between the third and fourth rows of sub-pixels; the eighth gate line Gate8 and the ninth gate line Gate9 are set between the fourth and fifth rows of sub-pixels; the tenth gate line Gate10 and the eleventh gate line Gate11 are set between the fifth and sixth rows of sub-pixels; and the twelfth gate line Gate12 is set on the side of the sixth row of sub-pixels away from the fifth row of sub-pixels.

[0062] The first data line Source1 is set between the 1st and 2nd columns of sub-pixels; the second data line Source2 is set between the 3rd and 4th columns of sub-pixels; the third data line Source3 is set between the 5th and 6th columns of sub-pixels; and the fourth data line Source4 is set between the 7th and 8th columns of sub-pixels.

[0063] The driving circuit board is configured to drive the array of sub-pixels in a dot inversion manner, such as Figure 5 As shown, it is understandable that in actual driving, the voltage amplitude of the data signal varies. In this embodiment, the fixed amplitude of 5 is used as an example only for the convenience of explanation, because this embodiment mainly focuses on the number of switching times. The specific driving mode is:

[0064] In the current frame period, the 12 gate lines are scanned row by row, wherein, when scanning the first gate line Gate1, the sub-pixel in the first row and the first column is charged with a +5V data signal through the first data line Source1, the sub-pixel in the first row and the third column is charged with a +5V data signal through the second data line Source2, the sub-pixel in the first row and the fifth column is charged with a +5V data signal through the third data line Source3, and the sub-pixel in the first row and the seventh column is charged with a +5V data signal through the fourth data line Source4.

[0065] When scanning the second gate line Gate2, the sub-pixel in the second row and second column is charged with a +5V data signal through the first data line Source1, the sub-pixel in the second row and fourth column is charged with a +5V data signal through the second data line Source2, the sub-pixel in the second row and sixth column is charged with a +5V data signal through the third data line Source3, and the sub-pixel in the second row and eighth column is charged with a +5V data signal through the fourth data line Source4.

[0066] When scanning the third gate line Gate3, the sub-pixel in the first row and second column is charged with a -5V data signal through the first data line Source1, the sub-pixel in the first row and fourth column is charged with a -5V data signal through the second data line Source2, the sub-pixel in the first row and sixth column is charged with a -5V data signal through the third data line Source3, and the sub-pixel in the first row and eighth column is charged with a -5V data signal through the fourth data line Source4.

[0067] When scanning the fourth gate line Gate4, the sub-pixel in the second row and the first column is charged with a -5V data signal through the first data line Source1, the sub-pixel in the second row and the third column is charged with a -5V data signal through the second data line Source2, the sub-pixel in the second row and the fifth column is charged with a -5V data signal through the third data line Source3, and the sub-pixel in the second row and the seventh column is charged with a -5V data signal through the fourth data line Source4.

[0068] When scanning the fifth gate line Gate5, the sub-pixel in the third row and second column is charged with a -5V data signal through the first data line Source1, the sub-pixel in the third row and fourth column is charged with a -5V data signal through the second data line Source2, the sub-pixel in the third row and sixth column is charged with a -5V data signal through the third data line Source3, and the sub-pixel in the third row and eighth column is charged with a -5V data signal through the fourth data line Source4.

[0069] When scanning the 6th gate line Gate6, the sub-pixel in the 4th row and 1st column is charged with a -5V data signal through the 1st data line Source1, the sub-pixel in the 4th row and 3rd column is charged with a -5V data signal through the 2nd data line Source2, the sub-pixel in the 4th row and 5th column is charged with a -5V data signal through the 3rd data line Source3, and the sub-pixel in the 4th row and 7th column is charged with a -5V data signal through the 4th data line Source4.

[0070] When scanning the 7th gate line Gate7, the sub-pixel in the 3rd row and 1st column is charged with a +5V data signal through the 1st data line Source1, the sub-pixel in the 3rd row and 3rd column is charged with a +5V data signal through the 2nd data line Source2, the sub-pixel in the 3rd row and 5th column is charged with a +5V data signal through the 3rd data line Source3, and the sub-pixel in the 3rd row and 7th column is charged with a +5V data signal through the 4th data line Source4.

[0071] When scanning the 8th gate line Gate8, the sub-pixel in the 4th row and 2nd column is charged with a +5V data signal through the 1st data line Source1, the sub-pixel in the 4th row and 4th column is charged with a +5V data signal through the 2nd data line Source2, the sub-pixel in the 4th row and 6th column is charged with a +5V data signal through the 3rd data line Source3, and the sub-pixel in the 4th row and 8th column is charged with a +5V data signal through the 4th data line Source4.

[0072] When scanning the 9th gate line Gate9, the sub-pixel in the 5th row and 1st column is charged with a +5V data signal through the 1st data line Source1, the sub-pixel in the 5th row and 3rd column is charged with a +5V data signal through the 2nd data line Source2, the sub-pixel in the 5th row and 5th column is charged with a +5V data signal through the 3rd data line Source3, and the sub-pixel in the 5th row and 7th column is charged with a +5V data signal through the 4th data line Source4.

[0073] When scanning the 10th gate line Gate10, the sub-pixel in the 6th row and 2nd column is charged with a +5V data signal through the 1st data line Source1, the sub-pixel in the 6th row and 4th column is charged with a +5V data signal through the 2nd data line Source2, the sub-pixel in the 6th row and 6th column is charged with a +5V data signal through the 3rd data line Source3, and the sub-pixel in the 6th row and 8th column is charged with a +5V data signal through the 4th data line Source4.

[0074] When scanning the 11th gate line Gate11, the sub-pixel in the 5th row and 2nd column is charged with a -5V data signal through the 1st data line Source1, the sub-pixel in the 5th row and 4th column is charged with a -5V data signal through the 2nd data line Source2, the sub-pixel in the 5th row and 6th column is charged with a -5V data signal through the 3rd data line Source3, and the sub-pixel in the 5th row and 8th column is charged with a -5V data signal through the 4th data line Source4.

[0075] When scanning the 12th gate line Gate12, the sub-pixel in the 6th row and 1st column is charged with a -5V data signal through the 1st data line Source1, the sub-pixel in the 6th row and 3rd column is charged with a -5V data signal through the 2nd data line Source2, the sub-pixel in the 6th row and 5th column is charged with a -5V data signal through the 3rd data line Source3, and the sub-pixel in the 6th row and 7th column is charged with a -5V data signal through the 4th data line Source4.

[0076] In the next frame period, the 12 gate lines are scanned row by row, and the driving method is the same as that of the current frame period mentioned above, except that the +5V data signal of the current frame period is converted into a -5V data signal, and the -5V data signal of the current frame period is converted into a +5V data signal, which will not be repeated here.

[0077] As can be seen from the above-described driving method, the array substrate provided in this embodiment switches the voltage polarity of the data line data signal only once every four sub-pixels are charged. Compared to the existing dual gate + (1+2 Dot Inversion) inversion method, where the data line data signal switches the voltage polarity every time two sub-pixels are charged, the number of voltage polarity switches on the data line is reduced by half, thereby achieving the goal of reducing power consumption. Existing automotive TFT LCD panels generally require the customer to provide a 3.3V VDD voltage. The DC-DC circuits on the module's PCBA and FPCA first generate the VSP and VSN voltages, which are then generated by a charge pump circuit to generate the VGH and VGL voltages. In other words, driving a TFT LCD panel requires the VDD, VSP, VSN, VGH, and VGL voltages. However, for TFT LCD panels with lower power consumption, a separate charge pump circuit is not required; the array substrate's driver circuit board can suffice. Therefore, the use of this embodiment does not require the use of an additional charge pump circuit, which can save a large number of electronic components and thus achieve the purpose of reducing costs. While reducing power consumption and costs, the arrangement of sub-pixels also achieves true dot inversion, so this embodiment also has good quality performance such as low flicker and low crosstalk.

[0078] Another embodiment of the present invention provides a display device comprising the array substrate provided in the above embodiment. The display device may be, for example, a liquid crystal display device comprising a color filter substrate, a backlight module, the above array substrate, and the like. The display device may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or an in-vehicle display screen, and this embodiment does not limit this.

[0079] Another embodiment of the present invention provides a driving method of an array substrate, wherein:

[0080] The array substrate includes a driving circuit board, N rows and 2M columns of sub-pixels arranged in an array, 2N gate lines and M data lines, wherein the mth data line is connected to the 2m-1th and 2mth columns of sub-pixels respectively, the 8n+1th gate line is connected to the sub-pixels in the odd columns in the 4n+1th row, the 8n+2th gate line is connected to the sub-pixels in the even columns in the 4n+2th row, the 8n+3th gate line is connected to the sub-pixels in the even columns in the 4n+1th row, the 8n+4th gate line is connected to the sub-pixels in the odd columns in the 4n+2th row, the 8n+5th gate line is connected to the sub-pixels in the even columns in the 4n+3th row, the 8n+6th gate line is connected to the sub-pixels in the odd columns in the 4n+4th row, the 8n+7th gate line is connected to the sub-pixels in the odd columns in the 4n+3th row, and the 8n+8th gate line is connected to the sub-pixels in the even columns in the 4n+4th row, m is a positive integer, and n is a natural number.

[0081] The driving method includes: driving a circuit board to drive the array of sub-pixels in a dot inversion manner.

[0082] In a possible implementation, the driving circuit board drives the array of sub-pixels in a dot inversion manner, including: in a current frame period, scanning the 2N gate lines row by row, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 4n+1th row and the 2m-1th column is charged with a data signal of a first polarity through the mth data line, when scanning the 8n+2th gate line, the sub-pixel in the 4n+2th row and the 2m-1th column is charged with a data signal of a first polarity through the mth data line, when scanning the 8n+3th gate line, the sub-pixel in the 4n+1th row and the 2m-2nd column is charged with a data signal of a second polarity through the mth data line, and when scanning the 8n+4th gate line, the sub-pixel in the 8n+5th row and the 2m-5th column is charged with a data signal of a second polarity through the mth data line. The sub-pixel in the 4n+2 row and the 2m-1 column is charged with the data signal of the second polarity through the m-th data line when scanning the 8n+5-th gate line, the sub-pixel in the 4n+3 row and the 2m-1 column is charged with the data signal of the second polarity through the m-th data line when scanning the 8n+6-th gate line, the sub-pixel in the 4n+4 row and the 2m-1 column is charged with the data signal of the second polarity through the m-th data line when scanning the 8n+7-th gate line, and the sub-pixel in the 4n+3 row and the 2m-1 column is charged with the data signal of the first polarity through the m-th data line when scanning the 8n+8-th gate line.

[0083] Furthermore, the driving circuit board drives the array of sub-pixels in a dot inversion manner and further includes: in the next frame period, scanning the 2N gate lines row by row, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the second polarity through the mth data line, when scanning the 8n+2th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line, when scanning the 8n+3th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the first polarity through the mth data line, and when scanning the 8n+4th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line. The sub-pixel in the 2m-1 column of the 4n+2 row is charged with a data signal of the first polarity, the sub-pixel in the 2m-1 column of the 4n+3 row is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+5-th gate line, the sub-pixel in the 2m-1 column of the 4n+4 row is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+6-th gate line, the sub-pixel in the 2m-1 column of the 4n+3 row is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+7-th gate line, and the sub-pixel in the 2m-1 column of the 4n+4 row is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+8-th gate line.

[0084] It should be noted that the driving method provided in this embodiment is similar to the principle and working process of the array substrate provided in the above embodiment. For relevant details, please refer to the above description and will not be repeated here.

[0085] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0086] It should also be noted that, in the description of the present invention, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0087] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in this field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present invention are still within the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: The invention comprises a driving circuit board, N rows and 2M columns of sub-pixels arranged in an array, 2N gate lines and M data lines, wherein the mth data line is connected to the 2m-1th and 2mth columns of sub-pixels respectively, the 8n+1th gate line is connected to the sub-pixels in the odd columns in the 4n+1th row, the 8n+2th gate line is connected to the sub-pixels in the even columns in the 4n+2th row, the 8n+3th gate line is connected to the sub-pixels in the even columns in the 4n+1th row, the 8n+4th gate line is connected to the sub-pixels in the odd columns in the 4n+2th row, the 8n+5th gate line is connected to the sub-pixels in the even columns in the 4n+3th row, the 8n+6th gate line is connected to the sub-pixels in the odd columns in the 4n+4th row, the 8n+7th gate line is connected to the sub-pixels in the odd columns in the 4n+3th row, and the 8n+8th gate line is connected to the sub-pixels in the even columns in the 4n+4th row, m is a positive integer, and n is a natural number; The driving circuit board is configured to drive the array of sub-pixels in a dot inversion manner.

2. The array substrate according to claim 1, wherein: The driving circuit board is configured to scan the 2N gate lines row by row in a current frame period, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the first polarity through the mth data line; when scanning the 8n+2th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the first polarity through the mth data line; when scanning the 8n+3th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the second polarity through the mth data line; when scanning the 8n+4th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line; The column sub-pixels are charged with a data signal of the second polarity, and when scanning the 8n+5th gate line, the sub-pixel in the 2mth column of the 4n+3th row is charged with a data signal of the second polarity through the mth data line, and when scanning the 8n+6th gate line, the sub-pixel in the 2m-1th column of the 4n+4th row is charged with a data signal of the second polarity through the mth data line, and when scanning the 8n+7th gate line, the sub-pixel in the 2m-1th column of the 4n+3th row is charged with a data signal of the first polarity through the mth data line, and when scanning the 8n+8th gate line, the sub-pixel in the 2mth column of the 4n+4th row is charged with a data signal of the first polarity through the mth data line.

3. The array substrate according to claim 2, wherein: The driving circuit board is configured to scan the 2N gate lines row by row in the next frame period, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the second polarity through the mth data line; when scanning the 8n+2th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line; when scanning the 8n+3th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the first polarity through the mth data line; when scanning the 8n+4th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line; The column sub-pixels are charged with a data signal of a first polarity, and when scanning the 8n+5th gate line, the sub-pixel in the 2mth column of the 4n+3th row is charged with a data signal of the first polarity through the mth data line, and when scanning the 8n+6th gate line, the sub-pixel in the 2m-1th column of the 4n+4th row is charged with a data signal of the first polarity through the mth data line, and when scanning the 8n+7th gate line, the sub-pixel in the 2m-1th column of the 4n+3th row is charged with a data signal of the second polarity through the mth data line, and when scanning the 8n+8th gate line, the sub-pixel in the 2mth column of the 4n+4th row is charged with a data signal of the second polarity through the mth data line.

4. The array substrate according to claim 1, wherein: Two gate lines are provided between two adjacent rows of sub-pixels and are respectively connected to some columns of sub-pixels in the two adjacent rows of sub-pixels.

5. The array substrate according to claim 1, wherein: The data line is arranged between two adjacent columns of sub-pixels connected to the data line.

6. The array substrate according to claim 1, wherein: The sub-pixel includes a transistor and a pixel electrode. The control electrode of the transistor is connected to the corresponding gate line, the first electrode is connected to the corresponding data line, and the second electrode is connected to the pixel electrode.

7. A display device, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 6.

8. A driving method for an array substrate, characterized in that: The array substrate includes a driving circuit board, N rows and 2M columns of sub-pixels arranged in an array, 2N gate lines and M data lines, wherein the mth data line is connected to the 2m-1th and 2mth columns of sub-pixels respectively, the 8n+1th gate line is connected to the sub-pixels in the odd columns in the 4n+1th row, the 8n+2th gate line is connected to the sub-pixels in the even columns in the 4n+2th row, the 8n+3th gate line is connected to the sub-pixels in the even columns in the 4n+1th row, the 8n+4th gate line is connected to the sub-pixels in the odd columns in the 4n+2th row, the 8n+5th gate line is connected to the sub-pixels in the even columns in the 4n+3th row, the 8n+6th gate line is connected to the sub-pixels in the odd columns in the 4n+4th row, the 8n+7th gate line is connected to the sub-pixels in the odd columns in the 4n+3th row, and the 8n+8th gate line is connected to the sub-pixels in the even columns in the 4n+4th row, m is a positive integer, and n is a natural number; The driving method includes: driving a circuit board to drive the array of sub-pixels in a dot inversion manner.

9. The method according to claim 8, characterized in that The driving circuit board drives the array of sub-pixels in a dot inversion manner, comprising: scanning the 2N gate lines row by row in a current frame period, wherein, when scanning the 8n+1th gate line, charging the sub-pixel in the 2m-1th column of the 4n+1th row through the mth data line with a data signal of a first polarity, when scanning the 8n+2th gate line, charging the sub-pixel in the 2m-1th column of the 4n+2th row through the mth data line with a data signal of a first polarity, when scanning the 8n+3th gate line, charging the sub-pixel in the 2m-2nd column of the 4n+1th row through the mth data line with a data signal of a second polarity, and when scanning the 8n+4th gate line, charging the sub-pixel in the 2m-1th column of the 4n+2th row through the mth data line with a data signal of a second polarity. The sub-pixel in the 2m-1 column of the 2nd row is charged with the data signal of the second polarity, the sub-pixel in the 2m-1 column of the 4n+3rd row is charged with the data signal of the second polarity through the m-th data line when scanning the 8n+5th gate line, the sub-pixel in the 2m-1 column of the 4n+4th row is charged with the data signal of the second polarity through the m-th data line when scanning the 8n+6th gate line, the sub-pixel in the 2m-1 column of the 4n+3rd row is charged with the data signal of the first polarity through the m-th data line when scanning the 8n+7th gate line, and the sub-pixel in the 2m-1 column of the 4n+3rd row is charged with the data signal of the first polarity through the m-th data line when scanning the 8n+8th gate line.

10. The method according to claim 9, characterized in that The driving circuit board drives the array of sub-pixels in a dot inversion manner further comprising: scanning the 2N gate lines row by row in the next frame period, wherein, when scanning the 8n+1th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the second polarity through the mth data line; when scanning the 8n+2th gate line, the sub-pixel in the 2m-1th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line; when scanning the 8n+3th gate line, the sub-pixel in the 2m-1th column of the 4n+1th row is charged with a data signal of the first polarity through the mth data line; and when scanning the 8n+4th gate line, the sub-pixel in the 2n-4th column of the 4n+2th row is charged with a data signal of the second polarity through the mth data line. The sub-pixel in the 2m-1 column of the 4n+2 row is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+5-th gate line, the sub-pixel in the 2m-1 column of the 4n+4 row is charged with a data signal of the first polarity through the m-th data line when scanning the 8n+6-th gate line, the sub-pixel in the 2m-1 column of the 4n+3 row is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+7-th gate line, and the sub-pixel in the 2m-1 column of the 4n+3 row is charged with a data signal of the second polarity through the m-th data line when scanning the 8n+8-th gate line.

Images