Display substrate, display panel and display device

Abstract

This disclosure provides a display substrate, a display panel, and a display device. The display substrate includes: multiple rows of pixel circuits, each row of pixel circuits arranged along a first direction, and two different rows of pixel circuits arranged along a second direction intersecting the first direction; a first gate driving circuit and a second gate driving circuit, respectively disposed on opposite sides of the multiple rows of pixel circuits along the first direction; a gating control circuit and multiple gate lines, each gate line having its two ends connected to the first gate driving circuit and the second gate driving circuit respectively via the gating control circuit. The gating control circuit is used to cause the first gate driving circuit and the second gate driving circuit to alternately drive the same gate line. This display substrate helps improve the uniformity of the display.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display substrate, a display panel, and a display device. Background Technology

[0002] This section is intended to provide background or context for the embodiments set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] To achieve the narrow bezel design, gate driving circuits are respectively set on the left and right bezels of the display substrate. The left gate driving circuit drives a portion of the pixel circuits through gate lines, and the right gate driving circuit drives another portion of the pixel circuits through gate lines.

[0004] Due to the resistance and distributed capacitance on the gate lines, the pixel circuits at the left and right positions on the gate lines connected to the left gate driving circuit experience significant differences in the gate voltage waveforms received, as do the pixel circuits at the left and right positions on the gate lines connected to the right gate driving circuit. This results in uneven display performance on the display substrate.

[0005] When the display substrate is large, this unevenness in display effect becomes more obvious. Summary of the Invention

[0006] This disclosure provides a display substrate, a display panel, and a display device.

[0007] This disclosure adopts the following technical solution: a display substrate, comprising:

[0008] The system comprises multiple rows of pixel circuits, each row of which is arranged along a first direction, and two different rows of pixel circuits are arranged along a second direction that intersects with the first direction.

[0009] The first gate driving circuit and the second gate driving circuit are respectively disposed on both sides of the multi-row pixel circuit along the first direction.

[0010] The system includes a gating control circuit and multiple gate lines. The two ends of each gate line are connected to the first gate driving circuit and the second gate driving circuit, respectively, through the gating control circuit. The gating control circuit is used to enable the first gate driving circuit and the second gate driving circuit to alternately drive the same gate line.

[0011] In some embodiments, the first gate driving circuit includes a plurality of first shift register units, the second gate driving circuit includes a plurality of second shift register units, the plurality of gate lines are divided into a plurality of first gate lines and a plurality of second gate lines, the plurality of first gate lines are respectively connected to a portion of the pixel circuits in a row of pixel circuits, and the plurality of second gate lines are respectively connected to the remaining pixel circuits in a row of pixel circuits.

[0012] The plurality of first shift register units are controlled by the gating control circuit to switch between a first state and a second state. The first state includes the first to Nth first shift register units being connected to a first gate line, and the second state includes the second to N+1th first shift register units being connected to a second gate line.

[0013] The plurality of second shift register units are controlled by the gating control circuit to switch between a third state and a fourth state. The third state includes the first to Nth second shift register units being connected to a second gate line, and the fourth state includes the first to Nth second shift register units being connected to a first gate line, where N is a positive integer.

[0014] In some embodiments, the first gate driving circuit includes a plurality of first shift register units, the second gate driving circuit includes a plurality of second shift register units, the plurality of gate lines are divided into a plurality of first gate lines and a plurality of second gate lines, the plurality of first gate lines are respectively connected to a portion of the pixel circuits in a row of pixel circuits, and the plurality of second gate lines are respectively connected to the remaining pixel circuits in a row of pixel circuits.

[0015] The plurality of first shift register units are controlled by the gating control circuit to switch between a first state and a second state. The first state includes the first to Nth first shift register units being connected to a first gate line, and the second state includes the first to Nth first shift register units being connected to a second gate line.

[0016] The plurality of second shift register units are controlled by the gating control circuit to switch between a third state and a fourth state. The third state includes the first to Nth second shift register units being connected to a second gate line, and the fourth state includes the first to Nth second shift register units being connected to a first gate line, where N is a positive integer.

[0017] In some embodiments, the first gate driving circuit includes a plurality of first shift register units, the second gate driving circuit includes a plurality of second shift register units, and each gate line is connected to a row of pixel circuits.

[0018] The plurality of first shift register units are controlled by the gating control circuit to switch between a first state and a second state. The first state includes the first to Nth first shift register units being connected to odd-numbered gate lines, and the second state includes the second to N+1th first shift register units being connected to even-numbered gate lines.

[0019] The plurality of second shift register units are controlled by the gating control circuit to switch between a third state and a fourth state. The third state includes the first to Nth second shift register units being connected to even-numbered gate lines, and the fourth state includes the first to Nth second shift register units being connected to odd-numbered gate lines, where N is a positive integer.

[0020] In some embodiments, the first gate driving circuit includes a plurality of first shift register units, the second gate driving circuit includes a plurality of second shift register units, and each gate line is connected to a row of pixel circuits.

[0021] The plurality of first shift register units are controlled by the gating control circuit to switch between a first state and a second state. The first state includes the first to Nth first shift register units being connected to odd-numbered gate lines, and the second state includes the first to Nth first shift register units being connected to even-numbered gate lines.

[0022] The plurality of second shift register units are controlled by the gating control circuit to switch between a third state and a fourth state. The third state includes the first to Nth second shift register units being connected to even-numbered gate lines, and the fourth state includes the first to Nth second shift register units being connected to odd-numbered gate lines, where N is a positive integer.

[0023] In some embodiments, the plurality of gate lines are divided into a first group of gate lines and a second group of gate lines;

[0024] The gating control circuit includes:

[0025] Multiple first switching elements are connected one-to-one with the gate lines in the first group of gate lines and connected to the first gate driving circuit;

[0026] The first gating control line is used to control the on / off state of the plurality of first switching elements;

[0027] Multiple second switching elements are connected one-to-one with the gate lines in the second group of gate lines and connected to the first gate drive circuit;

[0028] The second gating control line is used to control the on / off state of the plurality of second switching elements;

[0029] Multiple third switching elements are connected one-to-one with the gate lines in the first group of gate lines and connected to the second gate drive circuit;

[0030] The third gating control line is used to control the on / off state of the plurality of third switching elements;

[0031] Multiple fourth switching elements are connected one-to-one with the gate lines in the second group of gate lines and connected to the second gate drive circuit;

[0032] The fourth gating control line is used to control the on / off state of the plurality of fourth switching elements.

[0033] In some embodiments, the control voltages of the first switching element, the second switching element, the third switching element, and the fourth switching element have the same polarity in the on state, the first gating control line and the fourth gating control line are electrically connected, and the second gating control line and the third gating control line are electrically connected.

[0034] The present disclosure adopts the following technical solution: a display panel, including the aforementioned display substrate.

[0035] In some embodiments, the display panel is a liquid crystal display panel or an electronic paper display panel.

[0036] The present disclosure adopts the following technical solution: a display device, including the aforementioned display panel, and including a timing controller and a source driving circuit, wherein the timing controller is used to provide a gating control signal to the gating control circuit so that the first gate driving circuit and the second gate driving circuit alternately drive the same gate line, and the source driving circuit is used to provide a pixel voltage to the pixel circuit, wherein the pixel voltage is a pixel voltage including a frame flip mode.

[0037] In some embodiments, when the second to the N+1th first shift register units are respectively connected to a second gate line, the time when the source driving circuit writes a frame of display data to the display substrate is delayed by the display data writing time required by a row of pixel circuits.

[0038] In some embodiments, when the second to the (N+1)th first shift register units drive the pixel circuits located in even-numbered rows, the time when the source driving circuit writes a frame of display data to the display substrate is delayed by the display data writing time required by one row of pixel circuits. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure of a display substrate according to some embodiments of this disclosure.

[0040] Figure 2 yes Figure 1 The diagram shown is a circuit diagram of a single shift register unit in the first gate drive circuit and the second gate drive circuit of the display substrate.

[0041] Figure 3 yes Figure 2 The diagram shows the cascade relationship of the shift register units.

[0042] Figure 4 It includes Figure 1 The diagram shows the structure of a display device based on a display substrate.

[0043] Figure 5 yes Figure 4 The diagram shows the driving timing of the display device.

[0044] Figure 6 yes Figure 4 The diagram shown illustrates the principle of the display device in eliminating uneven display effects.

[0045] Figure 7 This is a schematic diagram of the structure of a display substrate according to other embodiments of this disclosure.

[0046] Figure 8 It includes Figure 7 The diagram shows the principle of a display device on a display substrate that eliminates uneven display effects.

[0047] Figure 9 This is a schematic diagram of the structure of a display substrate according to other embodiments of this disclosure.

[0048] Figure 10 This is a schematic diagram of the structure of a display substrate according to other embodiments of this disclosure.

[0049] Figure 11 It includes Figure 9 or Figure 10 The diagram shows the principle of a display device on a display substrate that eliminates uneven display effects. Detailed Implementation

[0050] The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.

[0051] refer to Figure 1 , Figure 7 , Figure 9 and Figure 10 The embodiments of this disclosure provide a display substrate P, comprising:

[0052] The system comprises multiple rows of pixel circuits, each row of which is arranged along a first direction, and two different rows of pixel circuits are arranged along a second direction that intersects with the first direction.

[0053] The first gate driving circuit GOA1 and the second gate driving circuit GOA2 are respectively disposed on both sides of the multi-row pixel circuit along the first direction.

[0054] The selection control circuit 1 and multiple gate lines GL, GL1, GL2 are connected at both ends of the gate lines GL, GL1, GL2 to the first gate drive circuit GOA1 and the second gate drive circuit GOA2 respectively through the selection control circuit 1. The selection control circuit 1 is used to make the first gate drive circuit GOA1 and the second gate drive circuit GOA2 alternately drive the same gate line GL, GL1, GL2.

[0055] Figure 1 , Figure 7 , Figure 9 and Figure 10 The diagram exemplifies a pixel circuit arranged in a rectangular array. The pixel circuit includes a switching element T0 (which may specifically be a thin-film transistor) and pixel electrodes R, G, and B. The control electrode of the switching element T0 is connected to gate lines GL, GL1, and GL2; the first electrode of the switching element T0 is connected to the data line DL; and the second electrode of the switching element T0 is connected to the pixel electrodes R, G, and B.

[0056] Pixel electrodes R, G, and B are not inherently different; the difference in designation simply indicates that they are used to form sub-pixels of different colors in the display panel or display device. For example, pixel electrode R is used to form a red pixel circuit and create a red sub-pixel in the display panel or display device; pixel electrode G is used to form a green pixel circuit and create a green sub-pixel in the display panel or display device; and pixel electrode B is used to form a blue pixel circuit and create a blue sub-pixel in the display panel or display device.

[0057] The first gate drive circuit GOA1 includes multiple shift register units, and the second gate drive circuit GOA2 includes multiple shift register units. Figure 1 , Figure 7 , Figure 9 and Figure 10 In the embodiments shown, according to the current view of each figure, the first gate driving circuit GOA1 is disposed on the left side of the pixel circuit, and the second gate driving circuit GOA2 is disposed on the right side of the pixel circuit.

[0058] Each gate line GL, GL1, GL2 is connected to the first gate drive circuit GOA1 and the second gate drive circuit GOA2. The on / off relationship between gate lines GL, GL1, GL2 and the first gate drive circuit GOA1, as well as the on / off relationship with the second gate drive circuit GOA2, is controlled by the gating control circuit 1.

[0059] Because the same gate lines GL, GL1, and GL2 are alternately driven by the first gate driving circuit GOA1 and the second gate driving circuit GOA2, in each pixel circuit connected to these gate lines GL, GL1, and GL2, except for the pixel circuit at the center, each pixel circuit is alternately located near and far from the gate driving circuit that outputs the gate driving signal. The various parameters of the gate driving signal received by these pixel circuits (e.g., voltage value, voltage fluctuation value, etc.) alternately fall within the optimal and unoptimized value ranges. Furthermore, when this display substrate P is used in a display panel, taking a liquid crystal display panel as an example, when the display panel displays a static image, the transmittance of the sub-pixels corresponding to the pixel circuits also alternately exhibits larger and smaller values. This improves the uniformity of the display effect on the left and right sides of the display panel. For example, the brightness or color of the left and right sides of the display panel is more uniform. When the display panel displays a dynamic image, the unevenness of the display is not obvious and can be approximately ignored.

[0060] Continue to refer to Figure 1 and Figure 7 In some embodiments, the first gate driving circuit GOA1 includes a plurality of first shift register units, the second gate driving circuit GOA2 includes a plurality of second shift register units, the plurality of gate lines are divided into a plurality of first gate lines GL1 and a plurality of second gate lines GL2, the plurality of first gate lines GL1 are respectively connected to a portion of the pixel circuits in a row of pixel circuits, and the plurality of second gate lines GL2 are respectively connected to the remaining pixel circuits in a row of pixel circuits;

[0061] The plurality of first shift register units are controlled by the gating control circuit 1 to switch between the following first state and second state. The first state includes the first to Nth first shift register units being connected to a first gate line GL1 respectively. The second state includes the second to N+1th first shift register units being connected to a second gate line GL2 respectively.

[0062] The plurality of second shift register units are controlled by the gating control circuit 1 to switch between a third state and a fourth state. The third state includes the first to Nth second shift register units being connected to a second gate line GL2 respectively. The fourth state includes the first to Nth second shift register units being connected to a first gate line GL1 respectively. N is a positive integer.

[0063] refer to Figure 1 The pixel circuit is divided into a red pixel circuit (containing pixel electrode R), a blue pixel circuit (containing pixel electrode G), and a green pixel circuit (containing pixel circuit B). The red, blue, and green pixel circuits are arranged periodically along the first direction, and pixel circuits of the same color are aligned and arranged along the second direction.

[0064] exist Figure 1 In the illustrated embodiment, odd-numbered gate lines serve as the first gate line GL1, connecting to the red pixel circuit and part of the blue pixel circuit in a row of pixel circuits, respectively. Even-numbered gate lines serve as the second gate line GL2, connecting to the green pixel circuit and the remaining blue pixel circuit in a row of pixel circuits, respectively.

[0065] Within a certain frame period, the first to Nth first shift register units are each connected to a first gate line GL1, and the first to Nth second shift register units are each connected to a second gate line GL2.

[0066] During the subsequent frame period, the second to the (N+1)th first shift register units are connected to a second gate line GL2, and the first to the Nth second shift register units are connected to a first gate line GL1.

[0067] If the timing of the first gate driving circuit GOA1 and the second gate driving circuit GOA2 is periodically fixed, the moment when the first first shift register unit outputs a valid signal is always one line cycle (the data write cycle of one row of pixel circuits) earlier than the moment when the first second shift register unit outputs a valid signal. In the subsequent frame cycles, compared to the aforementioned frame cycle, the moment when the first gate line (in this case, the first second gate line GL2) is driven is delayed by one line cycle. Correspondingly, in the display device, in the subsequent frame cycles, the moment when a frame of display data is written to the display substrate P is also delayed by one line cycle.

[0068] In embodiments of this disclosure, reference is made to Figure 2 The circuit structures of each of the first and second shift register units are identical. The shift register unit includes transistors M1 to M11, as well as M6', M8', M9', M10', M11' and M12', and signal terminals STV0, STV1, VDD1, VDD2, CLK, OUTPUT, RST_PU, LVGL and VGL.

[0069] Figure 3 The cascading relationship of the nine shift register units Gate1, Gate3, Gate5, Gate7, Gate9, Gate11, Gate13, Gate15, and Gate17 in the first gate drive circuit GOA1 and the cascading relationship of the nine shift register units Gate2, Gate4, Gate6, Gate8, Gate10, Gate12, Gate14, Gate16, and Gate18 in the second gate drive circuit GOA2 are shown. Figure 4 The exhibit includes Figure 1 A block diagram of a display device on display substrate P. Figure 5 What is being shown is Figure 4The timing diagram of the display device is shown. In this embodiment, the circuit structures of the first shift register unit and the second shift register unit are identical.

[0070] Signals VGL and LVGL are constant low-level voltages. Signal STV0 sets the voltage at node PU to a low level. Furthermore, nodes PD1 and PD2 set the voltage at the output terminal OUTPUT to a low level.

[0071] Signals STV1_R and STV1_L are the start signals received by the first shift register unit of the first gate drive circuit GOA1 and the second gate drive circuit GOA2, respectively. Specifically, signals STV1_R and STV1_L are connected to port STV1 of the first shift register unit of the first gate drive circuit GOA1 and the second gate drive circuit GOA2, respectively.

[0072] Signals CLK1_L to CLK6_L are clock signals provided to some shift register units in the first gate drive circuit GOA1. Specifically, signals CLK1_L to CLK6_L are respectively connected to the CLK of some signals in the first shift register units. The level states of signals VDD1 and VDD2 are complementary and are respectively connected to transistors M9 and M9' of each first shift register unit and each second shift register unit.

[0073] The above is merely an illustrative representation of the circuit structure of the gate drive circuit, and this disclosure does not impose any special limitations on it.

[0074] Combination Figure 1 Signals CH1 and CH2 are signals on the gating control lines L1, L2, L3, and L4.

[0075] When signal CH1 is high, the switching elements T1 and T4 it controls are turned on. The first gate drive circuit GOA1 is connected to the odd-numbered gate lines (i.e., the first gate line GL1), and the second gate drive circuit GOA2 is connected to the even-numbered gate lines (i.e., the second gate line GL2). At this time, when signal CH2 is low, the first gate drive circuit GOA1 is disconnected from the even-numbered gate lines, and the second gate drive circuit GOA2 is disconnected from the odd-numbered gate lines.

[0076] When signal CH2 is high, the switching elements T2 and T3 it controls are turned on. The second gate drive circuit GOA2 is connected to the odd-numbered gate lines (i.e., the second gate line G2), and the first gate drive circuit GOA1 is connected to the even-numbered gate lines (i.e., the first gate line GL1). At this time, when signal CH1 is low, the second gate drive circuit GOA2 is disconnected from the even-numbered gate lines, and the first gate drive circuit GOA1 is disconnected from the odd-numbered gate lines.

[0077] Combination Figure 4 The signal TP is a trigger signal sent by the timing controller TCON to the source drive circuit Driver, which triggers the source drive circuit Driver to output the source drive voltage to the data line DL of the display substrate P.

[0078] The signal Data represents the data voltage signal output by the source drive circuit Driver.

[0079] Specifically, refer to Figure 4 The timing controller TCON provides voltage signals VDDO, VDDE, and CPV1 to CPV4 to two level converters LS1 and LS2, respectively, and gating control signals CH1 and CH2 to another level converter LS2. Level converter LS1 converts the received signals into signals STV1_L, CLK1_L to CLK6_L required by the first gate drive circuit GOA1, and provides signals STV0, VDD1, and VDD2 to the first and second gate drive circuits GOA1 and GOA2. The other level converter LS2 converts the received signals into signals STV1_R, CLK1_R to CLK6_R required by the second gate drive circuit GOA2, and provides gating control signals CH1 and CH2 to gating control circuit 1.

[0080] The timing controller TCON provides signals TP, POL, and mLVDS to the source driver circuit. Signal TP is the start signal that triggers the source driver circuit to output the source voltages required for a row of pixel circuits R, G, and B. Signal POL controls whether the source driver circuit outputs a positive or negative data voltage. The source driver circuit interprets the mLVDS signal into a specific data voltage signal according to the protocol.

[0081] refer to Figure 6 When a display device displays two consecutive frames of static images, the display characteristics on the left and right sides of the Mth frame and the M+1th frame are interchanged. In the Mth frame, the left side of the screen appears bluish and the right side reddish, while in the M+1th frame, the left side appears reddish and the right side bluish. Overall, the human eye perceives the display effect as uniform across the entire screen.

[0082] refer to Figure 7The pixel circuit is divided into red pixel circuits (including pixel electrode R and switching element T0), blue pixel circuits (including pixel electrode G and switching element T0), and green pixel circuits (including pixel electrode B and switching element T0). The red, blue, and green pixel circuits are arranged periodically along a first direction, and pixel circuits of the same color are aligned and arranged along a second direction. It should be noted that the circuit structures of the red, blue, and green pixel circuits are identical; the only difference lies in the light-emitting color (e.g., the color of the corresponding color filter) of the pixel circuit when the display substrate is manufactured into a display panel or display device.

[0083] exist Figure 7 In the illustrated embodiment, odd-numbered gate lines serve as first gate lines GL1, connecting to pixel circuits in odd-numbered columns of a row of pixel circuits. Even-numbered gate lines serve as second gate lines GL2, connecting to pixel circuits in even-numbered columns of a row of pixel circuits.

[0084] When signal CH1 is high, the switching elements T1 and T4 it controls are turned on. The first gate drive circuit GOA1 is connected to the odd-numbered gate lines (i.e., the first gate line GL1), and the second gate drive circuit GOA2 is connected to the even-numbered gate lines (i.e., the second gate line GL2). At this time, when signal CH2 is low, the first gate drive circuit GOA1 is disconnected from the even-numbered gate lines, and the second gate drive circuit GOA2 is disconnected from the odd-numbered gate lines.

[0085] When signal CH2 is high, its controlled switching elements T2 and T3 are turned on. The first gate drive circuit GOA1 is connected to the even-numbered gate lines (i.e., Diehl gate lines GL2), and the second gate drive circuit GOA2 is connected to the odd-numbered gate lines (i.e., the first gate line GL1). At this time, when signal CH1 is low, the first gate drive circuit GOA1 is disconnected from the odd-numbered gate lines, and the second gate drive circuit GOA2 is disconnected from the even-numbered gate lines.

[0086] refer to Figure 8 In the consecutive M-th and M+1-th frames, vertical stripes appear on the displayed image because each gate line GL1 and GL2 is driven by a single-sided gate drive circuit. Since the time interval between two consecutive frames is very small, the brightness of the displayed image perceived by the user is relatively uniform, and the vertical stripes can be ignored.

[0087] In some embodiments, the first gate driving circuit includes a plurality of first shift register units, the second gate driving circuit includes a plurality of second shift register units, the plurality of gate lines are divided into a plurality of first gate lines and a plurality of second gate lines, the plurality of first gate lines are respectively connected to a portion of the pixel circuits in a row of pixel circuits, and the plurality of second gate lines are respectively connected to the remaining pixel circuits in a row of pixel circuits.

[0088] The plurality of first shift register units are controlled by the gating control circuit to switch between a first state and a second state. The first state includes the first to Nth first shift register units being connected to a first gate line, and the second state includes the first to Nth first shift register units being connected to a second gate line.

[0089] The plurality of second shift register units are controlled by the gating control circuit to switch between a third state and a fourth state. The third state includes the first to Nth second shift register units being connected to a second gate line, and the fourth state includes the first to Nth second shift register units being connected to a first gate line, where N is a positive integer.

[0090] In these embodiments, with Figure 1 and Figure 7 The difference in the illustrated embodiment is that the first shift register unit in the first gate drive circuit can drive the first gate line or the second gate line in different frame periods.

[0091] For example, in frame M, the first shift register unit of the first gate driving circuit drives the first gate line, and the first shift register unit of the second gate driving circuit drives the second gate line. In frame M+1, the first shift register unit of the first gate driving circuit drives the second gate line, and the first shift register unit of the second gate driving circuit drives the first gate line.

[0092] by Figure 4 For example, level conversion circuits LS1 and LS2 first provide a start signal to the first gate drive circuit GOA1 in the Mth frame, and first provide a start signal to the second gate drive circuit GOA2 in the M+1th frame.

[0093] In some embodiments, reference Figure 9 and Figure 10 The first gate driving circuit GOA1 includes multiple first shift register units, and the second gate driving circuit GOA2 includes multiple second shift register units. Each gate line GL is connected to a row of pixel circuits.

[0094] The plurality of first shift register units GOA1 are controlled by the gating control circuit 1 to switch between a first state and a second state. The first state includes the first to Nth first shift register units being connected to odd-numbered gate lines GL respectively, and the second state includes the second to N+1th first shift register units being connected to even-numbered gate lines GL respectively.

[0095] The plurality of second shift register units are controlled by the gating control circuit 1 to switch between the following third and fourth states. The third state includes the first to Nth second shift register units being connected to even-numbered gate lines GL, and the fourth state includes the first to Nth second shift register units being connected to odd-numbered gate lines GL, where N is a positive integer.

[0096] Specifically, in Figure 9 and Figure 10 In the illustrated embodiment, when signal CH1 is high, the switching elements T1 and T4 it controls are turned on. The first gate driving circuit GOA1 is connected to the odd-numbered gate lines GL and drives the odd-numbered pixel circuits. The second gate driving circuit GOA2 is connected to the even-numbered gate lines GL and drives the even-numbered pixel circuits. At this time, when signal CH2 is low, the first gate driving circuit GOA1 is disconnected from the even-numbered gate lines GL, and the second gate driving circuit GOA2 is disconnected from the odd-numbered gate lines GL.

[0097] When signal CH2 is high, its controlled switching elements T2 and T3 are turned on. The first gate driving circuit GOA1 is connected to the even-numbered gate lines GL and drives the even-numbered pixel circuits. The second gate driving circuit GOA2 is connected to the odd-numbered gate lines GL and drives the odd-numbered pixel circuits. At this time, when signal CH1 is low, the first gate driving circuit GOA1 is disconnected from the odd-numbered gate lines GL, and the second gate driving circuit GOA2 is disconnected from the even-numbered gate lines GL.

[0098] exist Figure 9 In the embodiment shown, pixel circuits of the same color in the same column are connected to the same data line DL. Figure 10 In the illustrated embodiment, the same data line DL connects half of the pixel circuits in the left and right columns of pixel circuits, respectively.

[0099] refer to Figure 11 ,for Figure 9 and Figure 10 The display panel or display device made of the display substrate shown in the figure, when displaying a static solid color grayscale image, shows gradient horizontal stripes in the Mth frame and the M+1th frame, but the overall display effect of the two consecutive frames is a relatively uniform solid color image.

[0100] In other embodiments, the first gate driving circuit GL1 includes a plurality of first shift register units, and the second gate driving circuit GL2 includes a plurality of second shift register units, with each gate line connected to a row of pixel circuits.

[0101] The plurality of first shift register units are controlled by the gating control circuit 1 to switch between a first state and a second state. The first state includes the first to Nth first shift register units being connected to odd-numbered gate lines GL respectively, and the second state includes the first to Nth first shift register units being connected to even-numbered gate lines GL respectively.

[0102] The plurality of second shift register units are controlled by the gating control circuit 1 to switch between a third state and a fourth state. The third state includes the first to Nth second shift register units being connected to even-numbered gate lines, and the fourth state includes the first to Nth second shift register units being connected to odd-numbered gate lines, where N is a positive integer.

[0103] In these embodiments, with Figure 9 and Figure 10 The difference in the illustrated embodiment is that the first shift register unit in the first gate drive circuit GOA1 can drive the first gate line GL or the second gate line GL in different frame periods.

[0104] For example, in frame M, the first shift register unit of the first gate drive circuit GOA1 drives the first gate line GL, and the first shift register unit of the second gate drive circuit GOA2 drives the second gate line GL. In frame M+1, the first shift register unit of the second gate drive circuit GOA2 drives the first gate line GL, and the first shift register unit of the first gate drive circuit GOA1 drives the second gate line GL.

[0105] Level conversion circuits LS1 and LS2 first provide a start signal to the first gate drive circuit in the Mth frame, and first provide a start signal to the second gate drive circuit in the M+1th frame.

[0106] In some embodiments, the plurality of gate lines GL, GL1, GL2 are divided into a first group of gate lines and a second group of gate lines;

[0107] The gating control circuit 1 includes:

[0108] Multiple first switching elements T1 are connected one-to-one with gate lines GL, GL1, and GL2 in the first group of gate lines, and are connected to the first gate drive circuit GOA1;

[0109] The first gating control line L1 is used to control the on / off state of the plurality of first switching elements T1;

[0110] Multiple second switching elements T2 are connected one-to-one with gate lines GL, GL1, and GL2 in the second group of gate lines, and are connected to the first gate drive circuit GOA1;

[0111] The second gating control line L2 is used to control the on / off state of the plurality of second switching elements T2;

[0112] Multiple third switching elements T3 are connected one-to-one with the gate lines GL, GL1, and GL2 in the first group of gate lines, and are connected to the second gate drive circuit GOA2;

[0113] The third gating control line L3 is used to control the on / off state of the plurality of third switching elements T3;

[0114] Multiple fourth switching elements T4 are connected one-to-one with gate lines GL, GL1, and GL2 in the second group of gate lines, and are connected to the second gate drive circuit GOA2;

[0115] The fourth gating control line L4 is used to control the on / off state of the plurality of fourth switching elements T4.

[0116] Specifically, in Figure 1 , Figure 7 , Figure 9 and Figure 10 In the embodiment shown, the first group of gate lines are odd-numbered gate lines, and the second group of gate lines are even-numbered gate lines.

[0117] It should be noted that in this embodiment, the increment direction of the gate line number is the same as the scanning direction of the gate line, and the number of the first gate line is 1.

[0118] Specifically, the first switching element T1, the second switching element T2, the third switching element T3, and the fourth switching element T4 have the same polarity in the on state of the control voltage. The first gating control line L1 and the fourth gating control line L4 are electrically connected, and the second gating control line L2 and the third gating control line L3 are electrically connected.

[0119] In some other embodiments, the first gating control line L1 and the fourth gating control line L4 are two independent lines, and the second gating control line L2 and the third gating control line L3 are two independent lines.

[0120] In the above embodiments, the first switching element T1, the second switching element T2, the third switching element T3, and the fourth switching element T4 are all NMOSFETs.

[0121] In some other embodiments, the first switching element T1 and the second switching element T2 have different polarities and are both connected to the same gating control line, and the third switching element T3 and the fourth switching element T4 have different polarities and are both connected to the same gating control line.

[0122] Based on the same inventive concept, embodiments of this disclosure also provide a display panel, including the aforementioned display substrate.

[0123] In some embodiments, the display panel is a liquid crystal display panel or an electronic paper display panel.

[0124] Based on the same inventive concept, embodiments of this disclosure also provide a display device, including the aforementioned display panel, and including a timing controller and a source driving circuit. The timing controller is used to provide a gating control signal to the gating control circuit so that the first gate driving circuit and the second gate driving circuit alternately drive the same gate line. The source driving circuit is used to provide a pixel voltage to the pixel circuit, and the pixel voltage is a frame flip mode.

[0125] Specifically, the timing controller provides a gating control signal to the gating control circuit via a level shifter. The aforementioned display defects are more pronounced in frame-flipping mode.

[0126] In some embodiments, combined with Figure 4 , Figure 1 and Figure 7 When the second to the N+1th first shift register units are connected to a second gate line, the time when the source drive circuit Driver writes a frame of display data to the display substrate P is delayed by the display data writing time required by a row of pixel circuits. For example, for a dual gate (two gate lines are set between adjacent pixel rows) display product with a resolution of 1920 (horizontal resolution) * 1080 (vertical resolution) and a refresh rate of 60Hz, the display data writing time required by a row of pixel circuits is 1 / 60 / 1080 / 2 seconds.

[0127] Combination Figure 4 , Figure 9 and Figure 10 When the second to the N+1th first shift register units drive the pixel circuits located in even-numbered rows, the time when the source drive circuit writes a frame of display data to the display substrate is delayed by the display data writing time required by a row of pixel circuits. For example, for a single-gate (one gate line between adjacent pixel rows) display product with a resolution of 1920 (horizontal resolution) * 1080 (vertical resolution) and a refresh rate of 60Hz, the display data writing time required by a row of pixel circuits is 1 / 60 / 1080 seconds.

[0128] This design ensures that the timing provided to the first gate drive circuit GOA1 and the second gate drive circuit GOA2 remains constant, requiring only adjustment of the writing time of the display data for the first row of pixel circuits.

[0129] Specifically, a display device can be any product or component with display functionality, such as a display module, mobile phone, laptop computer, monitor, tablet computer, television, navigator, or various human-computer interaction terminals.

[0130] The various embodiments in this disclosure are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0131] The scope of protection of this disclosure is not limited to the embodiments described above. Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its scope and spirit. If such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, then the intent of this disclosure also includes such modifications and variations.

Claims

1. A display substrate, characterized by, The display substrate comprises: a plurality of pixel circuits, each of which is arranged along a first direction, and any two of which are arranged along a second direction intersecting the first direction; a first gate drive circuit and a second gate drive circuit, which are respectively arranged on both sides of the plurality of pixel circuits along the first direction; the first gate drive circuit and the second gate drive circuit are driving circuits of the same structure; a plurality of gate lines, and a gate control circuit, two ends of each of the gate lines being connected to the first gate drive circuit and the second gate drive circuit through the gate control circuit, the gate control circuit being configured to alternately drive the same gate line by the first gate drive circuit and the second gate drive circuit; for the same gate line, the first gate drive circuit is configured to drive in an Mth frame period, and the second gate drive circuit is configured to drive in an (M+1)th frame period, M being a positive integer; the alternately driving of the gate control circuit causes each pixel circuit on the same gate line to alternately be at a near end and a far end of the first gate drive circuit and the second gate drive circuit in consecutive frame periods, so that the display state of the pixels at both ends of the gate line is integrated by the human visual persistence effect when displaying a static picture, and the display uniformity is improved; the plurality of gate lines are divided into first gate lines and second gate lines; the gate control circuit comprises: a plurality of first switch elements, each of which is connected to a corresponding one of the first gate lines and connected to the first gate drive circuit; a first gate control line configured to control the on-off state of the plurality of first switch elements; a plurality of second switch elements, each of which is connected to a corresponding one of the second gate lines and connected to the first gate drive circuit; a second gate control line configured to control the on-off state of the plurality of second switch elements; a plurality of third switch elements, each of which is connected to a corresponding one of the first gate lines and connected to the second gate drive circuit; a third gate control line configured to control the on-off state of the plurality of third switch elements; a plurality of fourth switch elements, each of which is connected to a corresponding one of the second gate lines and connected to the second gate drive circuit; a fourth gate control line configured to control the on-off state of the plurality of fourth switch elements.

2. The display substrate of claim 1, wherein: the first gate drive circuit comprises a plurality of first shift register units, the second gate drive circuit comprises a plurality of second shift register units, the plurality of first gate lines are respectively connected to part of the pixel circuits in a row of pixel circuits, and the plurality of second gate lines are respectively connected to the remaining pixel circuits in the row of pixel circuits; the plurality of first shift register units are controlled by the gate control circuit to switch between a first state and a second state, the first state comprising the first to Nth first shift register units being respectively connected to a first gate line, and the second state comprising the second to (N+1)th first shift register units being respectively connected to a second gate line. The plurality of second shift register units are controlled by the gate control circuit to switch between a third state and a fourth state, the third state including the first to Nth second shift register units being connected to a second gate line respectively, and the fourth state including the first to Nth second shift register units being connected to a first gate line respectively, N being a positive integer. 3.The display substrate of claim 1, wherein, The first gate driving circuit includes a plurality of first shift register units, and the second gate driving circuit includes a plurality of second shift register units, each of the plurality of first gate lines being connected to a part of pixel circuits in a row of pixel circuits, and each of the plurality of second gate lines being connected to the rest of pixel circuits in the row of pixel circuits. The plurality of first shift register units are controlled by the gate control circuit to switch between a first state and a second state, the first state including the first to Nth first shift register units being connected to a first gate line respectively, and the second state including the first to Nth first shift register units being connected to a second gate line respectively. The plurality of second shift register units are controlled by the gate control circuit to switch between a third state and a fourth state, the third state including the first to Nth second shift register units being connected to a second gate line respectively, and the fourth state including the first to Nth second shift register units being connected to a first gate line respectively, N being a positive integer.

4. The display substrate of claim 1, wherein, The first gate driving circuit includes a plurality of first shift register units, and the second gate driving circuit includes a plurality of second shift register units, each gate line being connected to a row of pixel circuits. The plurality of first shift register units are controlled by the gate control circuit to switch between a first state and a second state, the first state including the first to Nth first shift register units being connected to an odd-numbered gate line respectively, and the second state including the second to N+1th first shift register units being connected to an even-numbered gate line respectively. The plurality of second shift register units are controlled by the gate control circuit to switch between a third state and a fourth state, the third state including the first to Nth second shift register units being connected to an even-numbered gate line respectively, and the fourth state including the first to Nth second shift register units being connected to an odd-numbered gate line respectively, N being a positive integer.

5. The display substrate of claim 1, wherein, The first gate driving circuit includes a plurality of first shift register units, and the second gate driving circuit includes a plurality of second shift register units, each gate line being connected to a row of pixel circuits. The plurality of first shift register units are controlled by the gate control circuit to switch between a first state and a second state, the first state including the first to Nth first shift register units being connected to an odd-numbered gate line respectively, and the second state including the first to Nth first shift register units being connected to an even-numbered gate line respectively. The plurality of second shift register units are controlled by the gate control circuit to switch between a third state and a fourth state, the third state including the first to Nth second shift register units respectively connected to even-numbered gate lines, and the fourth state including the first to Nth second shift register units respectively connected to odd-numbered gate lines, N being a positive integer. 6.The display substrate of claim 1, wherein, The first switch element, the second switch element, the third switch element and the fourth switch element have the same polarity of control voltage in the on state, the first gate control line and the fourth gate control line are electrically connected, and the second gate control line and the third gate control line are electrically connected.

7. A display panel, characterized by comprising: The display substrate comprises the display substrate according to any one of claims 1 to 6.

8. The display panel of claim 7, wherein, The display panel is a liquid crystal display panel or an electronic paper display panel.

9. A display device, characterized by comprising: The display panel according to claim 7 or 8, and a timing controller and a source driving circuit, the timing controller being configured to provide a gate control signal to the gate control circuit to enable the first gate driving circuit and the second gate driving circuit to alternately drive the same gate line, and the source driving circuit being configured to provide a pixel voltage to the pixel circuit, the pixel voltage including a pixel voltage in a frame inversion mode.

10. The display device according to claim 9, wherein The display substrate according to claim 2, when the second to N+1th first shift register units are respectively connected to a second gate line, the source driving circuit writes a frame of display data to the display substrate with a delay of a display data writing time required by a row of pixel circuits.

11. The display device according to claim 9, wherein The display substrate according to claim 4, when the second to N+1th first shift register units drive the pixel circuits in even-numbered rows, the source driving circuit writes a frame of display data to the display substrate with a delay of a display data writing time required by a row of pixel circuits.

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