A driving control circuit, a driving method, and a display device for a display panel

Abstract

The present application discloses a driving control circuit, a driving method and a display device for a display panel. The driving control circuit includes: a GOA circuit, an EM signal generation circuit, and a pixel circuit. The GOA circuit includes a first control circuit and a second control circuit. Among them, the first control circuit and the second control circuit respectively receive a start signal and a shutdown signal sent by an external driving circuit, so as to be able to generate a first control signal and a second control signal correspondingly. The EM signal generation circuit receives the first control signal sent by the first control circuit or the second control signal sent by the second control circuit to determine the level state of the EM signal output correspondingly, and the pixel circuit receives the EM signal sent by the EM signal generation circuit to be able to drive the light-emitting unit to emit light or make the light-emitting unit not emit light based on the level state of the EM signal. By the above method, the present application can realize variable adjustment of the square-wave width of the EM signal of each display sub-frame, so as to ensure a better display effect.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular, to a driving control circuit, a driving method, and a display device for a display panel. Background Art

[0002] Nowadays, with the continuous development of display technologies, the functions of display panels have become more and more abundant and diverse. Among them, a complete driving circuit of a display panel not only requires input and output of digital signals, but also requires output of various analog signals.

[0003] However, in the existing digital-to-analog hybrid driving timing, the display of each display frame is specifically realized by combining multiple display sub-frames and controlling different emission times to achieve gray levels, that is, the emission times of each display sub-frame are different. Therefore, in a display frame, it is necessary to output EM (Emission) signals with multiple different widths of square wave signals to control the conduction duration of corresponding TFTs (Thin Film Transistors). The width of the EM square wave signal output by the existing GOA (Gate driver On Array) circuit is matched with the start signal STV (Scan Driver Start Pulse), and the start signal STV is provided by an external driving IC (Integrated Circuit). However, currently, the output square wave signal of the driving IC can only correspond to one square wave width and cannot generate multiple ones.

[0004] Therefore, the existing GOA circuit cannot output an EM driving signal with a width change that varies with sub-frames, and thus cannot ensure a better display effect. Summary of the Invention

[0005] The main technical problem to be solved by the present application is to provide a driving control circuit, a driving method, and a display device for a display panel, which can solve the problem that the driving circuit of the display panel in the prior art cannot output an EM driving signal with a width change that varies with display sub-frames, and thus cannot ensure a better display effect.

[0006] To solve the above technical problems, a technical solution adopted in this application is: to provide a driving and control circuit for a display panel, wherein the driving and control circuit includes: a GOA circuit, including a first control circuit and a second control circuit. The first control circuit receives a start signal sent by an external driving circuit to generate a first control signal, and the second control circuit receives a turn-off signal sent by the driving circuit to generate a second control signal; an EM signal generation circuit, coupled to the first control circuit and the second control circuit. The EM signal generation circuit receives the first control signal sent by the first control circuit or the second control signal sent by the second control circuit to determine the level state of the corresponding output EM signal; a pixel circuit, which includes a light-emitting unit. The light-emitting unit is coupled to the EM signal generation circuit, and the light-emitting unit receives the EM signal sent by the EM signal generation circuit to drive the light-emitting unit to emit light or not emit light based on the level state of the EM signal.

[0007] Wherein, the pixel circuit further includes an energy storage sub-circuit, which is coupled to the first control circuit. When the first control circuit receives the start signal sent by the driving circuit, it generates an initial voltage signal and sends the initial voltage signal to the energy storage sub-circuit to write a grayscale voltage in the energy storage sub-circuit.

[0008] Wherein, the first control circuit receives a first clock signal and a second clock signal sent by the driving circuit to, when receiving the start signal, sequentially generate an initial voltage signal and a first control signal based on the first clock signal and the second clock signal; the second control circuit receives the first clock signal and the second clock signal sent by the driving circuit to, when receiving the turn-off signal, generate a second control signal based on the first clock signal and the second clock signal.

[0009] Wherein, the EM signal generation circuit includes a first switching tube, a second switching tube and a first capacitor. The first end of the first switching tube is coupled to the first control circuit, the second end of the first switching tube is coupled to the high-level output terminal of the external power supply circuit, and the third end of the first switching tube is coupled to the third end of the second switching tube and the first end of the first capacitor to form an output terminal for the EM signal. The first end of the second switching tube is coupled to the second control circuit, the second end of the second switching tube is coupled to the low-level output terminal of the power supply circuit, and the second end of the first capacitor is coupled to the low-level output terminal of the power supply circuit.

[0010] Among them, the EM signal generation circuit includes a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, and a second capacitor. The first end of the third switching transistor is coupled to the first control circuit, the second end of the third switching transistor is coupled to the high-level output end of the external power supply circuit, and the third end of the third switching transistor is coupled to the second end of the fourth switching transistor, the first end of the first capacitor, the first end of the fifth switching transistor, and the first end of the sixth switching transistor. The first end of the fourth switching transistor is coupled to the second control circuit, the third end of the fourth switching transistor is coupled to the low-level output end of the power supply circuit, the second end of the first capacitor is coupled to the low-level output end of the power supply circuit, the second end of the fifth switching transistor is coupled to the high-level output end of the power supply circuit, the third end of the fifth switching transistor is coupled to the second end of the sixth switching transistor to form an output end for the EM signal, and the third end of the sixth switching transistor is coupled to the low-level output end of the power supply circuit.

[0011] Among them, when the EM signal generation circuit receives the first control signal sent by the first control circuit, the third switching transistor is turned on, the fourth switching transistor is turned off, the fifth switching transistor is turned on, and the sixth switching transistor is turned on. The third switching transistor receives the high-level signal sent by the power supply circuit to charge the second capacitor to a high level, and sends a low-level EM signal to the pixel circuit through the output end of the EM signal formed by the fifth switching transistor and the sixth switching transistor to drive the light-emitting unit to emit light. When the EM signal generation circuit receives the second control signal sent by the second control circuit, the third switching transistor is turned off, the fourth switching transistor is turned on, the fifth switching transistor is turned on, and the sixth switching transistor is turned on. The third switching transistor receives the low-level signal sent by the power supply circuit to discharge the second capacitor to a low level, and sends a high-level EM signal to the pixel circuit through the output end of the EM signal to make the light-emitting unit not emit light.

[0012] Among them, the EM signal generation circuit includes a first NAND gate circuit, a second NAND gate circuit, a seventh switching transistor, and an eighth switching transistor. The first end of the first NAND gate circuit is coupled to the first control circuit, the second end of the first NAND gate circuit is coupled to the third end of the second NAND gate circuit, and the third end of the first NAND gate circuit is coupled to the second end of the second NAND gate circuit, the first end of the seventh switching transistor, and the first end of the eighth switching transistor. The first end of the second NAND gate circuit is coupled to the second control circuit, the second end of the seventh switching transistor is coupled to the high-level output end of the external power supply circuit, the third end of the seventh switching transistor is coupled to the second end of the eighth switching transistor to form an output end for the EM signal, and the third end of the eighth switching transistor is coupled to the low-level output end of the power supply circuit.

[0013] Among them, when the EM signal generation circuit receives the first control signal sent by the first control circuit, the output end of the EM signal sends a low-level EM signal to the pixel circuit to drive the light-emitting unit to emit light. When the EM signal generation circuit receives the second control signal sent by the second control circuit, the output end of the EM signal sends a high-level EM signal to the pixel circuit to make the light-emitting unit not emit light.

[0014] To solve the above technical problems, another technical solution adopted in this application is: to provide a driving method for a display panel, wherein the driving method includes: receiving a start signal or a shutdown signal sent by an external driving circuit to correspondingly generate a first control signal or a second control signal; determining the level state of the EM signal sent to the light-emitting unit of the display panel according to the first control signal or the second control signal, so as to drive the light-emitting unit to emit light or make the light-emitting unit not emit light based on the level state of the EM signal.

[0015] To solve the above technical problems, another technical solution adopted in this application is: to provide a display device, wherein the display device includes a display panel and a driving and controlling circuit according to any one of claims 1-8. The display panel includes a driving circuit and a light-emitting unit. The driving and controlling circuit is coupled to the driving circuit and the light-emitting unit and is used to receive a start signal or a shutdown signal sent by the driving circuit to drive the light-emitting unit to emit light or make the light-emitting unit not emit light.

[0016] The beneficial effect of this application is: different from the prior art, the driving and controlling circuit provided in this application includes: a GOA circuit, an EM signal generating circuit, and a pixel circuit, and the GOA circuit further includes a first control circuit and a second control circuit; wherein, the first control circuit and the second control circuit are respectively used to receive a start signal and a shutdown signal sent by an external driving circuit to be able to correspondingly generate a first control signal and a second control signal; and when the EM signal generating circuit receives the first control signal sent by the first control circuit or the second control signal sent by the second control circuit, it can determine the level state of the EM signal output correspondingly and send the EM signal with the corresponding level state to the pixel circuit, so that the pixel circuit can drive the light-emitting unit to emit light or make the light-emitting unit not emit light based on the level state of the EM signal, thereby being able to realize variable adjustment of the conduction width of the EM signal corresponding to each display sub-frame by adjusting the output duration of the first control signal and the second control signal to ensure a better display effect. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings, where:

[0018] Figure 1 is a timing diagram of control signals of the driving method of the display panel in the prior art;

[0019] Figure 2 is a schematic structural diagram of the pixel circuit of the display panel;

[0020] Figure 3 is a schematic structural diagram of the first embodiment of the driving control circuit of the present application;

[0021] Figure 4 is adopted Figure 3 in the driving control circuit for driving and controlling the pixel circuit of the display panel;

[0022] Figure 5 is a schematic structural diagram of the second embodiment of the driving control circuit of the present application;

[0023] Figure 6 is a schematic structural diagram of the third embodiment of the driving control circuit of the present application;

[0024] Figure 7 is a schematic structural diagram of the fourth embodiment of the driving control circuit of the present application;

[0025] Figure 8 is a detailed schematic structural diagram of the NAND gate circuit;

[0026] Figure 9 is a schematic flow diagram of an embodiment of the driving method of the display panel of the present application;

[0027] Figure 10 is a schematic structural diagram of an embodiment of the display device of the present application. Detailed Description of the Invention

[0028] The inventors have found through long-term research that with the continuous development of display technology, the functions of display panels have become more and more rich and diverse. A complete set of driving circuits for display panels not only requires the input and output of digital signals, but also the output of various analog signals.

[0029] Among them, as Figure 1 shown, Figure 1 is a control signal timing diagram of the driving method of the display panel in the prior art. Currently, in the better digital-to-analog hybrid driving working timing, in each display sub-frame, after writing pixel data, the TFT needs to be controlled to turn on through the EM signal to ensure that the driving current flows through the path of the LED (light-emitting diode) to emit light. Then, at the end of the light-emitting time of this sub-frame, the TFT is controlled to turn off through the EM signal to cut off the current flowing through the LED, so that the LED does not emit light. That is, by controlling the EM on time, the gray scale of the digital driving part of the sub-frame is realized. And the magnitude of the LED current in the display sub-frame, that is, the light-emitting brightness of the analog driving part, is controlled by the analog voltage written to the gate of the driving TFT. And the driving pixel is a 7T1C circuit with a driving TFT threshold voltage compensation function.

[0030] It should be noted that, asFigure 2 As shown Figure 2 is a schematic structural diagram of a pixel circuit of a display panel. The pixel circuit specifically includes a 7T1C circuit, and the 7T1C circuit refers to a functional circuit including 7 thin-film transistors (T11-T17) and 1 capacitor (C11), so as to be able to correspondingly assist in driving the LED in the pixel circuit to emit light.

[0031] And in the above-mentioned digital-analog hybrid driving timing, each display sub-frame uses a combination of multiple sub-frames for display, so that different emission times are used to implement gray levels, that is, the emission times of each display sub-frame are different. Therefore, it is required that in one display frame, the EM signal needs to output square wave signals of multiple different widths, while the width of the square wave signal output by the conventional GOA is matched with the start signal STV, and the start signal STV is provided by an external driving IC. Currently, the output square wave signal of the driving IC can only have a fixed square wave width and cannot generate square wave signals of multiple widths. Therefore, the conventional GOA cannot output an EM driving signal whose width changes corresponding to the change of the display sub-frame.

[0032] In order to realize the variable adjustment of the conduction width of the EM square wave of each sub-frame to ensure a better display effect, the present application provides a driving circuit, a driving method and a display device for a display panel. The following will further describe the present application in detail with reference to the drawings and embodiments. It should be particularly noted that the following embodiments are only used to illustrate the present application, but do not limit the scope of the present application. Similarly, the following embodiments are only partial embodiments of the present application rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0033] Referring to "embodiment" in the present application means that the specific features, structures or characteristics described in combination with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0034] Please refer to Figure 3 , wherein, Figure 3 is a schematic structural diagram of the first embodiment of the driving control circuit of the present application. In this embodiment, the driving control circuit 10 includes: a GOA circuit 11, an EM signal generation circuit 12, and a pixel circuit 2, and the GOA circuit 11 further includes a first control circuit 111 and a second control circuit 112.

[0035] It should be noted that in the field of display technology, the pixel circuit 2 is usually driven by the GOA circuit to work. Among them, the GOA circuit 11 is specifically formed by cascading multiple GOA unit circuits, and each GOA unit circuit drives at least one row of pixels.

[0036] The GOA unit circuit can provide two types of signals:

[0037] (1) Scan (SCAN) signal. The scan signal is mainly used to turn on the thin-film transistors of the pixels in that row during a certain period of time, so as to input data signals to the pixels in that row and store electrical energy in the capacitors in the pixels in that row. The scan signal or its shifted signal can also be used to initialize the potential of the capacitor, or to initialize the anode of any reasonable light-emitting unit such as a micro LED (micrometer light-emitting diode), an LED, or an OLED (Organic Light-Emitting Diode).

[0038] (2) Emission (EM) signal. The EM signal is used to correctly read the data signal when the scan signal turns on the thin-film transistors on the row of pixels, so that the light-emitting unit emits light, and to prevent the light-emitting unit from emitting light during the process of reading data and initializing.

[0039] It can be seen from this that the traditional GOA unit circuit usually includes two separate parts, the SCAN circuit part and the EM circuit part, to provide the SCAN signal and the EM signal respectively.

[0040] In this embodiment, the GOA circuit 11 further includes a first control circuit 111 and a second control circuit 112. The first control circuit 111 is used to receive a start signal sent by an external drive circuit, that is, the drive IC of the corresponding display panel, to generate a first control signal. For example, it receives a start signal STV sent by the external drive circuit to adjust the level state to a low level or a high level at the corresponding moment, and outputs a first control signal of a low level or a high level correspondingly. The second control circuit 112 is used to receive the shutdown signal sent by the drive circuit to be able to generate a second control signal correspondingly.

[0041] Further, the EM signal generation circuit 12 is coupled to the first control circuit 111 and the second control circuit 112, so as to be able to receive the first control signal sent by the first control circuit 111 or the second control signal sent by the second control circuit 112 correspondingly, and thus be able to determine the level state of the EM signal output correspondingly based on the first control signal or the second control signal received. For example, when receiving the first control signal, an EM signal with a low level is output correspondingly, and when receiving the second control signal, an EM signal with a high level is output correspondingly; or, when receiving the first control signal, an EM signal with a high level is output correspondingly, and when receiving the second control signal, an EM signal with a low level is output correspondingly.

[0042] Among them, the pixel circuit 2 specifically includes a light-emitting unit, for example, any reasonable light-emitting device or light-emitting circuit such as a micro LED, an LED, or an OLED. The light-emitting unit is coupled to the EM signal generation circuit 12, so as to be able to receive the EM signal sent by the EM signal generation circuit 12, and further be able to drive the light-emitting unit to emit light or make the light-emitting unit not emit light based on the level state of the EM signal. For example, when the received EM signal is at a low level, the light-emitting unit is driven to emit light, and when the EM signal is at a high level, the light-emitting unit is driven not to emit light; or, when the received EM signal is at a high level, the light-emitting unit is driven to emit light, and when the EM signal is at a low level, the light-emitting unit is driven not to emit light.

[0043] In one embodiment, the pixel circuit 2 further includes an energy storage sub-circuit, for example, a circuit composed of a capacitor or any other reasonable energy storage device, and the energy storage sub-circuit is coupled to the first control circuit 111, so as to generate an initial voltage signal when the first control circuit 111 receives the start signal sent by the driving circuit, and then send the initial voltage signal to the energy storage sub-circuit to write a grayscale voltage in the energy storage sub-circuit, so as to be able to assist in driving the light-emitting unit to emit light subsequently.

[0044] In a specific embodiment, the pixel circuit 2 may specifically be Figure 2 the pixel circuit 2 including 7T1C as shown, and the energy storage sub-circuit is the capacitor C therein. When the first control circuit 111 of the GOA circuit 11 receives the start signal STV sent by the driving circuit, it can correspondingly output an initial voltage signal OUT1 to the capacitor C to write the grayscale voltage Vinit. Among them, 7T1C has a driving TFT threshold voltage compensation function, so as to be able to drive the light-emitting unit LED to emit light or make the LED not emit light correspondingly when receiving the corresponding EM signal.

[0045] In one embodiment, as Figure 4 shown, Figure 4 it is adopted Figure 3The timing diagram of the control signal for the driving control circuit 10 in [device] to drive and control the pixel circuit 2 of the display panel. Among them, the first control circuit 111 can also receive the first clock signal CK and the second clock signal CKB sent by the driving circuit. When receiving the start signal STV sent by the external driving circuit, the driving control circuit 10 can continuously detect and scan the level state of the start signal STV based on the first clock signal CK and the second clock signal CKB, so as to sequentially generate the initial voltage signal OUT1 and the first control signal OUT2. Through the initial voltage signal OUT1, the EM signal generation circuit 12 writes the gray-scale voltage Vinit to the pixel circuit 2, and by outputting the first control signal OUT2 to the EM signal generation circuit 12, the EM signal output by the EM signal generation circuit 12 to the pixel circuit 2 is adjusted to a low level, thereby driving the light-emitting unit in the pixel circuit 2 to emit light.

[0046] And the second control circuit 112 is used to receive the first clock signal CK and the second clock signal CKB sent by the driving circuit. When receiving the shutdown signal STVC sent by the external driving circuit, it can generate the second control signal QOUT2 based on the first clock signal CK and the second clock signal CKB. By outputting the second control signal QOUT2 to the EM signal generation circuit 12, the EM signal output by the EM signal generation circuit 12 to the pixel circuit 2 is adjusted to a high level, thereby making the light-emitting unit in the pixel circuit 2 not emit light.

[0047] The above solution does not need to input a variable-width square wave through an external driving circuit to achieve, which solves the problem that the external driving IC does not support the generation of variable-width square wave EM signals. In addition, in this application, there is no need to change the original pixel circuit 2. Only the GOA circuit 11 needs to be adjusted and an EM signal generation circuit 12 is added, so as to avoid adding 2T1C in the pixel circuit 2 to support the generation of variable-width square wave EM signals, and thus avoid the problems of insufficient layout space and complexity of the pixel circuit 2. At the same time, when adding 2T1C to the pixel circuit 2 to implement variable-width EM, there are also problems such as the capacitor cannot be made large and the state retention is unreliable. Adding the EM signal generation circuit 12 in the space of the GOA circuit 11 is relatively simpler and has less impact on the space of the GOA circuit 11.

[0048] Moreover, by designing the EM generation unit circuit 12 in the GOA circuit 11, an EM signal output with a width that can follow the sub-frame change is achieved. At the same time, the EM generation circuit is provided with an EM signal by the first control circuit 111 in the GOA circuit 11 to realize the output switching from high level to low level, and is provided with an EM signal by the second control circuit 112 in the GOA circuit 11 to realize the output switching from low level to high level. The intermediate state is maintained by a capacitor or an RS flip-flop in the EM signal generation circuit 12. Therefore, by only adjusting the input square-wave time interval of the start signal STV and the turn-off signal STVC, the square-wave width adjustment of the EM signal can be realized, without the need to input an EM signal with a variable width through an external drive circuit, solving the problem that the external drive circuit does not support the generation of a variable-width EM signal.

[0049] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of the second embodiment of the drive control circuit of the present application.

[0050] In this embodiment, the first control circuit 211 and the second control circuit 212 in the GOA circuit 21 in the drive control circuit 20 are respectively a SCAN GOA circuit 211 and a CLR GOA circuit 212. The SCAN GOA circuit 211 is specifically formed by cascading a first GOA unit circuit LS Unit1 and a second GOA unit circuit LS Unit2, and the CLR GOA circuit 212 is formed by cascading a third GOA unit circuit LS Unit3 and a fourth GOA unit circuit LS Unit4.

[0051] It can be understood that after receiving the start signal STV sent by the drive circuit of the display panel, LS Unit1 correspondingly outputs an initial voltage signal OUT1 to LS Unit2 and the pixel circuit 2 to write the grayscale voltage Vinit into the pixel circuit 2, and LS Unit2 can further output a first control signal OUT2 to the EM signal generation circuit 22 based on the first clock signal CK and the second clock signal CKB. LS Unit3 is used to receive the turn-off signal STVC sent by the drive circuit of the display panel to correspondingly output a voltage signal QOUT1 to LS Unit4, and LS Unit4 can further output a second control signal QOUT2 to the EM signal generation circuit 22 based on the first clock signal CK and the second clock signal CKB.

[0052] Further, the EM signal generation circuit 22 specifically includes a first switching transistor T1, a second switching transistor T2, and a first capacitor C1. The first end of the first switching transistor T1 is coupled to the first control circuit 211, the second end of the first switching transistor T1 is coupled to the high-level output terminal of the external power supply circuit, and the third end of the first switching transistor T1 is coupled to the third end of the second switching transistor T2 and the first end of the first capacitor C1 to form an output terminal for the EM signal. The first end of the second switching transistor T2 is coupled to the second control circuit 212, the second end of the second switching transistor T2 is coupled to the low-level output terminal of the power supply circuit, and the second end of the first capacitor C1 is coupled to the low-level output terminal of the power supply circuit.

[0053] Optionally, the first switching transistor T1 is a P-type transistor, and the second switching transistor T2 is an N-type transistor. In other embodiments, the first switching transistor T1 and the second switching transistor T2 may also be any other reasonable type of transistor, which is not limited in this application.

[0054] Specifically, please refer to Figure 4 and Figure 5 , the pixel circuit 2 is a conventional 7T1C circuit, and the SCAN GOA circuit 21 is used to provide a first control signal OUT2 for controlling the initialization and grayscale voltage writing stages of the pixel circuit 2. During the OUT1 output stage, the pixel circuit 2 is initialized: the pixel circuit 2 drives the TFT gate storage capacitor to write the initialization voltage Vinit; and during the OUT1 output stage, data is written: the grayscale voltage Vinit is written onto the TFT gate storage capacitor, and at the same time, the TFT threshold voltage is written as the Vgs voltage: Vinit + Vth, and the LED driving current is I LED = K(Vinit + Vds)2, but during this stage, the EM signal is at a high level, the TFT in the EM signal generation circuit 22 is in an off state, and the TFT and the light-emitting unit LED in the driving pixel circuit 2 have no working current and do not emit light; during the OUT2 output stage, the EM is turned on: OUT2 is at a low level, the second switching transistor T2 is turned on, and VGL (low level) is output. Then, the P-type TFT in the pixel circuit 2 is turned on, allowing I LED = K(Vinit + Vds)2 current to flow through the light-emitting unit LED in the pixel circuit 2 and enter the light-emitting stage of the sub-frame; additionally, during the OUT2 output stage, the first capacitor C1 will be charged to VGL and maintained. Then, after OUT2 output returns to a high level, the first switching transistor T1 and the second switching transistor T2 are turned off, and the VGL level of the EM signal is maintained by the first capacitor C1 until the end of the sub-frame light-emitting stage.

[0055] The CLR GOA circuit 212 is used to provide a second control signal QOUT2 for controlling the end of the sub-frame light emission of the pixel circuit 2. After the input turn-off signal STVC, the CLR GOA circuit 212 outputs the scan signals OUTC1 and OUTC2 row by row by the first clock signal CK and the second clock signal CKB. During the display sub-frame light emission stage, the turn-off signal STVC remains high all the time, then QOUT2 always outputs VGL to the EM signal generation circuit 22, and the first switch transistor T1 and the second switch transistor T2 always remain off, and the VGL corresponding to the output of the EM signal is maintained by the first capacitor C1. When the required light emission time of the sub-frame is reached, the turn-off signal STVC inputs a VGL low square wave. Then, following the first clock signal CK and the second clock signal CKB, QOUT2 of the CLR GOA circuit 212 will output a VGH low square wave signal, which turns on the first switch transistor T1, and the output EM is VGH (high level), then the P-type TFT in the pixel circuit 2 is turned off, and the cut-off current I LED =K(Vinit + Vds)2 will flow through the LED, and the display sub-frame enters the non-light emission stage. Additionally, during the output stage of the QOUT2 signal, the first capacitor C1 will be charged to VGH. Then, after the QOUT2 signal output resumes to a high level, the first switch transistor T1 and the second switch transistor T2 are turned off, and the VGH high level of the EM signal is always maintained by the first capacitor C1, and the display sub-frame will remain in the non-light emission state until the next sub-frame light emission stage.

[0056] It can be understood that the above VGL, VGH, and VDD in the pixel circuit 2 are specifically provided by the power supply circuit in the corresponding display panel, which will not be elaborated in this application.

[0057] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of the third embodiment of the driving control circuit of this application. The difference between the driving control circuit in this embodiment and the second embodiment of the driving control circuit provided in this application is that the EM signal generation circuit 32 in the driving control circuit 30 includes a third switch transistor T3, a fourth switch transistor T4, a fifth switch transistor T5, a sixth switch transistor T6, and a second capacitor C2.

[0058] Among them, the first control circuit 311 and the second control circuit 312 in the GOA circuit 31 in the driving control circuit 30 are the same as the first control circuit 211 and the second control circuit 212 in the GOA circuit 21 in the driving control circuit 20 respectively, and the first control circuit 311 and the second control circuit 312 are the SCAN GOA circuit 311 and the CLR GOA circuit 312 respectively, which will not be elaborated here.

[0059] Specifically, the first end of the third switching transistor T3 is coupled to the first control circuit 311, the second end of the third switching transistor T3 is coupled to the high-level output end of the external power supply circuit, and the third end of the third switching transistor T3 is coupled to the second end of the fourth switching transistor T4, the first end of the second capacitor C2, the first end of the fifth switching transistor T5, and the first end of the sixth switching transistor T6. The first end of the fourth switching transistor T4 is coupled to the second control circuit 312, the third end of the fourth switching transistor T4 is coupled to the low-level output end of the power supply circuit, the second end of the second capacitor C2 is coupled to the low-level output end of the power supply circuit, the second end of the fifth switching transistor T5 is coupled to the high-level output end of the power supply circuit, the third end of the fifth switching transistor T5 is coupled to the second end of the sixth switching transistor T6 to form an output end for the EM signal, and the third end of the sixth switching transistor T6 is coupled to the low-level output end of the power supply circuit.

[0060] Optionally, the third switching transistor T3 and the fifth switching transistor T5 are P-type transistors, while the fourth switching transistor T4 and the sixth switching transistor T6 are N-type transistors. In other embodiments, the third switching transistor T3, the fourth switching transistor T4, the fifth switching transistor T5, and the sixth switching transistor T6 can also be any other reasonable type of transistor, and the present application does not limit this.

[0061] Among them, when the EM signal generation circuit 32 receives the first control signal sent by the first control circuit 311, the third switching transistor T3 is turned on, the fourth switching transistor T4 is turned off, the fifth switching transistor T5 is turned on, and the sixth switching transistor T6 is turned on. The third switching transistor T3 receives the high-level signal sent by the power supply circuit to charge the second capacitor C2 to a high level, and sends a low-level EM signal to the pixel circuit 2 through the output end of the EM signal formed by the fifth switching transistor T5 and the sixth switching transistor T6 to drive the light-emitting unit to emit light. When the EM signal generation circuit 32 receives the second control signal sent by the second control circuit 312, the third switching transistor T3 is turned off, the fourth switching transistor T4 is turned on, the fifth switching transistor T5 is turned on, and the sixth switching transistor T6 is turned on. The third switching transistor T3 receives the low-level signal sent by the power supply circuit to discharge the second capacitor C2 to a low level, and sends a high-level EM signal to the pixel circuit 2 through the output end of the EM signal to make the light-emitting unit not emit light.

[0062] Specifically, please refer to Figure 4 and Figure 6, the pixel circuit 2 is a conventional 7T1C circuit, and the SCAN GOA circuit 311 is used to provide a first control signal OUT2 for controlling the initialization of the pixel circuit 2 and the grayscale voltage writing stage. Among them, after the SCAN GOA circuit 311 is input with the start signal STV, it outputs scan signals row by row under the first clock signal CK and the second clock signal CKB. Among them, in the OUT1 output stage, it is initialization: the pixel circuit 2 drives the TFT gate storage capacitor to write the initialization voltage Vinit; for example, in the OUT1 output stage, it is data writing: the grayscale voltage Vinit is written on the TFT gate storage capacitor, and at the same time, the TFT threshold voltage is written as the Vgs voltage: Vinit + Vth, and the driving current of the LED is I LED = K(Vinit + Vds)2, but in this stage, the EM signal is at a high level, and the TFT in the EM signal generation circuit 32 is in an off state, and the TFT and the light-emitting unit LED in the driving pixel circuit 2 have no working current and do not emit light; while in the OUT2 output stage, it is EM turn-on: OUT2 is at a low level, turning on the third switch tube T3, outputting VGH, and outputting the EM signal as VGL through the inverter composed of the fifth switch tube T5 and the sixth switch tube T6, then the TFT in the P-type EM signal generation circuit 32 in the pixel circuit 2 is turned on, allowing I LED = K(Vinit + Vds)2 current to flow through the LED and enter the light-emitting stage of the sub-frame; in addition, in the OUT2 output stage, the second capacitor C2 is kept charged to VGH. Then, after the OUT2 output returns to a high level, the third switch tube T3 and the fourth switch tube T4 are turned off, and the VGH level input to the inverter composed of the fifth switch tube T5 and the sixth switch tube T6 is always maintained by the second capacitor C2 until the end of the sub-frame light-emitting stage.

[0063] The CLR GOA circuit 312 is used to provide a second control signal QOUT2 for controlling the end of the sub-frame light emission of the pixel circuit 2. After the CLR GOA circuit 312 is input with the turn-off signal STVC, it outputs the scan signal OUTC and its inverted signal QOUT1 row by row under the first clock signal CK and the second clock signal CKB. In the display sub-frame light-emitting stage, the turn-off signal STVC is always kept at a high level, then QOUT2 always outputs VGL to the EM signal generation circuit 32, and the fourth switch tube T4 always remains off, ensuring the retention of VGH on the first capacitor C1. When the required light-emitting time of the sub-frame is reached, the turn-off signal STVC will input a VGL low square wave. Then, following the first clock signal CK and the second clock signal CKB, the QOUT2 of the CLR GOA circuit 312 outputs a VGH high square wave, turning on the fourth switch tube T4. Then, the input of the inverter composed of the fifth switch tube T5 and the sixth switch tube T6 is VGL, and the output EM signal is VGH. Then, the P-type TFT in the pixel circuit 2 is turned off, cutting off the current I LED=K(Vinit + Vds)2 will cause current to flow through the LED, indicating that the display sub-frame enters the non-emitting stage. Additionally, during the QOUT2 output stage, the second capacitor C2 is maintained discharged to VGL. Subsequently, after the QOUT2 output returns to a low level, the third switch transistor T3 and the fourth switch transistor T4 are turned off, and the VGL level input to the inverter formed by the fifth switch transistor T5 and the sixth switch transistor T6 is continuously maintained by the second capacitor C2. The display sub-frame will remain in the non-emitting state until the next sub-frame's emitting stage.

[0064] Please refer to Figure 7 , Figure 7 is a schematic structural diagram of the fourth embodiment of the driving control circuit of the present application. The difference between this embodiment and the second embodiment of the driving control circuit provided by the present application is that the EM signal generation circuit 42 includes a first NAND gate circuit NAND1, a second NAND gate circuit NAND2, a seventh switch transistor T7, and an eighth switch transistor T8.

[0065] Among them, the first control circuit 411 and the second control circuit 412 in the GOA circuit 41 of the driving control circuit 40 are respectively the same as the first control circuit 211 and the second control circuit 212 in the GOA circuit 21 of the driving control circuit 20, and the first control circuit 411 and the second control circuit 412 are respectively the SCAN GOA circuit 411 and the CLR GOA circuit 412, which will not be elaborated here.

[0066] Specifically, the first terminal of the first NAND gate circuit NAND1 is coupled to the first control circuit 411, the second terminal of the first NAND gate circuit NAND1 is coupled to the third terminal of the second NAND gate circuit NAND2, the third terminal of the first NAND gate circuit NAND1 is coupled to the second terminal of the second NAND gate circuit NAND2, the first terminal of the seventh switch transistor T7, and the first terminal of the eighth switch transistor T8. The first terminal of the second NAND gate circuit NAND2 is coupled to the second control circuit 212. The second terminal of the seventh switch transistor T7 is coupled to the high-level output terminal of the external power supply circuit. The third terminal of the seventh switch transistor T7 is coupled to the second terminal of the eighth switch transistor T8 to form an output terminal for the EM signal. The third terminal of the eighth switch transistor T8 is coupled to the low-level output terminal of the power supply circuit.

[0067] Optionally, the seventh switch transistor T7 is a P-type transistor, and the eighth switch transistor T8 is an N-type transistor to be able to form an inverter correspondingly. In other embodiments, the seventh switch transistor T7 and the eighth switch transistor T8 can also be any other reasonable type of transistor, and the present application does not limit this.

[0068] It should be noted that a NAND gate is a combination of an AND gate and a NOT gate. First, an AND operation is performed, and then a NOT operation. A NAND gate outputs a high level when one or more of the input terminals are at a low level; only when all inputs are at a high level, the output is at a low level. Specifically, please refer toFigure 8 , Figure 8 is a detailed structural schematic diagram of a NAND gate circuit. Specifically, the NAND gate circuit includes a ninth switching transistor Ta, a tenth switching transistor Tb, an eleventh switching transistor Tc, and a twelfth switching transistor Td, which can be connected through corresponding lines to form a NAND gate circuit. The specific electrical connection method is as shown in Figure 8 and will not be elaborated here.

[0069] Among them, when the EM signal generation circuit 42 receives the first control signal sent by the first control circuit 411, the output end of the EM signal sends a low-level EM signal to the pixel circuit 2 to drive the light-emitting unit to emit light; when the EM signal generation circuit 42 receives the second control signal sent by the second control circuit 412, the output end of the EM signal sends a high-level EM signal to the pixel circuit 2 to make the light-emitting unit not emit light.

[0070] Specifically, please refer to Figure 4 and Figure 7 . The pixel circuit 2 is a conventional 7T1C circuit. The SCAN GOA circuit 411 is used to provide the first control signal OUT2 for controlling the initialization and grayscale voltage writing stages of the pixel circuit 2. After the SCAN GOA circuit 411 is input with the start signal STV, it outputs scan signals row by row by the first clock signal CK and the second clock signal CKB. Among them, in the OUT1 output stage, it is for initialization: the pixel circuit 2 drives the TFT gate storage capacitor to write the initialization voltage Vinit; for example, in the OUT1 output stage, it is for data writing: the grayscale voltage Vinit is written on the TFT gate storage capacitor, and at the same time, the TFT threshold voltage is written as the Vgs voltage: Vinit + Vth. The LED drive current is ILED = K(Vinit + Vds)2, but in this stage, the EM signal is at a high level, and the TFT in the EM signal generation circuit 42 is in an off state, and the TFT and LED in the pixel circuit 2 have no working current and do not emit light; in the OUT2 output stage, it is for EM turn-on: OUT2 is a low-level square wave, NAND1 and NAND2 form an RS flip-flop, the SCAN input is VGL, and the output is VGH. After passing through the inverter composed of the seventh switching transistor T7 and the eighth switching transistor T8, the output EM is VGL, then the TFT in the P-type EM signal generation circuit 42 in the pixel circuit 2 is turned on, allowing LED I = K(Vinit + Vds)2 current to flow through the LED and enter the light-emitting stage of the sub-frame; in addition, after the OUT2 output returns to a high level, the RS flip-flop enters the output holding stage, and the output holds at VGL. The input of the inverter composed of the seventh switching transistor T7 and the eighth switching transistor T8 always maintains the VGH level until the end of the sub-frame light-emitting stage.

[0071] The CLR GOA circuit 412 is used to provide a second control signal QOUT2 for controlling the end of the sub-frame light emission of the pixel circuit 2. After the turn-off signal STVC is input to the CLR GOA circuit 412, the scan signal OUTC and its inverted signal QOUT1 are output row by row by the first clock signal CK and the second clock signal CKB. During the display sub-frame light emission stage, the turn-off signal STVC always maintains a high level, then QOUT2 always outputs VGL to the EM signal generation circuit 42, and the output of the RS flip-flop remains VGL. When the required light emission time of the sub-frame is reached, the turn-off signal STVC inputs a VGL low square wave. Then, following the first clock signal CK and the second clock signal CKB, QOUT2 of the CLR GOA circuit 412 outputs a VGH high square wave signal, the output of the RS flip-flop is VGL, and the output of the EM signal of the seventh switching transistor T7 and the eighth switching transistor T8 inverter is VGH. Then, the P-type TFT in the pixel circuit 2 is turned off, and the cut-off current I LED =K(Vinit + Vds)2. The current flows through the LED, and the sub-frame enters the non-light emission stage. After the output of QOUT2 returns to a low level, the RS flip-flop enters the holding state again. The VGL level input to the inverter composed of the seventh switching transistor T7 and the eighth switching transistor T8 is always held by the RS flip-flop. The display sub-frame will remain in the non-light emission state until the next sub-frame light emission stage.

[0072] Among them, through the simulation test of the third embodiment of the drive control circuit in Figure 6 , it can be known that the simulation time is: sub-frame 1(30H) + sub-frame 5(480H); the scanning conditions are: @C1 = 1pf → 1.5pf → 2.0pf → 2.5pf; VGH: 10V, VGL: -10V. It should be noted that the above @ means the experimental conditions (the same below).

[0073] The simulation results show that for the EM voltage Holding, the VGH output holding rate is 98.09%, and the VGL output holding rate is 88.29%; the VGL holding is worse than VGH due to the characteristic differences between NTFT and PTFT; for sub-frame 1, the current in the off stage is 743.573fA → 12.2212uA @ 3.112ms; the Q-point voltage is 9.9999V → 5.7818V; for sub-frame 5 (EM is driven by the EM Genertor), the current in the light emission stage is 12.6097uA → 12.2212uA @ 3.312ms; the Q-point voltage is 9.9999V → -5.2732V; the pixel P-point voltage is -0.8826V → -0.8608V @ 3.312ms; for sub-frame 5 (EM remains -10V), the current in the light emission stage is 12.736uA → 12.667uA @ 3.312ms; the decrease in the current in the light emission stage is affected by the change in the P-point voltage caused by the leakage of the pixel TFT.

[0074]

[0075] Simulation conditions, simulation time: sub-frame 5 (480H); scanning conditions: @VGL = -10V → -8V → -6V, VGH: 10V.

[0076] Simulation results: Adjusting VGL and reducing PTFT leakage current are beneficial to improving the EM voltage holding and LED current variation.

[0077]

[0078]

[0079] Among them, through the simulation test on the fourth embodiment of the driving control circuit in Figure 7 it can be known that the simulation time is sub-frame 1 (30H) + sub-frame 5 (480H); the scanning conditions are @VGH: 10V, VGL: -10V.

[0080] Simulation results: EM voltage Holding: The output holding rates of VGH and VGL are 100%; for sub-frame 1: the current in the off stage is 24.237pA → 2.127pA @ 3.112ms; for sub-frame 5: the current in the light-emitting stage is 12.704uA → 12.624uA @ 3.312ms; the voltage at pixel P is -0.9168V → -0.8865V @ 3.312ms; the decrease in the current in the light-emitting stage is affected by the change in the voltage at point P caused by the leakage current of the pixel TFT.

[0081]

[0082] It can be seen therefrom that by designing an EM generation unit circuit in the GOA circuit, an EM signal output with a width that can follow the sub-frame change can be realized. At the same time, the EM generation circuit is provided with a square wave by the first control circuit in the GOA circuit to achieve the output switching from high level to low level, and a square wave is provided by the second control circuit in the GOA circuit to achieve the output switching from low level to high level. The intermediate state is maintained by a capacitor or an RS flip-flop in the EM signal generation circuit. Therefore, only by adjusting the input square wave time interval of the start signal STV and the turn-off signal STVC, the square wave width of the EM signal can be adjusted, without the need to input a variable-width square wave EM signal through an external drive circuit, solving the problem that the external drive circuit does not support the generation of variable-width square waves. And by adding a large capacitor or an RS flip-flop in the EM signal generation circuit to maintain the output state, the feasibility and reliability are more advantageous. In addition, the added EM generation unit circuit in the GOA circuit is simple and has little impact on the space of the GOA circuit.

[0083] Please refer to Figure 9 , Figure 9It is a schematic flowchart of an embodiment of the driving method of the display panel of the present application. Specifically, it may include the following steps:

[0084] S51: Receive a start signal or a shutdown signal sent by an external driving circuit to correspondingly generate a first control signal or a second control signal.

[0085] It can be understood that the driving method in this embodiment is specifically a method of driving and controlling the light-emitting units of the display panel through a driving control circuit to enable the light-emitting units to emit light and display. The driving control circuit is coupled to the driving circuit and the light-emitting units of the display panel, and the driving control circuit is the driving control circuit 10, driving control circuit 20, driving control circuit 30, or driving control circuit 40 described in any one of the above embodiments. For details, please refer to Figures 3 - 9 and the relevant text content, which will not be elaborated here.

[0086] Specifically, the driving control circuit receives a start signal or a shutdown signal sent by an external driving circuit to be able to correspondingly generate a first control signal or a second control signal.

[0087] S52: Determine the level state of the EM signal sent to the light-emitting units of the display panel according to the first control signal or the second control signal, and drive the light-emitting units to emit light or make the light-emitting units not emit light based on the level state of the EM signal.

[0088] Furthermore, after receiving the first control signal or the second control signal, the driving control circuit can determine the level state of the EM signal sent to the light-emitting units of the display panel according to the first control signal or the second control signal, so as to further drive the light-emitting units to emit light or make the light-emitting units not emit light based on the level state of the EM signal.

[0089] Please refer to Figure 10 , Figure 10 It is a schematic structural diagram of an embodiment of the display device of the present application.

[0090] In this embodiment, the display device 60 includes a display panel 61 and a driving control circuit 62. The display panel 61 further includes a driving circuit 611 and light-emitting units 612. The driving control circuit 62 is coupled to the driving circuit 611 and the light-emitting units 612, and is used to receive a start signal or a shutdown signal sent by the driving circuit 611 to drive the light-emitting units 612 to emit light or make the light-emitting units not emit light. It should be noted that the driving control circuit 62 described in this embodiment is the driving control circuit 10, driving control circuit 20, driving control circuit 30, or driving control circuit 40 described in any one of the above embodiments. For details, please refer to Figures 3 - 9 and the relevant text content, which will not be elaborated here.

[0091] The beneficial effects of the present application are as follows: Different from the prior art, the drive control circuit provided by the present application includes: a GOA circuit, an EM signal generation circuit, and a pixel circuit, and the GOA circuit further includes a first control circuit and a second control circuit; wherein, the first control circuit and the second control circuit are respectively used to receive a start signal and a shutdown signal sent by an external drive circuit, so as to be able to correspondingly generate a first control signal and a second control signal; and when the EM signal generation circuit receives the first control signal sent by the first control circuit or the second control signal sent by the second control circuit, it can determine the level state of the EM signal corresponding to its output, and send the EM signal with the corresponding level state to the pixel circuit, so that the pixel circuit can drive the light-emitting unit to emit light or make the light-emitting unit not emit light based on the level state of the EM signal, thereby being able to realize variable adjustment of the conduction width of the EM signal corresponding to each display sub-frame by adjusting the output duration of the first control signal and the second control signal, so as to ensure a better display effect.

[0092] The above are only the embodiments of the present application, and do not limit the patent scope of the present application accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A driving and controlling circuit for a display panel, characterized in that, the driving and controlling circuit includes: A GOA circuit, including a first control circuit and a second control circuit. The first control circuit receives a start signal sent by an external driving circuit to generate a first control signal. The second control circuit receives a turn-off signal sent by the driving circuit to generate a second control signal. The first control circuit receives a first clock signal and a second clock signal sent by the driving circuit, and when receiving the start signal, sequentially generates an initial voltage signal and the first control signal based on the first clock signal and the second clock signal. The second control circuit receives the first clock signal and the second clock signal sent by the driving circuit, and when receiving the turn-off signal, generates the second control signal based on the first clock signal and the second clock signal; An EM signal generating circuit, coupled to the first control circuit and the second control circuit. The EM signal generating circuit receives the first control signal sent by the first control circuit and the second control signal sent by the second control circuit to determine the level state of the corresponding output EM signal; A pixel circuit, the pixel circuit includes a light-emitting unit. The light-emitting unit is coupled to the EM signal generating circuit. The light-emitting unit receives the EM signal sent by the EM signal generating circuit to drive the light-emitting unit to emit light or make the light-emitting unit not emit light based on the level state of the EM signal.

2. The driving and controlling circuit according to claim 1, characterized in that, the pixel circuit further includes an energy storage sub-circuit. The energy storage sub-circuit is coupled to the first control circuit. When the first control circuit receives the start signal sent by the driving circuit, it generates the initial voltage signal and sends the initial voltage signal to the energy storage sub-circuit to write a grayscale voltage in the energy storage sub-circuit.

3. The driving and controlling circuit according to claim 1, characterized in that, the EM signal generating circuit includes a first switching tube, a second switching tube and a first capacitor. The first end of the first switching tube is coupled to the first control circuit. The second end of the first switching tube is coupled to the high-level output end of an external power supply circuit. The third end of the first switching tube is coupled to the third end of the second switching tube and the first end of the first capacitor to form an output end for the EM signal. The first end of the second switching tube is coupled to the second control circuit. The second end of the second switching tube is coupled to the low-level output end of the power supply circuit. The second end of the first capacitor is coupled to the low-level output end of the power supply circuit.

4. The driving and controlling circuit according to claim 1, characterized in that, The EM signal generation circuit includes a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, and a second capacitor. The first end of the third switch transistor is coupled to the first control circuit. The second end of the third switch transistor is coupled to the high-level output terminal of the external power supply circuit. The third end of the third switch transistor is coupled to the second end of the fourth switch transistor, the first end of the second capacitor, the first end of the fifth switch transistor, and the first end of the sixth switch transistor. The first end of the fourth switch transistor is coupled to the second control circuit. The third end of the fourth switch transistor is coupled to the low-level output terminal of the power supply circuit. The second end of the second capacitor is coupled to the low-level output terminal of the power supply circuit. The second end of the fifth switch transistor is coupled to the high-level output terminal of the power supply circuit. The third end of the fifth switch transistor is coupled to the second end of the sixth switch transistor to form an output terminal for the EM signal. The third end of the sixth switch transistor is coupled to the low-level output terminal of the power supply circuit.

5. The drive control circuit according to claim 4, wherein, when the EM signal generation circuit receives the first control signal sent by the first control circuit, the third switch transistor is turned on, the fourth switch transistor is turned off, the fifth switch transistor is turned on, and the sixth switch transistor is turned on. The third switch transistor receives the high-level signal sent by the power supply circuit to charge the second capacitor to a high level, and sends a low-level EM signal to the pixel circuit through the output terminal of the EM signal formed by the fifth switch transistor and the sixth switch transistor to drive the light-emitting unit to emit light; when the EM signal generation circuit receives the second control signal sent by the second control circuit, the third switch transistor is turned off, the fourth switch transistor is turned on, the fifth switch transistor is turned on, and the sixth switch transistor is turned on. The third switch transistor receives the low-level signal sent by the power supply circuit to discharge the second capacitor to a low level, and sends a high-level EM signal to the pixel circuit through the output terminal of the EM signal to make the light-emitting unit not emit light.

6. The drive control circuit according to claim 1, wherein, the EM signal generation circuit includes a first NAND gate circuit, a second NAND gate circuit, a seventh switch transistor, and an eighth switch transistor. The first end of the first NAND gate circuit is coupled to the first control circuit. The second end of the first NAND gate circuit is coupled to the third end of the second NAND gate circuit. The third end of the first NAND gate circuit is coupled to the second end of the second NAND gate circuit, the first end of the seventh switch transistor, and the first end of the eighth switch transistor. The first end of the second NAND gate circuit is coupled to the second control circuit. The second end of the seventh switch transistor is coupled to the high-level output terminal of the external power supply circuit. The third end of the seventh switch transistor is coupled to the second end of the eighth switch transistor to form an output terminal for the EM signal. The third end of the eighth switch transistor is coupled to the low-level output terminal of the power supply circuit.

7. The drive control circuit according to claim 6, wherein, When the EM signal generation circuit receives the first control signal sent by the first control circuit, the output terminal of the EM signal sends a low-level EM signal to the pixel circuit to drive the light-emitting unit to emit light; When the EM signal generation circuit receives the second control signal sent by the second control circuit, the output terminal of the EM signal sends a high-level EM signal to the pixel circuit to make the light-emitting unit not emit light.

8. A driving method for a display panel, characterized in that, the driving method is implemented by the driving control circuit according to any one of claims 1 to 7, and the driving method includes: receiving a start signal and a shutdown signal sent by an external driving circuit to correspondingly generate a first control signal and a second control signal, including: receiving a first clock signal and a second clock signal sent by the driving circuit, and when receiving the start signal, sequentially generating an initial voltage signal and the first control signal based on the first clock signal and the second clock signal; receiving the first clock signal and the second clock signal sent by the driving circuit, and when receiving the shutdown signal, generating the second control signal based on the first clock signal and the second clock signal; determining the level state of the EM signal sent to the light-emitting unit of the display panel according to the first control signal and the second control signal, and driving the light-emitting unit to emit light or making the light-emitting unit not emit light based on the level state of the EM signal.

9. A display device, characterized in that, the display device includes a display panel and the driving control circuit according to any one of claims 1 to 7, the display panel includes a driving circuit and a light-emitting unit, and the driving control circuit is coupled to the driving circuit and the light-emitting unit for receiving the start signal and the shutdown signal sent by the driving circuit to drive the light-emitting unit to emit light or make the light-emitting unit not emit light.

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