Device and method for driving a display panel

Abstract

A device and method for driving a display panel. The display panel includes a pixel circuit (1), a gate driving circuit (2), and a source driving circuit (3). The device for driving the display panel is configured to: provide an invalid start signal to the gate driving circuit (2) and / or the light-emitting control driving circuit (4) in a first time period; provide a first power signal and a second power signal to the pixel circuit (1) in a second time period; and provide a valid start signal to the gate driving circuit (2) and / or the light-emitting control driving circuit (4) in a third time period. Such a device provides an improved power-on and / or power-off timing for the display panel, and can avoid problems such as display screen flicker or circuit short circuit caused by unstable internal circuit states of the display panel during power-on and / or power-off processes.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to display technologies, and more particularly, to an apparatus and a method for driving a display panel. Background Art

[0002] This section is only used to provide background art to facilitate a better understanding of the present disclosure. Therefore, statements in this section will be read from this perspective and do not involve an admission of what is in the prior art or what is not in the prior art.

[0003] With the development of display technologies, the circuit structure of display panels tends to be more complex.

[0004] For example, compared with a liquid crystal display (LCD) panel, an organic light-emitting diode (OLED) panel uses more thin-film transistors (TFTs) and has a more complex circuit.

[0005] A more complex circuit may lead to more potential problems. For example, during the power-on and / or power-off process of an OLED display panel, each transistor in the pixel circuit may be in an unstable state, resulting in problems such as a flickering screen and / or a short circuit in the circuit. Summary of the Invention

[0006] This summary briefly describes aspects of the present disclosure, which will be further described in the detailed description. This summary does not identify key features or essential features of the claimed subject matter, nor does it limit the scope of the claimed subject matter.

[0007] An object of the present disclosure is to provide an improved apparatus and method for driving a display panel to solve the above-mentioned problems or other problems that may occur during the power-on and / or power-off process of the display panel.

[0008] An aspect of the present disclosure provides an apparatus for driving a display panel. The display panel includes a pixel circuit, a gate driving circuit, and a source driving circuit. The apparatus for driving the display panel is configured to: provide an invalid start signal to the gate driving circuit and / or the light-emitting control driving circuit during a first time period; provide a first power signal and a second power signal to the pixel circuit during a second time period; and provide a valid start signal to the gate driving circuit and / or the light-emitting control driving circuit during a third time period.

[0009] In an embodiment of the present disclosure, during the first time period, the power supply terminal of the pixel circuit is grounded.

[0010] In an embodiment of the present disclosure, during the first time period, the source driving circuit outputs a ground signal.

[0011] In an embodiment of the present disclosure, the device for driving a display panel is configured to: in a first time period, provide a third power signal and a fourth power signal to a gate driving circuit; provide a clock signal to the gate driving circuit; and provide an invalid first start signal to the gate driving circuit.

[0012] In an embodiment of the present disclosure, the first start signal is kept invalid in the first time period and the second time period.

[0013] In an embodiment of the present disclosure, the device for driving a display panel is further configured to: in a third time period, enable a source driving circuit to provide a display data signal to a pixel circuit.

[0014] In an embodiment of the present disclosure, the display panel further includes a light emission control driving circuit for outputting a light emission control signal to the pixel circuit. The device for driving a display panel is further configured to: in the first time period, drive the light emission control driving circuit.

[0015] In an embodiment of the present disclosure, the device for driving a display panel is configured to: in the first time period, provide a third power signal and a fourth power signal to a power supply terminal of the light emission control driving circuit; provide a clock signal to the light emission control driving circuit; and provide an invalid second start signal to the light emission control driving circuit.

[0016] In an embodiment of the present disclosure, the device for driving a display panel is further configured to: in the third time period, enable the source driving circuit to provide a display data signal to the pixel circuit. In the first time period and the second time period, the first start signal provided to the source driving circuit and the second start signal provided to the light emission control driving circuit are kept invalid. In the third time period, the second start signal remains invalid before the first start signal of the gate driving circuit becomes valid.

[0017] In an embodiment of the present disclosure, in the first time period, the first start signal provided to the source driving circuit and the second start signal provided to the light emission control driving circuit are kept invalid. In the second time period, the second start signal remains invalid.

[0018] In an embodiment of the present disclosure, in the second time period, a display data signal corresponding to displaying black is provided to the pixel circuit.

[0019] In an embodiment of the present disclosure, the pixel circuit includes a driving power supply terminal and a reference power supply terminal. The device for driving a display panel is configured to: in the second time period, provide a first power signal and a second power signal to the driving power supply terminal; and supply power to the reference power supply terminal.

[0020] In an embodiment of the present disclosure, the first time period includes the duration of at least one display frame, and the second time period includes the duration of at least one display frame.

[0021] In an embodiment of the present disclosure, the first time period and the second time period do not overlap.

[0022] In an embodiment of the present disclosure, the display panel further includes a multiplexing circuit disposed between the source driver circuit and the pixel circuit. When the source driver circuit outputs a ground signal, the multiplexing circuit is turned on.

[0023] Another aspect of the present disclosure provides an apparatus for driving a display panel. The display panel includes a pixel circuit, a gate driver circuit, and a source driver circuit. The apparatus for driving the display panel is configured to: in a fourth time period, provide an invalid start signal to the gate driver circuit and / or the light emission control driver circuit; in a fifth time period, disconnect a first power signal and a second power signal provided to the pixel circuit; in a sixth time period, disconnect a third power signal and a fourth power signal provided to the gate driver circuit and / or the light emission control driver circuit.

[0024] In an embodiment of the present disclosure, in the fourth time period, an invalid start signal is provided to the light emission control driver circuit.

[0025] In an embodiment of the present disclosure, in the fourth time period, a valid start signal is provided to the gate driver circuit; and in the fourth time period, a display data signal corresponding to displaying black is provided to the pixel circuit.

[0026] In an embodiment of the present disclosure, in the fourth time period, an invalid start signal is provided to the gate driver circuit.

[0027] In an embodiment of the present disclosure, in the fifth time period, an invalid start signal is provided to the gate driver circuit and the light emission control driver circuit.

[0028] In an embodiment of the present disclosure, the pixel circuit includes a driving power supply terminal and a reference power supply terminal; wherein, in the fifth time period, the driving power supply terminal and the reference power supply terminal are grounded; wherein, in the fifth time period, the source driver circuit outputs a ground signal.

[0029] In an embodiment of the present disclosure, in the sixth time period, the power supply terminals of the gate driver circuit and / or the light emission control driver circuit are grounded.

[0030] Another aspect of the present disclosure provides an apparatus for driving a display panel. The display panel includes a pixel circuit, a gate driving circuit, and a source driving circuit. The apparatus for driving the display panel is configured to: in a first time period, provide an invalid start signal to the gate driving circuit and / or the light emission control driving circuit; in a second time period, provide a first power signal and a second power signal to the pixel circuit; in a third time period, provide a valid start signal to the gate driving circuit and / or the light emission control driving circuit; in a fourth time period, provide an invalid start signal to the gate driving circuit and / or the light emission control driving circuit; in a fifth time period, disconnect the first power signal and the second power signal provided to the pixel circuit; and in a sixth time period, disconnect the third power signal and the fourth power signal provided to the gate driving circuit and / or the light emission control driving circuit.

[0031] In an embodiment of the present disclosure, the apparatus for driving the display panel is integrated with the display panel.

[0032] Another aspect of the present disclosure further provides a method for driving a display panel using the apparatus for driving a display panel according to any one of the above embodiments.

[0033] Another aspect of the present disclosure further provides a display panel. The display panel includes: a pixel circuit, a gate driving circuit, a source driving circuit, and the apparatus for driving a display panel according to any one of the above embodiments.

[0034] According to an embodiment of the present disclosure, an improved power-on timing is provided for the display panel, which can avoid problems such as display screen flicker or circuit short circuit caused by unstable internal circuit states of the display panel during the power-on process. In addition, an improved power-off timing is provided for the display panel, which can avoid problems such as display screen flicker or circuit short circuit caused by unstable internal circuit states of the display panel during the power-off process. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0036] FIG. 1(a) is a block diagram showing the structure of an exemplary OLED display panel.

[0037] FIG. 1(b) is an exemplary block diagram of an apparatus for driving a display panel according to an embodiment of the present disclosure.

[0038] Figure 2 is an exemplary flowchart of a method for driving a display panel according to an embodiment of the present disclosure.

[0039] Figure 3 is a block diagram showing the structure of another exemplary OLED display panel.

[0040] FIG. 4(a) is a circuit diagram of an exemplary pixel unit.

[0041] FIG. 4(b) is a timing diagram of the pixel unit in FIG. 4(a) exemplarily.

[0042] FIG. 5(a) is a circuit diagram of an exemplary gate driving circuit.

[0043] FIG. 5(b) is a timing diagram of the gate driving circuit in FIG. 5(a) exemplarily.

[0044] FIG. 6(a) is a circuit diagram of an exemplary light emission control driving circuit.

[0045] FIG. 6(b) is a timing diagram of the light emission control driving circuit in FIG. 6(a) exemplarily.

[0046] FIG. 6(c) is a circuit diagram of another exemplary light emission control driving circuit.

[0047] FIG. 6(d) is a circuit diagram of another exemplary light emission control driving circuit.

[0048] FIG. 7(a) is a circuit diagram of another exemplary pixel unit.

[0049] FIG. 7(b) is a timing diagram of the pixel unit in FIG. 7(a) exemplarily.

[0050] FIG. 8(a) shows Figure 2 a flowchart of sub-steps of the method shown therein.

[0051] FIG. 8(b) shows Figure 2 a flowchart of additional steps of the method shown therein.

[0052] FIG. 8(c) shows Figure 2 a flowchart of additional steps of the method shown therein.

[0053] FIG. 8(d) is an exemplary timing diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.

[0054] Figure 9 is another exemplary timing diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.

[0055] Figure 10 is an exemplary test signal waveform diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.

[0056] Figure 11 is a block diagram showing the structure of another exemplary OLED display panel.

[0057] FIG. 12(a) is exemplary Figure 11 circuit diagram of pixel units in

[0058] FIG. 12(b) is an exemplary timing diagram of the pixel units in FIG. 12(a).

[0059] FIG. 13(a) is exemplary Figure 11 circuit diagram of an additional gate driving circuit in

[0060] FIG. 13(b) is an exemplary timing diagram of the additional gate driving circuit in FIG. 13(a).

[0061] Figure 14 is an exemplary timing diagram corresponding to a method for powering on an OLED display panel according to an embodiment of the present disclosure for Figure 11 in

[0062] Figure 15 is another exemplary flowchart showing a method for driving a display panel according to an embodiment of the present disclosure.

[0063] Figure 16 is corresponding to Figure 15 an exemplary timing diagram showing a method for driving a display panel according to an embodiment of the present disclosure as shown in

[0064] Figure 17 is corresponding to Figure 15 an exemplary test signal waveform diagram showing a method for driving a display panel according to an embodiment of the present disclosure as shown in

[0065] Figure 18 is corresponding to a method for powering off an OLED display panel according to an embodiment of the present disclosure for Figure 11 in DETAILED DESCRIPTION

[0066] To make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Terms such as "coupled" or "connected" are not limited to physical or mechanical coupling, but may include electrical coupling, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0068] FIG. 1(a) is a block diagram showing the structure of an exemplary OLED display panel.

[0069] As shown in FIG. 1(a), as a non-limiting example of a display panel, an Organic Light-Emitting Diode (OLED) display panel may include a pixel circuit 1, a gate driving circuit 2, and a source driving circuit 3. The gate driving circuit 2 and the source driving circuit 3 respectively provide a scan signal, a data signal, etc. to the pixel circuit 1. The pixel circuit 1 may include a plurality of pixel units in an array, and each pixel unit may include an OLED element.

[0070] In addition, as an optional part, depending on the specific structure of the pixel circuit, the OLED panel may further include a light emission control driving circuit 4 that outputs a light emission control signal to the pixel circuit 1. The light emission control driving circuit 4 may cooperate with the gate driving circuit 2 to drive the pixel circuit 1.

[0071] FIG. 1(b) is a block diagram showing an exemplary device for driving a display panel according to an embodiment of the present disclosure.

[0072] The device for driving a display panel in the embodiments of the present disclosure can be used to drive a display panel, and in particular, can execute the method for driving a display panel described in the embodiments of the present disclosure. For example, in the following Figure 2 、 8(a) ,8(b), 8(c), Figure 15 and so on.

[0073] As shown in FIG. 1(b), the device 5 for driving a display panel may include: a processor 501 and a memory 502. The processor 501 may be any type of processing component, such as one or more microprocessors or microcontrollers, or other digital hardware, such as a digital signal processor (DSP), application specific digital logic circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc. The memory 502 may be any type of storage component, such as a read only memory (ROM), random access memory, cache, flash memory device, optical storage device, etc.

[0074] The memory 502 may store software executed by the processor 501. When the processor 501 executes the software, it may be used to drive the display panel, especially to implement the method for driving a display panel in the embodiments of the present disclosure.

[0075] In the embodiments of the present disclosure, the device for driving a display panel may be integrated with the display panel or disposed inside the display panel. Therefore, the device may also be referred to as a driving device / module of the display panel, a power control device / module, or a power on / off device / module, etc.

[0076] Figure 2 FIG. [X] is an exemplary flowchart showing a method for driving a display panel according to an embodiment of the present disclosure.

[0077] The embodiments of the present disclosure may be applied to the OLED display panel shown in FIG. 1, as well as any other suitable display panel. Therefore, the embodiments of the present disclosure also include such display panels to which the method is applied. The display panels in the embodiments of the present disclosure may be driven by this method.

[0078] Figure 2 The method for driving a display panel shown may include: step S101, providing an invalid start signal to the gate driving circuit and / or the light emitting control driving circuit in a first time period; step S102, providing a first power signal and a second power signal to the pixel circuit in a second time period; and step S103, providing a valid start signal to the gate driving circuit and / or the light emitting control driving circuit in a third time period.

[0079] According to the embodiments of the present disclosure, during the power-on process of the display panel, operations such as driving the gate driving circuit, supplying power to the pixel circuit, and providing display data are performed in different time periods. In this way, it is possible to prevent the transistors in the pixel circuit from being driven when their states are unstable, thereby effectively preventing problems such as display screen flicker or circuit short circuit.

[0080] Note: The placeholder "" should have a specific figure number in the actual patent text. Here it is replaced with "FIG. [X]" for the sake of translation integrity. You may need to correct it according to the actual content.After completing the above power-on process, the display panel can enter the normal display process. That is, during the normal display process, the gate driver circuit periodically (for example, with a display frame as a cycle) drives the pixel circuit (to turn on or off the transistors in the pixel circuit according to a predetermined timing sequence), and the source driver periodically provides display data to the pixel circuit, so that the OLED in the pixel circuit operates corresponding to the display data of each display frame (for example, emits light with a corresponding brightness), so that the OLED display panel can display the image screen of each frame.

[0081] In an embodiment of the present disclosure, during a first time period, the power supply terminal in the pixel circuit can be grounded. In this way, the transistors in the pixel circuit can be made to be in a cut-off state more reliably, improving the anti-interference ability during the power-on process, and effectively preventing problems such as display screen flicker or circuit short circuit.

[0082] In an embodiment of the present disclosure, during a first time period, the source driver circuit can be made to output a ground signal. In this way, the pixel circuit receives the ground signal instead of the display data signal, which can further prevent interference signals during the power-on process from being input into the pixel circuit as display data, and effectively prevent problems such as display screen flicker or circuit short circuit.

[0083] In an embodiment of the present disclosure, the first time period and the second time period do not overlap. In this way, it can be ensured that after the gate driver circuit is initialized (that is, after the pixel circuit can be driven completely according to the predetermined display timing sequence), power supply and / or display data are provided to the pixel circuit. This can more effectively prevent problems such as display screen flicker or circuit short circuit.

[0084] In an embodiment of the present disclosure, the first time period includes the duration of at least one display frame, and the second time period includes the duration of at least one display frame. Considering that each circuit module such as the power supply may require a period of time to enter a stable state, in this way, it can be ensured that each circuit module enters a stable working state after the power-on process is completed, and problems such as screen flicker or circuit short circuit are avoided.

[0085] Hereinafter, in combination with an exemplary circuit structure of an exemplary OLED display panel, the method for driving a display panel described in the embodiments of the present disclosure will be further described. It should be understood that the following circuit structure is only exemplary and not for the method described in the embodiments of the present disclosure. The method for driving a display panel described in the embodiments of the present disclosure can be applied to the transformation and improvement of the following circuit structures.

[0086] Figure 3 is a block diagram showing the structure of another exemplary OLED display panel.

[0087] As shown Figure 3 in the figure, the pixel circuit 1 includes a plurality of pixel units in an array form, which can be denoted as the 1st row (Line[1]) to the y-th row (Line[y]), and the 1st column (Row[1]) to the x-th column (Row[x]). x and y are positive integers.

[0088] The OLED display panel can use a so-called line scanning operation mode. In one display frame, the gate driving circuit 2 and the light emission control driving circuit 4 sequentially scan each row of pixel units, and correspondingly, the source driving circuit 3 sequentially provides data signals to each row of pixel units being scanned. The display data signal can be represented by Source, Vdata, Data, etc. in the following parts of this article.

[0089] For example, taking the scanning of the pixel units in the 1st row (Line[1]) as an example, the gate driving circuit 2 first outputs a valid reset signal (RST[1]) so that the pixel units in the 1st row (Line[1]) are all reset. Then, the gate driving circuit 2 outputs a valid gate driving signal (GATE[1]) so that the data signal provided by the source driving circuit 3 can be written into the pixel units in the 1st row (Line[1]). This valid gate driving signal (GATE[1]) can also be used as the reset signal (RST[2]) for the pixel units in the 2nd row (Line[2]). Then, the light emission control driving circuit 4 outputs a valid light emission control signal (EM[1]) so that the OLEDs in the pixel units in the 1st row (Line[1]) operate corresponding to their respective display data (for example, generate their respective brightness). This display state can last until the end of this display frame.

[0090] The pixel units in the 2nd row (Line[2]) to the pixel units in the y-th row (Line[y]) will all be scanned in the same way.

[0091] It should be understood that an "effective" signal refers to a signal that can cause subsequent circuit elements (such as transistors) to enter a working state (such as conduction). Therefore, corresponding to different subsequent circuit elements, the specific attributes (such as amplitude) of this "effective" signal can be different. For example, for an N-type transistor, an effective signal can be a voltage signal with a relatively high level. And for a P-type transistor, an effective signal can be a voltage signal with a relatively low level. Correspondingly, an "invalid" signal refers to a signal that cannot cause subsequent circuit elements (such as transistors) to enter a working state (such as conduction), that is, it will cause subsequent circuit elements (such as transistors) to remain cut off.

[0092] In addition, in an embodiment of the present disclosure, the OLED display panel further includes a multiplexing circuit disposed between the source driver circuit and the pixel circuit. The output of the source driver circuit 3 can be coupled to the multiplexing circuit 31. Under the control of a switching signal, the display data provided by the source driver 3 can be respectively provided to pixel units in different columns via the multiplexing circuit. For example, as Figure 3 shown, signals for providing display data can be respectively provided to odd columns and even columns under the control of the switching signals MUX1 and MUX2. When MUX1 is valid, the switching elements corresponding to the pixel units in the odd columns in the multiplexing circuit 31 can be turned on, so that the output of the source driver circuit 3 is transmitted to the pixel units in the odd columns. When MUX2 is valid, the switching elements corresponding to the pixel units in the even columns in the multiplexing circuit 31 can be turned on, so that the output of the source driver circuit 3 is transmitted to the pixel units in the even columns. In this way, multiplexing of the source driver circuit 3 can be achieved, reducing the circuit elements required in the source driver circuit 3 and correspondingly reducing the occupied area, cost, etc.

[0093] In addition, during operation, the switching signals MUX1 and MUX2 can have completely opposite waveforms, that is, either provide to odd columns or even columns at the same moment, to achieve multiplexing of the output of the source driver circuit 3. Therefore, in the following description, MUX can also be used to represent multiple switching signals with such a fixed waveform relationship.

[0094] As a non-limiting example, Figure 3 the OLED display panel in Figure 3 can be, for example, an AMOLED (Active-matrix organic light-emitting diode) panel, specifically an LTPS (Low Temperature Poly-Silicon) AMOLED display panel. According to

[0095]

[0096] ​The pixel unit shown in FIG. 4(a) may include an eleventh transistor T11 to a seventeenth transistor T17, and an eleventh capacitor C11. In addition, it is described that this pixel unit is located in the Nth row.

[0097] The control electrode of the eleventh transistor T11 is used to input a reset signal Reset(N), the first electrode is coupled to a first reference power supply terminal VREFN (which may also be referred to as an initialization power supply terminal and may be at a low level), and the second electrode is coupled to the control electrode of the thirteenth transistor T13 and the first electrode of the twelfth transistor T12. The control electrode of the twelfth transistor T12 is used to input a gate driving signal Gate, and the second electrode is coupled to the second electrode of the thirteenth transistor T13 and the first electrode of the sixteenth transistor T16. The first electrode of the thirteenth transistor T13 is coupled to the first electrode of the fourteenth transistor T14 and the second electrode of the fifteenth transistor T15. The control electrode of the fourteenth transistor T14 is used to input a gate driving signal Gate, and the second electrode is used to input a display data signal Vdata. The control electrode of the fifteenth transistor T15 is used to input a light emission control signal EM, and the first electrode is coupled to a power supply terminal for inputting a first driving power supply ELVDD (i.e., provided as a first power signal) (a high level may be input). The control electrode of the sixteenth transistor T16 is used to input a light emission control signal EM, and the second electrode is coupled to the first electrode of the OLED (which may be an anode). The control electrode of the seventeenth transistor T17 is used to input a reset signal Reset(N + 1) of the pixel circuit in the next row (which may be the same as the gate driving signal Gate), the first electrode is coupled to the first reference power supply terminal VREFN, and the second electrode is coupled to the first electrode of the OLED. The second electrode of the OLED (which may be a cathode) is coupled to a power supply terminal for inputting a second driving power supply ELVSS (i.e., provided as a second power signal) (a low level may be input). The first end of the eleventh capacitor C11 is coupled to the power supply terminal for inputting the first driving power supply ELVDD, and the second end is coupled to the control electrode of the thirteenth transistor T13.

[0098] The control electrode of a transistor may be a gate, the first electrode may be either a source or a drain, and the second electrode may be the other of the source or the drain. In addition, the first electrodes of different transistors may be of different types, and the second electrodes may be of different types.

[0099] As shown in FIG. 4(b), during time periods t1 and t2, the light emission control signal remains invalid (invalid means that this signal cannot turn on the transistor, or in other words, makes the transistor turn off). During time period t1, the reset signal Reset(N) is valid (valid means that this signal can turn on the transistor), causing the voltage of the corresponding node in the corresponding pixel circuit to be reset, or initialized, or set to a reference voltage. During time period t2, the gate driving signal Gate is valid, causing the data signal Data (i.e., Vdata) to be written. After time period t3, the light emission control signal is valid, and the reset signal Reset(N) and the gate driving signal Gate are invalid. The OLED operates corresponding to the data signal Data (for example, emits light at a predetermined brightness).

[0100] As shown in FIG. 4(b), the high-level duration of the light emission control signal EM is greater than the time period 2H shown in the figure and encloses the low levels of the reset signal Reset and the gate driving signal Gate within time periods t1 and t2.

[0101] It should be understood that the reset signal Reset(N) can be the gate driving signal Gate(N - 1) of the previous row.

[0102] FIG. 5(a) is a circuit diagram of an exemplary gate driving circuit. FIG. 5(b) is a timing diagram of the gate driving circuit in FIG. 5(a).

[0103] The gate driving circuit can be composed of cascaded shift register units shown in FIG. 5(a). That is, the gate driving circuit operates in the manner of a shift register, and the shift register units at each stage sequentially output the above-mentioned reset signal and gate driving signal (which can also be collectively referred to as row scanning signals) to the pixel circuit.

[0104] As shown in FIG. 5(a), as a non-limiting example, such a shift register unit can include: the twenty-first transistor T21 to the twenty-eighth transistor T28, and the twenty-first capacitor C21 to the twenty-second capacitor C22.

[0105] The control electrode of the twenty-first transistor T21 is used to input a first clock signal GCK, the first electrode is used to input a first start signal GSTV, and the second electrode is coupled to the control electrode of the twenty-second transistor T22, the second electrode of the twenty-seventh transistor T27, and the first electrode of the twenty-eighth transistor T28. The first electrode of the twenty-second transistor T22 is used to input the first clock signal GCK, and the second electrode is coupled to the second electrode of the twenty-third transistor T23, the control electrode of the twenty-fourth transistor T24, and the control electrode of the twenty-sixth transistor T26. The control electrode of the twenty-third transistor T23 is used to input the first clock signal GCK, and the first electrode is coupled to a power supply terminal for inputting a low level VL (i.e., provided as a fourth power supply signal). The first electrode of the twenty-fourth transistor T24 is coupled to a power supply terminal for inputting a high level VH (i.e., provided as a third power supply signal), the second electrode is coupled to the first electrode of the twenty-fifth transistor T25, and is used to output a gate driving signal GO. The control electrode of the twenty-fifth transistor T25 is coupled to the second electrode of the twenty-eighth transistor T28, and the second electrode is used to input a second clock signal GCB. The first electrode of the twenty-sixth transistor T26 is coupled to a power supply terminal for inputting the high level VH, and the second electrode is coupled to the first electrode of the twenty-seventh transistor T27. The control electrode of the twenty-seventh transistor T27 is used to input the second clock signal GCB. The control electrode of the twenty-eighth transistor T28 is coupled to a power supply terminal for inputting the low level VL.

[0106] The twenty-first capacitor C21 is coupled between the control electrode and the first electrode of the twenty-fourth transistor T24. The twenty-second capacitor C22 is coupled between the control electrode and the first electrode of the twenty-fifth transistor T25.

[0107] For example, the high level VH may be a positive voltage of a predetermined amplitude, and the low level VL may be a negative voltage of a predetermined amplitude.

[0108] As shown in FIG. 5(b), taking the case where the shift register unit is located in the first stage (e.g., corresponding to the first row of pixel units) as an example, in the time period t1, the first start signal GSTV is valid, so that the shift register unit corresponding to the first row of pixel units starts to work. The states of the first start signal GSTV, the first clock signal GCK, and the second clock signal GCB change according to a predetermined timing, so that in the time period t2, a valid gate driving signal GO1 is output for the first row of pixel units. This gate driving signal GO1 also serves as a start signal for the next-stage shift register unit (e.g., corresponding to the second row of pixel units), so that the next-stage shift register unit outputs a valid gate driving signal GO2 in the time period t3 for the next row of pixel units. And so on, the shift register units of each stage work in turn to complete the output of the gate driving signals for all rows.

[0109] The circuit structures of the shift register units in adjacent rows are exactly the same, and two clock signals GCK and GCB can be shared by all stages.

[0110] FIG. 6(a) is a circuit diagram of an exemplary light emission control driving circuit. FIG. 6(b) is a timing diagram of the light emission control driving circuit in FIG. 6(a).

[0111] Similar to the gate driving circuit, the light emission control driving circuit can be composed of the shift register units shown in FIG. 6(a) connected in series stage by stage. That is, the light emission control driving circuit also operates in the manner of a shift register, and the shift register units at all stages sequentially output the above-mentioned light emission control signals (which can also belong to the row scanning signals) to the pixel circuit.

[0112] As shown in FIG. 6(a), as a non-limiting example, such a shift register unit may mainly include: the thirty-first transistor T31 to the thirty-eighth transistor T38, and the thirty-first capacitor C31 to the thirty-third capacitor C33. In the figure, N1, N2, and N3 represent nodes in the circuit.

[0113] The control electrode of the thirty-first transistor T31 is used to input the third clock signal ECK, the first electrode is used to input the second start signal ESTV, and the second electrode is coupled to the control electrodes of the thirty-third transistor T33, the thirty-fifth transistor T35, and the thirty-eighth transistor T38. The control electrode of the thirty-second transistor T32 is used to input the third clock signal ECK, the first electrode is coupled to the power supply terminal for inputting the low level VL, and the second electrode is coupled to the second electrode of the thirty-third transistor T33 and the control electrode of the thirty-sixth transistor T36. The first electrode of the thirty-third transistor T33 is used to input the third clock signal ECK. The control electrode of the thirty-fourth transistor T34 is coupled to the second electrode of the thirty-seventh transistor T37 and the second electrode of the thirty-eighth transistor T38, the first electrode is coupled to the power supply terminal for inputting the high level VH, the second electrode is coupled to the first electrode of the thirty-fifth transistor T35, and is used to output the light emission control signal EM. The second electrode of the thirty-fifth transistor T35 is coupled to the power supply terminal for inputting the low level VL. The first electrode of the thirty-sixth transistor T36 is coupled to the power supply terminal for inputting the low level VL, and the second electrode is coupled to the first electrode of the thirty-seventh transistor T37. The control electrode of the thirty-seventh transistor T37 is used to input the fourth clock signal ECB. The first electrode of the thirty-eighth transistor T38 is coupled to the power supply terminal for inputting the high level VH.

[0114] The first terminal of the thirty-first capacitor C31 is coupled to the control electrode of the thirty-fifth transistor T35, and the second terminal is used for inputting the fourth clock signal ECB. The thirty-second capacitor C32 is coupled between the control electrode and the first electrode of the thirty-fourth transistor T34. The first terminal of the thirty-third capacitor C33 is coupled to the control electrode of the thirty-sixth transistor T36, and the second terminal is used for inputting the fourth clock signal ECB.

[0115] As shown in FIG. 6(b), taking the case where the shift register unit is located in the first stage (for example, corresponding to the first row of pixel units) as an example, first, the second start signal ESTV is invalid, so that the shift register unit corresponding to the first row of pixel units outputs an invalid light emission control signal. The first start signal GSTV is changed to be valid later, and the states of the third clock signal ECK and the fourth clock signal ECB are changed according to a predetermined timing sequence, so that a continuously valid light emission control signal EO1 is output for the first row of pixel units. This light emission control signal EO1 simultaneously serves as a start signal for the next-stage shift register unit (for example, corresponding to the second row of pixel units), so that the next-stage shift register unit outputs a valid light emission control signal EO2 later for the pixel units of the next row. And so on, the shift register units of each stage work in sequence to complete the output of the light emission control signals for all rows.

[0116] FIG. 6(c) is a circuit diagram of another exemplary light emission control driving circuit.

[0117] As shown in FIG. 6(c), as a non-limiting example, such a shift register unit may mainly include: the seventy-first transistor T71 to the eighty-third transistor T83, and the seventy-first capacitor C71 to the seventy-third capacitor C73. In the figure, N71, N72, N73, N74, N75, N76 represent nodes in the circuit.

[0118] The control electrode of the seventy-first transistor T71 is coupled to the first electrode of the seventy-sixth transistor T76 and the control electrode of the eighty-second transistor T82; its first electrode is used to input the third clock signal ECK; its second electrode is coupled to the second electrode of the seventy-second transistor T72, the control electrode of the seventy-seventh transistor T77, and the first electrode of the seventy-eighth transistor T78. The control electrode of the seventy-second transistor T72 is used to input the third clock signal ECK; its first electrode is coupled to the power supply terminal for inputting the low level VL. The control electrode of the seventy-third transistor T73 is coupled to the control electrode of the seventy-fifth transistor T75 and the first electrode of the eighty-first transistor T81; its first electrode is used to input the fourth clock signal ECB; its second electrode is coupled to the first electrode of the seventy-seventh transistor T77. The control electrode of the seventy-fourth transistor T74 is coupled to the first electrode of the eightieth transistor T80 and the first electrode of the eighty-second transistor T82; its first electrode is coupled to the power supply terminal for inputting the high level VH; its second electrode is coupled to the first electrode of the seventy-fifth transistor T75 and (as the output terminal EO) is used to output the light emission control signal EM. The second electrode of the seventy-fifth transistor T75 is coupled to the power supply terminal for inputting the low level VL. The control electrode of the seventy-sixth transistor T76 is coupled to another input control signal VCX to make the seventy-sixth transistor T76 enter the on or off state as needed; its second electrode is coupled to the second electrode of the eighty-second transistor T82 and the power supply terminal for inputting the high level VH. The second electrode of the seventy-seventh transistor T77 is coupled to the power supply terminal for inputting the high level VH. The control electrode of the seventy-eighth transistor T78 is coupled to the power supply terminal for inputting the low level VL, and its second electrode is coupled to the control electrode of the seventy-ninth transistor T79. The first electrode of the seventy-ninth transistor T79 is coupled to the second electrode of the eightieth transistor T80; its second electrode is used to input the fourth clock signal ECB. The control electrode of the eightieth transistor T80 is used to input the fourth clock signal ECB. The control electrode of the eighty-first transistor T81 is coupled to the power supply terminal for inputting the low level VL; its second electrode is coupled to the first electrode of the eighty-third transistor T83. The control electrode of the eighty-third transistor T83 is used to input the third clock signal ECK; its second electrode is used to input the second start signal ESTV.

[0119] The seventy-first capacitor C71 is coupled between the control electrode and the second electrode of the seventy-third transistor T73. The seventy-second capacitor C72 is coupled between the control electrode and the first electrode of the seventy-ninth transistor T79. The seventy-third capacitor C73 is coupled between the control electrode and the first electrode of the seventy-fourth transistor T74.

[0120] The circuit structure in Fig. 6(c) has a corresponding and replaceable relationship with that in Fig. 6(a), and can be controlled by the same or similar timing (for example, both use the timing in Fig. 6(b)). In addition, the main difference between Fig. 6(c) and Fig. 6(a) is that the position of capacitor C33, the position and connection relationship of capacitor C31 in Fig. 6(a) are different from the relevant settings in Fig. 6(c). In Fig. 6(c), the seventy-eighth transistor T78 and the eighty-first transistor T81 are added to stabilize the potential of node N71.

[0121] Fig. 6(d) is a circuit diagram of another exemplary light-emitting control drive circuit.

[0122] As shown in Fig. 6(d), as a non-limiting example, such a shift register unit may mainly include: the ninety-first transistor T91 to the one-hundred-and-sixteenth transistor T106, the ninety-first capacitor C91 to the ninety-third capacitor C93. That is, a structure of 16 transistors and 3 capacitors (16T3C).

[0123] The control electrode of the ninety-first transistor T91 is coupled to the control electrode of the one-hundred-and-fifth transistor T105 and is used for inputting the third clock signal ECK; its first electrode is coupled to the first electrode of the one-hundred-and-fifth transistor T105 and is used for inputting the second start signal ESTV; its second electrode is coupled to the control electrode of the ninety-second transistor T92, the control electrode of the ninety-eighth transistor T98, the first electrode of the one-hundred-and-second transistor T102, and the first electrode of the one-hundred-and-third transistor T103. The first electrode of the ninety-second transistor T92 is used for inputting the third clock signal ECK; its second electrode is coupled to the first electrode of the ninety-third transistor T93, the control electrode of the ninety-fifth transistor T95, and the first electrode of the one-hundred-and-first transistor T101. The control electrode of the ninety-third transistor T93 is used for inputting the third clock signal ECK; its second electrode is coupled to the power supply terminal for inputting the low level VL. The control electrode of the ninety-fourth transistor T94 is coupled to the control electrode, the first electrode, and the first electrode of the one-hundred-and-sixth transistor T106 of the one-hundred-and-fourth transistor T104; its first electrode is used for inputting the fourth clock signal ECB; its second electrode is coupled to the first electrode of the ninety-fifth transistor T95. The second electrode of the ninety-fifth transistor T95 is coupled to the power supply terminal for inputting the high level VH. The control electrode of the ninety-sixth transistor T96 is coupled to the second electrode of the one-hundred-and-first transistor T101; its first electrode is used for inputting the fourth clock signal ECB; its second electrode is coupled to the first electrode of the ninety-seventh transistor T97. The control electrode of the ninety-seventh transistor T97 is used for inputting the fourth clock signal ECB; its second electrode is coupled to the first electrode of the ninety-eighth transistor T98 and the control electrode of the ninety-ninth transistor T99. The second electrode of the ninety-eighth transistor T98 is coupled to the power supply terminal for inputting the high level VH. The first electrode of the ninety-ninth transistor T99 is coupled to the power supply terminal for inputting the high level VH; its second electrode is coupled to the first electrode of the one-hundredth transistor T100 and serves as the output terminal (EO) for outputting the light emission control signal EM. The control electrode of the one-hundredth transistor T100 is coupled to the second electrode of the one-hundred-and-second transistor T102 and the second electrode of the one-hundred-and-fourth transistor T104; its second electrode is coupled to the power supply terminal for inputting the low level VL. The control electrode of the one-hundred-and-first transistor T101 is coupled to the power supply terminal for inputting the low level VL. The control electrode of the one-hundred-and-second transistor T102 is coupled to the control electrode of the one-hundred-and-sixth transistor T106. The control electrode of the one-hundred-and-third transistor T103 is coupled to another input control signal VEL to make the one-hundred-and-third transistor T103 enter the on or off state as needed; its second electrode is coupled to the power supply terminal for inputting the high level VH. The second electrode of the one-hundred-and-fifth transistor T105 is coupled to the second electrode of the one-hundred-and-sixth transistor T106.

[0124] The coupling of the ninety-first capacitor C71 is between the control electrode and the second electrode of the ninety-sixth transistor T96. The ninety-second capacitor C72 is coupled between the control electrode and the first electrode of the ninety-ninth transistor T99. The ninety-third capacitor C73 is coupled between the control electrode and the second electrode of the ninety-fourth transistor T94.

[0125] The circuit structures in FIGS. 6(d), 6(c), and 6(a) have a corresponding and replaceable relationship, and can be controlled by the same or similar timings (for example, all use the timing in FIG. 6(b)). Compared with FIGS. 6(a) and 6(c), in FIG. 6(d), T105 (paired with T91), T106 (paired with T102), T104, etc. are additionally provided to further increase the stability of the N71 node in FIG. 6(c) relative to the circuit structure in FIG. 6(c).

[0126] The circuit structure corresponding to T76 and T83 in FIG. 6(c) is retained in FIG. 6(d) and is used to reset the N1 node. When the transistors controlled by the N71 node need to be turned off, such as during the blank phase between frames, before the first frame is displayed, in case of an abnormality, etc. (i.e., when the low potential of VL is not required to be output), the high potential of VH is input to the N71 node.

[0127] The circuits shown in FIGS. 4(a), 5(a), 6(a) / 6(c) / 6(d) above can cooperate with each other. However, it should be understood that any one or more of these circuits can be replaced by circuits with the same function of other structures.

[0128] FIG. 7(a) is a circuit diagram of another exemplary pixel unit. FIG. 7(b) is a timing diagram of the pixel unit in FIG. 7(a).

[0129] The pixel unit shown in FIG. 7(a) may include the forty-first transistor T41 to the forty-seventh transistor T47, and the forty-first capacitor C41. In addition, it is also described that this pixel unit is located in the Nth row.

[0130] The control electrode of the forty-first transistor T41 is used to input a reset signal Reset(N), the first electrode is coupled to a first reference power supply terminal VREFN, and the second electrode is coupled to the first electrode of a forty-second transistor T42 and the control electrode of a forty-third transistor T43. The control electrode of the forty-second transistor T42 is used to input a gate drive signal Gate, and the second electrode is coupled to the second electrode of the forty-third transistor T43 and the first electrode of a forty-sixth transistor T46. The first electrode of the forty-third transistor T43 is coupled to the second electrode of a forty-seventh transistor T47 and a power supply terminal for inputting a first drive power supply ELVDD. The control electrode of the forty-fourth transistor T44 is used to input a gate drive signal Gate, the first electrode is used to input a display data signal Vdata, and the second electrode is coupled to the first electrode of a forty-fifth transistor T45 and the first electrode of the forty-seventh transistor T47. The control electrode of the forty-fifth transistor T45 is used to input a light emission control signal EM, and the second electrode is coupled to a second reference power supply terminal VREFP (which can also be referred to as an initialization power supply terminal and can be input with a high level). The control electrode of the forty-sixth transistor T46 is used to input a light emission control signal EM, and the second electrode is coupled to the first electrode of the OLED. The control electrode of the forty-seventh transistor T47 is used to input a reset signal Reset(N). The second electrode of the OLED (which can be a cathode) is coupled to a power supply terminal for inputting a second drive power supply ELVSS (which can input a low level). The first terminal of a forty-first capacitor C41 is coupled to the second electrode of the forty-fourth transistor T44, and the second terminal is coupled to the second electrode of the forty-first transistor T41.

[0131] The operating timing of Fig. 7(b) can be exactly the same as that of Fig. 4(b), and its description is omitted.

[0132] Above, taking all the transistors as P-type (or P-channel) transistors and the corresponding effective signals as signals with relatively low levels (e.g., 0V or negative voltage) as an example for illustration. It should be understood that some or all of the transistors can also be replaced with N-type without changing the overall function of the circuit, and the effective signals corresponding to this part or all of the replaced transistors will be signals with relatively high levels (e.g., positive voltages with a predetermined amplitude).

[0133] According to the specific structure of the applied OLED panel, Figure 2 the method shown may have additional steps, or Figure 2 each step in

[0134] Fig. 8(a) is a flowchart showing Figure 2 the sub-steps of the method shown in

[0135] As shown in FIG. 8(a), in an embodiment of the present disclosure, in a first time period, a method for driving a gate driving circuit includes: step S1011 of supplying power to a power supply terminal of the gate driving circuit (for example, providing a third power signal and a fourth power signal); step S1012 of providing a clock signal to the gate driving circuit; and step S1013 of providing an invalid first start signal to the gate driving circuit.

[0136] In an embodiment of the present disclosure, a pixel circuit includes a driving power supply terminal and a reference power supply terminal. In a second time period, a method for driving the pixel circuit includes: step S1021 of supplying power to the driving power supply terminal (for example, providing a first power signal and a second power signal); and step S1022 of supplying power to the reference power supply terminal.

[0137] FIG. 8(b) is a flowchart showing Figure 2 additional steps of the method shown in.

[0138] As shown in FIG. 8(b), in an embodiment of the present disclosure, when the display panel further includes a light emission control driving circuit for outputting a light emission control signal to the pixel circuit, a method for driving the display panel further includes: step S104 of driving the light emission control driving circuit in a first time period.

[0139] In an embodiment of the present disclosure, in a first time period, a method for driving the light emission control driving circuit may include: step S1041 of supplying power to a power supply terminal of the light emission control driving circuit (for example, providing a third power signal and a fourth power signal); step S1042 of providing a clock signal to the light emission control driving circuit; and step S1043 of providing an invalid second start signal to the light emission control driving circuit.

[0140] FIG. 8(c) is a flowchart showing Figure 2 additional steps of the method shown in.

[0141] In an embodiment of the present disclosure, a method for driving a display panel further includes: step S105 of causing a source driving circuit to provide a display data signal to a pixel circuit in a third time period. In the first time period and the second time period, the first start signal and the second start signal remain invalid. In the third time period, the second start signal remains invalid until the first start signal of the gate driving circuit becomes valid.

[0142] FIG. 8(d) is an exemplary timing diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.

[0143] As shown in FIG. 8(d), the first time period may at least include a first frame, i.e., the 1st frame. In this first frame, power supply is started for the power supply terminal of the gate driving circuit, and two supply voltages VH and VL are provided (for example, a high level and a low level may be provided respectively). For the gate driving circuit, a clock signal GCLK is provided, which may represent the above-mentioned first clock signal GCK and the second clock signal GCB. An invalid first start signal GSTV is provided for the gate driving circuit.

[0144] In an embodiment of the present disclosure, in the first time period and the second time period, the first start signal may be kept invalid.

[0145] As shown in FIG. 8(d), the second time period may at least include a second frame, i.e., the 2nd frame. In this first frame and the second frame, the first start signal GSTV may be kept invalid.

[0146] Specifically, as shown in FIG. 8(d), from the power-on of the OLED panel until the display, it can be roughly divided into the following stages.

[0147] 1. After the OLED panel receives an instruction of "Display on" via an interface (I / F), the GOA power supplies VH and VL are powered on. Except that the GOA input signals (STV, CLK) (ESTV and GSTV can be collectively referred to as STV; ECLK and GCLK can be collectively referred to as CLK) output a high level or a low level according to the specific GOA circuit design, other power supplies and signals of the panel maintain an output GND state to prevent current from appearing in the short-circuit loop that may be formed in the pixel circuit during the power-on process.

[0148] 2. Enter the GOA initialization frame in the first time period of the above power-on method, and the power supplies VH and VL of the gate driving circuit and / or the light-emitting control driving circuit (hereinafter, simply referred to as GOA) are powered on, and the driving circuit is initialized using one frame time.

[0149] ① Except for T3 shown in FIGS. 4(a) and 7(a) in the pixel circuit, the gate control of each transistor needs to be completed by the GOA. Therefore, when the panel is powered on, the GOA needs to be operated first.

[0150] ② The GOA has a multi-stage cascaded architecture where the output of the previous stage serves as the input of the next stage. After the GOA is powered on, the output states of each stage are uncertain (possible output states: VH, VL, or even a certain voltage between VH and VL), which may cause the transistors in the pixel circuit to be in an undesired on state. If the relevant power supplies (VREFN, ELVDD, ELVSS) of the pixel circuit are powered on without additional operations and / or a display data signal (Source) is provided, a short circuit may occur due to a possible path formed between different power supplies. Moreover, if there is current flowing through the OLED device at this time, an instant flash phenomenon will occur. Therefore, it is necessary to determine the states of each stage of the GOA at the beginning of power-on; since each stage of the GOA is cascaded, it takes one frame refresh cycle to complete the operation of determining the output states of each stage.

[0151] In an embodiment of the present disclosure, during the first time period, the multiplexing circuit can remain conducting or switch normally (i.e., the Mux outputs a low level or alternately outputs high and low levels normally). Alternatively, when the source driver circuit outputs a grounding signal, the multiplexing circuit can also remain conducting.

[0152] In this GOA initialization frame, the signal output from the source driver circuit to the pixel circuit in this frame can be a grounding signal GND, and the switching signal Mux can output a low level or output normally. Corresponding to the P-type transistor as a switch, it is conducting when outputting a low level, allowing the data signal to pass through. Normal output (toggle) refers to the output during normal display, the same as the 4th Frame. Whether the Mux outputs a low level or normally, the GND output by the source driver circuit (Source Driver) can reach the pixel circuit, achieving the purpose of discharging as many parts of the lines connected to the source driver circuit in the panel to GND as possible. At this time, the voltages of ELVDD, ELVSS, VREFP, and VREFN are also all GND. Therefore, most of the pixel circuit is GND, and an uncontrollable current cannot be formed in the pixel circuit. At this time, it is better to output a low level, which can allow GND to be injected into the panel by the source driver circuit to prevent flashing. The first start signal GSTV and the second start signal ESTV output a high level (invalid), and the clock signal GCLK of the gate driver circuit and the clock signal ECLK of the light emission control driver circuit (which can represent the above-mentioned third clock signal ECK and the fourth clock signal ECB) are the same as the clock signals input to the gate driver circuit (Gate GOA) and the light emission control driver circuit (EMGOA) during normal display. After this frame is completed, for example, except for the thirteenth transistor T13 in the pixel circuit shown in FIG. 4(a), the gate states of all TFTs are in a high level state (invalid), and the TFTs enter the cut-off state.

[0153] 3. Enter the pixel power-on frame in the second time period of the above power-on method. The second start signal ESTV of the light emission control drive signal and the clock signal ECLK maintain the states in the GOA initialization frame. The first start signal GSTV of the gate drive signal and the clock signal GCLK maintain the states in the GOA initialization frame. In this frame, since the pixel circuit is not in the state of writing data, the voltage of the data signal Source and the state of the switching signal Mux in this frame data can be not specified. If the power-on speed is too slow (the power-on time is late or the rise time is long), this frame can be changed from one frame to multiple frames to wait for the power-on to complete.

[0154] At this time, the gate states of each transistor (e.g., TFT) in the pixel circuit are determined, and the relevant power supplies of the pixel circuit can be powered on. The pixel power supplies ELVDD, ELVSS, and VREFN are powered on (for some pixel circuits, the pixel power supply VREFP, etc. are also powered on together). The source driver for providing display data (represented by Source for its output) can also start to work, but it does not necessarily provide the data signal for normal display to the pixel circuit.

[0155] 4. Enter the start display frame, and the panel starts to display from this frame. The first start signal GSTV of the gate drive signal, the clock signal GCLK, the clock signal ECLK of the light emission control drive signal, the switching signal Mux, and the data signal Source can be normally output.

[0156] In addition, the data signal has not been written into the pixel circuit in the previous frame. Therefore, at the beginning of this frame, the light emission control EM of the pixel circuit cannot be pulled low (effective), otherwise flicker may occur. Therefore, the second start signal ESTV of the light emission control drive signal needs to maintain a high level (invalid) at the beginning of this frame until the second start signal ESTV is pulled low at the position where it is pulled low within one display frame during normal display. That is, during normal display, the second start signal ESTV has two low-level periods within one frame, and the first low-level period of the second start signal ESTV in this frame needs to be pulled high and then pulled low during the second period.

[0157] 5. After the power-on is completed, the panel displays normally.

[0158] In addition, since the low-level width of the first start signal GSTV is very narrow, if the first start signal GSTV and the clock signal GCLK of the gate driving circuit are working properly, then at the end of the display screen of one display frame, the gate driving signals Gate of all rows in the panel are at a high level (the same as the state of the gate driving signals Gate of all rows in the panel at the end of one frame when the first start signal GSTV is always pulled high and the clock signal GCLK is working properly). Therefore, the working state of the first start signal GSTV in the GOA initialization frame can also be the same as the state during normal display, that is, the same as the 4th frame, etc.

[0159] Figure 9 is another exemplary timing diagram corresponding to the method for driving a display panel according to an embodiment of the present disclosure.

[0160] In an embodiment of the present disclosure, in the first time period, the first start signal and the second start signal are kept invalid. In the second time period, the second start signal is kept invalid.

[0161] In an embodiment of the present disclosure, in the second time period, a display data signal corresponding to displaying black is provided to the pixel circuit.

[0162] As Figure 9 shown, the power-on of the OLED panel and the GOA initialization frame can both be the same as shown in FIG. 8(d).

[0163] In the pixel power-on frame (2nd frame), the main difference from that shown in FIG. 8 is that the first start signal GSTV of the gate driving circuit can be in the same state as during normal display and has a stage of being pulled low (effective). That is to say, the display data signal can be written into the pixel circuit.

[0164] Correspondingly, considering the supply voltage conditions of each pixel circuit during the power-on process, the written display data signal can be configured as a voltage that can turn off the thirteenth transistor T13 (for example, corresponding to displaying black). This can also prevent screen flickering, circuit short circuits, etc.

[0165] If the power-on speed of the power supply is too slow (the power-on time is late or the rise time is long), this frame can be changed from one frame to multiple frames to wait for the power-on to complete.

[0166] In addition, at the start of entering the display frame, that is, the third frame (3rd frame), the difference from FIG. 8(d) is that since the display data (such as black) has been written into the pixel circuit in the previous frame, at the start of this frame, the write control signal EM of the pixel circuit can be normally pulled low (effective), that is, the second start signal ESTV of the write control driving circuit can also work properly.

[0167] In addition, similar to FIG. 8(d), the operating state of the first start signal GSTV in the GOA initialization frame can also be the same as that in normal display, i.e., the same as that in the 4th frame etc.

[0168] In addition, in the pixel power-on frame (2nd Frame), since the first start signal GSTV of the gate driving circuit is pulled low, the voltage of the display data signal Source will be written, and it is forced to write black data. Therefore, the clock signal GCLK of the gate driving circuit can work normally in this frame (the same as the 4th frame), but it can also not work (for example, according to different compositions of the gate driving circuit, keep high level or low level).

[0169] Figure 10 It is an exemplary test signal waveform diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.

[0170] Specifically, Figure 10 can correspond to Figure 9 the power-on timing shown. In Figure 10 , SPIMOSI corresponds to I / F. The falling edge of TE indicates the start of a new frame, and the rising edge indicates the end of the previous frame. In Figure 10 , SWIRE is a signal for providing the first driving power supply ELVDD and the second driving power supply ELVSS to the pixel circuit. Once SWIRE is pulled high, the first driving power supply ELVDD and the second driving power supply ELVSS immediately start to supply power.

[0171] In Figure 10 , it can be seen that the display data signal SRC (i.e., source) may be coupled to interference signals in the first frame (1st frame), generating voltage fluctuations (glitches). At this time, if the display process is directly started, it may cause phenomena such as screen flickering. According to an embodiment of the present disclosure, in the first frame (1st frame), no display is performed, but the gate driving circuit etc. are initialized, which can effectively avoid such phenomena.

[0172] After the initialization and power-on processes are all completed, for example, Figure 10 in the 4th frame in

[0173] , the normal display process starts, and start signals such as ESTV can be normally output. Figure 10In the [description], due to the actual application conditions of components such as chips in the test object, the first reference power supply terminal VREFN may already be in a powered-on state in the first frame (1st frame). This partial power supply setting can also play a certain role in preventing display screen flickering caused by unstable internal circuit states of the display panel or circuit short circuits. Of course, a more preferred implementation is that the pixel circuit is completely not powered in the first frame (1st frame).

[0174] Figure 11 FIG. [number] is a block diagram showing the structure of another exemplary OLED display panel.

[0175] Figure 11 The structure in [description] can be used for an LTPO (Low Temperature Polycrystalline Oxide) AMOLED panel. Compared with Figure 3 the LTPS AMOLED panel shown in [figure reference], there is an additional gate driving circuit (NGate GOA). This gate driving circuit (NGate GOA) is used to provide the additional gate driving signal NGATE and reset signal NRST required for the pixel circuit.

[0176] FIG. 12(a) is a circuit diagram of the pixel unit in the exemplary Figure 11 [figure reference]. FIG. 12(b) is a timing diagram of the pixel unit in the exemplary FIG. 12(a).

[0177] The LTPO pixel circuit is shown in FIG. 12(a). Compared with FIG. 4, the eleventh transistor T11 and the twelfth transistor T12 are replaced with N-channel transistors (for example, indium gallium zinc oxide thin film transistors, indium gallium zinc oxide thin film transistor, IGZO TFT), and these two TFTs are individually driven by the additional gate driving circuit (NGate GOA).

[0178] Specifically, in FIG. 12(b), during the time period T1, the required additional reset signal NReset is further provided. During the time period T2, the required additional gate driving signal NGate is further provided. That is, except for the change in the polarity of the driving signals of the eleventh transistor T11 and the twelfth transistor T12, the other signals have the same signal timing as those in FIG. 4(b).

[0179] FIG. 13(a) is a circuit diagram of the additional gate driving circuit in the exemplary Figure 11 [figure reference]. FIG. 13(b) is a timing diagram of the additional gate driving circuit in the exemplary FIG. 13(a).

[0180] As shown in FIG. 13(a), as a non-limiting example, the shift register unit of such an additional gate driving circuit may include: the fifty-first transistor T51 to the sixty-third transistor T63, the fifty-first capacitor C51 to the fifty-third capacitor C53. The control electrode of the fifty-first transistor T51 is used to input the fifth clock signal GCK’, the first electrode is coupled to the second electrode of the sixty-third transistor T63, and the second electrode is coupled to the control electrode of the fifty-second transistor T52 and the first electrode of the sixty-second transistor T62. The first electrode of the fifty-second transistor T52 is used to input the fifth clock signal GCK’, and the second electrode is coupled to the second electrode of the fifty-third transistor T53, the control electrode of the fifty-fifth transistor T55, and the first electrode of the sixty-first transistor T61. The control electrode of the fifty-third transistor T53 is used to input the fifth clock signal GCK’, and the first electrode is coupled to the power supply terminal for inputting the low level VL. The control electrode of the fifty-fourth transistor T54 is coupled to the control electrodes of the fifty-eighth transistor T58, the sixtieth transistor T60, and the second electrode of the sixty-second transistor T62. The first electrode is used to input the sixth clock signal GCB’, and the second electrode is coupled to the second electrode of the fifty-fifth transistor T55. The first electrode of the fifty-fifth transistor T55 is coupled to the power supply terminal for inputting the high level VH. The control electrode of the fifty-sixth transistor T56 is coupled to the second electrode of the sixty-first transistor T61. The first electrode is used to input the sixth clock signal GCB’, and the second electrode is coupled to the first electrode of the fifty-seventh transistor T57. The control electrode of the fifty-seventh transistor T57 is used to input the sixth clock signal GCB’, and the second electrode is coupled to the first electrode of the fifty-eighth transistor T58 and the control electrode of the fifty-ninth transistor T59. The second electrode of the fifty-eighth transistor T58 is used to input the sixth clock signal GCB’. The first electrode of the fifty-ninth transistor T59 is used to input the sixth clock signal GCB’, and the second electrode is coupled to the first electrode of the sixtieth transistor T60 and is used to output the auxiliary gate driving signal NGox (x may represent the number of rows). The second electrode of the sixtieth transistor T60 is coupled to the power supply terminal for inputting the low level VL. The control electrode of the sixty-first transistor T61 is coupled to the power supply terminal for inputting the low level VL. The control electrode of the sixty-second transistor T62 is coupled to the power supply terminal for inputting the low level VL. The control electrode of the sixty-third transistor T63 is used to input the sixth clock signal GCB’, and the first electrode is coupled to the auxiliary gate driving signal NGox-1 output from the previous row (x may represent the number of rows).

[0181] The fifty-first capacitor C51 is coupled between the control electrode and the second electrode of the fifty-sixth transistor T56. The fifty-second capacitor C52 is coupled between the control electrode and the first electrode of the fifty-ninth transistor T59. The fifty-third capacitor C53 is coupled between the control electrode and the second electrode of the fifty-fourth transistor T54.

[0182] Comparing the timing of FIG. 13(b) with that of FIG. 5(b), the difference is that the start signal NGSTV of the additional gate driving circuit and the additional gate driving signals NGO (including NGO1 for the first row and NGO2 for the second row) in FIG. 13(b) are both active high. In addition, the levels of the fifth clock signal GCK’ and the sixth clock signal GCB’ in FIG. 13(b) are adjusted correspondingly.

[0183] Figure 14 is an exemplary timing diagram corresponding to a method for powering on an Figure 11 OLED display panel according to an embodiment of the present disclosure.

[0184] As Figure 14 shown, except that the polarities of the driving signals of the eleventh transistor T11 and the twelfth transistor T12 in the pixel circuit change and thus the start signal NGSTV of the additional gate driving circuit and the clock signal NGCLK need to be provided, there is no other difference from the Figure 9 shown timing. In addition, the start signal NGSTV of the additional gate driving circuit and the clock signal NGCLK can be opposite to the start signal GSTV of the gate driving circuit and the clock signal GCLK respectively. That is to say, in each time period, when the start signal GSTV of the gate driving circuit is valid, the start signal NGSTV of the additional gate driving circuit is also in a valid state.

[0185] Figure 15 is another exemplary flowchart showing a method for driving a display panel according to an embodiment of the present disclosure. The display panel in the embodiment of the present disclosure can also be driven by this method.

[0186] Figure 15 The method for driving a display panel shown can include: step S201, in the fourth time period, providing an invalid start signal to the gate driving circuit and / or the light emission control driving circuit; step S202, in the fifth time period, disconnecting the first power signal and the second power signal provided to the pixel circuit; step S203, in the sixth time period, disconnecting the third power signal and the fourth power signal provided to the gate driving circuit and / or the light emission control driving circuit.

[0187] According to an embodiment of the present disclosure, during the power-off process of the display panel, operations such as stopping the driving of the gate driving circuit and / or the light emission control driving circuit, disconnecting the power supply of the pixel circuit, and disconnecting the power supply of the gate driving circuit and / or the light emission control driving circuit are performed in different time periods. In this way, it is possible to prevent the transistors in the pixel circuit from being powered off when their states are unstable, thereby effectively preventing problems such as display screen flickering or circuit short circuit.

[0188] In an embodiment of the present disclosure, the first time period and the second time period do not overlap. In this way, it can be ensured that after the corresponding circuit elements (e.g., transistors) in the pixel circuit are turned off by the gate driving circuit according to a predetermined timing for display, the power supply to the pixel circuit is then disconnected. This can more effectively prevent problems such as display screen flickering or circuit short - circuiting.

[0189] In an embodiment of the present disclosure, the first time period includes the duration of at least one display frame. Since the matrix of the pixel circuit is scanned row - by - row, it takes at least one frame time to reliably turn off the corresponding circuit elements in all pixel circuits.

[0190] In an embodiment of the present disclosure, in the fourth time period, an invalid start signal is provided to the light - emitting control driving circuit. According to an embodiment of the present disclosure, after providing an invalid start signal to the light - emitting control driving circuit, the light - emitting control driving circuit cannot output a valid control signal to the pixel circuit. The control elements related to the light - emitting process of the light - emitting elements in the pixel circuit are turned off / cut off. For example, the control element can be a transistor for turning on / off the current flowing through the light - emitting element. According to an embodiment of the present disclosure, during the power - down process of the display panel, regardless of whether the gate driving circuit is operating, the light - emitting elements will not emit light.

[0191] In an embodiment of the present disclosure, in the fourth time period, a valid start signal is provided to the gate driving circuit; and in the fourth time period, a display data signal corresponding to displaying black is provided to the pixel circuit.

[0192] According to an embodiment of the present disclosure, a display data signal corresponding to displaying black can be written into the pixel circuit to prevent the pixel circuit from still storing the previously written data signal or other interferences. Thereby, problems such as flickering can be further prevented. This can be a relatively preferred solution.

[0193] In addition, in an embodiment of the present disclosure, it can also be that in the fourth time period, an invalid start signal is provided to the gate driving circuit. According to an embodiment of the present disclosure, this will cause the display data signal not to be written into the pixel circuit. Therefore, during the power - down process of the display panel, the specific state of the display data signal can also be not concerned about.

[0194] In an embodiment of the present disclosure, in the fifth time period, invalid start signals are provided to the gate driving circuit and the light - emitting control driving circuit. According to an embodiment of the present disclosure, in the fifth time period, the state where the relevant control elements in the pixel circuit are turned off / cut off can be continuously maintained.

[0195] In an embodiment of the present disclosure, the pixel circuit includes a driving power supply terminal and a reference power supply terminal. In the fifth time period, the driving power supply terminal and the reference power supply terminal are grounded; and, in the fifth time period, the source driver circuit outputs a ground signal. According to an embodiment of the present disclosure, in the fifth time period, each power supply terminal and input terminal (for example, the display data signal input terminal connected to the source driver circuit) of the pixel circuit can also be grounded. This can prevent the voltages stored by filtering capacitors, parasitic capacitors, etc. on these power supply terminals and input terminals from not being released, thereby affecting the power-down speed of the display panel.

[0196] In an embodiment of the present disclosure, in the sixth time period, the power supply terminal of the gate driver circuit and / or the light emission control driver circuit is grounded. According to an embodiment of the present disclosure, once the power-down of the pixel circuit is completed, the power signal of the gate driver circuit and / or the light emission control driver circuit can be disconnected as soon as possible, and the power supply terminal of the gate driver circuit and / or the light emission control driver circuit can be further grounded to complete the power-down process of the entire display panel.

[0197] Figure 16 corresponds to Figure 15 An exemplary timing diagram of a method for driving a display panel according to an embodiment of the present disclosure as shown.

[0198] As an example, this timing can also be applied to Figure 3 the AMOLED panel shown, and the panel can include various circuit structures as shown in FIGS. 4(a), 5(a), and 6(a). Alternatively, the panel can also include the circuit structure shown in FIG. 7(a).

[0199] As Figure 16 shown, from the normal display of the OLED panel until it is turned off, it can be roughly divided into the following stages.

[0200] In an embodiment of the present disclosure, upon receiving a Display off instruction, it takes one display frame time to turn off the elements (such as transistors TFT) for light emission control in the pixel circuit. This is because the display brightness of the AMOLED display panel is related to many voltages, and the power-down of each voltage is not completed instantaneously, but is completed in the order of milliseconds. If the power supply is suddenly powered down, the display content of the display panel within the order of milliseconds will be uncontrollable. The preferred approach is to turn off each control element and related circuit in the pixel circuit and then perform the power-down operation of the power supply. The display panel mostly uses a cascaded driver circuit architecture (GOA), and it takes one frame time to use the driver circuit to turn off the relevant elements in the pixel circuits of all rows.

[0201] Specifically, in the fourth time period, an invalid start signal is provided to the light emission control driving circuit. That is, in this time period, corresponding to the type of transistor in the light emission control driving circuit shown in, for example, FIG. 6(a), the second start signal ESTV is always in a high level (invalid) state. In such a case, the light emission control driving circuit will not be able to output a predetermined valid (for example, including a low level, or including a level that changes from high to low) light emission control signal as shown in FIG. 6(b) to the pixel circuit. EO1 can represent the light emission control signal output to the pixel circuit of the first row. EO2 can represent the light emission control signal output to the pixel circuit of the second row.

[0202] Referring to FIGS. 4(a) and 4(b), when the light emission control signal (represented by EM) of this pixel circuit is invalid (always high), the fifteenth transistor T15 and the sixteenth transistor T16 are always turned off. During this period, regardless of the state of the thirteenth transistor T13, current cannot flow through the OLED in the pixel circuit via the fifteenth transistor T15 and the sixteenth transistor T16, and the OLED will not be able to emit light.

[0203] At this time, it is possible to provide either an invalid (always high) or a normally valid (for example, including a low level, or including a level that changes from low to high) first start signal GSTV to the gate driving circuit.

[0204] As an example, in the fourth time period, a valid start signal is provided to the gate driving circuit, and a display data signal corresponding to displaying black is provided to the pixel circuit. Alternatively, the specific state of the display data signal may not be cared about.

[0205] In addition, since the matrix of the pixel circuit is scanned row by row, and the gate driving circuit (Gate GOA) and the light emission control driving circuit (EM GOA) are respectively cascade structures, it takes at least one display frame time to reliably turn off the corresponding circuit elements in all pixel circuits through the gate driving circuit (Gate GOA) and the light emission control driving circuit (EM GOA).

[0206] When the relevant control elements in the pixel circuit have been turned off, the relevant power supplies (VREFN, ELVDD, ELVSS, Source) of the pixel circuit can be powered down. In order to maintain the off state of the control elements, the relevant control signals cannot be removed yet (for example, the control signals applied to the gates of the transistors need to maintain the relevant levels).

[0207] Specifically, in the fifth time period, the power supply related to the pixel circuit is powered down. At the end of the fourth time period, the corresponding circuit elements (e.g., the above-mentioned various transistors) in all pixel circuits have been in the off / cut-off state. This state continues to be maintained in the fifth time period, so the second start signal ESTV and the first start signal GSTV still remain invalid (always high).

[0208] Referring to the unit of the gate driving circuit (Gate GOA) in Fig. 5(a), if the first start signal GSTV is always high, the gate driving circuit will not be able to output a predetermined valid (e.g., including a low level, or a level with high-low transformation) gate driving signal as shown in Fig. 5(b) to the pixel circuit. GO1 can represent the gate driving signal output to the pixel circuit of the first row. GO2 can represent the gate driving signal output to the pixel circuit of the second row.

[0209] Referring to the pixel circuit in Fig. 4(a), since the gate driving signal Gate is maintained at a high level in this stage, the data signal Data cannot be written into the storage element (e.g., the eleventh capacitor C11) in the pixel circuit. When the data signal cannot be written, the states of the switching signals MUX (e.g., MUX1, MUX2) as shown Figure 3 and the state of the data signal Data itself can be unrestricted, which can further simplify the power-down control logic.

[0210] In the fifth time period, after the corresponding circuit elements (e.g., the above-mentioned various transistors) in all pixel circuits have been in the off / cut-off state, the power supply terminals (e.g., for VREFN, ELVDD, ELVSS) and input terminals (e.g., for Source) of the pixel circuit can be powered off. In particular, they can be grounded to GND to prevent the voltages stored by filtering capacitors, parasitic capacitors, etc. on these power supply terminals and input terminals from not being released, thus affecting the power-down speed of the display panel. After they are discharged to GND, the fifth time period ends.

[0211] The power supply related to the pixel circuit has been disconnected when the control element is in the off / cut-off state. At this time, even if the control element is in the on / conducting state again, no current will flow through the control element and the OLED device is lit. At this time, the power supplies of each driving circuit can be disconnected. Thus, the entire power-down process of the panel is completed.

[0212] Specifically, in the sixth time period, the power - down of the pixel circuit has been completed, and then the power - down of the driving circuits (e.g., the gate driving circuit, the light - emitting control driving circuit) can be started. In this stage, each driving circuit stops outputting driving signals in the form of pulses. After the pulse output stops, the power supply of the driving circuit can be disconnected as soon as possible, and thus the power - down process is all completed. In particular, the power supply terminal of the driving circuit can also be grounded.

[0213] It should be understood that during the power - down process, the specific levels of the above - mentioned "valid" and "invalid" signals are still determined according to the specific circuit structure. For example, when using different types of transistors to form pixel circuits, driving circuits, etc., the high level can also become the valid level.

[0214] Figure 17 corresponds to Figure 15 An exemplary test signal waveform diagram of the method for driving a display panel according to an embodiment of the present disclosure as shown.

[0215] Specifically, Figure 17 can correspond to Figure 16 the power - down timing as shown. In Figure 17 the MIPI in Figure 16 corresponds to the MIPI in Figure 17 This signal belongs to one type of the interface signal I / F and can indicate the start of the power - down process alone or together with other signals. The falling edge of TE / VS represents the start of a new frame, and the rising edge represents the end of the previous frame. In

[0216] The above - mentioned fourth time period is represented by TFT off in Figure 17 The above - mentioned fifth time period is represented by PixelPWR off in Figure 17 The above - mentioned sixth time period is represented by GOA PWR off in Figure 17

[0217] Figure 18 corresponds to an exemplary timing diagram of the method for power - down of the OLED display panel in Figure 11 according to an embodiment of the present disclosure.

[0218] As Figure 18 ​As shown, except that the driving signal polarities of the eleventh transistor T11 and the twelfth transistor T12 in the pixel circuit change and thus the start signal NGSTV and the clock signal NGCLK of the additional gate driving circuit need to be provided, there is no other difference from Figure 16 the timing shown. In each time period, when the start signal GSTV of the gate driving circuit is valid, the start signal NGSTV of the additional gate driving circuit is also in the valid state.

[0219] According to an embodiment of the present disclosure, an improved power-on timing is provided for the OLED display panel, which can avoid problems such as display screen flickering or circuit short-circuiting caused by unstable internal circuit states of the display panel during the power-on process. In particular, when the panel power-on can be completed in a short time (for example, two frames), problems such as power-on instant flash and internal circuit short-circuiting can be avoided.

[0220] In addition, according to an embodiment of the present disclosure, an improved power-off timing is also provided for the OLED display panel, which can avoid problems such as display screen flickering or circuit short-circuiting caused by unstable internal circuit states of the display panel during the power-off process. In particular, when the panel power-off can be completed in a short time (for example, as short as two frames), problems such as power-off instant flash and internal circuit short-circuiting can be avoided.

[0221] It should be understood that the above are only exemplary specific embodiments of the present disclosure, and the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A device for driving a display panel, wherein, The display panel includes a pixel circuit, a gate driving circuit, a light emission control driving circuit, and a source driving circuit, wherein the gate driving circuit and the source driving circuit are respectively configured to provide a scanning signal and a data signal to the pixel circuit; wherein the pixel circuit includes a plurality of pixel units arranged in an array, and each pixel unit includes an OLED element; wherein the light emission control driving circuit is configured to output a light emission control signal to the pixel circuit; wherein the device is configured to: in a first time period, provide an invalid start signal to the gate driving circuit and the light emission control driving circuit; in a second time period, provide a first power signal and a second power signal to the pixel circuit; and in a third time period, provide a valid start signal to the gate driving circuit and the light emission control driving circuit; wherein the device for driving the display panel is further configured to: in the third time period, enable the source driving circuit to provide a display data signal to the pixel circuit; wherein in the first time period and the second time period, the first start signal provided to the gate driving circuit and the second start signal provided to the light emission control driving circuit remain invalid; and wherein in the third time period, the second start signal remains invalid before the first start signal of the gate driving circuit becomes valid.

2. The device for driving a display panel according to claim 1, wherein, In the first time period, ground the power supply terminal of the pixel circuit.

3. The device for driving a display panel according to any one of claims 1 to 2, wherein, In the first time period, enable the source driving circuit to output a ground signal.

4. The device for driving a display panel according to any one of claims 1 to 2, wherein, The device is further configured to: in the first time period, provide a third power signal and a fourth power signal to the power supply terminal of the gate driving circuit; provide a clock signal to the gate driving circuit; and provide an invalid first start signal to the gate driving circuit.

5. The device for driving a display panel according to claim 4, wherein, In the first time period and the second time period, keep the first start signal invalid.

6. The device for driving a display panel according to any one of claims 1 to 2, is further configured to: in the third time period, enable the source driving circuit to provide a display data signal to the pixel circuit.

7. The device for driving a display panel according to any one of claims 1 to 2, wherein The display panel further includes the light emission control driving circuit for outputting a light emission control signal to the pixel circuit; The device is further configured to: in the first time period, drive the light emission control driving circuit.

8. The device for driving a display panel according to claim 7, wherein, The device is further configured to: in the first time period, provide a third power signal and a fourth power signal to the power supply terminal of the light emission control driving circuit; provide a clock signal to the light emission control driving circuit; and provide an invalid second start signal to the light emission control driving circuit.

9. The device for driving a display panel according to claim 1, wherein, In the first time period, the first start signal provided to the gate driving circuit and the second start signal provided to the light emission control driving circuit remain invalid; and wherein, in the second time period, the second start signal remains invalid.

10. The device for driving a display panel according to claim 9, wherein, In the second time period, provide a display data signal corresponding to displaying black to the pixel circuit.

11. The device for driving a display panel according to any one of claims 1 to 2, wherein, The pixel circuit includes a driving power supply terminal and a reference power supply terminal; and wherein the device is further configured to, in the second time period, Supply the first power signal and the second power signal to the driving power supply terminal; And Supply power to the reference power supply terminal.

12. The device for driving a display panel according to any one of claims 1 to 2, wherein, The first time period includes the duration of at least one display frame, and the second time period includes the duration of at least one display frame.

13. The device for driving a display panel according to any one of claims 1 to 2, wherein, The first time period and the second time period do not overlap.

14. The device for driving a display panel according to any one of claims 1 to 2, wherein, The display panel further includes a multiplexing circuit disposed between the source driver circuit and the pixel circuit; Wherein, when the source driver circuit outputs a ground signal, the multiplexing circuit is turned on.

15. The device for driving a display panel according to any one of claims 1-2, wherein, The device for driving the display panel is integrated with the display panel.

16. A device for driving a display panel, wherein the display panel includes a pixel circuit, a gate driver circuit, a light emission control driver circuit, and a source driver circuit, Among them, The gate driver circuit and the source driver circuit are respectively configured to supply a scan signal and a data signal to the pixel circuit; Wherein, the pixel circuit includes a plurality of pixel units in an array, and each pixel unit includes an OLED element; Wherein, the light emission control driver circuit is configured to output a light emission control signal to the pixel circuit; Wherein, the device is configured to: In a fourth time period, supply an invalid start signal to the gate driver circuit and the light emission control driver circuit; In a fifth time period, disconnect the first power signal and the second power signal supplied to the pixel circuit; In a sixth time period, disconnect the third power signal and the fourth power signal supplied to the gate driver circuit and the light emission control driver circuit; Wherein, in the fifth time period, supply an invalid start signal to the gate driver circuit and the light emission control driver circuit; Wherein, the pixel circuit includes a driving power supply terminal and a reference power supply terminal; wherein, in the fifth time period, the driving power supply terminal and the reference power supply terminal are grounded; Wherein, in the fifth time period, the source driver circuit outputs a ground signal.

17. The device for driving a display panel according to claim 16, wherein, In the fourth time period, supply an invalid start signal to the light emission control driver circuit.

18. The device for driving a display panel according to claim 17, wherein, In the fourth time period, supply a valid start signal to the gate driver circuit; and wherein, in the fourth time period, supply a display data signal corresponding to displaying black to the pixel circuit.

19. The device for driving a display panel according to claim 17, wherein, In the fourth time period, supply an invalid start signal to the gate driver circuit.

20. The device for driving a display panel according to claim 16, wherein, In the sixth time period, the power supply terminals of the gate driver circuit and / or the light emission control driver circuit are grounded.

21. The device for driving a display panel according to any one of claims 16-20, wherein, The device for driving the display panel is integrated with the display panel.

22. A device for driving a display panel, wherein, The display panel includes a pixel circuit, a gate driver circuit, a light emission control driver circuit, and a source driver circuit, Wherein, the gate driver circuit and the source driver circuit are respectively configured to supply a scan signal and a data signal to the pixel circuit; Wherein, the pixel circuit includes a plurality of pixel units in an array, and each pixel unit includes an OLED element; Wherein, the light emission control driver circuit is configured to output a light emission control signal to the pixel circuit; Wherein, the device is configured to: In a first time period, supply an invalid start signal to the gate driver circuit and the light emission control driver circuit; During a second time period, a first power signal and a second power signal are provided to the pixel circuit; During a third time period, a valid start signal is provided to the gate driving circuit and the light emission control driving circuit; During a fourth time period, an invalid start signal is provided to the gate driving circuit and the light emission control driving circuit; During a fifth time period, the first power signal and the second power signal provided to the pixel circuit are disconnected; and During a sixth time period, a third power signal and a fourth power signal provided to the gate driving circuit and the light emission control driving circuit are disconnected; wherein the apparatus for driving the display panel is further configured to: during the third time period, cause the source driving circuit to provide a display data signal to the pixel circuit; wherein, during the first time period and the second time period, a first start signal provided to the gate driving circuit and a second start signal provided to the light emission control driving circuit are kept invalid; and wherein, during the third time period, the second start signal remains invalid until the first start signal of the gate driving circuit becomes valid.

23. The device for driving a display panel according to claim 22, wherein, The apparatus for driving the display panel is integrated with the display panel.

24. A method of driving a display panel using the apparatus for driving a display panel according to any one of claims 1-23.

25. A display panel, comprising: A pixel circuit, a gate driving circuit, a light emission control driving circuit, a source driving circuit, and the apparatus for driving a display panel according to any one of claims 1-23.

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