A controller, method, device and medium supporting receiving multi-dp master card

Abstract

The application discloses a kind of to support, receive the controller of multiple DP master card, method, device and medium, applied to data transmission field.The controller provided in the application supports multiple DP master card, applied to the distributed control system of multi-link communication, the system includes electronic equipment, main controller and FPGA, wherein, one end of FPGA is connected with electronic equipment, the other end of FPGA is connected with main controller, for obtaining the data information needed, according to the format of data information judging the source of data information, data information is converted, interface timing is obtained, and interface timing is sent to main controller.The same controller from station equipment can be on multiple links, high speed and long distance transmission can be considered, and the cost performance is relatively high in the application scene with more measuring points.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data transmission, in particular to a controller, method, device and medium supporting and receiving multiple DP master cards. BACKGROUND

[0002] In recent years, the IO devices to be configured by the main controller of the DCS system are increasing, and the environment of each IO module and the distance from the main controller are different when the controller communicates with the IO devices, which requires that the baud rate, interval time of periodic data and other parameters of each IO module be different.

[0003] The traditional implementation method is to use multiple master controllers to implement different application modules classified under different master controllers. The most direct impact of such an implementation method is an increase in overall cost. Moreover, the controller has only one communication link, supports few slave devices, and all slave devices of the same controller are on one link, which cannot balance high speed and long distance transmission, and has low cost performance in the application scenario with many measurement points.

[0004] In view of the above-mentioned technology, seeking a design method of a controller supporting multiple DP master cards is a problem to be solved by those skilled in the art. SUMMARY

[0005] The purpose of the present application is to provide a controller, method, device and medium supporting and receiving multiple DP master cards. The controller supports many slave devices, and all slave devices of the same controller can be distributed on different links, which can balance high speed and long distance transmission and has high cost performance.

[0006] To solve the above-mentioned technical problem, the present application provides a controller supporting multiple DP master cards, which is applied to a distributed control system of multi-link communication. The system includes an electronic device, a master controller and an FPGA:

[0007] One end of the FPGA is connected to the electronic device, and the other end of the FPGA is connected to the master controller, for obtaining required data information, judging the source of the data information according to the format of the data information, converting the data information, obtaining the interface timing, and sending the interface timing to the master controller.

[0008] Preferably, the FPGA includes an asynchronous transceiver, a DP parameter configuration register, a dual-port RAM management register, a parallel bus processing interface, a timing conversion module, a dual-port RAM module, an ARM master card and a bus.

[0009] The first end of the asynchronous transceiver is connected to the electronic device, and the second end of the asynchronous transceiver is connected to the first end of the DP parameter configuration register.

[0010] The second end of the DP parameter configuration register is connected with a dual-port RAM management register, and the third end of the DP parameter configuration register is connected with a timing conversion module;

[0011] The second end of the dual-port RAM management register is connected with the first end of the parallel bus processing interface;

[0012] The second end of the timing conversion module is connected with the first end of the bus;

[0013] The second end of the bus is connected with an ARM master card, and the third end of the bus is connected with the first end of the dual-port RAM module;

[0014] The second end of the dual-port RAM module is connected with the second end of the parallel bus processing interface;

[0015] The third end of the parallel bus processing interface is connected with a master controller.

[0016] Preferably, the number of FPGAs is 1 / 2 of the number of specific links in the distributed control system of multi-link communication, wherein each FPGA supports communication of two links.

[0017] Preferably, the parallel bus processing interface adopts a 16-bit data and address interface.

[0018] To solve the above problems, the application further provides a control method supporting a multi-DP master card, applied to a distributed control system of multi-link communication, wherein the distributed control system comprises an electronic device, a master controller and an FPGA, and the method comprises:

[0019] Obtaining required data information;

[0020] Judging the source of the data information according to the format of the data information;

[0021] Converting the data information to obtain an interface timing;

[0022] Sending the interface timing to the master controller.

[0023] Preferably, converting the data information to obtain the interface timing comprises:

[0024] Timing-converting the data information to obtain a read-write timing;

[0025] Converting the read-write timing in the control register to obtain the interface timing.

[0026] Preferably, before converting the read-write timing in the control register to obtain the interface timing, the method further comprises:

[0027] According to the corresponding relationship between the data information and the address, controlling the control module to realize dual-port switching.

[0028] To solve the above problems, the application further provides a method for receiving control data of a multi-DP master card, applied to a distributed control system for multi-link communication, the system comprising an electronic device, a master controller and an FPGA, the method comprising:

[0029] receiving interface timing sent by the FPGA, wherein the interface timing is obtained by converting the data information;

[0030] receiving a processing signal of the data information;

[0031] sending the processed data information to the FPGA.

[0032] To solve the above problems, the application further provides a control device supporting a multi-DP master card, applied to a distributed control system for multi-link communication, the distributed control system comprising an electronic device, a master controller and an FPGA, the device comprising:

[0033] an acquisition module for acquiring required data information;

[0034] a judgment module for judging the source of the data information according to the format of the data information;

[0035] a conversion module for converting the data information to obtain interface timing;

[0036] a sending module for sending the interface timing to the master controller.

[0037] To solve the above problems, the application further provides a computer-readable storage medium, the computer-readable storage medium storing a computer program, the computer program being executed by a processor to implement the steps of the control method supporting a multi-DP master card.

[0038] The application provides a controller supporting a multi-DP master card, applied to a distributed control system for multi-link communication, the system comprising an electronic device, a master controller and an FPGA, wherein one end of the FPGA is connected to the electronic device, the other end of the FPGA is connected to the master controller, the FPGA is used for acquiring required data information, judging the source of the data information according to the format of the data information, converting the data information to obtain interface timing, and sending the interface timing to the master controller. The same controller from the station device can be used on multiple links, and high speed and long distance transmission can be considered at the same time, and the cost performance is relatively high in the application scenario with more measurement points. BRIEF DESCRIPTION OF DRAWINGS

[0039] To more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0040] Figure 1 A system architecture diagram for Profibus-DP communication in the DCS system;

[0041] Figure 2 A block diagram of a controller supporting multiple DP master cards provided by an embodiment of the present application;

[0042] Figure 3 A system architecture diagram of a controller supporting multiple DP master cards provided by an embodiment of the present application;

[0043] Figure 4 A general architecture of a controller supporting multiple DP master cards provided by an embodiment of the present application;

[0044] Figure 5 An internal design scheme of an FPGA provided by an embodiment of the present application;

[0045] Figure 6 A structure diagram of a Loongson interface module provided by an embodiment of the present application;

[0046] Figure 7 A flowchart of a control method supporting multiple DP master cards provided by another embodiment of the present application;

[0047] Figure 8 A module diagram of a control device supporting multiple DP master cards provided by another embodiment of the present application. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0049] The core of the present application is to provide a controller, method, device and medium supporting and receiving multiple DP master cards.

[0050] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0051] Profibus-DP is a commonly used field high-speed data bus. The master station periodically reads the input data of the slave station and periodically sends the output data to the slave station. The bus cycle time must be shorter than the master station (PLC) program cycle time. In addition to periodic user data transmission, Profibus-DP also provides non-periodic communication required by intelligent devices for configuration, diagnosis and alarm processing. Profibus-DP can connect up to 128 slave stations on the same link.

[0052] Currently, the Profibus-DP communication system in the conventional DCS system is as follows Figure 1 As shown in the figure, the Profibus-DP master station function is integrated in the master controller, and each IO module is a Profibus-DP slave station. The master station periodically accesses the slave station for data interaction.

[0053] As shown in the figure, the Profibus-DP communication system in the conventional DCS system is as follows Figure 1 As shown in the figure, the Profibus-DP communication system in the conventional DCS system is as follows

[0054] Figure 2 The block diagram of the controller supporting multiple DP master cards provided by the embodiment of the application is shown in the figure. A controller supporting multiple DP master cards is applied to a distributed control system for multi-link communication. The system includes electronic equipment, a master controller and an FPGA:

[0055] One end of the FPGA is connected to the electronic equipment, and the other end of the FPGA is connected to the master controller. The FPGA is used to obtain required data information, judge the source of the data information according to the format of the data information, convert the data information, obtain interface timing, and send the interface timing to the master controller.

[0056] In specific embodiments, as shown in the figure, the electronic equipment is 2, the FPGA is 3, and the master controller is 1. Figure 2

[0057] One end of the FPGA is connected to the electronic equipment, and the other end of the FPGA is connected to the master controller. The FPGA is used to obtain required data information, judge the source of the data information according to the format of the data information, convert the data information, obtain interface timing, and send the interface timing to the master controller.

[0058] Figure 3 ​The system architecture diagram of the controller supporting multiple DP master cards provided in the embodiment of the application is shown in the figure, the history station 1A and the history station 1B are history stations for storing data, the operator station 1.1 and the operator station 1.k are screens for operators to operate, the master controller 1 is a master controller, and the DP1-DP6 are six link communications. The slave stations are electronic devices.

[0059] In the embodiment, six independent DP links are designed in the master controller module, 128 IO slave stations can be configured for each link, different baud rates can be configured for each link independently, different functional modules can be placed in one link according to actual needs, or modules requiring redundancy can be placed in different links in a higher safety requirement field to enhance safety.

[0060] The controller supporting multiple DP master cards provided in the embodiment of the application is applied to a distributed control system of multi-link communication, and the system includes electronic devices, a master controller and an FPGA. One end of the FPGA is connected to the electronic devices, and the other end of the FPGA is connected to the master controller, for obtaining required data information, judging the source of the data information according to the format of the data information, converting the data information, obtaining interface timing, and sending the interface timing to the master controller. The slave device of the same controller can be on multiple links, and high speed and long distance transmission can be considered at the same time, and the cost performance is higher in the application scenario with more measurement points.

[0061] On the basis of the above embodiment, as a preferred embodiment, the number of FPGAs is 1 / 2 of the specific link value in the distributed control system of multi-link communication, and each FPGA supports communication of two links.

[0062] In a specific embodiment, as shown in Figure 4 , Figure 4 The overall architecture of the controller supporting multiple DP master cards provided in the embodiment of the application is shown in the figure. The DP master card and the controller are designed on the same board card. The master controller adopts a Loongson 2K1000 dual-core processor as a master CPU, responsible for IEC operation and data copying. The master card is realized by an FPGA with an M3 core. From the perspective of fault dispersion, three FPGAs are designed to realize six master card functions, that is, one FPGA realizes two DP master cards. The overall running logic is that the slave module transmits the collected field data to the DP master station through DP communication, the master controller CPU periodically obtains the input data of the DP master station, refreshes the output data area of the DP master station after IEC operation, the DP master station transmits the data to the DP slave station through communication, and the slave module outputs the controller command to drive the field device.

[0063] Each FPGA is connected to two RS-485-1 and RS-485-2, and each two is redundant.

[0064] It should be noted that the above embodiment is only one possible implementation, but is not limited to only this implementation. If eight-way communication is required, four FPGAs are needed, and the user can set it up as needed.

[0065] On the basis of the above embodiment, as a preferred embodiment, the FPGA comprises: an asynchronous transceiver, a DP parameter configuration register, a dual-port RAM management register, a parallel bus processing interface, a timing conversion module, a dual-port RAM module, an ARM master card, a bus:

[0066] The first end of the asynchronous transceiver is connected to the electronic device, and the second end of the asynchronous transceiver is connected to the first end of the DP parameter configuration register.

[0067] The second end of the DP parameter configuration register is connected to the dual-port RAM management register, and the third end of the DP parameter configuration register is connected to the timing conversion module.

[0068] The second end of the dual-port RAM management register is connected to the first end of the parallel bus processing interface.

[0069] The second end of the timing conversion module is connected to the first end of the bus.

[0070] The second end of the bus is connected to the ARM master card, and the third end of the bus is connected to the first end of the dual-port RAM module.

[0071] The second end of the dual-port RAM module is connected to the second end of the parallel bus processing interface.

[0072] The third end of the parallel bus processing interface is connected to the host controller.

[0073] In specific embodiments, Figure 5 The FPGA internal design scheme provided in the embodiments of the present application, Figure 5 corresponds to Table 1.

[0074] The connection interface of the electronic device 2 and the FPGA is 35, the asynchronous transceiver is 36, the DP parameter configuration register is 37, the dual-port RAM management register is 38, the parallel bus processing interface is 39, the Loongson 2K is the host controller 1, the ARM master card is 31, the FPGA internal bus is 32, the timing conversion module is 33, and the dual-port RAM module is 34.

[0075] The asynchronous transceiver 36 is used for receiving data of the electronic device and sending data to the electronic device; the DP parameter configuration register 37 is used for storing data formats of different electronic devices, so that the user can understand the data of different electronic devices, and the data of different electronic devices can be analyzed for different electronic devices when the data is transmitted; the dual-port RAM management register 38 is used for storing data, so that the ARM master card 31 and the Loongson 2k1 can obtain the data; the timing conversion module 33 is used for converting data; the bus is used for transmission, the dual-port RAM module 34 is used for data interaction, and the parallel bus processing interface 39 is used for data transmission.

[0076] Table I

[0077]

[0078] The Loongson communicates with three FPGAs through the LIO bus, and the high bits of the address are used for decoding in the design to distinguish different devices, that is, the chip selection function. The main function of the mpc_bus_top control module is to provide a data interaction interface between the Loongson and the FPGA. The interface adopts a parallel 16-bit data and address interface, which is used for transmitting and saving state parameters and data generated in the running process of the device, such as Figure 6 .

[0079] MPC_BUS_TOP: Loongson LIO interface top module; BRIDGE_MPC_BUS: convert the timing of the Loongson LIO interface into the register read-write timing inside;

[0080] MPC_BUS_INTERFACE: realize the dual-port RAM, DDR, tri-buffer switching control, and the read-write of other command states according to address decoding. The FPGA internally produces 128K dual-port RAM for DP data interaction, and 128K registers are used for the interaction of some commands.

[0081] The address allocation is shown in Table II.

[0082] Table II

[0083] Data address and size assigned by Loongson LIO to FPGA Start address Address space size Fpga1_reg 0x1C150000 0x10000 fpga1_dpram 0x1C160000 0x10000 fpga2_reg 0x1C250000 0x10000 fpga2_dpram 0x1C260000 0x10000 fpga3_reg 0x1C350000 0x10000 fpga3_dpram 0x1C360000 0x10000

[0084] To solve the above problems, the application further provides a control method supporting multiple DP master cards, applied to a distributed control system of multi-link communication, wherein the distributed control system comprises an electronic device, a master controller and an FPGA, and the method comprises the following flow as shown in Figure 7 .

[0085] S10: Obtain the required data information.

[0086] S11: Judge the source of the data information according to the format of the data information.

[0087] S12: converting the data information to obtain interface timing.

[0088] S13: sending the interface timing to the main controller.

[0089] In specific embodiments, the asynchronous transceiver receives the required data information, the DP parameter configuration register determines the source of the data information according to the format of the data information, the dual-port RAM management register, the parallel bus processing interface, the timing conversion module, the dual-port RAM module, the ARM master card, and the bus are used to convert the data information to obtain interface timing and send it to the main controller, i.e. the Loongson 2k.

[0090] The control method provided by the application supports multiple DP master cards and is applied to a distributed control system for multi-link communication. The system includes an electronic device, a main controller, and an FPGA. The method includes obtaining required data information, determining the source of the data information according to the format of the data information, converting the data information to obtain interface timing, and sending the interface timing to the main controller. The same controller from the station device can be on multiple links, which can balance high speed and long distance transmission, and is cost-effective in application scenarios with more measurement points.

[0091] Based on the above embodiments, as a preferred embodiment, converting the data information to obtain interface timing includes:

[0092] Timing converting the data information to obtain read-write timing;

[0093] The control register converts the read-write timing to obtain interface timing.

[0094] And before the control register converts the read-write timing to obtain interface timing, it further includes:

[0095] According to the correspondence between the data information and the address, the control module is controlled to realize dual-port switching.

[0096] Since the embodiments of the method part correspond to the embodiments of the device part, the embodiments of the method part are described in the description of the embodiments of the device part, which will not be described here.

[0097] To solve the above problems, the application further provides a method for receiving control data of multiple DP master cards, which is applied to a distributed control system for multi-link communication. The system includes an electronic device, a main controller, and an FPGA. The method includes:

[0098] Receiving interface timing sent by the FPGA, wherein the interface timing is obtained by converting the data information;

[0099] Receiving a processing signal of the data information;

[0100] The processed data information is sent to the FPGA.

[0101] In a specific embodiment, the main controller receives interface timing sent by the FPGA, wherein the interface timing is converted from the data information, and receives a processing signal of the data information, which is sent by an operator, and the main controller sends the processed data information to the FPGA, so as to realize data interaction.

[0102] Figure 8 A control device module diagram for supporting a multi-DP master card is provided for another embodiment of the present application, and is applied to a distributed control system for multi-link communication. The distributed control system includes an electronic device, a main controller and an FPGA. The device includes the following modules, as shown in Figure 8 .

[0103] The acquisition module 11 acquires the required data information.

[0104] The judgment module 12 is configured to judge the source of the data information according to the format of the data information.

[0105] The conversion module 13 is configured to convert the data information to obtain read-write timing.

[0106] The sending module 14 is configured to send the read-write timing to the main processor.

[0107] Since the embodiments of the device part correspond to the embodiments of the method part, the embodiments of the device part are described in the description of the embodiments of the method part, and are not described here.

[0108] Finally, the present application also provides a corresponding embodiment of a computer readable storage medium. The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps described in the above method embodiments.

[0109] It can be understood that if the method in the above embodiments is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and executes all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0110] The above introduces in detail a controller, method, device and medium supporting and receiving multiple DP master cards provided by the present application. The embodiments in the specification are described in a progressive manner, and each embodiment mainly explains the difference from other embodiments. The same or similar parts of each embodiment can be understood by referring to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be understood by referring to the method part. It should be pointed out that for ordinary skilled persons in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0111] It should also be noted that in the present specification, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A controller supporting multiple DP master cards, characterized in that, The application discloses a distributed control system applied to multi-link communication, which comprises an electronic device, a main controller and FPGAs; wherein the number of the FPGAs is 1 / 2 of the number of specific links in the distributed control system applied to multi-link communication, and each of the FPGAs supports communication of two links, and the communication of the two links is redundant to each other. One end of the FPGA is connected with the electronic device, and the other end of the FPGA is connected with the main controller, so as to acquire required data information, judge the source of the data information according to the format of the data information, convert the data information, obtain read-write timing, convert the read-write timing, obtain interface timing, and send the interface timing to the main controller. The FPGA comprises an asynchronous transceiver, a DP parameter configuration register, a dual-port RAM management register, a parallel bus processing interface, a timing conversion module, a dual-port RAM module, an ARM master card and a bus; wherein the parallel bus processing interface adopts a 16-bit data and address interface. The first end of the asynchronous transceiver is connected with the electronic device, and the second end of the asynchronous transceiver is connected with the first end of the DP parameter configuration register. The second end of the DP parameter configuration register is connected with the dual-port RAM management register, and the third end of the DP parameter configuration register is connected with the timing conversion module. The second end of the dual-port RAM management register is connected with the first end of the parallel bus processing interface. The second end of the timing conversion module is connected with the first end of the bus. The second end of the bus is connected with the ARM master card, and the third end of the bus is connected with the first end of the dual-port RAM module. The second end of the dual-port RAM module is connected with the second end of the parallel bus processing interface. The third end of the parallel bus processing interface is connected with the main controller.

2. A control method of supporting a multi-DP host card, the method comprising: The application discloses a distributed control system applied to multi-link communication, which comprises an electronic device, a main controller and FPGAs; wherein the number of the FPGAs is 1 / 2 of the number of specific links in the distributed control system applied to multi-link communication, and each of the FPGAs supports communication of two links, and the communication of the two links is redundant to each other. The application discloses a distributed control system applied to multi-link communication, which comprises an electronic device, a main controller and FPGAs; wherein the number of the FPGAs is 1 / 2 of the number of specific links in the distributed control system applied to multi-link communication, and each of the FPGAs supports communication of two links, and the communication of the two links is redundant to each other. The application discloses a distributed control system applied to multi-link communication, which comprises an electronic device, a main controller and FPGAs; wherein the number of the FPGAs is 1 / 2 of the number of specific links in the distributed control system applied to multi-link communication, and each of the FPGAs supports communication of two links, and the communication of the two links is redundant to each other. The application discloses a distributed control system applied to multi-link communication, which comprises an electronic device, a main controller and FPGAs; wherein the number of the FPGAs is 1 / 2 of the number of specific links in the distributed control system applied to multi-link communication, and each of the FPGAs supports communication of two links, and the communication of the two links is redundant to each other. The application discloses a distributed control system applied to multi-link communication, which comprises an electronic device, a main controller and FPGAs; wherein the number of the FPGAs is 1 / 2 of the number of specific links in the distributed control system applied to multi-link communication, and each of the FPGAs supports communication of two links, and the communication of the two links is redundant to each other. The application discloses a distributed control system applied to multi-link communication, which comprises an electronic device, a main controller and FPGAs; wherein the number of the FPGAs is 1 / 2 of the number of specific links in the distributed control system applied to multi-link communication, and each of the FPGAs supports communication of two links, and the communication of the two links is redundant to each other.

3. The control method of claim 2, wherein, ​ ​ 4. A method of receiving control data for a multi-DP host card, the method comprising: ​ ​ ​ ​ 5. A control device supporting a multi-DP host card, characterized by, ​ ​ ​ A conversion module is configured to perform timing conversion on the data information to obtain read-write timing; and a control register is configured to perform conversion on the read-write timing to obtain interface timing. A sending module is configured to send the interface timing to the host controller.

6. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the control method for supporting multiple DP master cards according to any one of claims 2 or 3.

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