A novel chip protection ring structure

Abstract

The application discloses a novel chip protection ring structure, wherein the protection ring surrounds the outside of a circuit area arranged on a chip, and comprises a first protection ring segment and a second protection ring segment; the first protection ring segment is located at the corresponding side of a first sub-circuit area and comprises, from bottom to top, a first insulating layer, a first via layer and a first metal layer which are connected to an active area of a substrate; the second protection ring segment comprises, from bottom to top, a second via layer and a second metal layer which are connected to the active area of the substrate; the first via layer and the first metal layer are connected to the second via layer and the second metal layer correspondingly; the first insulating layer is in close contact with the second via layer through the side walls thereof, so that the noise current from a second sub-circuit area is blocked by the first insulating layer when flowing along the second metal layer to the first metal layer, and the passage of the noise current to the substrate is blocked, thereby preventing the performance of sensitive devices such as analog circuits and / or radio frequency circuits in the chip from being damaged, and meanwhile, the stress protection and water vapor blocking effects are achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a novel chip protection ring structure. Background Technology

[0002] Please see Figure 1 With the development of integrated circuit technology, most semiconductor integrated circuit manufacturers will set a protective ring 13 around the semiconductor chip 10. The protective ring 13 surrounds the circuit area 15 of the chip 10 and is in contact with the chip 10. The protective ring 13 is generally composed of two inner and outer protective rings 12 and 11 between the chip 10 and the dicing groove, which can prevent moisture, corrosive gases and chemicals from penetrating into the chip.

[0003] Please see Figure 2 The traditional chip protection ring 13 structure is generally a graphic structure composed of active areas 19, vias 20, through-holes 22, and a metal layer 21 stacked according to certain design rules. The vias 20, through-holes 22, and metal layer 21 in the protection ring 13 are located within the oxide layer. A passivation layer may also be provided on the metal layer 21, thus acting like a dam to protect the chip 10. The main function of the protection ring 13 is to prevent mechanical stress damage to the chip 10 during dicing, and it also has some derivative functions: for example, grounding the protection ring 13 can shield the chip 10 from external interference; it can also prevent moisture from entering the chip 10 from the side cut.

[0004] The pads 14 on chip 10 are typically located along the outer edge of the circuit region 15 on chip 10, and are therefore very close to the guard ring 13. For a typical guard ring 13, noise currents originating from the power input signal lines or signal output pads of the digital circuit 17 in the circuit region 15 can propagate through the guard ring 13 and may enter the substrate 18 near sensitive devices such as analog and / or RF circuits 16 through conductive vias 20, which may adversely affect the performance of sensitive devices.

[0005] To address the aforementioned issues, existing improvements involve forming two breaks in the inner protection ring 12 near sensitive devices such as analog and / or RF circuits 16, creating an independent inner protection ring segment. This segment can be further coupled to an independent ground via an interconnect, or an opening can be formed in the inner protection ring near the sensitive device to reduce noise current interference. However, this structure allows the oxide layer inside the chip 10 to communicate with the oxide layer between the two protection rings 12 and 11 through the incompletely sealed protection ring 13 structure. Thus, if the outer protection ring 11 is damaged, it may communicate with the surrounding environment, failing to effectively prevent moisture from entering the chip 10. Therefore, such improved protection ring 13 structures, to varying degrees, sacrifice the moisture-blocking effect achieved by maintaining the continuity of the protection ring 13. Summary of the Invention

[0006] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide a novel chip protection ring structure.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] A novel chip protection ring structure is disclosed, wherein the protection ring surrounds a dielectric layer between a circuit region located in the center of the chip and a scribe groove located outside the circuit region. The circuit region includes a first sub-circuit region and a second sub-circuit region located on different sides of the chip. The protection ring includes a first protection ring segment and a second protection ring segment connected in a ring shape. The first protection ring segment is located on the corresponding side of the first sub-circuit region. The first protection ring segment includes, from bottom to top, a first insulating layer, a first via layer, and a first metal layer connected to an active region on a substrate. The second protection ring segment includes, from bottom to top, a second via layer and a second metal layer connected to the active region on the substrate. The first via layer, the first metal layer, the second via layer, and the second metal layer are correspondingly connected. The first insulating layer and the second via layer are in close contact through their respective sidewalls, so that the noise current originating from the second sub-circuit region is blocked by the first insulating layer from flowing downward to the substrate when it flows along the second metal layer to the first metal layer.

[0009] Furthermore, multiple protective rings are arranged in parallel.

[0010] Furthermore, the first insulating layer, the first via layer, and the second via layer are respectively provided with multiple vias from the inside out.

[0011] Furthermore, the substrate includes a P-type substrate, on which a P-well is also provided, and the P+ type active region is located on the P-well.

[0012] Furthermore, the first insulating layer comprises, from bottom to top, a stacked structure of a first oxide layer, a first semiconductor layer, and a first nitride layer, wherein the first oxide layer is connected to the active region, and the first nitride layer is connected to the first via layer.

[0013] Furthermore, the first oxide layer, the first semiconductor layer, and the first nitride layer are located on the corresponding process layers as the gate oxide layer, gate layer, and nitride layer in the gate structure provided in the circuit region.

[0014] Furthermore, the first metal layer comprises, from bottom to top, multiple layers of first metal interconnect lines and a first via layer connecting two adjacent layers of first metal interconnect lines. The second metal layer comprises, from bottom to top, multiple layers of second metal interconnect lines and a second via layer connecting two adjacent layers of second metal interconnect lines. The first metal interconnect lines are correspondingly connected to the second metal interconnect lines, and the first via layer is correspondingly connected to the second via layer.

[0015] Furthermore, the first metal interconnect line layer and the second metal interconnect line layer are located on the corresponding process level as the third metal interconnect line layer in the metal interconnect layer provided in the circuit region, and the first via layer and the second via layer are located on the corresponding process level as the third via layer in the metal interconnect layer located between two adjacent third metal interconnect line layers.

[0016] Furthermore, the first through-hole layer and the second through-hole layer are provided with multiple through-holes from the inside out.

[0017] Furthermore, the first sub-circuit region is provided with at least one of analog circuits and radio frequency circuits, and the second sub-circuit region is provided with digital circuits including power input signal lines and signal output pads.

[0018] As can be seen from the above technical solution, the present invention designs a protection ring on the substrate in the form of a multi-layer structure from bottom to top, consisting of a well region, an active region, a first insulating layer, a first via layer, and a first metal layer, on the side of the sensitive device (first sub-circuit region) where analog circuits and / or radio frequency circuits are located. This achieves the effect of not affecting the anti-cutting stress of the protection ring itself, while effectively blocking moisture from entering the chip through the complete and leak-free metal wall (first via layer and first metal layer) located in the dielectric layer. At the same time, the novel chip protection ring structure of the present invention, by setting a non-conductive first insulating layer between the first via layer and the active region, prevents the first via layer and the active region from forming a ground state due to insulation. Therefore, it can prevent noise current from flowing downward into the substrate near the sensitive device, thereby preventing damage to the performance of sensitive devices such as analog circuits and / or radio frequency circuits in the chip. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a planar structure of a traditional chip protection ring;

[0020] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure of the protective ring in the AA direction;

[0021] Figure 3 This is a planar schematic diagram of a novel chip protection ring structure according to a preferred embodiment of the present invention;

[0022] Figure 4 for Figure 3 A cross-sectional schematic diagram of a novel chip protection ring structure in the middle-BB direction;

[0023] Figure 5 for Figure 3 A cross-sectional schematic diagram of a novel chip protection ring structure in the CC direction. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0025] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0026] Please see Figure 3 , Figure 3 This is a planar schematic diagram of a novel chip protection ring structure according to a preferred embodiment of the present invention. Figure 3 As shown, a novel chip protection ring structure of the present invention includes a protection ring 203 disposed on a chip 200 and located between a circuit region 205 and a dicing groove. The circuit region 205 is located in the middle of the chip 200, and the protection ring 203 surrounds the outer side of the circuit region 205 and is located inside the dicing groove. The protection ring 203 forms a closed ring structure and, together with the circuit devices in the circuit region 205, resides in the dielectric layer on the chip 200.

[0027] Please see Figures 4-5The entire chip 200 can be built on a substrate 208, which can be a conventional semiconductor substrate 208, such as a silicon substrate 208, a germanium substrate 208, a germanium-silicon substrate 208, etc. The substrate 208 may include a P-type substrate 208. A P-well 209 may also be provided in the P-type substrate 208; a P+ type active region 210 may be provided on the P-well 209. A guard ring 203 is built on the substrate 208 and connected to the P+ type active region 210 to form the integrated guard ring 203 structure of this invention.

[0028] Please see Figure 3 Circuit region 205 includes a first sub-circuit region 206 and a second sub-circuit region 207 located on different sides of chip 200. The first sub-circuit region 206 may contain analog circuitry and / or radio frequency circuitry. The second sub-circuit region 207 may contain digital circuitry including power input signal lines and signal output pads. Each circuit in circuit region 205 has pads 204 on the surface of chip 200, and these pads 204 are typically located along the outer edge of chip 200, very close to the guard ring 203, thus easily generating crosstalk.

[0029] In some embodiments, multiple protection rings 203 may be arranged side by side on the outer side of the circuit region 205. For example, two protection rings 203 may be arranged side by side, including an inner protection ring 202 located on the inner side and an outer protection ring 201 located on the outer side of the inner protection ring 202, thereby providing dual protection for the circuit region 205 on the chip 200.

[0030] The protection ring 203 includes a first protection ring segment 2031 and a second protection ring segment 2032 connected end-to-end to form a ring structure. The first protection ring segment 2031 is located on the corresponding side of the first sub-circuit region 206, and the second protection ring segment 2032 is connected to the protection ring 203 located outside the two sides of the first sub-circuit region 206.

[0031] When the protection ring 203 has multiple rings, such as an inner protection ring 202 and an outer protection ring 201, each protection ring 203 will have a first protection ring segment 2031 and a second protection ring segment 2032 with corresponding positions.

[0032] Please see Figure 4 The diagram shows a cross-sectional structure of the first protection ring segment 2031. The first protection ring segment 2031 is located on the substrate 208 outside the first sub-circuit region 206. The first protection ring segment 2031 may include, from bottom to top, a first insulating layer 211, a first via layer 212, and a first metal layer 215 connected to the P+ active region 210 located on the P- substrate 208.

[0033] Please see Figure 5The diagram shows the cross-sectional structure of the second protection ring segment 2032. The second protection ring segment 2032 is also located on the substrate 208 and connects to both ends of the first protection ring segment 2031. That is, the second protection ring segment 2032 needs to be positioned to avoid the first sub-circuit region 206 and surround the outside of other circuit regions in the circuit region 205, including the second sub-circuit region 207, excluding the first sub-circuit region 206. The second protection ring segment 2032 may include, from bottom to top, a second via layer 217 and a second metal layer 220 connected to the P+ active region 210 located on the P- substrate 208.

[0034] Specifically, the first via layer 212 on the first protective ring segment 2031 and the second via layer 217 on the second protective ring segment 2032 are connected accordingly. The first metal layer 215 on the first protective ring segment 2031 and the second metal layer 220 on the second protective ring segment 2032 are connected accordingly. Furthermore, the first insulating layer 211 and the second via layer 217 are in close contact through their respective sidewalls.

[0035] Thus, between the circuit region 205 of the chip 200 and the dicing groove, an annular dam is formed by a protective ring 203 (first protective ring segment 2031 and second protective ring segment 2032) connected to the substrate 208, which effectively protects the chip 200. This includes preventing the chip 200 from being damaged by mechanical stress during dicing, shielding the chip 200 from external interference through grounding, and preventing moisture from entering the chip 200 from the side cut.

[0036] Meanwhile, by providing a non-conductive first insulating layer 211 between the first via layer 212 and the active region 210 on the first protection ring segment 2031, the first via layer 212 and the active region 210 cannot form a ground state due to insulation. This prevents the noise current originating from the second sub-circuit region 207 from flowing downwards to the substrate 208 along the second metal layer 220 to the first metal layer 215 of the first sub-circuit region 206. Therefore, the noise current originating from the power input signal line or signal output pad of the digital circuit (second sub-circuit region 207) can be prevented from flowing downwards into the substrate 208 near sensitive analog and / or RF circuits (first sub-circuit region 206), thus preventing damage to the performance of sensitive devices such as analog and / or RF circuits in the chip 200.

[0037] Furthermore, the novel protective ring 203 structure of the present invention does not sacrifice the moisture barrier effect of the interlayer dielectric layer (compared to the prior art). It does not allow the dielectric layer (oxide layer) inside the chip 200 to communicate with the dielectric layer (oxide layer) between the inner and outer protective rings 202 and 201 through the incompletely closed protective ring 203 structure, nor does it communicate with the external environment if the outer protective ring 201 is damaged. Therefore, it does not reduce the moisture barrier effect of the interlayer dielectric layer.

[0038] Please see Figures 4-5 In some embodiments, the first insulating layer 211, the first via layer 212, and the second via layer 217 may be provided with multiple layers corresponding to each other from the inside out. For example, Figures 4-5 The example shows an inner protective ring 202 structure with four corresponding first insulating layers 211, first via layers 212 and second via layers 217, and an outer protective ring 201 structure with two corresponding first insulating layers 211, first via layers 212 and second via layers 217.

[0039] In some embodiments, the first insulating layer 211 on the first protective ring segment 2031 may include a stacked structure of a first oxide layer, a first semiconductor layer, and a first nitride layer from bottom to top. The first oxide layer is connected to the active region 210; the first nitride layer is connected to the first via layer 212.

[0040] Furthermore, the first oxide layer, the first semiconductor layer, and the first nitride layer are located on the corresponding process layers as the gate oxide layer, gate layer, and nitride layer in the gate structure provided in the circuit region 205.

[0041] In some embodiments, the first oxide layer material may include silicon oxide, silicon oxynitride, hafnium oxide, etc.

[0042] In some embodiments, the material of the first semiconductor layer may include materials such as polycrystalline silicon.

[0043] In some embodiments, the first nitride layer material may include materials such as silicon nitride.

[0044] In some embodiments, the first via layer 212 and the second via layer 217 may include tungsten vias, aluminum vias, copper vias, or alloy vias.

[0045] Please see Figures 4-5 In some embodiments, the first metal layer 215 may include, from bottom to top, multiple layers of first metal interconnect lines 214, and a first via layer 213 connecting adjacent layers of first metal interconnect lines 214. The second metal layer 220 may include, from bottom to top, multiple layers of second metal interconnect lines 219, and a second via layer 218 connecting adjacent layers of second metal interconnect lines 219. For example, Figures 4-5 The example shows a structure with three layers of first metal interconnect line layers 214 and second metal interconnect line layers 219, and four first via layers 213 / second via layers 218 located between two adjacent layers of first metal interconnect line layers 214 / second metal interconnect line layers 219 on the inner protective ring 202, and two first via layers 213 / second via layers 218 located between two adjacent layers of first metal interconnect line layers 214 / second metal interconnect line layers 219 on the outer protective ring 201.

[0046] In some embodiments, a first top metal interconnect layer 223 / second top metal interconnect layer 222, and a first top via layer 216 / second top via layer 221 connecting the uppermost first metal interconnect layer 214 / second metal interconnect layer 219 of the first metal layer 215 / second metal layer 220 may be further provided. The first top metal interconnect layer 223 / second top metal interconnect layer 222 can be used to form the pad 204 structure.

[0047] Specifically, the first metal interconnect layer 214 is connected to the second metal interconnect layer 219, and the first via layer 213 is connected to the second via layer 218. The first top metal interconnect layer 223 is connected to the second top metal interconnect layer 222, and the first top via layer 216 is connected to the second top via layer 221. Together with the first insulating layer 211, the first via layer 212, and the second via layer 217, they form a closed protective ring 203 structure.

[0048] Furthermore, the first metal interconnect layer 214 and the second metal interconnect layer 219 are located on the corresponding process level as the third metal interconnect layer in the metal interconnect layer provided in the circuit region 205, and the first via layer 213 and the second via layer 218 are located on the corresponding process level as the third via layer in the metal interconnect layer located between two adjacent third metal interconnect layers.

[0049] Furthermore, the first top metal interconnect layer 223 and the second top metal interconnect layer 222 are located on the corresponding process layers as the third top metal interconnect layer on the uppermost third metal interconnect layer in the circuit region 205, and the first top via layer 216 and the second top via layer 221 are located on the corresponding process layers as the third top via layer between the uppermost third metal interconnect layer and the third top metal interconnect layer.

[0050] In some embodiments, the first metal interconnect layer 214 and the second metal interconnect layer 219, the first top metal interconnect layer 223 and the second top metal interconnect layer 222 may be made of metals such as copper and aluminum.

[0051] In some embodiments, the first through-hole layer 213 and the second through-hole layer 218, the first top through-hole layer 216 and the second top through-hole layer 221 may be tungsten through-holes, copper through-holes, aluminum through-holes or alloy through-holes, etc.

[0052] The dielectric layer material may include silicon oxide, silicon oxynitride, hafnium oxide, etc.

[0053] Therefore, the active region 210, the first insulating layer 211, the first via layer 212 / second via layer 217, and the first metal layer 215 / second metal layer 220 in the novel chip protection ring 203 structure of the present invention can be fabricated simultaneously using the same process and materials as the active region 210, gate structure, via structure, and metal interconnect layer structure located at the same process level in the circuit region 205 (of course, the polysilicon layer (first semiconductor layer) in the first insulating layer 211 can omit the doping process step).

[0054] In summary, this invention designs a multi-layered structure on the substrate 208 on the side of the sensitive device (first sub-circuit region 206) containing analog circuits and / or radio frequency circuits. This structure comprises a well 209 region, an active region 210, a first insulating layer 211, a first via layer 212, and a first metal layer 215, arranged from bottom to top. This achieves both the protection ring 203's anti-cutting stress function and the effective prevention of moisture from entering the chip 200 by relying on the intact and leak-free metal walls (first via layer 212 and first metal layer 215) located in the dielectric layer. Furthermore, the novel chip protection ring 203 structure of this invention, by providing a non-conductive first insulating layer 211 between the first via layer 212 and the active region 210, prevents the first via layer 212 from forming a ground state with the active region 210. This prevents noise current from flowing downwards into the substrate 208 near the sensitive device, thus avoiding damage to the performance of sensitive devices such as analog circuits and / or radio frequency circuits in the chip 200.

[0055] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A novel chip protection ring structure, characterized in that, The protective ring surrounds a dielectric layer between a circuit region located in the center of the chip and a scribe groove located outside the circuit region. The circuit region includes a first sub-circuit region and a second sub-circuit region located on different sides of the chip. The protective ring includes a first protective ring segment and a second protective ring segment connected in a ring shape. The first protective ring segment is located on the corresponding side of the first sub-circuit region. The first protective ring segment includes, from bottom to top, a first insulating layer, a first via layer, and a first metal layer connected to an active region on the substrate. The second protective ring segment includes, from bottom to top, a second via layer and a second metal layer connected to the active region on the substrate. The first insulating layer prevents the first via layer from forming a ground state due to insulation with the active region. The first via layer, the first metal layer, the second via layer, and the second metal layer are correspondingly connected. The first insulating layer and the second via layer are in close contact through their respective sidewalls, so that the noise current originating from the second sub-circuit region is blocked by the first insulating layer from flowing downward to the substrate when it flows along the second metal layer to the first metal layer.

2. The novel chip protection ring structure according to claim 1, characterized in that, Multiple protective rings are arranged in parallel.

3. The novel chip protection ring structure according to claim 1, characterized in that, The first insulating layer, the first via layer, and the second via layer are provided with multiple vias from the inside out.

4. The novel chip protection ring structure according to claim 1, characterized in that, The substrate includes a P-type substrate, on which a P-well is further provided, and the P+ type active region is located on the P-well.

5. The novel chip protection ring structure according to claim 1, characterized in that, The first insulating layer comprises, from bottom to top, a stacked structure of a first oxide layer, a first semiconductor layer, and a first nitride layer, wherein the first oxide layer is connected to the active region and the first nitride layer is connected to the first via layer.

6. The novel chip protection ring structure according to claim 5, characterized in that, The first oxide layer, the first semiconductor layer, and the first nitride layer are located at the corresponding process layers as the gate oxide layer, gate layer, and nitride layer in the gate structure provided in the circuit region.

7. The novel chip protection ring structure according to claim 1, characterized in that, The first metal layer comprises, from bottom to top, multiple layers of first metal interconnect lines and a first via layer connecting two adjacent layers of first metal interconnect lines. The second metal layer comprises, from bottom to top, multiple layers of second metal interconnect lines and a second via layer connecting two adjacent layers of second metal interconnect lines. The first metal interconnect lines are correspondingly connected to the second metal interconnect lines, and the first via layer is correspondingly connected to the second via layer.

8. The novel chip protection ring structure according to claim 7, characterized in that, The first metal interconnect layer and the second metal interconnect layer are located at the corresponding process level to the third metal interconnect layer in the metal interconnect layer provided in the circuit region. The first via layer and the second via layer are located at the corresponding process level to the third via layer located between two adjacent third metal interconnect layers in the metal interconnect layer.

9. The novel chip protection ring structure according to claim 7, characterized in that, The first through-hole layer and the second through-hole layer are provided with multiple through-holes from the inside out.

10. The novel chip protection ring structure according to claim 1, characterized in that, The first sub-circuit region is provided with at least one of analog circuits and radio frequency circuits, and the second sub-circuit region is provided with digital circuits including power input signal lines and signal output pads.

Images