An array substrate and a display device

Abstract

An embodiment of the present application discloses an array substrate and a display device. The array substrate includes a display area and a non-display area. The display area includes a first display area and a second display area. Among them, the fan-out line electrically connected to the target signal line in the second display area includes a target connection lead extending along a first direction in the display area. The target connection line in the non-display area is electrically connected to the target signal line through the target connection lead. In this way, by designing part of the fan-out line electrically connected to the target signal line in the display area, and using the target connection lead extending along the first direction in the display area, the length of the fan-out line electrically connected to the target signal line in the second display area is extended, thereby reducing the resistance difference between the fan-out line electrically connected to the signal line in the second display area and the existing fan-out line electrically connected to the signal line in the first display area, and improving the problem of display screen splitting.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and more specifically, to an array substrate and a display device. Background Art

[0002] Currently, in the design of display screens, narrow-bezel screen bodies have gradually emerged. With the progress of products, the bezels of the screen bodies are continuously reduced, and a borderless design has emerged. However, due to the large number of traces in the non-display area of the screen body, which occupies a large amount of space, in order to reduce the bezel, the prior art adopts the technology of distributing some of the traces of the fan-out lines in the display area (fanout in AA, FIAA), that is, in the prior art solution, the signal lines located at the edge are electrically connected to the connection lines in the non-display area through the connection leads located in the display area, and the signal lines located in the middle are directly electrically connected to the connection lines in the non-display area. However, in the prior art solution, since the signal lines located at the edge are electrically connected to the signal lines in the non-display area through the connection leads located in the display area, and the fan-out lines electrically connected to the signal lines in the middle do not include the connection leads, there is a difference in the resistance of the two types of fan-out lines, resulting in the problem of uneven display of the display screen. Summary of the Invention

[0003] The purpose of the present application is to provide an array substrate and a display device. For the fan-out lines electrically connected to the signal lines corresponding to the second display area in the array substrate, a method of designing part of the traces in the display area is also adopted. The connection lines in the non-display area are electrically connected to the signal lines through the connection leads designed in the display area. In this way, the resistance difference between the fan-out lines electrically connected to the signal lines in the second display area and the existing fan-out lines electrically connected to the signal lines in the first display area is reduced, and the problem of display screen splitting is improved.

[0004] To achieve the above purpose:

[0005] In a first aspect, the present application provides an array substrate. The array substrate includes a display area and at least a part of a non-display area surrounding the display area. The array substrate includes signal lines, a first connection lead, and a target connection lead located in the display area, and also includes a first connection line and a target connection line located in the non-display area. The display area includes a first display area and a second display area. The signal lines include a first signal line and a target signal line. The first signal line is located in the first display area, and the target signal line is located in the second display area; the first signal line is electrically connected to the first connection line through the first connection lead; the target signal line is electrically connected to the target connection line through the target connection lead;

[0006] Wherein, the target connection lead extends along a first direction, the first connection lead includes a first sub-segment extending along the first direction and a second sub-segment extending along a second direction, and the second sub-segment overlaps at least one of the signal lines; the first direction is the same as the extending direction of the signal lines, and the second direction intersects with the first direction.

[0007] In a second aspect, the present application further provides a display device, and the display device includes the array substrate according to any one of the first aspect.

[0008] In an embodiment of the present application, an array substrate and a display device are provided. The array substrate includes a display area and a non-display area. The display area includes a first display area and a second display area. Wherein, the fan-out line electrically connected to the target signal line in the second display area includes a target connection lead arranged in the display area and extending along a first direction. The target connection line in the non-display area is electrically connected to the target signal line through the target connection lead. In this way, by designing part of the fan-out line electrically connected to the target signal line in the display area, and using the target connection lead extending along the first direction in the display area, the length of the fan-out line electrically connected to the target signal line in the second display area is extended, thereby reducing the resistance difference between the fan-out line electrically connected to the signal line in the second display area and the existing fan-out line electrically connected to the signal line in the first display area, and improving the problem of display split screen. Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0010] Figure 1 It is a top view schematic diagram of an array substrate in the prior art;

[0011] Figure 2 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application;

[0012] Figure 3 It is a top view schematic diagram of another array substrate provided by an embodiment of the present application;

[0013] Figure 4 It is a top view schematic diagram of still another array substrate provided by an embodiment of the present application;

[0014] Figure 5 It is a top view schematic diagram of yet another array substrate provided by an embodiment of the present application;

[0015] Figure 6 Another top view schematic diagram of an array substrate provided by an embodiment of the present application;

[0016] Figure 7 Another top view schematic diagram of an array substrate provided by an embodiment of the present application;

[0017] Figure 8 Another top view schematic diagram of an array substrate provided by an embodiment of the present application;

[0018] Figure 9 For an embodiment of the present application Figure 8 A cross-sectional schematic diagram at the position of the tangent line z-z' in the middle;

[0019] Figure 10 For an embodiment of the present application Figure 8 A cross-sectional schematic diagram at the position of the tangent line q-q' in the middle;

[0020] Figure 11 A schematic diagram of a display device provided by an embodiment of the present application. Embodiment

[0021] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0022] Currently, in the design of display screens, narrow-bezel screen bodies have gradually emerged. With the progress of products, the bezels of the screen bodies are continuously reduced. However, due to the large number of traces in the non-display area of the screen body, which occupy a large amount of space, in order to reduce the bezel, a technology of distributing some of the fan-out lines in the display area (fanout in AA, FIAA) is adopted. In the existing solution, the signal lines located at the edge are electrically connected to the connection lines in the non-display area through the connection leads located in the display area, and the signal lines located in the middle are directly electrically connected to the connection lines in the non-display area.

[0023] Specifically, Figure 1 A top view schematic diagram of an array substrate in the prior art, see Figure 1As shown in the figure, the array substrate includes a display area B and a non-display area A. The display area B includes a first display area B1 and a second display area B2. In the existing array substrate, the fan-out line electrically connected to the target signal line a1 located in the second display area B2 includes the target connection line a3 located in the non-display area A. The fan-out line electrically connected to the target signal line a1 is entirely arranged in the non-display area A, that is, the signal line in the middle is directly electrically connected to the connection line in the non-display area. However, the fan-out line electrically connected to the first signal line b1 includes the first connection line b3 located in the non-display area A and the first connection lead b2 in the display area B. Among them, the first connection lead b2 includes b21 extending along the y direction shown in the figure and b22 extending along the x direction shown in the figure. That is, the signal line at the edge is electrically connected to the connection line in the non-display area A through the connection lead in the display area B, and the fan-out line electrically connected to the target signal line does not include this connection lead. Therefore, the lengths of the fan-out line connected to the target signal line and the fan-out line connected to the first signal line are different, resulting in different resistances and causing the problem of uneven display of the display screen.

[0024] In the embodiment of the present application, in view of the situation in the prior art solution where the fan-out lines connected to the target signal line and the fan-out lines connected to the first signal line have different resistances and uneven display occurs, the following technical solutions are adopted for improvement: The fan-out line electrically connected to the target signal line in the second display area includes a target connection lead extending along the first direction arranged in the display area and a target connection line arranged in the non-display area. The target connection line in the non-display area is electrically connected to the target signal line through this target connection lead; in this way, by designing part of the fan-out line electrically connected to the target signal line in the display area, and using the target connection lead extending along the first direction in the display area to extend the length of the fan-out line electrically connected to the target signal line, the resistance difference between the fan-out line electrically connected to the target signal line and the existing fan-out line electrically connected to the first signal line is reduced, and the problem of uneven display of the display screen is improved.

[0025] Next, a detailed introduction to an array substrate in the present application will be given:

[0026] Appendix Figure 2 is a top view schematic diagram of an array substrate provided by an embodiment of the present application. Refer to Appendix Figure 2As shown, in the embodiment of the present application, the array substrate includes a display area B and at least a part of a non-display area A surrounding the display area. The array substrate includes signal lines, a first connection lead b2, and a target connection lead a2 located in the display area B, and further includes a first connection line b3 and a target connection line a3 located in the non-display area A. The display area includes a first display area B1 and a second display area B2. The signal lines include a first signal line b1 and a target signal line a1. The first signal line b1 is located in the first display area B1, and the target signal line a1 is located in the second display area B2. The first signal line b1 is electrically connected to the first connection line b3 through the first connection lead b2. The target signal line a1 is electrically connected to the target connection line a3 through the target connection lead a2.

[0027] Among them, the target connection lead a2 extends along a first direction y. The first connection lead b2 includes a first sub-segment b21 extending along the first direction y and a second sub-segment b22 extending along a second direction x, and the second sub-segment overlaps at least one of the signal lines. The first direction y is the same as the extension direction of the signal lines, and the second direction x intersects the first direction y.

[0028] Specifically, in this embodiment of the present application, the second sub-segment b22 included in the first connection lead b2 needs to cross at least one signal line to connect to the first signal line b1. Specifically, at least one of the signal lines overlapping with the second sub-segment is insulated from the second sub-segment b22.

[0029] It should be noted that the signal line can be a data line, and in other embodiments, it can also be other types of signal lines, which are specifically determined according to the used scenario and are not limited here. The driving chip IC is generally arranged in the non-display area of the lower border of the screen. The signal line is electrically connected to the driving chip through a fan-out line to obtain a pixel data signal. Among them, when the signal line is a data line, a column of pixels (not shown in the figure) in the display area B corresponds to one data line, and the data line generally adopts a vertically extending wiring method, as shown in the figure.

[0030] Specifically, in this embodiment of the present application, it is schematically shown that there are first display areas on both sides of the second display area. One first display area B1, the second display area B2, and another first display area B1 are arranged in a direction perpendicular to the first direction y. In other embodiments, there may also be a first display area on only one side of the second display area, and the present application does not limit this.

[0031] It should be noted that, in order to improve the strength and aesthetics of the display screen, rounded corners are respectively formed at the four corners of the screen body during the design process, and the edge pixels in the area where the rounded corners need to be formed are removed along the arc, corresponding to the formation of a chamfered area. In the embodiments of the present application, when the screen has a chamfered area, the range of the first display area can be part of the column pixels included in the chamfered area or all of the column pixels included in the chamfered area, or can be the column pixels included in the chamfered area and part of the column pixels close to the chamfered area. No limitation is made here, and those skilled in the art can determine according to the actual situation, which are all within the protection scope of the present application.

[0032] It should be noted that, in the embodiments of the present application, the second direction x can also be perpendicular to the first direction y, and the second direction x can also intersect the first direction y at any angle.

[0033] Further, Figure 3 shows a top view schematic diagram of an array substrate. Referring to Figure 3 , in the embodiments of the present application, the second sub-segment b22 of the first connection lead b2 extends along the second direction x, and the second direction x can intersect the first direction y at any angle. Among them, Figure 3 shows one of the embodiments, and does not limit the angle at which the second direction x intersects the first direction y.

[0034] Further, Figure 4 shows another top view schematic diagram of an array substrate, which is a schematic diagram of a possible wiring method in the actual wiring situation. Referring to Figure 4 as shown, the array substrate in the embodiments of the present application may further include that the wiring direction of the target connection lead a2 as a whole extends along the first direction y, including a wiring method with a deviation and inclination, that is, the target connection lead a2 can extend along the first direction y or along a direction y' that is inclined at a preset angle θ with respect to the first direction y. The preset angle θ can be determined according to the actual situation without causing the target connection lead a2 to intersect other data lines.

[0035] Further, Figure 5 shows another top view schematic diagram of an array substrate. Referring to Figure 5 , in the array substrate in the embodiments of the present application: the first connection lead b2 may further include a third sub-segment b23, and the third sub-segment b23 extends along the first direction y. The second sub-segment b22 is electrically connected to the first signal line b1 through the third sub-segment b23.

[0036] Further, in the array substrate in the embodiments of the present application: at least part of the length of the first connection line b3 is equal to at least part of the length of the target connection line a3. Specifically, it can be as shown in Figure 2For the array substrate shown, when there is sufficient space in the non-display area, in the embodiments of the present application, the connection lines in the non-display area B include a first connection line b3 and a target connection line a3. The first connection line b3 is electrically connected to the driving chip IC and extends in the first direction y, and then is connected to the corresponding connection lead; it can also be as shown in the appendix Figure 6 For the array substrate shown in the appendix, the wiring in the non-display area is in a fan-out form, that is, the further to the two sides, the longer the connection lines in the non-display area. The following explains two wiring methods for the connection lines in the non-display area:

[0037] On the one hand, for the wiring method of the connection lines in the non-display area B as shown in the appendix Figure 2 when there is sufficient space in the non-display area B, in the embodiments of the present application, the connection lines in the non-display area B include a first connection line b3 and a target connection line a3, which can be electrically connected to the driving chip IC, extend in the first direction y, and then are connected to the corresponding connection leads.

[0038] In this embodiment of the present application, the length of the target connection lead a2 is determined according to the resistance to be compensated. Since the first connection lead b2 needs to cross the pixels and be connected to the first signal line b1 in the first display area B2, that is, it needs to wind around, resulting in a difference in resistance. Since the resistance is determined by the resistivity, cross-sectional area, and length of the wire, but since the difference in the cross-sectional area of the traces on the array substrate is very small, in order to improve the processing efficiency, the difference in the cross-sectional area can be ignored here. Therefore, when the length of the first connection line b3 and the target connection line a3 in the non-display area is the same and the resistivity of the connection lines is the same, only the resistance difference between the target connection lead a2 and the first connection line b3 needs to be considered, so that the resistance to be compensated of the target connection lead a2 is equal to the resistance of the first connection lead b2, thereby solving the problem of resistance difference.

[0039] On the other hand, for the wiring method of the connection lines in the non-display area as shown in the appendix Figure 6 when the wiring in the non-display area is in a fan-out form, that is, the further to the two sides, the longer the connection lines in the non-display area. Since the wiring length of the connection lines on both sides of the non-display area gradually increases, the resistance of the connection lines on both sides is greater than the resistance of the connection lines near the middle position, that is, the wiring length of the target connection line a3 gradually increases towards the two sides of the frame, the resistance of the first connection line b3 is greater than the resistance of the target connection line a3, and the wiring length of the corresponding target connection lead a2 is longer the closer it is to the middle position. Through the compensation of the wiring length, the overall resistance is made equal.

[0040] Specifically, in this embodiment of the present application, the array substrate:

[0041] The second display area B2 includes a first area B2-1 and a second area B2-2, the first area B2-1 is located between the second area B2-2 and the first display area B1, and the length of the target connecting lead a2 at least partially located in the second area B2-2 is greater than the length of the target connecting lead a2 at least partially located in the first area B2-1.

[0042] Furthermore, the array substrate of the embodiment of the present application may further include: along a third direction k, the length of the target connection lead a2 gradually shortens; the third direction k is a direction from the second area B2-2 to the first area B2-1.

[0043] It should be noted that the length of the target connecting lead a2 is the total length of the target connecting lead a2 on the array substrate.

[0044] For further information, see the attached Figure 6 The array substrate of the embodiment of the present application may further include: when the resistance of the target connection lead a2 to be compensated is large, that is, the total wiring length required for the target connection lead a2 is long, the target connection lead a2 can be wired in a folded wiring manner, that is, when the target connection lead a2 reaches the edge away from the driver chip, it is routed through a horizontal line and then looped back, as shown in the attached figure. Figure 6 The target connecting line a3 is shown as being bent back in the second region. Specifically, the target connecting line a2 includes a first target line segment a21, a second target line segment a22, and a third target line segment a23. The first target line segment a21 is electrically connected to the third target line segment a23 via the second target line segment a22. The first target line segment a21 and the third target line segment a23 extend along the first direction y, and the second target line segment a22 extends along a fourth direction h, which intersects the first direction y.

[0045] It should be noted that the fourth direction h may be the same as or different from the third direction k.

[0046] Furthermore, in the array substrate of the embodiment of the present application, the resistivity of the first connecting line may be the same as or different from the resistivity of the target connecting line.

[0047] Below, two situations are described respectively:

[0048] In the first aspect, when the resistivity of the first connecting line is the same as the resistivity of the target connecting line:

[0049] In the embodiment of the present application, the conductive layer used for the first connection line may be the same as the conductive layer used for the target connection line. Specifically, the array substrate includes a substrate, a first conductive layer, a second conductive layer, a fourth conductive layer, and a fifth conductive layer. The first conductive layer is located on one side of the substrate, the second conductive layer is located on the side of the first conductive layer away from the substrate, the fourth conductive layer is located on the side of the second conductive layer away from the substrate, and the fifth conductive layer is located on the side of the fourth conductive layer away from the substrate. Among them, the first connection line and the target connection line may be disposed on the first conductive layer (i.e., on the same layer as the gate of the thin film transistor (TFT)) and / or the second conductive layer (i.e., on the same layer as the pixel region capacitor). When the conductive layer used for the first connection line is the same as the conductive layer used for the target connection line, since the first connection lead includes a lateral connection lead that spans the pixel and requires wire winding, the wire winding results in a relatively large resistance of the first connection lead. Thus, the greater the resistance of the target connection lead that needs to be compensated.

[0050] Among them, the first sub-segment of the first connection lead is disposed on the same layer as the target connection lead, the target connection lead is disposed on the fifth conductive layer (i.e., on the same layer as the power line), and the second sub-segment of the first connection lead is disposed on the fourth conductive layer (i.e., on the same layer as the data line).

[0051] Among them, the target signal line may be disposed on the fourth conductive layer or the fifth conductive layer. Specifically, the target connection lead is disposed on the same layer as the target signal line; or, the target connection lead and the target signal line are disposed on different conductive layers, and the target connection lead and the target signal line are connected through a via.

[0052] Optionally, the materials used for the conductive layers in the array substrate are different; specifically, the first conductive layer and the second conductive layer include a molybdenum metal layer. The fourth conductive layer and the fifth conductive layer each include three sub-conductive layers, which are, in the direction perpendicular to the substrate, a titanium metal layer, an aluminum metal layer, and a titanium metal layer in sequence.

[0053] Specifically, when the target signal line adopts the fifth conductive layer, refer to Appendix Figure 2 and Appendix Figure 6 , the target connection lead a2 can be directly connected to the target signal line a1 through a lead on the same conductive layer. The wiring method of the fan-out line in this embodiment may be as follows:

[0054] (1)Fan-out lines electrically connected to the first signal line b1: including a first connection line b3, a first sub-segment b21, and a second sub-segment b22; wherein, the first connection line b3 is located in the first conductive layer and / or the second conductive layer, and in the non-display area A, it is connected to the first sub-segment b21 of the fifth conductive layer through a via (not shown in the figure), then in the fifth conductive layer, it is connected to the second sub-segment b22 of the fourth conductive layer through a via (not shown in the figure), and then the second sub-segment is connected to the first signal line b1 of the fifth conductive layer through a via (not shown in the figure).

[0055] It should be noted that referring to the appendix Figure 5 , the first connection lead b2 may further include a third sub-segment b23, the third sub-segment b23 extends in the first direction y, the second sub-segment b22 is electrically connected to the first signal line b1 through the third sub-segment b23, and the third sub-segment b23 uses the same conductive layer as the first sub-segment b21, that is, the first connection lead b2 may further include a third sub-segment b23 using the fifth conductive layer, the second sub-segment b22 is electrically connected to the third sub-segment b23 of the fifth conductive layer through a via (not shown in the figure), and then the third sub-segment b23 is directly connected to the first signal line b1 of the fourth conductive layer.

[0056] (2)Fan-out lines electrically connected to the target signal line a1: including a target connection line a3 and a target connection lead a2; wherein, the target connection line a3 uses the first conductive layer and / or the second conductive layer, and in the non-display area A, it is connected to the target connection lead a2 of the fifth conductive layer through a via (not shown in the figure), and then the target connection lead a2 is directly connected to the target signal line a1 of the fifth conductive layer.

[0057] It should be noted that referring to the appendix Figure 6 , when the wiring length of the target connection lead a2 is too long and a fold-back design is required, that is, when the target connection lead a2 includes a first target segment a21, a second target segment a22, and a third target segment a23, the first target segment a21, the second target segment a22, and the third target segment a23 are all arranged in the fifth conductive layer.

[0058] Specifically, when the target signal line a1 uses the fourth conductive layer, referring to the appendix Figure 7 , appendix Figure 8 and appendix Figure 9 , where the schematic cross-sectional view of the array substrate in appendix Figure 9 is a cross-section of an array substrate at the tangent z-z' position in appendix Figure 8 , where appendix Figure 9 only shows some film layers of the cross-section of the array substrate. Specifically, appendix Figure 9It includes an insulating layer N4 and an insulating layer N5, a target connection lead a2 located on the fifth conductive layer M4, and a target signal line a1 located on the fourth conductive layer M3. Among them, the target connection lead a2 of the fifth conductive layer M4 is electrically connected to the target signal line a1 of the fourth conductive layer M3 through a via O. In this embodiment, the wiring method of the fan-out line can be as follows:

[0059] (1) The fan-out line electrically connected to the first signal line b1: It includes a first connection line a3, a first sub-segment b21, and a second sub-segment b22; among them, the first connection line b3 is arranged on the first conductive layer and / or the second conductive layer, and is connected to the first sub-segment b21 of the fifth conductive layer through a via (not shown in the figure) in the non-display area A, and then is connected to the second sub-segment b22 of the fourth conductive layer through a via (not shown in the figure), and then the second sub-segment b22 is directly connected to the first signal line b1.

[0060] It should be noted that referring to the appendix Figure 5 , the first connection lead b2 may further include a third sub-segment b23. The third sub-segment b23 extends in the first direction y. The second sub-segment b22 is electrically connected to the first signal line b1 through the third sub-segment b23. The third sub-segment b23 is arranged on the same conductive layer as the first sub-segment b21, that is, the first connection lead b2 may further include a third sub-segment b23 using the fifth conductive layer. The second sub-segment b22 is electrically connected to the third sub-segment b23 of the fifth conductive layer through a via (not shown in the figure), and then the third sub-segment b23 is connected to the first signal line b1 of the fourth conductive layer through a via (not shown in the figure).

[0061] (2) The fan-out line electrically connected to the target signal line a1: It includes a target connection line a3 and a target connection lead a2; among them, the target connection line a3 is arranged on the first conductive layer and / or the second conductive layer, and is connected to the target connection lead a2 of the fifth conductive layer through a via (not shown in the figure) in the non-display area A, and then the target connection lead a2 is electrically connected to the target signal line a1 of the fourth conductive layer through a via (not shown in the figure).

[0062] It should be noted that when the wiring length of the target connection lead a2 is too long and a fold-back design is required, that is, when the target connection lead a2 includes a first target segment a21, a second target segment a22, and a third target segment a23, the first target segment a21, the second target segment a22, and the third target segment a23 are all arranged on the fifth conductive layer.

[0063] Second aspect, when the resistivity of the first connection line is different from that of the target connection line:

[0064] Since the first connection lead includes a second sub-segment extending in the second direction across the pixel, wire routing is required, which results in a relatively large resistance of the first connection lead. To further reduce the routing length of the target connection line and save the space occupied by the routing, for the connection lines in the non-display area, the resistance can be further compensated by reducing the resistance of the first connection line. The resistance of the first connection line is minimized as much as possible. In this way, the shorter the routing length of the target connection lead to be compensated, specifically, the resistivity of the first connection line is less than the resistivity of the target connection lead.

[0065] Among them, the first connection line and the target connection line in the non-display area can be arranged in a conductive layer with a resistivity such that the resistivity of the conductive layer corresponding to the first connection line is less than the resistivity of the target connection line. Specifically: The array substrate includes a substrate, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. The first conductive layer is located on one side of the substrate, the second conductive layer is located on the side of the first conductive layer away from the substrate, the third conductive layer is located on the side of the second conductive layer away from the substrate, and the fourth conductive layer is located on the side of the third conductive layer away from the substrate; among them, the target connection line is disposed in the first conductive layer and / or the second conductive layer, and the first connection line is disposed in the third conductive layer and / or the fourth conductive layer. The array substrate further includes a fifth conductive layer, and the fifth conductive layer is located on the side of the fourth conductive layer away from the substrate. The target connection line can be disposed in the first conductive layer (i.e., on the same layer as the gate of the thin film transistor (TFT)) and / or the second conductive layer (i.e., on the same layer as the pixel area capacitor), and the first connection line can be disposed in the third conductive layer (i.e., on the same layer as the source and drain of the TFT) and / or the fourth conductive layer (i.e., on the same layer as the data line).

[0066] It should be noted that the first sub-segment of the first connection lead is disposed on the same layer as the target connection lead. The target connection lead is disposed in the fifth conductive layer (i.e., on the same layer as the power line), the second sub-segment of the first connection lead is disposed in the fourth conductive layer (i.e., on the same layer as the data line), and the target signal line can be disposed in the fourth conductive layer (i.e., on the same layer as the data line) or the fifth conductive layer (i.e., on the same layer as the power line).

[0067] Among them, the materials used for the conductive layers in the array substrate are different; specifically, the first conductive layer and the second conductive layer include a molybdenum metal layer. The third conductive layer, the fourth conductive layer, and the fifth conductive layer each include three sub-conductive layers, which are, in order from the direction perpendicular to the substrate, a titanium metal layer, an aluminum metal layer, and a titanium metal layer.

[0068] Specifically, different from the solution where the upper part of the first connection line b3 and the target connection line a3 use the same conductive layer, in this embodiment of the present application, the target connection line a3 is disposed on the first conductive layer and / or the second conductive layer, and the first connection line b3 is disposed on the third conductive layer and / or the fourth conductive layer. In terms of the specific connection method: among the fan-out lines electrically connected to the first signal line b1, the first connection line b3 is disposed on the third conductive layer and / or the fourth conductive layer, and in the non-display area A, it is connected to the first sub-segment b21 of the fifth conductive layer through a via. Among the fan-out lines electrically connected to the target signal line a1: the target connection line a3 is disposed on the first conductive layer and / or the second conductive layer, and in the non-display area A, it is connected to the target connection lead b2 of the fifth conductive layer through a via.

[0069] It should be noted that an insulating layer is provided between the conductive layers to prevent short-circuit problems between the conductive layers. Specifically, the insulating layer between the first conductive layer and the second conductive layer is an inorganic insulating material, such as silicon oxide; the insulating layer between the second conductive layer and the third conductive layer is also an inorganic insulating material; the insulating layer between the third conductive layer and the fourth conductive layer is an organic insulating material; the insulating layer between the fourth conductive layer and the fifth conductive layer is an organic insulating material, such as polyimide. The above specific insulating materials are only examples, and the specific materials of the insulating layer of the present application are not limited here. Any insulating material that can be used in the array substrate is within the protection scope of the present application.

[0070] Furthermore, in the array substrate of this embodiment of the present application, when the target connection line is disposed on the first conductive layer and / or the second conductive layer, and the first connection line is disposed on the third conductive layer and / or the fourth conductive layer, in order to save the space resources occupied by the wiring, a part of the wiring of the target connection line and the first connection line can be overlapped in the direction perpendicular to the plane of the substrate. Specifically, at least part of the target connection line and at least part of the first connection line are overlapped in the direction perpendicular to the plane of the substrate.

[0071] On the other hand, as shown in the cross-sectional schematic diagram of the array substrate Figure 10 shown, this cross-sectional schematic diagram of the array substrate is Figure 8A cross-section of an array substrate at the position of the middle tangent q-q'. The array substrate includes a first conductive layer M1, a second conductive layer MC, a third conductive layer M2, and a fourth conductive layer M3. An insulating layer is provided between every two conductive layers. Optionally, the insulating layer N1 and the insulating layer N2 are inorganic insulating layers, and the insulating layer N3 and the insulating layer N4 are organic insulating layers. To reduce the capacitive interference between lines, some target connection lines and some first connection lines can be overlapped with each other in different layers. Specifically, at least some of the target connection lines provided in the first conductive layer M1 overlap with at least some of the first connection lines provided in the third conductive layer M2 in a direction perpendicular to the plane where the substrate SUB is located; at least some of the target connection lines provided in the second conductive layer MC overlap with at least some of the first connection lines provided in the fourth conductive layer M3 in a direction perpendicular to the plane where the substrate SUB is located.

[0072] In the embodiment of the present application, improvements are made through the above design scheme of the array substrate: the array substrate includes a display area and a non-display area. The display area includes a first display area and a second display area. Among them, the fan-out lines electrically connected to the target signal lines in the second display area include target connection leads arranged in the display area and extending along a first direction. The target connection lines in the non-display area are electrically connected to the target signal lines through the target connection leads. In this way, by designing some of the fan-out lines electrically connected to the target signal lines in the display area, and using the target connection leads extending along the first direction in the display area, the length of the fan-out lines electrically connected to the target signal lines in the second display area is extended, thereby reducing the resistance difference between the fan-out lines electrically connected to the signal lines in the second display area and the existing fan-out lines electrically connected to the signal lines in the first display area, and improving the problem of display split screen.

[0073] Please refer to Figure 11 , Figure 11 which is a schematic diagram of a display device 100 provided by an embodiment of the present application. The display device 100 includes the above array substrate.

[0074] Among them, the specific structure of the array substrate has been described in detail in the above embodiments and will not be elaborated here. Of course, Figure 11 the shown display device is only for illustrative purposes, and the display device can be any electronic device with a display function such as a mobile phone, a tablet computer, a laptop computer, an e-book, or a television.

[0075] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An array substrate, characterized in that, The array substrate includes a display area and a non-display area at least partially surrounding the display area. The array substrate includes signal lines, first connection leads, and target connection leads located in the display area, and also includes a first connection line and a target connection line located in the non-display area. The display area includes a first display area and a second display area. The signal lines include a first signal line and a target signal line. The first signal line is located in the first display area, and the target signal line is located in the second display area. The first signal line is electrically connected to the first connection line through the first connection lead. The target signal line is electrically connected to the target connection line through the target connection lead. Wherein, the target connection lead extends in a first direction. The first connection lead includes a first sub-segment extending in the first direction and a second sub-segment extending in a second direction, and the second sub-segment overlaps at least one of the signal lines. The first direction is the same as the extension direction of the signal lines, and the second direction intersects the first direction. The second display area includes a first region and a second region. The first region is located between the second region and the first display area. The length of at least part of the target connection lead located in the second region is greater than the length of at least part of the target connection lead located in the first region.

2. The array substrate according to claim 1, wherein At least one of the signal lines overlapping with the second sub-segment is insulated from the second sub-segment.

3. The array substrate according to claim 1, wherein, Along a third direction, the length of the target connection lead gradually decreases. The third direction is the direction from the second region to the first region.

4. The array substrate according to claim 1, wherein The target connection lead includes a first target segment, a second target segment, and a third target segment. The first target segment is electrically connected to the third target segment through the second target segment. The first target segment and the third target segment extend in the first direction, and the second target segment extends in a fourth direction. The fourth direction intersects the first direction.

5. The array substrate according to claim 1, wherein The resistivity of the first connection line is less than the resistivity of the target connection line.

6. The array substrate according to claim 5, wherein, The array substrate includes a substrate, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. The first conductive layer is located on one side of the substrate. The second conductive layer is located on the side of the first conductive layer away from the substrate. The third conductive layer is located on the side of the second conductive layer away from the substrate. The fourth conductive layer is located on the side of the third conductive layer away from the substrate. Wherein, the target connection line is disposed on the first conductive layer and / or the second conductive layer, and the first connection line is disposed on the third conductive layer and / or the fourth conductive layer.

7. The array substrate according to claim 6, wherein The first conductive layer and the second conductive layer include a molybdenum metal layer. The third conductive layer and the fourth conductive layer each include three sub-conductive layers, which are, in order along the direction perpendicular to the substrate, a titanium metal layer, an aluminum metal layer, and a titanium metal layer.

8. The array substrate according to claim 6, wherein, At least part of the target connection line overlaps at least part of the first connection line in the direction perpendicular to the plane of the substrate.

9. The array substrate according to claim 8, wherein At least a part of the target connection line disposed on the first conductive layer overlaps at least a part of the first connection line disposed on the third conductive layer in a direction perpendicular to the plane of the substrate; at least a part of the target connection line disposed on the second conductive layer overlaps at least a part of the first connection line disposed on the fourth conductive layer in a direction perpendicular to the plane of the substrate.

10. The array substrate according to claim 1, wherein The first sub-segment is disposed on the same layer as the target connection lead.

11. The array substrate according to claim 1, wherein, The target connection lead is disposed on the same layer as the target signal line; Or, The target connection lead and the target signal line are disposed on different conductive layers, and the target connection lead and the target signal line are connected by vias.

12. The array substrate according to claim 1, wherein The signal line is a data line.

13. A display device, characterized in that, The display device includes the array substrate according to any one of claims 1-12.

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