Image sensors, camera modules and electronic devices

Abstract

The present application discloses an image sensor, a camera module, and an electronic device, belonging to the field of image processing technology. The device comprises: a pixel array, a conversion gain selection logic module, and a cache row decoding driver module; the pixel array comprises N rows of pixel units and M columns of pixel units, the N pixel units in the same column being connected to the conversion gain selection logic module via a first connection line; the M pixel units in the same row being connected to the cache row decoding driver module via a second connection line; the conversion gain selection logic module being configured to determine a dual-gain mode selection signal corresponding to each pixel unit based on a first pixel output signal of each pixel unit; and the pixel unit being configured to write the corresponding dual-gain mode selection signal to the pixel unit upon receiving a cache control signal sent by the cache row decoding driver module, where M and N are both positive integers.

Description

Technical Field

[0001] The present application belongs to the field of image processing technology, and specifically relates to an image sensor, a camera module and an electronic device. Background Art

[0002] In a Complementry Metal-Oxide Semiconductor (CMOS) image sensor, the dynamic range of an image is generally adjusted by changing the pixel exposure time of all pixels and performing an overall adjustment on the pixel signal gain.

[0003] In mainstream High Dynamic Range (HDR) or Wide Dynamic Range (WDR) technologies, whether using multi-frame, row-interleaved, or dual-gain schemes, all pixels use the same exposure time. The HDR modulation effect is modified by adjusting the exposure time and the output signal gain. For example, in Dual Conversion Gain (DCG) technology, all pixels use the same long or short exposure, but the output signal is amplified with different gains, meaning the readout signal is amplified with high or low gain.

[0004] However, in the related art, based on the DCG-HDR function, due to the inability to perform pixel-by-pixel modulation during implementation, all pixel units in the pixel array often need to be exposed in high gain (High Conversion Gain, HCG) mode first, and then exposed in low gain (Low Conversion Gain, LCG) mode after reading. This method not only has high requirements for computing power, but also the synthesized HDR image often has brightness / color stratification and signal-to-noise ratio (SNR) differences due to processing defects. For example, in scenes with complex changes in brightness and darkness, the existing DCG-HDR technology outputs images in some scenes where some pixels are locally overexposed or some pixels are underexposed. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide an image sensor, a camera module and an electronic device that can solve the problem of poor output image imaging effect caused by the inability to perform pixel-by-pixel modulation during the implementation of the DCG-HDR function.

[0006] In a first aspect, an embodiment of the present application provides an image sensor, comprising: a pixel array, a conversion gain selection logic module, and a cache line decoding driver module;

[0007] The pixel array includes N rows of pixel units and M columns of pixel units, the N pixel units in the same column are connected to the conversion gain selection logic module via a first connection line; the M pixel units in the same row are connected to the cache row decoding driver module via a second connection line;

[0008] The conversion gain selection logic module is used to determine the dual gain mode selection signal corresponding to each pixel unit according to the first pixel output signal of each pixel unit;

[0009] The pixel unit is used to write a dual-gain mode selection signal corresponding to the pixel unit when receiving a cache control signal sent by the cache row decoding driving module, where M and N are both positive integers.

[0010] In a second aspect, an embodiment of the present application provides a camera module comprising the image sensor as described in the first aspect.

[0011] In a third aspect, an embodiment of the present application provides an electronic device comprising the camera module as described in the second aspect.

[0012] In an embodiment of the present application, the conversion gain selection logic module can automatically determine the corresponding dual-gain mode selection signal for each pixel unit based on the sampling of the pixel output signal of each pixel unit, and send the dual-gain mode selection signal to the corresponding pixel unit, so that each pixel unit can determine whether it should operate in high-gain mode or low-gain mode according to the dual-gain mode selection signal within each frame time, thereby realizing pixel-level gain adjustment, avoiding the high computing power requirements and poor adjustment effect caused by the overall adjustment of the pixel array, and the adjustment mode of each pixel unit is determined based on the pixel output signal in the current time, ensuring the accuracy and effectiveness of the pixel adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Schematic diagram of the structure of a pixel array in the related art;

[0014] Figure 2 This is one of the schematic diagrams of the image sensor structure provided in an embodiment of the present application;

[0015] Figure 3 This is one of the schematic diagrams of the conversion gain selection logic module structure provided in an embodiment of the present application;

[0016] Figure 4 This is a second structural diagram of an image sensor provided in an embodiment of the present application;

[0017] Figure 5 This is the second structural diagram of the conversion gain selection logic module provided in an embodiment of the present application;

[0018] Figure 6 This is the third structural diagram of the image sensor provided in the embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0020] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0021] The image sensor, camera module, and electronic device provided in the embodiments of the present application are described in detail below with reference to specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0022] In related technologies, the implementation of DCG-HDR technology relies on the improvement of the traditional 4-in-1 pixel array (4-Transistor Active Pixel Sensor, 4T-APS) pixels. Figure 1 is a structural diagram of a pixel array in related art, such as Figure 1 As shown, a traditional RGGB pixel array or a composite pixel array (such as a 4-in-1 pixel array) includes components for implementing the DCG function in the pixel circuit module: a typical design is a DCG transistor and a corresponding capacitor C.

[0023] The basic operating principle is as follows: The photodiode (PD) in the pixel's optical module is responsible for light sensing and photoelectric conversion during each frame. The generated charge e- is buffered in the floating diffusion (FD) capacitor after passing through the TX transistor switch. During the readout phase, the charge e- in the FD is amplified by the source follower (SF) transistor and converted into a corresponding voltage. After passing through the SEL transistor switch, the pixel signal PIX_OUT is output to the outside of the pixel. The RST transistor is responsible for resetting the FD to voltage VDD. The DCG function is implemented by changing the size of the FD. In HCG mode, the FD needs to be as small as possible. In LCG mode, the FD needs to be as large as possible. Therefore, a DCG transistor switch and capacitor C are added. The DCG transistor switch is responsible for switching between HCG and LCG modes, while capacitor C is responsible for expanding the FD capacitance. When the pixel needs to be in HCG mode, the DCG transistor switch is turned off, and the FD is responsible for receiving the charge e- transferred from the PD. When the pixel needs to operate in LCG mode, the DCG transistor closes, connecting FD and C to expand the capacitance (the RST transistor switch must remain open to prevent resetting). Therefore, the charge e- transferred from PD is FD + C. In summary, the essential method for implementing DCG function is to adjust the size of FD capacitance according to the needs.

[0024] In the field of computational photography, pixel-by-pixel control technology can achieve pixel-level dynamic range control to avoid image overexposure or underexposure. Specifically, it can encode overexposed or underexposed pixels pixel by pixel and perform gain control, which can effectively eliminate the problem of overexposure or underexposure. By modulating a single pixel, the problem of overly abrupt regional edges can be effectively avoided.

[0025] Figure 2 This is one of the schematic diagrams of the image sensor structure provided in the embodiment of the present application, such as Figure 2 As shown, it includes: a pixel array 11, a conversion gain selection logic module 12, and a cache row decoding driving module 13;

[0026] The pixel array 11 includes N rows of pixel units and M columns of pixel units 110. The M pixel units 110 in the same row are connected to the cache row decoding and driving module 13 via a second connection line 111; the N pixel units 110 in the same column are connected to the conversion gain selection logic module 12 via a first connection line 112.

[0027] The conversion gain selection logic module 12 is configured to determine a dual gain mode selection signal corresponding to each pixel unit 110 according to the first pixel output signal of each pixel unit 110 ;

[0028] The pixel unit 110 is configured to write a dual-gain mode selection signal corresponding to the pixel unit 110 upon receiving a cache control signal sent by the cache row decoding driving module 13 , where M and N are both positive integers.

[0029] Specifically, the pixel array described in the embodiment of the present application includes multiple pixel units, which may specifically include N pixel rows in the same row and M pixel columns in the same column, corresponding to NxM pixel units in each pixel array.

[0030] In the embodiment of the present application, the conversion gain selection logic module and the cache row decoding driver module both use a row / column parallel wiring layout to transmit or control signals to the pixel array.

[0031] Specifically, in order to further save wiring space, the M pixel units in the same row are connected to the cache row decoding driver module through the same connection line. Accordingly, each pixel row in the pixel array is connected to the cache row decoding driver module through its corresponding connection line.

[0032] Accordingly, the cache row decoding driving module may transmit a cache control signal to each pixel row respectively. More specifically, the cache row decoding driving module may transmit a corresponding cache control signal to each pixel unit in the pixel row.

[0033] Specifically, also for the consideration of saving wiring space, the N pixel units in the same column may also be connected to the conversion gain selection logic module through the same connection line.

[0034] The first pixel output signal of the pixel unit described in the embodiment of the present application can specifically be the pixel output signal output by the pixel unit in the current frame after reset and exposure processing. The first pixel output signal of each pixel unit can be a different pixel output signal.

[0035] The conversion gain selection logic module described in the embodiment of the present application is specifically used to further determine whether each pixel unit is suitable for high gain mode or low gain mode based on the first pixel output signal of each pixel unit, and then obtain the dual gain mode selection signal corresponding to each pixel unit.

[0036] In an embodiment of the present application, the dual gain mode selection signal corresponding to each pixel unit can be a digital signal or an analog signal. The dual gain mode selection signal will control the pixel unit to output the pixel signal according to the gain mode indicated by the dual gain mode selection signal within this frame time.

[0037] The cache row decoding driver module described in the embodiments of the present application may specifically include a decoder and a driver controlled by a control logic unit. The cache row decoding driver module may output a cache control signal for one or more pixel rows. After the pixel unit receives the cache control signal, it may activate the cache within the pixel unit and write a dual-gain mode selection signal into the cache of the pixel unit, so that when the pixel output signal is subsequently read, the pixel output signal may be gain amplified according to the gain mode indicated by the dual-gain mode selection signal.

[0038] In an embodiment of the present application, the conversion gain selection logic module can automatically determine the corresponding dual-gain mode selection signal for each pixel unit based on the sampling of the pixel output signal of each pixel unit, and send the dual-gain mode selection signal to the corresponding pixel unit, so that each pixel unit can determine whether it should operate in high-gain mode or low-gain mode according to the dual-gain mode selection signal within each frame time, thereby realizing pixel-level gain adjustment, avoiding the high computing power requirements and poor adjustment effect caused by the overall adjustment of the pixel array, and the adjustment mode of each pixel unit is determined based on the pixel output signal in the current time, ensuring the accuracy and effectiveness of the pixel adjustment.

[0039] Optionally, the pixel unit specifically includes: an in-pixel cache device, the in-pixel cache device is connected to the cache row decoding driver module via the first connection line;

[0040] The in-pixel buffer device is used to buffer the dual-gain mode selection signal.

[0041] More specifically, in the embodiment of the present application, an in-pixel cache device is newly provided in each pixel unit, and the in-pixel cache module is specifically used to cache the dual-gain mode selection signal of the pixel unit within the current frame time.

[0042] The in-pixel cache devices of the pixel units in the same row are all connected to the cache row decoding driver module through the first connecting line. After the cache row decoding driver module determines the dual-gain mode selection signal corresponding to each pixel unit based on the first pixel output signal of each pixel unit, it will transmit the dual-gain mode selection signal corresponding to each pixel unit to the in-pixel cache device through the first connecting line.

[0043] After the pixel unit receives the cache control signal sent by the cache row decoding driver module, the pixel unit activates the in-pixel cache device, receives the dual-gain mode selection signal output by the cache row decoding driver module through the first connection line, writes the received dual-gain mode selection signal into the in-pixel cache device, and deletes the dual-gain mode selection signal of the previous frame originally stored in the in-pixel cache device.

[0044] In an embodiment of the present application, the dual-gain mode selection signal corresponding to each pixel unit can be stored separately through the in-pixel cache device, which can effectively realize pixel adjustment on a pixel-by-pixel basis. Moreover, the in-pixel cache device can effectively update the dual-gain mode selection signal in the in-pixel cache device within each frame time, effectively realizing pixel adjustment processing on a time frame-by-time frame basis, thereby ensuring the accuracy of image adjustment.

[0045] Optionally, the conversion gain selection logic module includes: M first conversion gain selection logic submodules, the first conversion gain selection logic submodule includes: a first mode selection unit and a first analog-to-digital conversion unit, the first mode selection unit and the first analog-to-digital conversion unit are connected;

[0046] The pixel units in the same column are connected to the corresponding first analog-to-digital conversion unit via a third connection line, and the in-pixel buffer devices in the pixel units in the same column are connected to the corresponding first mode selection unit via the first connection line;

[0047] The first analog-to-digital conversion unit is used to perform analog-to-digital conversion on the first pixel output signal of the pixel unit to obtain a first pixel output digital signal;

[0048] The first mode selection unit is used to analyze the first pixel output digital signal to obtain a dual-gain mode selection signal, and transmit the dual-gain mode selection signal to the in-pixel buffer device of the corresponding pixel unit.

[0049] Figure 3 This is one of the schematic diagrams of the conversion gain selection logic module structure provided in the embodiment of the present application, such as Figure 3 As shown, it includes: each first conversion gain selection logic submodule 121 includes: a first mode selection unit 1211 and a first analog-to-digital conversion unit 1212, the first analog-to-digital conversion unit can be specifically a successive approximation register, the first mode selection unit 1211 and the first analog-to-digital conversion unit 1212 are connected, Figure 4 This is the second structural diagram of the image sensor provided in the embodiment of the present application, as shown in FIG. Figure 4 As shown, the first conversion gain selection logic submodule 121 includes: a first mode selection unit 1211 and a first analog-to-digital conversion unit 1212. The pixel unit 110 in each pixel column can be connected to its corresponding first conversion gain selection logic submodule 121 through a third connection line, that is, M pixel columns are connected to M first conversion gain selection logic submodules.

[0050] More specifically, in an embodiment of the present application, each pixel unit in the same column is connected to its corresponding first analog-to-digital conversion unit through a third connecting line, and at the same time, the pixel in-pixel cache device in the pixel unit in the same column is connected to the corresponding first mode selection unit through the first connecting line.

[0051] The first analog-to-digital conversion unit is a successive approximation register;

[0052] The successive approximation register is used to convert the first pixel output signal into a 2-bit digital signal through successive approximation register logic to obtain a first pixel output digital signal.

[0053] More specifically, the first pixel output signal of each pixel unit in the pixel column first enters the first analog-to-digital conversion unit through the third connection line to perform analog-to-digital conversion processing, converting the first pixel output signal into a digital signal to obtain a first pixel output digital signal.

[0054] More specifically, the first analog-to-digital conversion unit in the embodiment of the present application can employ a successive approximation register (SAR) analog-to-digital conversion architecture with a 2-bit resolution. The first pixel output signal (φPIX) is converted into a 2-bit digital signal (SAR_OUT[S1, S0]), i.e., the first pixel output digital signal, via successive approximation register logic (SAR Logic).

[0055] V in the first analog-to-digital conversion unit SAR and V REF To modulate the bias voltage, the user can change the input voltage range and resolution of the first analog-to-digital conversion unit by changing the magnitudes of these two voltages.

[0056] More specifically, the first mode selection unit performs mode selection analysis based on the digital information output by the first pixel, thereby obtaining a dual-gain mode selection signal for each pixel unit.

[0057] After calculating and obtaining the dual-gain mode selection signal, the first mode selection unit may transmit the dual-gain selection signal corresponding to each pixel unit to the in-pixel buffer device of the pixel unit through the first connection line.

[0058] Optionally, the first mode selection unit includes: a first adder and a mode selection logic subunit;

[0059] The first adder is used to add the first pixel output digital signal and a preset increase threshold signal to obtain an adder output signal;

[0060] The mode selection logic subunit is used to obtain a dual-gain mode selection signal according to the adder output signal, and transmit the dual-gain mode selection signal to the in-pixel buffer device of the corresponding pixel unit.

[0061] More specifically, in the embodiment of the present application, the user may also wish to artificially increase the output value of the first pixel output digital signal SAR_OUT[S1, S0], and therefore a first adder may be further added to the first mode selection unit. The first adder may specifically be a 2-bit adder that cooperates with the 2-bit first pixel output digital signal.

[0062] The preset increase threshold signal described in the embodiment of the present application may specifically be a preset increase threshold signal CG_THR[T1, T0].

[0063] Specifically, the first adder may add the first pixel output digital signal SAR_OUT[S1, S0] and the preset increase threshold signal CG_THR[T1, T0] to obtain an adder output signal, and then send the adder output signal to the logic selection unit for processing.

[0064] The mode selection logic subunit in the embodiment of the present application may be specifically configured with a preset truth table, which may specifically match the dual-gain mode selection signal corresponding to the adder output signal through truth table 1.

[0065] For example, truth table 1 is shown in Table 1 below:

[0066] Table 1

[0067]

[0068] Where [C, A1, A0] is the adder output signal, (φDCG_SEL) is the dual-gain mode selection signal. When (ΦDCG_SEL) is 0, the dual-gain mode selection signal corresponds to the low-gain mode. When (ΦDCG_SEL) is 1, the dual-gain mode selection signal corresponds to the high-gain mode.

[0069] Optionally, in an embodiment of the present application, a user-controlled master control signal CG_SET[I1, I0] is preset in the selection logic subunit. Through this preset master control signal, the form of the output dual-gain mode selection signal can be specified, thereby achieving normal operation in high-gain or low-gain mode to capture and output images when the conversion gain selection logic module is shielded or fails.

[0070] The mode selection logic subunit analyzes and obtains the dual-gain mode selection signal corresponding to each pixel, and transmits the dual-gain mode selection signal to the pixel buffer device in the corresponding pixel unit.

[0071] In an embodiment of the present application, the first pixel output signal is sampled by a first conversion gain selection logic submodule including a first analog-to-digital conversion unit, and the first analog-to-digital conversion unit can adopt a high-speed, low-power analog-to-digital conversion unit, which can effectively increase the mode selection rate and reduce operating power consumption. At the same time, the generation of the dual-gain mode selection signal does not rely on the intervention of external equipment.

[0072] Optionally, the conversion gain selection logic module includes: M second conversion gain selection logic sub-modules, the second conversion gain selection logic sub-module includes: a second mode selection unit and a comparator unit, and the second mode selection unit is connected to the comparator unit;

[0073] The pixel units in the same column are connected to the corresponding comparator units via a fourth connection line, and the in-pixel buffer devices in the pixel units in the same column are connected to the corresponding second mode selection units via the first connection line.

[0074] The comparator unit is configured to obtain a comparator unit output signal according to a preset modulation bias voltage signal and the first pixel output signal;

[0075] The second mode selection unit is configured to determine a dual-gain mode selection signal according to an output signal of the comparator unit, and transmit the dual-gain mode selection signal to an in-pixel buffer device of a corresponding pixel unit.

[0076] Figure 5 This is the second schematic diagram of the conversion gain selection logic module structure provided in the embodiment of the present application, as shown in FIG. Figure 5 As shown, it includes: M second conversion gain selection logic submodules 141, the second conversion gain selection logic submodule 141 includes: a second mode selection unit 1411 and a comparator unit 1412, and the second mode selection unit 1411 and the comparator unit 1412 are connected;

[0077] Figure 6 The third structural diagram of the image sensor provided in the embodiment of the present application is as follows: Figure 6 As shown, the second conversion gain selection logic submodule 141 includes: a second mode selection unit 1411 and a comparator unit 1412. The pixel unit 110 in each pixel column can be connected to its corresponding second conversion gain selection logic submodule 141 through a fourth connection line, that is, M pixel columns are connected to M second conversion gain selection logic submodules.

[0078] More specifically, the pixel column is directly connected to the comparator unit in the second conversion gain selection logic submodule through the fourth connection line. The second mode selection unit is connected in series after the comparator unit. The first pixel output signal of each pixel unit is first input into the comparator unit and the preset modulation bias voltage signal V THR Perform comparative analysis and obtain the comparator unit output signal based on the comparative analysis result.

[0079] The second mode selection unit will further perform gain mode analysis based on the output signal of the comparator unit to obtain a dual gain mode selection signal corresponding to each pixel unit, and then the second mode selection unit will transmit the dual gain mode selection signal to the pixel cache device in the corresponding pixel unit through the first connecting line.

[0080] Optionally, the comparator unit is specifically configured to:

[0081] When the preset modulation bias voltage signal is greater than the first pixel output signal, the comparator unit outputs a low-level output signal;

[0082] When the preset modulation bias voltage signal is less than or equal to the first pixel output signal, the comparator unit output signal is a high-level output signal;

[0083] Wherein, the second mode selection unit is used to determine that the dual-gain mode selection signal is a low-gain mode selection signal according to the low-level output signal;

[0084] Alternatively, the second mode selection unit is configured to determine, based on the high-level output signal, that the dual-gain mode selection signal is a high-gain mode selection signal.

[0085] The preset modulation bias voltage signal described in the embodiment of the present application may be an externally input voltage signal, the voltage magnitude and period of which may be pre-modulated by the user.

[0086] After entering the comparator unit, the first pixel output signal inputted by each pixel unit is firstly compared with the preset modulation bias voltage signal.

[0087] When the preset modulation bias voltage signal is greater than the first pixel output signal, the comparator unit always outputs a low level (COMP_OUT=0), that is, the output signal of the comparator unit at this time is a low level output signal.

[0088] When the preset modulation bias voltage signal is less than or equal to the first pixel output signal, the comparator unit always outputs a high level (COMP_OUT=1), that is, the comparator unit output signal at this time is a high level output signal.

[0089] After obtaining the output signal of the comparator unit, it is input into the second mode selection unit for calculation. The second mode selection unit can be configured with a preset truth table 2, and the dual gain mode selection corresponding to the comparator unit output is matched through truth table 2.

[0090] For example, truth table 2 is shown in Table 2 below:

[0091]

[0092] Among them, COMP_OUT is the output signal of the comparator unit. When the output signal of the comparator unit is a low-level output signal 0, the dual-gain mode selection signal (ΦDCG_SEL) is determined to be the low-gain mode selection signal 0. When the output signal of the comparator unit is a high-level output signal 1, the dual-gain mode selection signal is determined to be the high-gain mode selection signal 1.

[0093] Optionally, the second mode selection unit in the embodiment of the present application is also pre-configured with a user-controlled master control signal CG_SET[I1, I0]. This pre-set master control signal can specify the form of the output dual-gain mode selection signal, thereby enabling normal operation in high-gain or low-gain mode to capture and output images even if the conversion gain selection logic module is blocked or fails.

[0094] In the embodiment of the present application, a simple comparator unit is used to effectively improve the efficiency of generating the gain mode selection signal, while effectively reducing the area occupied by the conversion gain selection logic module in the image sensor. The conversion gain selection logic module calculates the corresponding dual gain mode selection signal for the first pixel output signal of each pixel unit, which can effectively implement gain mode adjustment for each pixel unit and effectively ensure the final imaging effect.

[0095] Optionally, the pixel array further includes: a signal reading module;

[0096] The N pixel units in the same column are connected to the signal reading module via a fifth connecting line;

[0097] The signal reading module is used to read the second pixel output signal of each pixel unit, and the second pixel output signal is obtained after the pixel unit performs signal gain processing according to the signal gain mode corresponding to the written dual gain mode selection signal.

[0098] Specifically, the fifth connecting line described in the embodiment of the present application may be the same connecting line as the third connecting line or the fourth connecting line in the above embodiment.

[0099] In the embodiment of the present application, within each frame time, after each pixel unit completes resetting and exposure, it enters the reading phase, at which time the signal reading module reads the pixel output signal of each pixel unit.

[0100] In the process of reading the pixel output signal, the gain mode corresponding to the pixel unit is determined according to the dual gain mode selection signal cached by the intra-pixel cache device in each pixel unit, that is, whether each pixel unit is suitable for high gain mode or low gain mode.

[0101] In the process of reading the pixel output signal, the signal is output according to the gain mode corresponding to the pixel unit, and finally a second pixel output signal after gain processing is obtained.

[0102] Optionally, in an embodiment of the present application, after obtaining the second pixel output signal, the second pixel output signal can be used as the first pixel output signal in the next frame time to help each pixel unit in the next frame select its corresponding dual gain mode selection signal.

[0103] In an optional embodiment, the conversion gain selection logic module described in the embodiments of the present application can be specifically a simple decoder, and the dual gain mode selection signal required by each pixel unit can be specifically provided by an external module. The dual gain mode selection signal required by each pixel unit can be issued through the conversion gain selection logic module.

[0104] Optionally, an embodiment of the present application also provides a camera module including the above-mentioned image sensor, through which pixel-by-pixel modulation can be performed in the process of realizing the DCG-HDR function, thereby effectively ensuring the imaging effect of the output image.

[0105] Optionally, an embodiment of the present application further provides an electronic device, which includes the camera module in the above embodiment, and the electronic device can be a terminal or other device other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc., and can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), an ATM or a self-service machine, etc., and the embodiment of the present application does not make specific limitations.

[0106] The electronic device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0107] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0108] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0109] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. An image sensor, characterized in that: include: Pixel array, conversion gain selection logic module, cache row decoding driver module, analog-to-digital conversion module and column scanner; The pixel array includes N rows of pixel units and M columns of pixel units, the N pixel units in the same column are connected to the conversion gain selection logic module via a first connection line; the M pixel units in the same row are connected to the cache row decoding driver module via a second connection line; the N pixel units in the same column are connected to the analog-to-digital conversion module via a third connection line, and the analog-to-digital conversion module is connected to the column scanner; The conversion gain selection logic module is used to determine the dual gain mode selection signal corresponding to each pixel unit according to the first pixel output signal of each pixel unit; The pixel unit is used to write the dual gain mode selection signal corresponding to the pixel unit when receiving the cache control signal sent by the cache row decoding driver module, where M and N are both positive integers; wherein the conversion gain selection logic module is a low-power module with low computing power requirements.

2. The image sensor according to claim 1, wherein The pixel unit specifically includes: an in-pixel cache device, the in-pixel cache device is connected to the cache row decoding driver module via the first connection line; The in-pixel buffer device is used to buffer the dual-gain mode selection signal.

3. The image sensor according to claim 2, wherein: The conversion gain selection logic module includes: M first conversion gain selection logic submodules, the first conversion gain selection logic submodule includes: a first mode selection unit and a first analog-to-digital conversion unit, the first mode selection unit and the first analog-to-digital conversion unit are connected; The pixel units in the same column are connected to the corresponding first analog-to-digital conversion units through the third connection line, and the in-pixel buffer devices in the pixel units in the same column are connected to the corresponding first mode selection unit through the first connection line; The first analog-to-digital conversion unit is used to perform analog-to-digital conversion on the first pixel output signal of the pixel unit to obtain a first pixel output digital signal; The first mode selection unit is used to analyze the first pixel output digital signal to obtain a dual-gain mode selection signal, and transmit the dual-gain mode selection signal to the in-pixel buffer device of the corresponding pixel unit.

4. The image sensor according to claim 3, wherein: The first analog-to-digital conversion unit is a successive approximation register; The successive approximation register is used to convert the first pixel output signal into a 2-bit digital signal through successive approximation register logic to obtain a first pixel output digital signal.

5. The image sensor according to claim 3, wherein: The first mode selection unit includes: a first adder and a mode selection logic subunit; The first adder is used to add the first pixel output digital signal and a preset increase threshold signal to obtain an adder output signal; The mode selection logic subunit is used to obtain a dual-gain mode selection signal according to the adder output signal, and transmit the dual-gain mode selection signal to the in-pixel buffer device of the corresponding pixel unit.

6. The image sensor according to claim 2, wherein: The conversion gain selection logic module includes: M second conversion gain selection logic submodules, the second conversion gain selection logic submodule includes: a second mode selection unit and a comparator unit, the second mode selection unit is connected to the comparator unit; The pixel units in the same column are connected to the corresponding comparator units via a fourth connection line, and the in-pixel buffer devices in the pixel units in the same column are connected to the corresponding second mode selection units via the first connection line. The comparator unit is configured to obtain a comparator unit output signal according to a preset modulated bias voltage signal and the first pixel output signal; The second mode selection unit is configured to determine a dual-gain mode selection signal according to an output signal of the comparator unit, and transmit the dual-gain mode selection signal to an in-pixel buffer device of a corresponding pixel unit.

7. The image sensor according to claim 6, wherein: The comparator unit is specifically used for: When the preset modulation bias voltage signal is greater than the first pixel output signal, the comparator unit outputs a low-level output signal; When the preset modulation bias voltage signal is less than or equal to the first pixel output signal, the comparator unit output signal is a high-level output signal; Wherein, the second mode selection unit is used to determine that the dual-gain mode selection signal is a low-gain mode selection signal according to the low-level output signal; Alternatively, the second mode selection unit is configured to determine, based on the high-level output signal, that the dual-gain mode selection signal is a high-gain mode selection signal.

8. The image sensor according to claim 1, wherein The pixel array further includes: a signal reading module; The N pixel units in the same column are connected to the signal reading module via a fifth connecting line; The signal reading module is used to read the second pixel output signal of each pixel unit, and the second pixel output signal is obtained after the pixel unit performs signal gain processing according to the signal gain mode corresponding to the written dual gain mode selection signal.

9. A camera module, characterized in that: The apparatus comprises the image sensor according to any one of claims 1 to 8.

10. An electronic device, characterized in that: Including the camera module as described in claim 9.

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