System and method for cache coherency

Abstract

An extensible cache coherence protocol for a system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller can implement a precise directory of cache blocks from a memory to which the memory controller is coupled. A plurality of requests for a cache block can be outstanding, and a snoop and completion of a request can include an expected cache state at a receiving agent as indicated by a directory in the memory controller when the request is processed to allow the receiving agent to detect race conditions. In one embodiment, the cache states can include a primary shared state and a secondary shared state. The primary shared state can apply to a coherent agent responsible for transmitting a copy of the cache block to a requesting agent. In one embodiment, at least two types of snoops can be supported: snoop forwarding and snoop back.

Description

Background Technology Technical Field

[0002] The implementation scheme described in this article relates to a cache consistency system.

[0003] Related technical descriptions

[0004] Various systems may include multiple agents that access memory during use. If one or more agents cache data, it is possible for one agent to read that data from memory while another agent has cached (and may have modified) that data. Many systems implement cache coherence mechanisms to distinguish between cached copies of data and the data in memory, thereby ordering accesses to the same data according to a memory ordering model and allowing data to be moved to agents for caching.

[0005] Additional communication between the consistency controller and various agents and memory is typically used to maintain cache consistency. As the number of agents increases, the number of such messages also increases, potentially overwhelming the interconnect between agents and memory. Even with sufficient bandwidth to carry messages, along with read and write traffic, to memory, the sheer volume of messages degrades system performance due to increased memory latency. Attached Figure Description

[0006] The following detailed description refers to the accompanying drawings, which will now be briefly described.

[0007] Figure 1 This is a block diagram of one implementation scheme for a cache coherence system as a System-on-Chip (SoC).

[0008] Figure 2 This is a block diagram illustrating one implementation of a three-way cross-chain protocol for consistent delivery of cache blocks.

[0009] Figure 3 This is a block diagram illustrating one implementation of the competition between managing the filling of one consistent transaction and the snooping of another consistent transaction.

[0010] Figure 4 This is a block diagram illustrating one implementation of the competition between the snooping of one consistent transaction and the confirmation of another consistent transaction.

[0011] Figure 5 This is a block diagram of one implementation of a consistent agent.

[0012] Figure 6 This is a flowchart illustrating the operation of one implementation of processing requests at the consistency controller.

[0013] Figure 7This is a flowchart illustrating the operation of one implementation of a consistent agent that sends a request to the memory controller to process the completion associated with that request.

[0014] Figure 8 This is a flowchart illustrating the operation of one implementation of a consistent agent receiving snooping.

[0015] Figure 9 This is a block diagram illustrating a chain of conflict requests for cache blocks according to one implementation scheme.

[0016] Figure 10 This is a flowchart illustrating one implementation of a consistent agent for concurrent snooping.

[0017] Figure 11 This is a block diagram illustrating one implementation of a non-cached request.

[0018] Figure 12 This is a flowchart illustrating the operation of one implementation of a consistency controller for generating snooping based on the cacheable and non-cacheable nature of requests.

[0019] Figure 13 It is a table showing the states of multiple caches according to one implementation of a consistency protocol.

[0020] Figure 14 This is a table showing multiple messages that can be used in one implementation of the consistency protocol.

[0021] Figure 15 This is a flowchart illustrating the operation of one implementation of a consistency controller for handling changes to exclusive condition requests.

[0022] Figure 16 This is a flowchart illustrating the operation of one implementation of a consistency controller for reading directory entries and generating snoops.

[0023] Figure 17 This is a flowchart illustrating the operation of one implementation of a consistency controller for handling exclusive, no-data requests.

[0024] Figure 18 Is included Figure 1 The diagram shows a block diagram of one implementation of a SOC system.

[0025] Figure 19 It is a block diagram of one implementation scheme of computer-accessible storage media.

[0026] While the embodiments described herein may be subject to various modifications and alternatives, specific embodiments thereof are shown by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the drawings and specific embodiments thereof are not intended to limit the embodiments to the particular forms disclosed, but rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims. The headings used herein are for organizational purposes only and are not intended to limit the scope of the specification. Detailed Implementation

[0027] A scalable cache coherence protocol for a system comprising multiple coherence agents coupled to one or more memory controllers is described. Coherence agents typically include caches for cache memory data or any circuitry that may otherwise possess one or more cache blocks and potentially modify those cache blocks locally. Coherence agents participate in the cache coherence protocol to ensure that modifications made by one coherence agent are visible to other agents subsequently reading the same data, and to ensure that modifications made by two or more coherence agents in a specific order (as determined at a sorting point in the system, such as at the memory controller storing the cache blocks) are observed in that order in each of the coherence agents.

[0028] Cache coherence protocols can specify a set of messages or commands that can be emitted between an agent and a memory controller (or a coherence controller within the memory controller) to complete a coherence transaction. These messages can include requests, snoops, snoop responses, and completions. A “request” is a message that initiates a transaction and specifies the requested cache block (e.g., the address of the cache block) and the state (or minimum state, or in some cases, a more permissive state) that the requesting party will receive the cache block from. As used herein, a “snoop” or “snoop message” refers to a message emitted to a coherence agent that requests a state change for the cache block, and may also request the coherence agent to provide the cache block if the coherence agent has an exclusive copy of the cache block or is otherwise in charge of the cache block. A “completion” or “snoop response” can be a message from a coherence agent indicating that a state change has been made and, if applicable, providing a copy of the cache block. In some cases, completion may also be provided by the source of certain requests.

[0029] A "state" or "cache state" typically refers to a value indicating whether a copy of a cache block is valid in the cache and may also indicate other attributes of the cache block. For example, a state may indicate whether a cache block has been modified relative to its copy in memory. A state may indicate the ownership level of a cache block (e.g., whether an agent with a cache is allowed to modify the cache block, whether the agent is responsible for providing the cache block or returning it to the memory controller in the event of eviction, etc.). A state may also indicate that a cache block may exist in other coherent agents (e.g., a "shared" state may indicate that a copy of the cache block can be stored in one or more other cacheable agents).

[0030] Various implementations of cache coherence protocols may include several features. For example, each memory controller may implement a coherence controller and a directory corresponding to cache blocks in the memory controlled by that memory controller. The directory may track the state of cache blocks across multiple cacheable agents, allowing the coherence controller to determine which cacheable agents to snoop on to change the state of cache blocks and, where possible, provide copies of the cache blocks. That is, based on a request received at the cache controller, snooping does not need to be broadcast to all cacheable agents, but can be emitted to those agents that have copies of the cache blocks affected by the request. Once a snoop has been generated, the directory can be updated to reflect the state of cache blocks in each coherence agent after the snoop has been processed and data has been provided to the request source. Thus, the directory can be accurate for the next request processed to the same cache block. For example, snooping can be minimized compared to a broadcast solution, thereby reducing traffic on the interconnect between the coherence agents and the memory controller. In one implementation, a "3-cross-chain" protocol may be supported, where one cache consensus agent in the cache consensus broker provides a copy of the cache block to the requesting source, or, if no cache consensus agent exists, the memory controller provides the copy. Therefore, the data is set across three "cross-chains" (or messages emitted via the interface): a request from the source to the memory controller, a snooping on the consensus broker that will respond to the request, and a completion from the consensus broker to the requesting source with the cache block data. In the absence of a cache copy, two cross-chains may exist: a request from the source to the memory controller and a completion from the memory controller to the source with the data. Additional messages may exist (e.g., an indication from another broker that a request state change has been made when multiple snoops exist for the request), but the data itself may be set across three cross-chains. In contrast, many cache consensus protocols are four-cross-chain protocols, where the consensus broker responds to a snooping by returning the cache block to the memory controller, and the memory controller forwards the cache block to the source. In one implementation, the protocol may support four cross-chain flows in addition to three.

[0031] In one implementation, requests for cache blocks can be handled by a consistency controller, and the directory can be updated once a snoop has been generated (and / or, in the case of no cached copy, completion from the memory controller). Another request for the same cache block can then be served. Therefore, requests for the same cache block can be deserialized, as is the case with some other cache consistency protocols. Various race conditions can occur when there are multiple unresolved requests for cache blocks, as messages related to subsequent requests can arrive at a given consistency broker before messages related to previous requests (where "subsequent" and "previous" refer to requests ordered as at the consistency controller in the memory controller). To allow brokers to categorize requests, messages (e.g., snoops and completions) can include the expected cache state at the receiving broker, as indicated by the directory when the request is processed. Thus, if the receiving broker does not have a cache block in the state indicated in the message, the receiving broker can delay processing the message until the cache state changes to the expected state. This change to the expected state can occur via messages related to previous requests. Additional descriptions of race conditions and how to resolve them using the expected cache state are provided below relative to... Figures 3-4 and Figures 6-8 supply.

[0032] In one implementation, these cache states may include a first-level shared state and a second-level shared state. The first-level shared state may be suitable for a consistent broker responsible for sending copies of cache blocks to the request broker. Even snooping on the second-level shared broker may not be necessary during the processing of a given request (e.g., a read of a cache block that is allowed to be returned in shared state). Additional details regarding the first-level and second-level shared states will be provided relative to... Figure 14 and Figure 16 describe.

[0033] In one implementation, at least two types of snooping can be supported: snoop forwarding and snoop backing. Snoop forwarding messages can be used to cause a consistency broker to forward a cache block to a requesting broker, while snoop backing messages can be used to cause a consistency broker to return a cache block to the memory controller. In one implementation, snoop invalidation messages (and may also include forwarding variants and backing variants for completion-specified destinations) can also be supported. Snoop invalidation messages cause a cache consistency broker to invalidate a cache block. Supporting snoop forwarding and snoop backing flows can provide, for example, both cacheable (snoop forwarding) and non-cacheable (snoop backing) behaviors. Snoop forwarding can be used to minimize the number of messages when providing cache blocks to a cache broker, as the cache broker can store the cache block and potentially use the data within it. On the other hand, a non-consistent broker may not store the entire cache block, and therefore a copy returned to memory ensures that the complete cache block is captured in the memory controller. Therefore, the snooping forwarding variant and snooping bounce variant or type can be selected based on the capabilities of the request broker (e.g., based on the identity of the request broker) and / or based on the type of request (e.g., cacheable or non-cacheable). Additional details regarding snooping forwarding and snooping bounce messages are provided below relative to... Figure 11 , Figure 12 and Figure 14 Various other features are shown in the remaining diagrams and will be described in more detail below.

[0034] Figure 1This is a block diagram of an implementation of a system-on-a-chip (SOC) 10 coupled to one or more memories, such as memories 12A-12m. SOC 10 may include multiple coherence agents (CAs) 14A-14n. These coherence agents may include one or more processors (Ps) 16 coupled to one or more caches (e.g., cache 18). SOC 10 may include one or more non-coherence agents (NCAs) 20A-20p. SOC 10 may include one or more memory controllers 22A-22m, each memory controller coupled to a corresponding memory 12A-12m during use. Each memory controller 22A-22m may include coherence controller circuitry 24 (more briefly, a "coherence controller" or "CC") coupled to directory 26. Memory controllers 22A-22m, non-coherence agents 20A-20p, and coherence agents 14A-14n may be coupled to interconnect 28 to communicate between various components 22A-22m, 20A-20p, and 14A-14n. As the name suggests, in one implementation, the components of the SOC 10 can be integrated onto a single integrated circuit "chip". In other implementations, the various components can be on other chips outside the SOC 10 or on additional discrete components. Any number of integrated or discrete components can be used. In one implementation, a subset of the coherent agents 14A-14n and memory controllers 22A-22m can be coupled together to form Figure 1 The components shown in the SOC 10 are implemented in one of a plurality of integrated circuit chips.

[0035] The consistency controller 24 implements the memory controller portion of the cache consistency protocol. Generally, the consistency controller 24 can be configured (e.g., via one or more queues (not shown) in memory controllers 22A-22m) to receive requests from interconnect 28 for cache blocks mapped to memories 12A-12m coupled to memory controllers 22A-22m. The directory may include multiple entries, each tracking the consistency state of a corresponding cache block in the system. The consistency state may include, for example, the cache state of the cache block in various consistency agents 14A-14N (e.g., in cache 18, or in other caches such as a cache in processor 16 (not shown)). Therefore, based on the directory entries for cache blocks corresponding to a given request and the type of the request, the consistency controller 24 can be configured to determine which consistency agents 14A-14n will receive snooping and the type of snooping (e.g., snooping invalid, snooping shared, changed to shared, changed to owned, changed to invalid, etc.). The consistency controller 24 can also independently determine whether to forward or back off a snooping. The coherence agent 14A-14n can receive snoops, process snoops to update the cache block state in the coherence agent 14A-14n, and provide a copy of the cache block (if specified by the snoop) to the requesting coherence agent 14A-14n or the memory controller 22A-22m that issued the snoop. Additional details will be provided below.

[0036] As described above, the coherence agents 14A-14n may include one or more processors 16. Processor 16 may serve as the central processing unit (CPU) of the SOC 10. The CPU of the system includes one or more processors that execute the main system control software, such as an operating system. Typically, the software executed by the CPU during use controls other components of the system to achieve the desired functions of the system. The processor may also execute other software such as application programs. Application programs provide user functions and may rely on the operating system for lower-level device control, scheduling, memory management, etc. Therefore, the processor may also be referred to as an application processor. The coherence agents 14A-14n may also include other hardware, such as cache 18 and / or interfaces to other components of the system (e.g., interfaces to interconnect 28). Other coherence agents may include processors other than the CPU. Furthermore, other coherence agents may not include processors (e.g., fixed-function circuitry such as display controllers or other peripheral circuitry, fixed-function circuitry with processor assistance via one or more embedded processors, etc., may be coherence agents).

[0037] Typically, a processor may include any circuitry and / or microcode configured to execute instructions defined in the instruction set architecture implemented by the processor. A processor may encompass a processor core implemented on an integrated circuit having other components as a system-on-a-chip (SoC) or other level of integration. A processor may further encompass discrete microprocessors, processor cores and / or microprocessors integrated into a multi-chip module implementation, processors implemented as multiple integrated circuits, etc. The number of processors 16 in a given coherence agent 14A-14n may differ from the number of processors 16 in another coherence agent 14A-14n. Generally, one or more processors may be included. Additionally, processors 16 may differ in microarchitectural implementation, performance, and power characteristics. In some cases, processors may even differ in the instruction set architecture implemented by these processors, the functionality of these processors (e.g., CPU, graphics processing unit (GPU) processor, microcontroller, digital signal processor, image signal processor, etc.).

[0038] Cache 18 can have any capacity and configuration, such as set-associative, direct-mapped, or fully associative. The cache block size can be any desired size (e.g., 32 bytes, 64 bytes, 128 bytes, etc.). A cache block can be a unit of allocation and deallocation within cache 18. Additionally, in this embodiment, a cache block can be a unit on which consistency is maintained (e.g., a consistent granular segment of the memory address space alignment). In some cases, a cache block may also be referred to as a cache line.

[0039] In addition to the coherence controller 24 and catalog 26, the memory controllers 22A-22m typically include circuitry for receiving memory operations from other components of the SOC 10 and for accessing the memories 12A-12m to complete the memory operations. The memory controllers 22A-22m can be configured to access any type of memory 12A-12m. For example, the memories 12A-12m can be static random access memory (SRAM), dynamic RAM (DRAM) such as synchronous DRAM (SDRAM) including double data rate (DDR, DDR2, DDR3, DDR4, etc.), non-volatile memory, graphics DRAM such as graphics DDR DRAM (GDDR), and high bandwidth memory (HBM). Low-power / mobile versions of DDR DRAM (e.g., LPDDR, mDDR, etc.) may be supported. The memory controllers 22A-22m may include a queue for memory operations to order (and potentially reorder) the operations and present them to the memories 12A-12m. Memory controllers 22A-22m may also include data buffers for storing write data awaiting writing to memory and read data awaiting return to the memory operation source (in cases where the data is not provided from a snoop). In some embodiments, memory controllers 22A-22m may include a memory cache for storing recently accessed memory data. For example, in a specific SOC implementation, a memory cache can reduce power consumption in the SOC by preventing re-access to data from memory 12A-12m when it is expected to be accessed again soon. In some cases, the memory cache may also be referred to as a system cache, which differs from a proprietary cache such as cache 18 or the cache in processor 16, which serves only certain components. Furthermore, in some embodiments, a system cache does not need to be located within memory controllers 22A-22m.

[0040] The non-uniform agent 20A-20p typically includes various additional hardware functions (e.g., "peripherals") included in the SOC 10. For example, peripherals may include video peripherals such as image signal processors, GPUs, video encoders / decoders, scalers, rotators, mixers, etc., configured to process image capture data from cameras or other image sensors. Peripherals may include audio peripherals such as microphones, speakers, interfaces to microphones and speakers, audio processors, digital signal processors, mixers, etc. Peripherals may include interface controllers for various interfaces external to the SOC 10, including interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI) (including PCI High Speed ​​(PCIe)), serial ports, and parallel ports, etc. Peripherals may include networking peripherals such as Media Access Controllers (MACs). Any set of hardware may be included. In one embodiment, the non-uniform agent 20A-20p may also include a bridge to a set of peripherals.

[0041] Interconnector 28 can be any communication interconnect and protocol used for communication between components of SOC 10. Interconnector 28 can be bus-based, including shared bus configurations, crossbar configurations, and hierarchical buses with bridges. Interconnector 28 can also be packet-based or circuit-switched, and can be hierarchical, crossbar, point-to-point, or other interconnects with bridges. In one embodiment, interconnector 28 may include multiple independent communication configurations.

[0042] Generally, the quantity of each component 22A-22m, 20A-20p, and 14A-14n can vary depending on the implementation scheme, and any quantity can be used. As indicated by the suffixes "m", "p", and "n", the quantity of one type of component can differ from the quantity of another type. However, the quantity of a given type can also be the same as the quantity of another type. Furthermore, although... Figure 1 The system is shown as having multiple memory controllers 22A-22m, but an implementation with a single memory controller 22A-22m is also conceived and can implement the cache coherence protocol described herein.

[0043] Next turn Figure 2The diagram illustrates a block diagram of multiple consistency agents 12A-12D and a memory controller 22A performing a consistency transaction for a cacheable read exclusive request (CRdEx) according to an implementation of a scalable cache coherence protocol. A read exclusive request can be a request for an exclusive copy of a cache block, so that consistency agents 14A-14D invalidate any other copies, and the requester has a single valid copy when the transaction completes. Memory 12A-12m, which has a memory location assigned to a cache block, has data at the location of the cache block assigned to memory 12A-12m, but that data will also be "stale" if the requester modifies it. Read exclusive requests can be used, for example, to enable the requester to modify the cache block without issuing an additional request in the cache coherence protocol. If an exclusive copy is not required, other requests can be used (e.g., a read shared request CRdSh can be used if the requester does not necessarily need a writable copy). The "C" in the "CRdEx" label can refer to "cacheable". Other transactions can be handled by non-consistent agents (e.g., ...). Figure 1 The agent in the transaction (20A-20p) issues the request, and such transactions can be marked as "NC" (e.g., NCRd). Additional discussion of request types and other messages in transactions is provided below for an implementation scheme. Figure 14 Further details and a further discussion of cache state are provided below regarding the implementation scheme relative to... Figure 13 Further details will be provided.

[0044] exist Figure 2 In the example, consensus agent 14A can initiate a transaction by sending a read exclusive request to memory controller 22A (which controls the memory location assigned to the address in the read exclusive request). Memory controller 22A (and more specifically, consensus controller 24 in memory controller 22A) can read entries in directory 26 and determine that consensus agent 14D has a cache block in first-level shared state (P), and thus can provide the cache block to the consensus agent requesting consensus agent 14D. Consensus controller 24 can generate a snoop forwarding (SnpFwd[st]) message for consensus agent 14D and can issue snoop forwarding messages to consensus agent 14D. According to directory 26, consensus controller 24 may include an identifier of the current state in the consensus agent receiving the snoop. For example, in this case, according to directory 26, the current state in consensus agent 14D is "P". Based on the snoop, consensus agent 14D can access the cache storing the cache block and generate a fill completion (CPC) with data corresponding to the cache block. Figure 2The Fill in the context of the consensus agent 14D can send the completed fill to the consensus agent 14A. Therefore, the system implements a “3-cross-chain” protocol for delivering data to the requester: CRdEx, SnpFwd[st], and Fill. As indicated by “[st]” in the SnpFwd[st] message, the state of the cache block to which the consensus agent will transition after processing the snoop can also be used to encode the snoop forwarding message. In various implementations, different variations of the message may exist, or the state may be carried as a field in the message. Figure 2 In the example, the new state of the cache block in the consistent broker can be invalid because the request is a read-exclusive request. Other requests may allow new shared state.

[0045] Additionally, the consistency controller 24 can determine from the directory entries of the cache blocks that the consistency agents 14B-14C have cache blocks in a second-level shared state (S). Therefore, a snoop can be issued to each consistency agent that meets the following conditions: (i) it has a cached copy of the cache block; and (ii) the state of the block in the consistency agent will change based on a transaction. Since the consistency agent 14A is acquiring an exclusive copy, the shared copy will fail, and therefore the consistency controller 24 can generate a snoop failure (SnpInvFw) message for the consistency agents 14B-14C and issue the snoop to the consistency agents 14B-14C. The snoop failure message includes an identifier indicating that the current state in the consistency agents 14B-14C is shared. The consistency agents 14B-14C can process the snoop failure request and provide an acknowledgment (Ack) completion to the consistency agent 14A. Note that in the illustrated protocol, the message from the snooping agent to the consistency controller 24 is not implemented in this embodiment. The consistency controller 24 can issue an update directory entry based on the snoop and can process the next transaction. Therefore, as previously mentioned, in this implementation, transactions on the same cache block may not be serialized. The consistency controller 24 may allow additional transactions on the same cache block to begin and may rely on the current state indication in the snoops to identify which snoops belong to which transactions (e.g., the next transaction on the same cache block will detect the cache state corresponding to a previously completed transaction). In the illustrated implementation, the snoop failure message is the SnpInvFw message because completion is sent to the initiating consistency broker 14A as part of a three-way cross-chain protocol. In one implementation, a four-way cross-chain protocol is also supported for some brokers. In this implementation, the SnpInvBk message can be used to instruct the snoop broker to send completion back to the consistency controller 24.

[0046] Therefore, the cache state identifier in the snoop allows the consistency broker to resolve contention between messages that form different transactions for the same cache block. That is, the order in which messages are received may not be consistent with the order in which the consistency controller processes the corresponding requests. The order in which the consistency controller 24 processes requests for the same cache block through directory 26 can define the order of requests. That is, the consistency controller 24 can be the sorting point for transactions received in a given memory controller 22A-22m. On the other hand, message serialization can be managed in consistency brokers 14A-14n based on the current cache state corresponding to each message and the cache state in consistency brokers 14A-14n. A given consistency broker can access cache blocks within the consistency broker based on a snoop and can be configured to compare the cache state specified in the snoop with the current cache state in the cache. If the states do not match, the snoop belongs to a transaction that was ordered after another transaction that changed the cache state in the broker to the state specified in the snoop. Therefore, the snooping agent can be configured to delay processing of snooping based on a mismatch between a first state and a second state, until the second state changes back to the first state in response to different communication related to a request different from the first request. For example, the state can be changed based on fill completion received by the snooping agent from a different transaction.

[0047] In one implementation, snooping may include a completion count (Cnt) indicating the number of completions corresponding to a transaction, so that the requesting party can determine when all completions related to the transaction have been received. The consistency controller 24 may determine the completion count based on the status indicated in the directory entries of cache blocks. The completion count may be, for example, the number of completions minus one (e.g., in...). Figure 2 In the example, it is 2 because there are three completions. This specific implementation allows the completion count to be used as the initialization of the completion counter for the transaction when the request broker receives the initial completion of the transaction (e.g., the completion count has been decremented to reflect the reception of the completions carrying the completion count). Once the count has been initialized, additional completions for the transaction can cause the request broker to update the completion counter (e.g., decrement the counter). In other implementations, the actual completion count can be provided and decremented by the requester to initialize the completion count. Generally, the completion count can be any value that identifies the number of completions the requester will observe before the transaction is fully completed. That is, the request broker can complete the request based on the completion counter.

[0048] Figure 3 and Figure 4This illustrates exemplary race conditions that can occur when transactions have access to the same cache block, and the use of the current cache state of a given agent (also referred to as the "expected cache state") as reflected in the directory when a transaction is processed in the memory controller, and the current cache state in the given agent (e.g., as reflected in the cache of the given agent or in a buffer where cache data can be temporarily stored). Figure 3 and Figure 4 In the diagram, the consistency agents are listed as CA0 and CA1, and the memory controller associated with the cache block is shown as MC. Vertical lines 30, 32, and 34 for CA0, CA1, and MC indicate the source (root of the arrow) and destination (head of the arrow) of the various messages corresponding to the transaction. (Time in...) Figure 3 and Figure 4 The process proceeds from top to bottom. If the memory to which the memory controller is coupled includes memory locations whose addresses are assigned to cache blocks, then the memory controller may be associated with a cache block.

[0049] Figure 3 This illustrates the race condition between the completion of filling a single transaction on the same cache block and snooping by different transactions. Figure 3 In the example, CA0 initiates a read exclusive transaction to MC using a CRdEx request (arrow 36). CA1 also initiates a read exclusive transaction using a CRdEx request (arrow 38). MC processes the CA0 transaction first, thus establishing the CA0 transaction as ordered before the CA1 request. In this example, the directory indicates that the cached copy of the cache block does not exist in the system, and therefore MC responds to the CA0 request with fill in the exclusive state (fillE, arrow 40). MC updates the directory entry for the cache block for CA0 in the exclusive state.

[0050] The MC selects the CRdEx aspect from CA1 for processing and detects that CA0 has a cache block in an exclusive state. Therefore, the MC can generate a snoop forwarding request to CA0, requesting CA0 to invalidate its cache block and make the cache block available to CA1 (SnpFwdI). The snoop forwarding request also includes an identifier of the E-state of the cache block in CA0, as this is reflected in the cache state in CA0's directory. The MC can issue the snoop (arrow 42) and update the directory to indicate that CA1 has an exclusive copy and CA0 no longer has a valid copy.

[0051] Snooping and fill completion can arrive at CA0 in either time order. Messages can propagate through different virtual channels, and / or other delays in the interconnect can allow messages to arrive in either order. In the example shown, snooping arrives at CA0 before fill completion. However, because the expected state (E) in the snooping does not match the current state (I) of the cache block in CA0, CA0 can delay processing the snooping. Subsequently, fill completion can arrive at CA0. CA0 can write the cache block into the cache and set the state to exclusive (E). CA0 can also be allowed to perform at least one operation on the cache block to support the progress of the task in CA0, and this operation can change the state to modified (M). In the cache coherence protocol, directory 26 may not track the M state separately (e.g., it can be regarded as E), but can match the E state to the expected state in the snooping. CA0 can issue fill completion (FillM, arrow 44) to CA1 if the state is modified. Therefore, the race condition between snooping and fill completion for two transactions has been properly handled.

[0052] Although Figure 3 In the example, the CRdEx request is issued by CA1 after the CRdEx request from CA0, but the CRdEx request can be issued by CA1 before the CRdEx request from CA0, and since MC is the ordering point of the transaction, the CRdEx request from CA0 can still be ordered by MC before the CRdEx request from CA1.

[0053] Figure 4 This illustrates the race condition between the snooping of one consistent transaction on the same cache block and the completion of another consistent transaction. Figure 4 In the above scenario, CA0 initiates a write-back transaction (CWB) (arrow 46) to write the modified cache block to memory, but the cache block may actually be tracked as exclusive in the directory as mentioned above. For example, if CA0 evicts a cache block from its cache, but the cache block is in a modified state, a CWB can be issued. CA1 initiates a read-share transaction (CRdS) (arrow 48) for the same cache block. The CA1 transaction is ordered by the MC before the CA0 transaction. The MC reads the directory entry for the cache block and determines that CA0 has the cache block in an exclusive state. The MC issues a snoop forwarding request to CA0 and requests a change to a second-level shared state (SnpFwdS, arrow 50). The identifier in the snoop indicates the current cache exclusive state (E) in CA0. The MC updates the directory entry to indicate that CA0 has the cache block in a second-level shared state, and CA1 has a copy in a first-level shared state (because the previous exclusive copy is being provided to CA1).

[0054] The MC processes the CWB request from CA0, thereby rereading the directory entry for the cache block. The MC issues an Ack completion, indicating in the Ack completion that the current cache state in CA0 is second-level shared (S) with an identifier of the cache state (arrow 52). CA0 may delay processing the Ack completion based on the mismatch between the expected second-level shared state and the current modified state. Processing the Ack completion will allow CA0 to discard the cache block, and in response to a later-arriving SnpFwdS request, CA0 will not then provide a copy of the cache block to CA1. Upon receiving the SnpFwdS request, CA0 may provide a fill completion to CA1 (arrow 54), thereby providing the cache block in first-level shared (P) state. CA0 may also change the state of the cache block in CA0 to second-level shared (S). The state change matches the expected state for the Ack completion, and thus CA0 can invalidate the cache block and complete the CWB transaction.

[0055] Figure 5 This is a more detailed block diagram of one embodiment of the consensus agent 14A. Other consensus agents 14B-14n may be similar. In the illustrated embodiment, the consensus agent 14A may include request control circuitry 60 and request buffer 62. Request buffer 62 is coupled to request control circuitry 60, and both request buffer 62 and request control circuitry 60 are coupled to cache 18 and / or processor 16 and interconnect 28.

[0056] Request buffer 62 can be configured to store multiple requests generated by cache 18 / processor 16 for a consistent cache block. That is, request buffer 62 can store requests that initiate transactions on interconnect 28. Figure 5 The diagram shows one entry for request buffer 62, and other entries may be similar. This entry may include a valid (V) field 63, a request (Req.) field 64, a count valid (CV) field 66, and a completion count (CompCnt) field 68. The valid field 63 may store a valid indication (e.g., a valid bit) indicating whether the entry is valid (e.g., storing an unresolved request). The request field 64 may store data defining the request (e.g., request type, address of a cache block, tag for a transaction, or other identifier). The count valid field 66 may store a valid indication of the completion count field 68, indicating that the completion count field 68 has been initialized. Request control circuitry 68 may use the count valid field 66 to determine, when processing completion information received from interconnect 28 for a request, whether to initialize a field with a completion count included in the completion (where the count field is not valid) or to update the completion count, such as decrementing the completion count (where the count field is valid). The completion count field 68 may store the current completion count.

[0057] Request control circuitry 60 can receive requests from cache 18 / processor 16 and can allocate request buffer entries in request buffer 62 to requests. Request control circuitry 60 can track requests in buffer 62, thereby causing requests to be issued on interconnect 28 (e.g., according to any kind of arbitration scheme) and track the completion of received requests to complete transactions and forward cache blocks to cache 18 / processor 16.

[0058] Turn now Figure 6 The diagram illustrates a flowchart of an embodiment of the consistency controller 24 in memory controllers 22A-22m, based on the operation of receiving a request to be processed. When a request has been selected from the service requests received in memory controllers 22A-22m via any desired arbitration algorithm, the following can be executed: Figure 6 The operation is described. However, for ease of understanding, the block diagram is shown in a specific order, but other orders may be used. Blocks can be executed in parallel within combinational logic in the consistency controller 24. Blocks, combinations of blocks, and / or flowcharts as a whole can be pipelined over multiple clock cycles. The consistency controller 24 can be configured to implement... Figure 6 The operation is shown in the figure.

[0059] Consistency controller 24 can be configured to read directory entries from directory 26 based on the requested address. Consistency controller 24 can be configured to determine which snoops will be generated based on the type of request (e.g., the state of the requester's request for a cache block) and the current state of the cache blocks in the various consistency agents 14A-14n, as indicated in the directory entries (box 70). Additionally, consistency controller 24 can generate a current state to be included in each snoop based on the current state of the consistency agents 14A-14n that will receive snoops, as indicated in the directory. Consistency controller 24 can be configured to insert the current state into the snoops (box 72). Consistency controller 24 can also be configured to generate a completion count and insert the completion count into each snoop (box 74). As previously mentioned, in one embodiment, the completion count can be the number of completions minus one, or the total number of completions. The number of completions can be the number of snoops, and, in the case that cache blocks will be provided by memory controllers 22A-22m, the number of filling completions from memory controllers 22A-22m. In most cases where snooping exists for cacheable requests, one of the snooping consensus agents 14A-14n can provide cache blocks, and therefore the number of completions can be the number of snoopings. However, in cases where no consensus agent 14A-14n has a copy of the cache block (no snooping), for example, the memory controller can provide fill completion. The consensus controller 24 can be configured to queue snoopings for issuance to consensus agents 14A-14n (box 76). Once a snooping is successfully queued, the consensus controller 24 can be configured to update directory entries to reflect the completion of the request (box 78). For example, the update may change the cache state tracked in the directory entry to match the cache state requested by the snooping, change the agent identifier indicating which agent will provide a copy of the cache block to the consensus agent 14A-14n that will have the cache block in an exclusive, modified, owned, or first-level shared state upon transaction completion, etc.

[0060] Turn now Figure 7 The diagram illustrates an embodiment of the request control circuitry 60 in the consistent agent 14A-14n, showing a flowchart of the operation based on the completion of an unresolved request received in the request buffer 62. However, for ease of understanding, the block diagrams are shown in a specific order, and other orders may be used. The blocks can be executed in parallel within the combinational logic circuitry of the request control circuitry 60. The blocks, combinations of blocks, and / or flowcharts as a whole can be pipelined over multiple clock cycles. The request control circuitry 60 can be configured to implement... Figure 7 The operation is shown in the figure.

[0061] Request control circuitry 60 can be configured to access the request buffer entry in request buffer 62 associated with the received completion and the request to which it is associated. If the count validity field 66 indicates that the completion count is valid (decision box 80, "Yes" branch), request control circuitry 60 can be configured to decrement the count in request count field 68 (box 82). If the count is zero (decision box 84, "Yes" branch), the request is completed and request control circuitry 60 can be configured to forward the completion indication (and the received cache block, if applicable) to the cache 18 and / or processor 16 that generated the request (box 86). Completion may cause the state of the cache block to be updated. If the new state of the cache block after the update is consistent with the expected state in the pending snoop (decision box 88, "Yes" branch), request control circuitry 60 can be configured to process the pending snoop (box 90). For example, request control circuitry 60 can be configured to pass the snoop to cache 18 / processor 16 to generate a completion corresponding to the pending snoop (and change the state of the cache block as indicated by the snoop).

[0062] If the new state is the same as the expected state, then the new state can be consistent with the expected state. Alternatively, if the expected state is the state tracked by directory 26 for the new state, then the new state can be consistent with the expected state. For example, in one implementation, the modified state is tracked as an exclusive state in directory 26, and therefore the modified state is consistent with the expected exclusive state. For example, if the state is set to fill completion issued by another consistency agent 14A-14n, which has a cache block as exclusive and locally modifies the cache block, then the new state can be modified.

[0063] If the valid count field 66 indicates that the completion count is valid (Decision Box 80) and the completion count is not zero after decrementing (Decision Box 84, "No" branch), then the request is not completed and therefore remains pending in the request buffer 62 (and any pending snoops waiting for the request to complete may remain pending). If the valid count field 66 indicates that the completion count is not valid (Decision Box 80, "No" branch), then the request control circuit 60 may be configured to initialize the completion count field 68 (Box 92) with the completion count set in completion. The request control circuit 60 may still be configured to check that the completion count is zero (e.g., if there is only one completion for the request, then the completion count may be zero in completion) (Decision Box 84), and processing may continue as discussed above.

[0064] Figure 8This is a flowchart illustrating one implementation of the Consistency Agent 14A-14n based on the operation of receiving a snoop. However, for ease of understanding, the block diagram is shown in a specific order, but other orders may be used. The blocks can be executed in parallel within the combinational logic of the Consistency Agent 14A-14n. The blocks, combinations of blocks, and / or the flowchart as a whole can be pipelined over multiple clock cycles. The Consistency Agent 14A-14n can be configured to implement... Figure 8 The operation is shown in the figure.

[0065] Consistency brokers 14A-14n can be configured to check the expected state in a snoop against the state in cache 18 (decision box 100). If the expected state is inconsistent with the current state of the cache block (decision box 100, "No" branch), completion is unresolved, which changes the current state of the cache block to the expected state. Completion corresponds to transactions ordered before those corresponding to the snoop. Therefore, consistency brokers 14A-14n can be configured to put a snoop on hold, thus delaying processing of the snoop until the current state changes to the expected state indicated in the snoop (box 102). In one implementation, the pending snoop can be stored in a buffer specifically provided for pending snoops. Alternatively, the pending snoop can be incorporated into entries in the request buffer 62 that is storing conflicting requests, as follows relative to... Figure 10 More details will be discussed later.

[0066] If the expected state is consistent with the current state (Decision Box 100, "Yes" branch), then the consistency agent 14A-14n can be configured to process state changes based on snooping (Box 104). That is, snooping can indicate the expected state change. The consistency agent 14A-14n can be configured to generate completions (e.g., padding if the snooping is a snooping forwarding request, a replica return snooping response if the snooping is a snooping return request, or an acknowledgment (forwarding or return, based on snooping type) if the snooping is a state change request). The consistency agent can be configured to generate completions with completion counts based on snoopings (Box 106) and queue the completions for emission to the requesting consistency agent 14A-14n (Box 108).

[0067] Using the cache coherence algorithm described in this paper, cache blocks can be emitted from one coherence broker 14A-14n to another coherence broker via a chain of conflicting requests with low message bandwidth overhead. For example, Figure 9 This is a block diagram illustrating the issuance of cache blocks across four coherent proxies CA0 to CA3. Similar to... Figure 3 and Figure 4Consistent agents are listed as CA0 through CA3, and the memory controller associated with the cache block is shown as MC. Vertical lines 110, 112, 114, 116, and 118 for CA0, CA1, CA2, CA3, and MC respectively indicate the source (root of the arrow) and destination (head of the arrow) of the various messages corresponding to the transaction. Time in Figure 9 Progressing from top to bottom. (In the corresponding...) Figure 9 At the top of the timeline, the consistent agent CA3 has cache blocks involved in the transaction that are in a modified state (tracked as exclusive in directory 26). Figure 9 All transactions in the cache are for the same cache block.

[0068] Consistent agent CA0 initiates a read exclusive transaction to the memory controller using a CRdEx request (arrow 120). Consistent agents CA1 and CA2 also initiate read exclusive transactions (arrows 122 and 124, respectively). As indicated in the header at line 118 of arrows 120, 122, and 124, the memory controller MC sorts the transactions in order: CA0, then CA1, and finally CA2. The directory state of the transaction from CA0 is CA3, which is in an exclusive state, and therefore, a snoop forwarding and invalidation (SnpFwdI) is issued while the current cache state is exclusive (arrow 126). Consistent agent CA3 receives the snoop and forwards the FillM completion with the data to consistent agent CA0 (arrow 128). Similarly, the directory state of a transaction from CA1 is that of the exclusive coordinating agent CA0 (from a previous transaction on CA0), and therefore the memory controller MC issues SnpFwdI to the coordinating agent CA0, whose current cache state is E (arrow 130), and the directory state of a transaction from CA2 is that of the coordinating agent CA1, whose current cache state is E (arrow 132). Once the coordinating agent CA0 has had the opportunity to perform at least one memory operation on a cache block, the coordinating agent CA0 responds with a FillM completion to the coordinating agent CA1 (arrow 134). Similarly, once the coordinating agent CA1 has had the opportunity to perform at least one memory operation on a cache block, the coordinating agent CA1 responds with a FillM completion to the coordinating agent CA2 (arrow 136) to its snooping. Although the order and timing of various messages can vary (e.g., similar to...), Figure 3 and Figure 4 (As shown in the race condition), but generally speaking, when the conflict request is resolved, the cache block can be moved from the broker to the broker with an additional message (FillM complete).

[0069] In one implementation, due to the aforementioned race condition, a snoop can be received before it completes filling (detected by the snoop carrying the expected cache state). Additionally, a snoop can be received before Ack completion is collected and filling completion can be processed. Ack completion is generated by the snoop and therefore depends on the progress in the virtual channel carrying the snoop. Therefore, conflicting snoops (waiting with delay on the expected cache state) can fill the internal buffer and put pressure back into the construction, potentially leading to deadlock. In one implementation, the consistent agent 14A-14n can be configured to swallow a snoop forward and a snoop failure into the unresolved request in the request buffer, rather than allocating separate entries. Non-conflicting snoops, or conflicting snoops that reach a point that can be processed without further interconnect dependencies, can then bypass conflicting snoop flow and avoid deadlock. The swallowing of a snoop forward and a snoop failure can be sufficient because when a snoop forward is performed, the forwarding responsibility is transferred to the target. Therefore, another snoop forward will not occur until the requester completes its current request and issues another new request after the previous snoop forward has completed. When the snooping failure is complete, the requester fails according to the directory and will not receive another failure until the requester processes the previous failure, requesting the cache block again and obtaining a new copy.

[0070] Therefore, the consistency agent 14A-14n can be configured to help ensure forward movement and / or prevent deadlock by detecting snoops received by the consistency agent for a cache block for which the consistency agent has unresolved requests that have been ordered prior to the snoops. The consistency agent can be configured to incorporate a second snoop into the unresolved request (e.g., into a request buffer entry for a storage request). The consistency agent can process the swapped snoop after completing the unresolved request. For example, if the swapped snoop is a snoop forwarding request, the consistency agent can be configured to forward the cache block to another consistency agent indicated in the snoop forwarding snoop after completing the unresolved request (and can change the cache state to the state indicated by the snoop forwarding request). If the swapped snoop is a snoop invalidation request, the consistency agent can update the cache state to invalidation and issue a completion acknowledgment after completing the unresolved request. Swapping snoops into conflict requests can be implemented, for example, by including additional storage in each request buffer entry for data describing the swapped snoop.

[0071] Figure 10This is a flowchart illustrating one implementation of the Consistency Agent 14A-14n based on the operation of receiving a snoop. However, for ease of understanding, the block diagram is shown in a specific order, but other orders may be used. The blocks can be executed in parallel within the combinational logic of the Consistency Agent 14A-14n. The blocks, combinations of blocks, and / or the flowchart as a whole can be pipelined over multiple clock cycles. The Consistency Agent 14A-14n can be configured to implement... Figure 10 The operations shown in the diagram. For example, Figure 10 The operation shown could be a snooping that detects an expected cache state that is inconsistent with the expected cache state and is pending resolution. Figure 8 It is part of decision boxes 100 and 102 in the document.

[0072] Consistent Proxy 14A-14n can be configured to compare the address of a snoop pending due to a lack of consistent cache state with the address of an unresolved request (or pending request) in Request Buffer 62. If an address conflict is detected (Decision Box 140, "Yes" branch), Request Buffer 62 can swallow the snoop and assign it to a buffer entry for the pending request for which it detected an address conflict (Box 142). If no address conflict exists with the pending request (Decision Box 140, "No" branch), Consistent Proxy 14A-14n can be configured to allocate a separate buffer location for the snoop (e.g., in Request Buffer 62 or another buffer in Consistent Proxy 14A-14n) and can be configured to store data describing the snoop in a buffer entry (Box 144).

[0073] As previously mentioned, in one implementation, the cache coherence protocol can support both cacheable and non-cacheable requests while maintaining the consistency of the data involved. Non-cacheable requests may be issued, for example, by non-coherent agents 20A-20p, which may not have the ability to consistently store cache blocks. In one implementation, coherent agents 14A-14n may also issue non-cacheable requests, and the coherent agents may not cache the data provided in response to such requests. Therefore, for example, if the data requested by a given non-coherent agent 20A-20p is in a modified cache block in one of the coherent agents 14A-14n and will be forwarded to the given non-coherent agent 20A-20p, and it is expected that the modified cache block will be reserved by the given non-coherent agent 20A-20p, a snooping forwarding request for a non-cacheable request would be inappropriate.

[0074] To support consistent non-cacheable transactions, implementations of the Scalable Cache Coherence Protocol may include various types of snooping. For example, in one implementation, snooping may include snoop forwarding requests and snoop rollback requests. As previously mentioned, a snoop forwarding request may cause a cache block to be forwarded to a request broker. On the other hand, a snoop rollback request may cause a cache block to be issued back to the memory controller. In one implementation, snoop invalidation requests may also be supported to invalidate a cache block (having forwarded and rollback versions for bootstrapping completion).

[0075] More specifically, the memory controllers 22A-22m receiving the request (and even more specifically, the coherence controller 24 within memory controllers 22A-22m) can be configured to read from directory 26 the entry corresponding to the cache block identified by the address in the request. Memory controllers 22A-22m can be configured to issue a snooping to a given agent in coherence agents 14A-14m that has a cached copy of the cache block, based on the entry. The snooping instructs the given agent to issue a cache block to the request source based on the first request being of a first type (e.g., a cacheable request). The snooping instructs the given agent to issue a first cache block to the memory controller based on the first request being of a second type (e.g., a non-cacheable request). Memory controllers 22A-22n can be configured to complete a response to the request source based on receiving a cache block from a given agent. Additionally, as with other coherence requests, memory controllers 22A-22n can be configured to update entries in directory 26 based on issuing multiple snoopings for non-cacheable requests to reflect the completion of the non-cacheable request.

[0076] Figure 11 This is a block diagram illustrating an example of non-cacheable transactions being consistently managed in one implementation. Figure 11 This could be an example of a 4-chain cross-chain protocol used to pass snooping data through the memory controller to the requester. The non-consistent agent is listed as NCA0, the consistent agent as CA1, and the memory controller associated with the cache block is listed as MC. Vertical lines 150, 152, and 154 for NCA0, CA1, and MC show the source (root of the arrow) and destination (head of the arrow) of the various messages corresponding to the transaction. Time in Figure 11 The process proceeds from top to bottom.

[0077] In corresponding Figure 11At the top of the time, the coordinating agent CA1 has a cache block in an exclusive (E) state. NCA0 issues a non-cacheable read request (NCRd) to MC (arrow 156). MC determines, according to catalog 26, that CA1 has a cache block in an exclusive state containing the data requested by the NCRd, and generates a snoop back request (SnpBkI(E)) for CA1 (arrow 158). CA1 provides MC with a snoop back response (CpBkSR) containing a copy of the cache block data (arrow 160). If the data is modified, MC can update memory with the data and can fulfill the request by providing the data for the non-cacheable read request to NCA0 in a non-cacheable read response (NCRdRsp) (arrow 162). In one implementation, there may be more than one type of NCRd request: a request to invalidate the cache block in the snooping coordinating agent and a request to allow the snooping coordinating agent to keep the cache block. The above discussion illustrates invalidation. In other cases, the snooping agent may keep the cache block in the same state.

[0078] Non-cacheable write requests can be executed in a similar manner, using a snooping back request to obtain a cache block and modifying the cache block with the non-cacheable write data before writing it to memory. Non-cacheable write responses can still be provided to the non-cacheable broker ( Figure 11 The NCA0 notification has been completed.

[0079] Figure 12 This is a flowchart illustrating the operation of one embodiment of memory controllers 22A-22m (and more specifically, in one embodiment, coherence controller 24 within memory controllers 22A-22m) in response to a request, showing cacheable and non-cacheable operations. For example, Figure 12 The operation shown can be Figure 6 A more detailed description of a portion of the operations shown is provided. However, for ease of understanding, the block diagrams are shown in a specific order, but other orders may be used. Blocks can be executed in parallel within combinational logic in the consistency controller 24. Blocks, combinations of blocks, and / or flowcharts as a whole can be pipelined over multiple clock cycles. The consistency controller 24 can be configured to implement... Figure 12 The operation is shown in the figure.

[0080] Consistency controller 24 can be configured to read the directory based on the address in the request. If the request is a directory hit (decision box 170, "Yes" branch), the cached block exists in one or more caches of the consistency agents 14A-14n. If the request is non-cacheable (decision box 172, "Yes" branch), consistency controller 24 can be configured to issue a snoop rollback request to the consistency agents 14A-14n responsible for providing copies of the cached blocks (and, if applicable, a snoop invalidation request to the shared agents (rollback variant) – box 174). Consistency controller 24 can be configured to update the directory to reflect snoop completion (e.g., invalidate the cached block in the consistency agents 14A-14n – box 176). Consistency controller 24 can be configured to wait for a copy rollback snoop response (decision box 178, "Yes" branch) and any Ack snoop responses from the shared consistency agents 14A-14n, and can be configured to generate a non-cacheable completion (NCRdRsp or NCWrRsp, depending on the case) to the requesting agent (box 180). If a cache block is modified, data can also be written to memory by memory controllers 22A-22m.

[0081] If the request is cacheable (Decision Box 172, "No" branch), then the consistency controller 24 can be configured to generate peek forwarding requests to the consistency agents 14A-14n responsible for forwarding cache blocks (Box 182), and, if necessary, generate additional peeks to other cache consistency agents 14A-14n. The consistency controller 24 can update the directory 24 to reflect the completion of transactions (Box 184).

[0082] If the request is not found in directory 26 (decision box 170, "No" branch), then there is no cached copy of the cache block in the consistency agents 14A-14n. In this case, no snooping is generated, and memory controllers 22A-22m can be configured to generate a fill completion (for cacheable requests) or a non-cacheable completion (for non-cacheable requests) to provide data or complete the request (box 186). In the case of a cacheable request, consistency controller 24 can update directory 26 to create entries for the cache block, and can initialize the requesting consistency agent 14A-14n with a copy of the cache block that was requested by consistency agent 14A-14n and is in a cached state (box 188).

[0083] Figure 13Table 190 illustrates exemplary cache states that can be implemented in one implementation of consistent agents 14A-14n. Other implementations may employ different cache states, subsets of the shown cache states and other cache states, supersets of the shown cache states and other cache states, etc. A modified state (M) or “dirty exclusive” state can be a state in consistent agents 14A-14n that only has a cached copy of a cache block (which is exclusive), and the data in the cached copy has been modified relative to the corresponding data in memory (e.g., at least one byte of the data differs from the corresponding byte in memory). The modified data may also be referred to as dirty data. An owned state (O) or “dirty shared” state can be a state in consistent agents 14A-14n that has a modified copy of a cache block but can share a copy with at least one other consistent agent 14A-14n (although the other consistent agent 14A-14n may subsequently evict the shared cache block). Another consistent agent 14A-14n will have a cache block in a second-level shared state. The Exclusive (E) state, or "Clean Exclusive" state, can be a state in the coherent agent 14A-14n that has only a cached copy of the cache block, but the data in the cached copy is the same as the corresponding data in memory. The Exclusive No Data (EnD) state, or "Clean Exclusive, No Data" state, can be a state in the coherent agent 14A-14n similar to the Exclusive (E) state, except that the cached block data has not been delivered to the coherent agent. This state can be used in cases where the coherent agent 14A-14n will modify every byte in the cache block, and therefore there may be no benefit or consistency reason to supply the previous data in the cache block. The EnD state can be an optimization for reducing traffic on interconnect 28 and may not be implemented in other embodiments. The Level 1 Shared (P) state, or "Clean Shared Level 1" state, can be a state in the coherent agent 14A-14n that has a shared copy of the cache block but is also responsible for forwarding the cache block to another coherent agent based on snooping forwarding requests. The Level 2 Shared (S) state, or "Clean Shared Level 2" state, can be a state in which a shared copy of a cache block exists but is not responsible for providing the cache block if another consensus agent 14A-14n has a cache block in the Level 1 Shared state. In some implementations, if no consensus agent 14A-14n has a cache block in the Level 1 Shared state, the consensus controller 24 may select a Level 2 Shared agent to provide the cache block (and may send a snoop forwarding request to the selected consensus agent). In other implementations, if no consensus agent 14A-14n in the Level 1 Shared state exists, the consensus controller 24 may cause the memory controllers 22A-22m to provide the cache block to the requesting party.The invalid state (I) can be a state in a coherent agent 14A-14n that does not have a cached copy. A coherent agent 14A-14n in the invalid state may not have previously had the requested copy, or may have had any copy and invalidated the copy based on snooping or eviction based on a cached block to cache a different cached block.

[0084] Figure 14 Table 192 illustrates various messages that can be used in one implementation of a scalable cache coherence protocol. Other implementations may include alternative messages, subsets of shown messages and supplementary messages, supersets of shown messages and supplementary messages, etc. These messages may carry transaction identifiers linking messages from the same transaction (e.g., initial request, snoop, completion). Initial requests and snoops may carry the address of the cache block affected by the transaction. Some other messages may also carry addresses. In some implementations, all messages may carry addresses.

[0085] A cacheable read transaction can be initiated using a cacheable read request message (CRd). Various versions of CRd requests may exist to request different cache states. For example, CRdEx may request an exclusive state, CRdS may request a second-level shared state, etc. The cache state actually provided in response to a cacheable read request can be at least as permissive as the requested state, and can be more permissive. For example, CRdEx may receive a cache block in an exclusive or modified state. CRdS may receive a block in a first-level shared, exclusive, owned, or modified state. In one implementation, opportunistic CRd requests can be implemented, and the most permissive state possible can be granted (without invalidating other copies of the cache block) (e.g., exclusive if no other consistent broker has a copy of the cached block, owned or first-level shared if a copy of the cached block exists, etc.).

[0086] A Change to Exclusive (CtoE) message can be used by a consistency agent that has a copy of a cache block in a state where modification is not permitted (e.g., owned, first-level shared, second-level shared), and the consistency agent is attempting to modify the cache block (e.g., the consistency agent needs exclusive access to change the cache block to modified). In one implementation, a conditional CtoE message can be used for a store condition directive. A store condition directive is part of a load hold / store condition pair in which a copy of the cache block is loaded and a hold is set for that cache block. Consistency agents 14A-14n can monitor access to the cache block by other agents and can conditionally perform a store based on whether the cache block has not yet been loaded and stored by another consistency agent 14A-14n (if the cache block has not been modified, the store is successful; if the cache block has been modified, the store is not performed). Additional details are provided below.

[0087] In one implementation, when the consensus broker 14A-14n modifies an entire cache block, a cache read exclusive, data-only (CRdE Donly) message can be used. If the cache block has not been modified in another consensus broker 14A-14n, the requesting consensus broker 14A-14n can use the EnD cache state and modify all bytes of the block without transferring the previous data in the cache block to the broker. If the cache block has been modified, the modified cache block can be transferred to the requesting consensus broker 14A-14n, and the requesting consensus broker 14A-14n can use the M cache state.

[0088] Non-cacheable transactions can be initiated using non-cacheable read and non-cacheable write (NCRd and NCWr) messages.

[0089] As previously described, snoop forwarding and snoop back (SnpFwd and SnpBk, respectively) can be used for snooping. Messages may exist to request the reception of various states (e.g., invalid or shared) in consistent agents 14A-14n after snooping has been processed. Snoop forwarding messages may also exist for CRdE Donly requests, which request forwarding if the cache block has been modified, otherwise not forwarding, and invalidation at the receiver. In one implementation, invalidation-only snoop forwarding requests and snoop back requests (e.g., snooping that causes the receiver to invalidate and acknowledge to the requesting party or memory controller, respectively, without returning data) may also exist, as shown in Table 192 as SnpInvFw and SnpInvBk.

[0090] Completion messages may include a fill message (Fill) and an acknowledgment message (Ack). The fill message specifies the status of the cache block that the requester will present upon completion. A cacheable write-back (CWB) message can be used to issue a cache block to memory controllers 22A-22m (e.g., based on evicting a cache block from the cache). A copy rollback snoop response (CpBkSR) can be used to issue a cache block to memory controllers 22A-22m (e.g., based on a snoop rollback message). Non-cacheable write completion (NCWrRsp) and non-cacheable read completion (NCRdRsp) can be used to complete non-cacheable requests.

[0091] Figure 15 This is a flowchart illustrating one implementation of the consistency controller 24 based on the operation of receiving a condition change to exclusive (CtoECond) message. For example, in one implementation, Figure 15 It can be Figure 6A more detailed description of a portion of block 70 is provided. However, for ease of understanding, the block diagram is shown in a specific order, but other orders may be used. Blocks can be executed in parallel within combinational logic in the consistency controller 24. Blocks, combinations of blocks, and / or flowcharts as a whole can be pipelined over multiple clock cycles. The consistency controller 24 can be configured to implement... Figure 15 The operation is shown in the figure.

[0092] The CtoECond message can be issued by the Consistency Broker 14A-14n (“Source”) based on the execution of a storage condition instruction. If the Source loses a copy of a cache block before the storage condition instruction (e.g., the copy is no longer valid), the storage condition instruction may fail locally in the Source. If the Source still has a valid copy (e.g., in a Level 2 or Level 1 shared state, or in an owned state), it is still possible that when the storage condition instruction is executed, another transaction will be ordered before a change-to-exclusive message from the Source, which causes the Source to invalidate its cached copy. The same transaction that invalidates the cached copy will also cause the storage condition instruction to fail in the Source. To avoid cache block invalidation and to transfer cache blocks to the Source where the storage condition instruction will fail, the CtoECond message may be provided and used by the Source.

[0093] A CtoECond message can be defined as having at least two possible outcomes when ordered by the consistency controller 24. If the source still has a valid copy of the cache block as indicated in directory 26 when the CtoECond message is ordered and processed, then CtoECond can proceed similarly to an unconditional CtoE message: issuing a snoop and obtaining exclusive status of the cache block. If the source does not have a valid copy of the cache block, the consistency controller 24 can cause the CtoE transaction to fail, thereby returning Ack completion to the source using the CtoE failure indication. The source can terminate the CtoE transaction based on Ack completion.

[0094] like Figure 15 As shown, the consistency controller 24 can be configured to read directory entries for an address (box 194). If the source maintains a valid copy of the cache block (e.g., in a shared state) (decision box 196, "Yes" branch), the consistency controller 24 can be configured to generate a snoop based on the cache state in the directory entry (e.g., a snoop to invalidate the cache block so that the source can change to an exclusive state) (box 198). If the source does not maintain a valid copy of the cache block (decision box 196, "No" branch), the cache controller 24 can be configured to send an acknowledgment of completion to the source, thereby indicating that the CtoECond message failed (box 200). The CtoE transaction can therefore be terminated.

[0095] Turn now Figure 16The diagram illustrates a flowchart of one embodiment of the consistency controller 24 reading directory entries and determining the snooping operation (e.g., in one embodiment, Figure 6 (At least a portion of block 70 in the diagram). However, for ease of understanding, the block diagram is shown in a specific order, but other orders may also be used. Blocks can be executed in parallel within combinational logic in the consistency controller 24. Blocks, combinations of blocks, and / or flowcharts as a whole can be pipelined over multiple clock cycles. The consistency controller 24 can be configured to implement... Figure 16 The operation is shown in the figure.

[0096] like Figure 16 As shown, the consistency controller 24 can be configured to read the directory entry for the requested address (box 202). Based on the cache state in the directory entry, the consistency controller 24 can be configured to generate snoops. For example, based on the cache state of at least Level 1 shared in one of the agents (decision box 204, "Yes" branch), the consistency controller 24 can be configured to launch a SnpFwd snoop to that Level 1 shared agent, thereby instructing the Level 1 shared agent to launch the cache block to the requesting agent. For other agents (e.g., in Level 2 shared state), the consistency controller 24 can be configured to generate an invalidation-only snoop (SnpInv), which instructs the other agents not to launch the cache block to the requesting agent (box 206). In some cases (e.g., a CRdS request requesting a shared copy of the cache block), other agents do not need to receive snoops because these other agents do not need to change their state. If the cache state is a cache state that is at least as permissible as Level 1 shared (e.g., ...), Figure 13 If the implementation scheme includes first-level sharing, ownership, exclusive ownership, or modification, then the agent may have a cache state as at least first-level sharing.

[0097] If no agent has a cache state that is at least Level 1 shared (Decision Box 204, "No" branch), then the consistency controller 24 can be configured to determine whether one or more agents have cache blocks in a Level 2 shared state (Decision Box 208). If yes (Decision Box 208, "Yes" branch), then the consistency controller 24 can be configured to select one of the agents with a Level 2 shared state and issue a SnpFwd request instruction to the selected agent to forward the cache block to the requesting agent. The consistency controller 24 can be configured to generate SnpInv requests for other agents in a Level 2 shared state, which instruct the other agents not to issue the cache block to the requesting agent (Box 210). As mentioned above, if other agents do not need to change their state, they may not generate and issue SnpInv messages.

[0098] If no agent has a cache state in a second-level shared state (Decision Box 208, "No" branch), then the consistency controller 24 can be configured to generate a fill completion and can be configured to cause the memory controller to read cache blocks for emission to the requesting agent (Box 212).

[0099] Figure 17 This is a flowchart illustrating one embodiment of the consistency controller 24 reading directory entries and determining the snooping operation in response to a CRdE Donly request (e.g., in one embodiment, Figure 6 (At least a portion of block 70 in the diagram). However, for ease of understanding, the block diagram is shown in a specific order, but other orders may also be used. Blocks can be executed in parallel within combinational logic in the consistency controller 24. Blocks, combinations of blocks, and / or flowcharts as a whole can be pipelined over multiple clock cycles. The consistency controller 24 can be configured to implement... Figure 17 The operation is shown in the figure.

[0100] As described above, a CRdE Donly request can be used by a coherence agent 14A-14n that wants to modify all bytes in a cache block. Therefore, the coherence controller 24 can cause other agents to invalidate the cache block. If an agent modifies the cache block, the agent can supply the modified cache block to the requesting agent. Otherwise, the agent may not supply the cache block.

[0101] Consistency controller 24 can be configured to read the directory entry for the requested address (box 220). Based on the cache state in the directory entry, consistency controller 24 can be configured to generate snoops. More specifically, if a given agent may have a modified copy of a cache block (e.g., a given agent has a cache block in an exclusive or level 1 state) (box 222, "Yes" branch), cache controller 24 can generate a snoop forwarding to the agent - dirty only (SnpFwdDonly) to launch the cache block to the requesting agent (box 224). As described above, a SnpFwdDonly request can cause the receiving agent to launch the cache block if the data has been modified, otherwise not launch the cache block. In either case, the receiving agent can invalidate the cache block. If the data has been modified and the modified cache block is provided, the receiving agent can launch a fill complete. Otherwise, the receiving agent can launch an Ack complete. If no agent has the modified copy (decision box 222, "No" branch), the consistency controller 24 can be configured to generate a snoop invalidation (SnpInv) for each agent with a cached copy of the cache block (box 226). In another implementation, even if the cache block is modified, the consistency controller 24 can request not to forward the data because the requester is modifying the entire cache block. That is, the consistency controller 24 can cause the agent with the modified copy to invalidate the data without forwarding it.

[0102] Computer System

[0103] Next turn Figure 18 A block diagram of one embodiment of system 700 is shown. In the illustrated embodiment, system 700 includes at least one instance of a system-on-a-chip (SOC) 10 coupled to one or more peripheral devices 704 and external memory 702. A power supply unit (PMU) 708 is provided to supply power voltage to the SOC 10 and to supply one or more power voltages to the memory 702 and / or peripheral devices 154. In some embodiments, more than one instance of SOC 10 may be included (and more than one memory 702 may also be included). In one embodiment, memory 702 may include Figure 1 The memory 12A-12m shown is illustrated.

[0104] Depending on the type of system 700, peripheral device 704 may include any desired circuitry. For example, in one embodiment, system 704 may be a mobile device (e.g., a personal digital assistant (PDA), smartphone, etc.), and peripheral device 704 may include devices for various types of wireless communications, such as Wi-Fi, Bluetooth, cellular, GPS, etc. Peripheral device 704 may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 704 may include user interface devices, such as displays, including touch displays or multi-touch displays, keyboards or other input devices, microphones, speakers, etc. In other embodiments, system 700 may be any type of computing system (e.g., a desktop PC, laptop, workstation, network set-top box, etc.).

[0105] External memory 702 may include any type of memory. For example, external memory 702 may be SRAM, dynamic RAM (DRAM) (such as synchronous DRAM (SDRAM)), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, RAMBUSDRAM, low-power versions of DDR DRAM (e.g., LPDDR, mDDR, etc.), etc. External memory 702 may include one or more memory modules to which memory devices can be mounted, such as single in-line memory modules (SIMM), dual in-line memory modules (DIMM), etc. Alternatively, external memory 702 may include one or more memory devices mounted on the SOC 10 in a chip-on-chip or package-on-package embodiment.

[0106] As shown in the figure, system 700 is illustrated as having applications in a wide range of fields. For example, system 700 can be used as part of a chip, circuit, component, etc., in a desktop computer 710, laptop computer 720, tablet computer 730, cellular or mobile phone 740, or television 750 (or a set-top box coupled to a television). A smartwatch and a health monitoring device 760 are also shown. In some embodiments, the smartwatch may include various general computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functions. For example, the health monitoring device may monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communication to emergency services in the event of a health crisis, etc. In various embodiments, the aforementioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, implantable devices, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0107] System 700 can also be used as part of cloud-based service 770. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 700 can be used in one or more devices in the home in addition to those previously mentioned. For example, home appliances can monitor and detect noteworthy situations. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) can monitor the status of the devices and provide alerts to the homeowner (or, for example, a repair service) upon detecting a specific event. Alternatively, a thermostat can monitor the temperature in the home and can automatically adjust the heating / cooling system based on the homeowner's history of responses to various situations. Figure 18 The document also illustrates the application of System 700 to various modes of transportation. For example, System 700 can be used as a control and / or entertainment system for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, and (for rental or private use) scooters. In various cases, System 700 can be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc. Many of these other implementations are possible and contemplated. It should be noted that... Figure 18 The devices and applications shown are merely illustrative and not intended to be limiting. Other devices are possible and envisioned.

[0108] Computer-readable storage media

[0109] Turn now Figure 19This diagram illustrates a block diagram of one embodiment of a computer-readable storage medium 800. Generally, a computer-readable storage medium can include any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, a computer-readable storage medium can include storage media such as magnetic or optical media, such as discs (fixed or removable), tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-ray discs. Storage media can also include volatile or non-volatile memory media such as RAM (e.g., Synchronous Dynamic RAM (SDRAM), Rambus DRAM (RDRAM), Static RAM (SRAM), etc.), ROM, or flash memory. The storage medium may be physically included within a computer to which instructions / data are provided. Alternatively, the storage medium may be connected to a computer. For example, the storage medium may be connected to a computer via a network or wireless link such as a network-attached storage device. The storage medium may be connected via a peripheral interface such as a Universal Serial Bus (USB). Typically, computer-accessible storage medium 800 can store data in a non-transitory manner, where non-transitory in this context can mean not transmitting instructions / data via signals. For example, a non-transitory storage device can be volatile (and may lose stored instructions / data in response to a power outage) or non-volatile.

[0110] Figure 19 The computer-accessible storage medium 800 can store a database 804 representing the SOC 10. Generally, the database 804 can be a database that can be read by a program and used directly or indirectly to manufacture hardware including the SOC 10. For example, the database can be a behavioral-level description or register-transfer-level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. This description can be read by a synthesis tool, which can synthesize the description to generate a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including the SOC 10. The netlist can then be placed and routed to generate a dataset describing the geometry to be applied to a mask. The mask can then be used in various semiconductor manufacturing steps to produce semiconductor circuits corresponding to the SOC 10. Alternatively, the database 804 on the computer-accessible storage medium 800 can be a netlist (with or without a synthesis library) or a dataset, depending on the requirements.

[0111] While computer-accessible storage medium 800 stores a representation of SOC 10, other implementations may carry a representation of any portion of SOC 10 as needed, including any subset of the consistent agents 14A-14n, memory controllers 22A-22m, non-consistent agents 20A-20p, consistent controller 24, directory 26, etc. Database 804 may represent any of the above portions.

[0112] Based on this disclosure, a system may include: a plurality of consensus agents, wherein a given agent among the plurality of consensus agents includes one or more caches for caching memory data. The system may further include: a memory controller coupled to one or more memory devices, wherein the memory controller includes a directory configured to track which consensus agent among the plurality of consensus agents is caching copies of a plurality of cache blocks in the memory devices and the status of the cached copies among the plurality of consensus agents. Based on a first request from a first agent among the plurality of consensus agents for a first cache block, the memory controller may be configured to: read an entry corresponding to the first cache block from the directory, send a snooping request to a second agent among the plurality of consensus agents that has a cached copy of the first cache block, and include an identifier of the first status of the first cache block in the second agent in the snooping request. Based on the snooping, the second agent can be configured to: compare the first state with the second state of the first cache block in the second agent, and delay processing of the snooping based on a mismatch between the first and second states until the second state changes to the first state in response to different communication relating to a request different from the first request. In one embodiment, the memory controller can be configured to: determine a completion count indicating the number of completions the first agent will receive for the first request, wherein the determination is based on these states from the entry; and include the completion count in a plurality of snoopings issued based on the first request, including the snoopings issued to the second agent. The first agent can be configured to: initialize a completion counter using the completion count based on receiving an initial completion from one of the plurality of coherent agents, update the completion counter based on receiving a subsequent completion from another of the plurality of coherent agents, and complete the first request based on the completion counter. In one embodiment, the memory controller can be configured to: update these states in the entry of the directory to reflect the completion of the first request based on a plurality of snoopings issued according to the first request. In one implementation, the first agent may be configured to detect a second snoop received by the first agent regarding the first cache block, wherein the first agent may be configured to incorporate the second snoop into the first request. In one implementation, the first agent may be configured to process the second snoop after completing the first request. In one implementation, the first agent may be configured to forward the first cache block to a third agent indicated in the second snoop after completing the first request. In one implementation, the third agent may be configured to generate a request to change the condition of a second cache block that is valid at the third agent to exclusive status based on a storage condition instruction.The memory controller may be configured to: determine whether the third agent maintains a valid copy of the second cache block based on a second entry in the directory associated with the second cache block, and the memory controller may be configured to: issue a completion indicating failure to the third agent, and terminate the condition change to exclusive request based on the determination that the third agent no longer maintains the valid copy of the second cache block. In one embodiment, the memory controller may be configured to: issue one or more snoops to other consistent agents among the plurality of consistent agents, as indicated by the second entry, based on the determination that the third agent maintains the valid copy of the second cache block. In one embodiment, the snoop indicates that the second agent will issue the first cache block to the first agent based on the first state being level 1 shared, and wherein the snoop indicates that the second agent will not issue the first cache block based on the first state being level 2 shared. In one embodiment, the snoop indicates that the second agent will issue the first cache block, even if the first state is level 2 shared.

[0113] In another embodiment, a system includes: a plurality of consensus agents, wherein a given agent among the plurality of consensus agents includes one or more caches for caching memory data. The system further includes: a memory controller coupled to one or more memory devices. The memory controller includes a directory configured to track which consensus agent among the plurality of consensus agents is caching copies of a plurality of cache blocks in the memory device and the state of the cached copies among the plurality of consensus agents. Based on a first request from a first agent among the plurality of consensus agents for a first cache block, the memory controller may be configured to: read an entry corresponding to the first cache block from the directory and, based on the entry, issue a snooping request to a second agent among the plurality of consensus agents that has a cached copy of the first cache block. The snooping request may instruct the second agent to issue the first cache block to the first agent based on the entry indicating that the second agent has the first cache block in at least a level-one shared state. The snooping request may also instruct the second agent not to issue the first cache block to the first agent based on a different agent having the first cache block in at least the level-one shared state. In one implementation, if the different agents are in the first-level shared state, then the first agent is in the second-level shared state of the first cache block. In one implementation, the snooping instructs the first agent to invalidate the first cache block based on the fact that the different agents have the first cache block in at least the first-level shared state. In one implementation, the memory controller is configured not to send snooping requests to the second agent based on the fact that the different agents have the first cache block in the first-level shared state and that the first request is for a shared copy of the first cache block. In one implementation, the first request may be for an exclusive state of the first cache block, and the first agent may want to modify the entire first cache block. The snooping may instruct the second agent to issue the first cache block if the first cache block is in a modified state in the second agent. In one implementation, the snooping instructs the second agent to invalidate the first cache block if the first cache block is not in a modified state in the second agent.

[0114] In another embodiment, a system includes: a plurality of consensus agents, wherein a given agent among the plurality of consensus agents includes one or more caches for caching memory data. The system also includes: a memory controller coupled to one or more memory devices. The memory controller includes a directory configured to track which of the plurality of consensus agents is caching copies of a plurality of cache blocks in the memory device and the status of the cached copies among the plurality of consensus agents. Based on a first request for a first cache block, the memory controller may be configured to: read an entry corresponding to the first cache block from the directory and, based on the entry, issue a snooping request to a second agent among the plurality of consensus agents that has a cached copy of the first cache block. The snooping may instruct the second agent to issue the first cache block to the source of the first request based on an attribute associated with the first request having a first value, and the snooping may instruct the second agent to issue the first cache block to the memory controller based on the attribute having a second value. In one embodiment, the attribute is the type of request, the first value is cacheable, and the second value is non-cacheable. In another implementation, the attribute is the source of the first request. In one implementation, the memory controller may be configured to respond to the source of the first request based on receiving the first cache block from the second agent. In one implementation, the memory controller is configured to update the status of the entry in the directory based on issuing multiple snoops in response to the first request to reflect the completion of the first request.

[0115]

[0116] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or substitutions that fall within the substance or scope of this disclosure.

[0117] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with an embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. Given the existence of possible factors outside this disclosure, any potential advantages described herein should not be construed as a claim limitation that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to show one or more types of improvements available to a designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0118] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The embodiments disclosed in this invention are intended to be exemplary and not restrictive, without requiring any statement to the contrary in this invention. Therefore, this application is intended to allow for the coverage of the claims of the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art who are aware of the effective effects of this disclosure.

[0119] For example, features in this application can be combined in any suitable manner. Therefore, new claims may be made for any such combination of features during the proceedings of this patent application (or a patent application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0120] Therefore, while the appended dependent claims may be drafted such that each dependent claim is subordinate to a single other claim, additional dependent relationships are also contemplated. Any combination of dependent features conforming to this disclosure is contemplated, and such combinations may be protected by the claims in this patent application or another patent application. In short, the combinations are not limited to those specifically listed in the appended claims.

[0121] Where appropriate, it is also anticipated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0122]

[0123] Because this disclosure is a legal document, various terms and phrases are subject to administrative and judicial interpretation. It is hereby announced that the following paragraphs, as well as the definitions provided throughout this disclosure, will be used to determine how the claims drafted based on this disclosure should be interpreted.

[0124] Unless the context clearly specifies otherwise, references to the singular form of an item (i.e., nouns or noun phrases preceded by "an," "a," or "the") are intended to mean "one or more." Therefore, references to "item" in a claim do not exclude additional instances of that item without context. "A plurality of" items refers to a collection of two or more items.

[0125] The word “may” is used in this text in a permissible sense (i.e., potentially possible, capable) rather than in a mandatory sense (i.e., must).

[0126] The terms “include” and “including” and their forms are open-ended and mean “including but not limited to”.

[0127] When the term “or” is used in this disclosure relative to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the expression “x or y” is equivalent to “x or y, or both,” and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0128] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0129] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit”, “second circuit”, “specific circuit”, “given circuit”, etc.) refer to different instances of the feature. Furthermore, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0130] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0131] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor along with other unspecified factors. Consider the phrase “responding to B to execute A.” This phrase specifies that B is a factor that triggers the execution of A or a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover implementations where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0132]

[0133] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured” to perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as “configured” to perform a task refers to a physical thing used to perform that task, such as a device, circuit, system with processor units, and memory storing executable program instructions. This phrase is not used herein to refer to intangible things.

[0134] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0135] The term "configured as" is not intended to mean "configurable as". For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA may be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0136] For the purposes of this U.S. patent application based on this disclosure, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended not to invoke 35 USC § 112(f) for that claim element. If an applicant wishes to invoke part 112(f) in the course of filing a U.S. patent application based on this disclosure, it will use the structure “means for [performing a function]” to state the elements of the claims.

[0137] Different “circuits” may be described in this disclosure. These circuits or “circuits” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuitry.

[0138] Therefore, the circuits / units / components and other elements disclosed in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0139] In various implementations, as discussed in the preceding paragraphs, the arrangement of circuits, cells, and other elements defined by the functions or operations they are configured to perform, relative to each other, and the manner in which such circuits / cells / components interact, forms a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain the final design database that is transferred to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented in the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0140] The fact that a circuit of the same specifications can be implemented using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0141] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

[0142] Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. This disclosure is intended to make the following claims interpretable as encompassing all such variations and modifications.

Claims

1. A system for implementing cache coherency, comprising: Multiple consensus agents, wherein a given agent among the multiple consensus agents includes one or more caches for cache memory data; A memory controller coupled to one or more memory devices, wherein the memory controller includes a directory configured to track which of the plurality of consensus agents is caching copies of a plurality of cache blocks in the memory device and the status of the cached copies in the plurality of consensus agents; Wherein, based on a first request for a first cache block from a first agent among the plurality of consistent agents, the memory controller is configured as follows: Read the entry corresponding to the first cache block from the directory. Based on the entry, a snooping request is sent to the second agent among the plurality of consistent agents that has a cached copy of the first cache block, and The identifier of the first state of the first cache block in the second agent is included in the snooping; and Based on the spying, the second agent is configured as follows: The first state is compared with the second state of the first cache block in the second agent, and Processing of the snooping is delayed based on the mismatch between the first state and the second state until the second state changes back to the first state in response to different communication relating to a request different from the first request.

2. The system according to claim 1, The memory controller is configured to: Determine a completion count, indicating the number of completions the first agent will receive in response to the first request, wherein the determination is based on the status from the entry. Include the completion count in a plurality of snoopings issued based on the first request, including the snoopings issued to the second agent; and The first agent is configured as follows: Based on the initial completion received from one of the plurality of consensus agents, the completion counter is initialized using the completion count. The completion counter is updated based on the receipt of subsequent completion from another consensus agent among the plurality of consensus agents, and The first request is completed based on the completion counter.

3. The system of claim 1 or claim 2, wherein the memory controller is configured to: update the status of the entries in the directory to reflect the completion of the first request based on a plurality of snoops issued in accordance with the first request.

4. The system of claim 1 or claim 2, wherein the first agent is configured to: detect a second snooping on the first cache block received by the first agent, wherein the first agent is configured to: incorporate the second snooping into the first request.

5. The system of claim 4, wherein the first agent is configured to process the second snooping after the first request is completed.

6. The system of claim 5, wherein the first agent is configured to forward the first cache block to the third agent indicated in the second snooping after the first request is completed.

7. The system according to any one of claims 1, 2, 5 and 6, wherein: The fourth agent is configured to: generate a request to change the condition of a second cache block that is valid at the fourth agent to an exclusive state, based on storage condition instructions; The memory controller is configured to: determine whether the fourth agent maintains a valid copy of the second cache block based on a second entry in the directory associated with the second cache block, and The memory controller is configured to: based on determining that the fourth agent no longer holds a valid copy of the second cache block, send a completion indicating failure to the fourth agent and terminate the condition change to an exclusive request.

8. The system of claim 7, wherein the memory controller is configured to: based on determining that the fourth agent holds a valid copy of the second cache block, issue one or more snoops to other consistent agents among the plurality of consistent agents, as indicated by the second entry.

9. The system according to any one of claims 1, 2, 5, 6 and 8, wherein the snooping instructs the second agent to issue the first cache block to the first agent based on the first state being level 1 shared, and wherein the snooping instructs the second agent not to issue the first cache block based on the first state being level 2 shared.

10. The system of claim 9, wherein the snooping instructs the second agent to launch the first cache block, even if the first state is a second-level shared state.

11. The system according to any one of claims 1, 2, 5, 6, and 8, wherein, based on a second request for a second cache block from a fourth agent among the plurality of consensus agents, the memory controller is configured to: Read the entry corresponding to the second cache block from the directory, and According to the entry, a snooping is sent to a fifth agent among the plurality of consistent agents that has a cached copy of the first cache block, wherein the snooping instructs the fifth agent to issue the second cache block to the fourth agent based on the entry indicating that the fifth agent has the second cache block in at least a level-one shared state, and wherein the snooping instructs the fifth agent not to issue the second cache block to the fourth agent based on the fact that different agents have the first cache block in at least the level-one shared state.

12. The system of claim 11, wherein the memory controller is configured to: not send a snooping request to the fifth agent based on the fact that the different agents have a second cache block in a second-level shared state and that the second request is a request for a shared copy of the first cache block.

13. The system according to any one of claims 1, 2, 5, 6, 8, 10, and 12, wherein, based on a third request for a third cache block, the memory controller is configured to: Read the entry corresponding to the third cache block from the directory, and According to the entry, a snooping is sent to a sixth agent among the plurality of coherent agents that has a cached copy of the third cache block, wherein the snooping instructs the sixth agent to launch the third cache block to the source of the third request based on a first value of an attribute associated with the third request, and wherein the snooping instructs the sixth agent to launch the third cache block to the memory controller based on a second value of the attribute.

14. The system of claim 13, wherein the attribute is the type of the first request, and wherein the first value is cacheable and the second value is not cacheable.

15. The system of claim 13, wherein the attribute is an identifier of the source.

16. A method for achieving cache coherency, comprising: A memory controller, coupled to one or more memory devices, includes a directory configured to track which of a plurality of consensus agents is caching copies of a plurality of cache blocks in the memory device and the status of the cached copies in the plurality of consensus agents, and to read an entry corresponding to the first cache block from the directory based on a first request from a first agent in the plurality of consensus agents for the first cache block. The memory controller, based on the entry, sends a snooping request to the second agent among the plurality of coherent agents that has a cached copy of the first cache block; The memory controller includes the identifier of the first state of the first cache block in the second agent in the snooping. The second agent compares the first state with the second state of the first cache block in the second agent based on the snooping. as well as Processing of the snooping is delayed based on the mismatch between the first state and the second state until the second state changes back to the first state in response to different communication relating to a request different from the first request.

17. The method of claim 16, further comprising: The first agent detects the second snooping on the first cache block received by the first agent; The first agent incorporates the second snooping into the first request; The second snooping is processed after the first request is completed; as well as After the first request is completed, the first cache block is forwarded to the third agent indicated in the second snoop.

18. The method of claim 16 or 17, wherein the snooping instructs the second agent to issue the first cache block to the first agent based on the first state being level 1 shared, and wherein the snooping instructs the second agent not to issue the first cache block based on the first state being level 2 shared.

19. The method according to claim 16 or 17, further comprising: The memory controller reads the entry corresponding to the second cache block from the directory based on a second request for the second cache block from the fourth agent among the plurality of consistent agents; as well as The memory controller, according to the entry, sends a snoop to a fifth agent among the plurality of coherent agents that has a cached copy of the first cache block, wherein the snoop indicates that the fifth agent will issue the second cache block to the fourth agent based on the entry indicating that the fifth agent has the second cache block in at least a level-one shared state, and wherein the snoop indicates that the fifth agent will not issue the second cache block to the fourth agent based on the fact that different agents have the first cache block in at least the level-one shared state.

20. The method of claim 16 or 17, further comprising: Based on a third request for a third cache block, the memory controller is configured to: The memory controller reads the entry corresponding to the third cache block from the directory based on a third request for the third cache block; and According to the entry, a snooping is sent to a sixth agent among the plurality of coherent agents that has a cached copy of the third cache block, wherein the snooping instructs the sixth agent to launch the third cache block to the source of the third request based on a first value of an attribute associated with the third request, and wherein the snooping instructs the sixth agent to launch the third cache block to the memory controller based on a second value of the attribute.

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