Display device and method of controlling the same

Abstract

A display device includes: a panel driving unit; a display panel including a plurality of pixels; and a processor for controlling the panel driving unit, wherein: in a first mode, the processor controls the panel driving unit such that gate signals are sequentially output to a plurality of gate lines one at a time, thereby processing image data at a first driving frequency; and in a second mode, the processor controls the panel driving unit such that gate signals are output to a plurality of gate lines one at a time, thereby processing image data at a second driving frequency higher than the first driving frequency; and in the second mode, each gate signal output to the plurality of gate lines one at a time via at least two gate lines may have a different output timing from each other.

Description

Technical Field

[0001] This disclosure relates to a display device and a method for controlling the display device, and more particularly to a display device that can display images via high-speed driving and a method for controlling the display device. Background Technology

[0002] With the recent development of electronic technology, images with high frame rates (HFR) are becoming available. Such images can be reproduced without interruption by display devices capable of processing image data at frequencies such as 120Hz or 240Hz (i.e., capable of being driven at high speeds).

[0003] However, traditional display devices can only process image data at a predetermined driving frequency or a frequency lower than the predetermined driving frequency. Therefore, when a driving frequency of, for example, 60Hz is set, there is a problem that the display device cannot operate at a driving frequency of 120Hz or higher.

[0004] This causes interruptions when reproducing game images, motion pictures, etc. with high frame rates (or high frames per second), resulting in users being unable to enjoy the images smoothly. Summary of the Invention

[0005] Technical issues

[0006] This disclosure is designed to solve the above-mentioned problems, and the purpose of this disclosure is to provide a display device capable of smoothly and uninterruptedly reproducing images with high frame rates through high-speed driving, and a method for controlling the display device.

[0007] Technical solution

[0008] A display device according to an embodiment of the present disclosure includes: a panel driving unit; a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines via a plurality of switching elements; and a processor configured to: control the panel driving unit to output gate signals via the plurality of gate lines, and control the panel driving unit to apply data voltages to the plurality of pixels connected to the plurality of switching elements to which the gate signals are output via the plurality of data lines, wherein the processor may be configured to: in a first mode, control the panel driving unit sequentially output gate signals to the plurality of gate lines one at a time, thereby processing image data at a first driving frequency; and in a second mode, control the panel driving unit output gate signals to the plurality of gate lines one at a time, thereby processing image data at a second driving frequency higher than the first driving frequency, and in the second mode, the respective gate signals output to the plurality of gate lines one at a time via at least two gate lines may have different output timings from each other.

[0009] The processor can be configured such that, when operating in a first mode, the control panel driver unit applies data voltages to multiple pixels based on the output timing of gate signals that are sequentially output to multiple switching elements one gate line at a time, and when operating in a second mode, the control panel driver unit applies data voltages to multiple pixels based on the different output timings of individual gate signals that are output to multiple switching elements one gate line at a time.

[0010] The gate line may include a first gate line and a second gate line, and the processor may be configured such that, when operating in a first mode, the control panel driving unit outputs a first gate signal to a plurality of switching elements connected to the first gate line via the first gate line at a first timing, so that a first data voltage is charged into a plurality of pixels connected to the first gate line, and the control panel driving unit outputs a second gate signal to a plurality of switching elements connected to the second gate line via the second gate line at a second timing, so that a second data voltage is charged into a plurality of pixels connected to the second gate line.

[0011] The gate line may include a first gate line and a second gate line, and the processor may be configured such that, when operating in a second mode, the control panel driving unit outputs a first gate signal to a plurality of switching elements connected to the first gate line via the first gate line at a first timing, so that a first data voltage is charged into a plurality of pixels connected to the first gate line, and the control panel driving unit outputs a second gate signal to a plurality of switching elements connected to the second gate line via the second gate line at a second timing, so that the first data voltage and the second data voltage are charged into a plurality of pixels connected to the second gate line.

[0012] Multiple pixels connected to the second gate line can be charged by the first data voltage during the first time period based on the second timing, and can be charged by the second data voltage during the second time period.

[0013] The gate line may also include a third gate line, and the processor may be configured such that the control panel drive unit outputs a third gate signal to a plurality of switching elements connected to the third gate line at a third timing point, thereby charging a second data voltage into a plurality of pixels connected to the third gate line.

[0014] Multiple pixels connected to the second gate line can be charged by a third value between the first value and the second value, wherein multiple pixels connected to the first gate line are charged with the first data voltage at the first value, and multiple pixels connected to the third gate line are charged with the second data voltage at the second value.

[0015] The processor can be configured to: perform an automatic content recognition (ACR) function and determine the type of image data based on image data received from an external source; operate in a first mode and process the image data at a first drive frequency based on determining that the type of image data is a first type; and operate in a second mode and process the image data at a second drive frequency based on determining that the type of image data is a second type.

[0016] The processor can be configured to: determine the number of frames per second (fps) of the image data received from the outside, and operate in a first mode and process the image data at a first drive frequency based on the fps of the image data as a first value, and operate in a second mode and process the image data at a second drive frequency based on the fps of the image data as a second value.

[0017] The processor can be configured to: convert image data into second image data with a second value of fps based on first image data received from the outside with a first value of fps, and process the second image data at a second driving frequency.

[0018] Meanwhile, the control method for a display device according to embodiments of this disclosure includes: outputting gate signals through multiple gate lines; and applying data voltages to multiple pixels connected to multiple switching elements to which the gate signals are output through multiple data lines. In the process of outputting gate signals: in a first mode, gate signals can be sequentially output from one gate line to multiple gate lines at a time to process image data at a first driving frequency; and in a second mode, gate signals can be output from at least two gate lines to multiple gate lines at a time to process image data at a second driving frequency higher than the first driving frequency. In the second mode, each gate signal output from at least two gate lines to multiple gate lines at a time can have different output timings.

[0019] During the application of data voltage: when operating in the first mode, data voltage can be applied to multiple pixels based on the output timing of gate signals that are sequentially output to multiple switching elements one gate line at a time; and when operating in the second mode, data voltage can be applied to multiple pixels based on the different output timing of each gate signal that is output to multiple switching elements one at a time through at least two gate lines.

[0020] The gate line may include a first gate line and a second gate line, and during the output gate signal process: when operating in a first mode, a first gate signal may be output to a plurality of switching elements connected to the first gate line through the first gate line at a first timing, so that a first data voltage is charged into a plurality of pixels connected to the first gate line; and a second gate signal may be output to a plurality of switching elements connected to the second gate line through the second gate line at a second timing, so that a second data voltage is charged into a plurality of pixels connected to the second gate line.

[0021] The gate line may include a first gate line and a second gate line, and during the output gate signal process: when operating in the second mode, a first gate signal may be output to a plurality of switching elements connected to the first gate line through the first gate line at a first timing, so that a first data voltage is charged into a plurality of pixels connected to the first gate line; and a second gate signal may be output to a plurality of switching elements connected to the second gate line through the second gate line at a second timing, so that the first data voltage and the second data voltage are charged into a plurality of pixels connected to the second gate line.

[0022] Multiple pixels connected to the second gate line can be charged by the first data voltage during the first time period based on the second timing, and can be charged by the second data voltage during the second time period.

[0023] The gate line may also include a third gate line, and during the output gate signal process: the third gate signal can be output through the third gate line to multiple switching elements connected to the third gate line at a third timing point, so that the second data voltage is charged into multiple pixels connected to the third gate line.

[0024] Multiple pixels connected to the second gate line can be charged by a third value between the first value and the second value, wherein multiple pixels connected to the first gate line are charged with the first data voltage at the first value, and multiple pixels connected to the third gate line are charged with the second data voltage at the second value.

[0025] Meanwhile, the control method for the display device may also include: based on receiving image data from the outside, performing an automatic content recognition (ACR) function and determining the type of image data; based on determining that the type of image data is a first type, operating in a first mode and processing the image data at a first driving frequency; and based on determining that the type of image data is a second type, operating in a second mode and processing the image data at a second driving frequency.

[0026] Furthermore, the control method for the display device may also include: determining the number of frames per second (fps) of the image data based on receiving image data from the outside; operating in a first mode and processing the image data at a first driving frequency based on the fps of the image data as a first value; and operating in a second mode and processing the image data at a second driving frequency based on the fps of the image data as a second value.

[0027] Furthermore, the control method for the display device may also include: based on first image data with a first value of fps received from the outside, converting the image data into second image data with a second value of fps, and processing the second image data at a second driving frequency.

[0028] Effects of the present invention

[0029] According to the various embodiments of this disclosure as described above, a display device capable of smoothly and uninterruptedly reproducing images with high frame rates and a method for controlling the display device can be provided.

[0030] Furthermore, according to this disclosure, the output timing of each gate signal is controlled differently by outputting each gate signal through at least two gate lines at a time, thus compensating for the resolution degradation that may occur due to outputting each gate signal at the same timing. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0032] Figure 2 This is a diagram illustrating a driving display device according to an embodiment of the present disclosure;

[0033] Figure 3 This is a diagram illustrating an embodiment of outputting a gate signal through at least two gate lines at a time, according to an embodiment of the present disclosure;

[0034] Figure 4 This is a diagram illustrating an embodiment of outputting gate signals sequentially one gate line at a time according to an embodiment of the present disclosure;

[0035] Figure 5 This is a diagram illustrating the configuration of a display device according to an embodiment of the present disclosure;

[0036] Figure 6 This is a block diagram of a display device according to an embodiment of the present disclosure;

[0037] Figure 7 These are detailed block diagrams of a display device according to embodiments of the present disclosure; and

[0038] Figure 8 This is a flowchart illustrating a control method for a display according to an embodiment of the present disclosure. Detailed Implementation

[0039] First, the terms used in this specification and claims are general terms chosen with consideration of the functions described in the disclosure. However, these terms may vary depending on the intent of those skilled in the art, legal or technical specifications, and the emergence of new technologies. Furthermore, there are terms arbitrarily designated by the applicant, the meaning of which can be explained according to the definitions in this specification. Terms not explicitly defined in this disclosure may be explained based on the overall content of this specification and common technical knowledge in the relevant field.

[0040] Furthermore, if it is determined that a detailed description of a known function or configuration in the course of describing this disclosure may unnecessarily obscure the spirit of the disclosure, such detailed description will be omitted or removed.

[0041] Furthermore, although embodiments of this disclosure will be described in detail with reference to the following drawings and the content described therein, this disclosure is not intended to be limited by the embodiments.

[0042] This disclosure will be described in detail below with reference to the accompanying drawings.

[0043] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure, and Figure 2 This is a diagram illustrating a driving display device according to an embodiment of the present disclosure.

[0044] According to embodiments of this disclosure, the display device 100 may be various types of electronic devices including a display, such as a TV, monitor, laptop computer, tablet computer, PDA, smartphone, etc.

[0045] Reference Figure 1 The display device 100 according to the embodiments of the present disclosure may include a display panel 110, a panel driving unit 120 and a processor 130.

[0046] Display panel 110 can display various images. As an example, display panel 110 can display not only pre-stored images, but also images received from external devices. Here, external devices can be various types of electronic devices capable of sending images to display device 100, such as servers, computers, laptops, smartphones, etc.

[0047] Meanwhile, the images include at least one of still images or moving images, and the display panel 110 can display various images such as broadcast content, multimedia content, etc. In addition, the display panel 110 can display various types of user interfaces (UIs) and icons.

[0048] Specifically, the display panel 110 can display images with a high frame rate (HFR) for example, through a panel driving unit 120 operating at a driving frequency of 120 (Hz) or 240 (Hz). Here, an HFR image is an image whose frames per second (fps) is, for example, 120 frames or more; it can be, for example, a game image, a motion image, etc., but is not necessarily limited to this.

[0049] The display panel 110 described above can be implemented as a liquid crystal display (LCD) panel. However, according to the embodiment, the display panel 110 can be implemented as various types of displays, such as light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), liquid crystal on silicon (LCoS), digital light processing (DLP), etc. Furthermore, the display 110 may also include driving circuitry, which can be implemented in the form of a-si TFTs, low-temperature polycrystalline silicon (LTPS) TFTs, organic TFTs (OTFTs), etc., and a backlight unit, etc.

[0050] Furthermore, the display panel 110 can be combined with a touch detection unit to realize a touch screen.

[0051] In addition, the display panel 110 may include multiple pixels connected to multiple gate lines and multiple data lines via multiple switching elements.

[0052] The panel driving unit 120 can display images using multiple pixels included in the display panel 110.

[0053] Reference Figure 2 The panel driving unit 120 may include a gate driving unit 121 and a data driving unit 122. The gate driving unit 121 is connected to the switching elements included in each pixel PX through multiple gate lines GL1, GL2, ..., and GLn, and the data driving unit 122 is connected to the switching elements included in each pixel PX through multiple data lines DL1, DL2, ..., and DLn.

[0054] Here, a pixel may include a switching element, a pixel electrode connected to the switching element, and a common electrode.

[0055] In addition, the switching element can be, for example, a thin-film transistor (TFT).

[0056] The switching element can be turned on by a gate signal output through a gate line. In this case, as described later, multiple data lines connected to the data driving unit 122 can be electrically connected to multiple on switches, and the data driving unit 122 can apply (or charge) a data voltage to the pixel electrode (e.g., a capacitor) included in each pixel along the multiple data lines. For this purpose, a first terminal of the switching element can be connected to the gate line, and a second terminal of the switching element can be connected to the data line.

[0057] Meanwhile, when a gate low signal is output through the gate line, the switching element can be turned off, and in this case, the data voltage charged into the pixel electrode can be maintained for a predetermined time.

[0058] The gate drive unit 121 can receive gate drive control signals from the processor 130. Here, the gate drive control signals may include: a scan start signal containing scan start information; and a clock control signal for controlling the output timing of the gate signal.

[0059] Furthermore, the gate drive unit 121 can adjust the output timing of the gate signal according to the scan start signal. Here, the gate signal is an example, and it can be output as a pulse signal sequentially to the switching elements included in each pixel PX through at least one gate line.

[0060] In this configuration, the switching element can be turned on by a gate signal output through the gate line, and the data line and pixel electrode can be electrically connected.

[0061] According to embodiments of this disclosure, when the display device 100 operates in a first mode, the gate driving unit 121 can sequentially output gate signals one gate line at a time. (See below for further details.) Figure 4 This needs to be explained.

[0062] Furthermore, when the display device 100 operates in the second mode, the gate driving unit 121 can output gate signals through at least two gate lines at a time. (See below for further details.) Figure 3 This needs to be explained.

[0063] The data driving unit 122 can receive data driving control signals and digital image signals from the processor 130. Here, the digital image signals may include information about multiple grayscale values ​​corresponding to multiple pixels in at least one matrix (or, a horizontal line) located among multiple pixels.

[0064] Furthermore, the data driving unit 122 can obtain a data voltage (or grayscale voltage) corresponding to the digital image signal based on information about multiple grayscale values ​​included in the digital image signal. Then, the data driving unit 122 can apply the data voltage to multiple pixel electrodes included in multiple pixels through multiple data lines.

[0065] Here, the pixel, including the pixel electrode to which the data voltage is applied, can be a pixel including a switching element that is turned on according to the gate signal.

[0066] The data voltage applied via multiple data lines can be applied to the pixel electrode of the pixel including the switching element through a conducting switching element. For this purpose, the third terminal of the switching element can be connected to the pixel electrode included in each pixel.

[0067] Simultaneously, based on the difference between the data voltage applied to the pixel electrode and the common voltage applied to the common electrode, the liquid crystal particles in each pixel can change their orientation. Accordingly, the transmittance of each pixel changes, and the display panel 110 achieves grayscale according to the change in transmittance.

[0068] Processor 130 controls the overall operation of display device 100. Processor 130 can control hardware or software components connected to it and perform various data processing and operations by driving an operating system or application. Furthermore, processor 130 can load and process instructions or data received from at least one of other components into volatile memory and store various data in non-volatile memory. Processor 130 may be, for example, a timing controller, but is not limited thereto.

[0069] The processor 120 can control the control drive unit 120 (e.g., gate drive unit 121) to output gate signals through multiple gate lines, and control the control drive unit 120 (e.g., data drive unit 122) to apply data voltages to multiple pixels connected to multiple switching elements to which the gate signals are output through multiple data lines.

[0070] Specifically, the processor 130 can process digital image signals (or image data) received from the outside and generate digital image signals corresponding to each pixel of the display panel 110. Then, the processor 130 can generate gate drive control signals and data drive control signals based on horizontal synchronization signals, vertical synchronization signals and clock signals received from the outside, send the gate drive control signals to the gate drive unit 121, and send the digital image signals and data drive control signals to the data drive unit 122.

[0071] Here, the gate drive control signal may include: a scan start signal containing scan start information; and a clock control signal for controlling the output timing of the gate signal. The gate drive unit 121 may output the gate signal at an appropriate timing point through at least one gate line or through at least two gate lines at a time, depending on the scan start signal or the clock control signal.

[0072] In this case, multiple switching elements connected to the gate line of the output gate signal can be turned on.

[0073] Data-driven control signals may include, for example, a horizontal synchronization start signal containing information about the start of data transmission, and control signals that control the application of data voltages through multiple data lines.

[0074] The data driving unit 122 can apply data voltages to multiple pixels via multiple data lines at appropriate timings based on the horizontal synchronization start signal and the control signal. Here, the pixels to which the data voltages are applied can be pixels connected to a switching element that is turned on when the gate signal is output.

[0075] The processor 130 can process image data received from the outside at a high-speed drive frequency.

[0076] Specifically, the processor 130 can process image data at a second frequency higher than a first frequency preset in the display device 100. Here, the first frequency can be 60 (Hz) and the second frequency can be 120 (Hz). However, this is merely an embodiment, and the first and second frequencies can vary depending on the embodiment, for example, the first frequency is 120 (Hz) and the second frequency is 240 (Hz), etc.

[0077] Therefore, the processor 130 can control the panel driving unit 120 to output gate signals through at least two gate lines at a time. Specifically, the processor 130 can control the panel driving unit 120 to output gate signals with different output timings through at least two gate lines at a time. Here, the panel driving unit 120 can be the aforementioned gate driving unit 121.

[0078] As an example, processor 130 can control gate drive unit 121 to output gate signals through two gate lines at a time. Here, as described above, the individual gate signals output to multiple gate lines through two gate lines at a time can have different output timings.

[0079] Specifically, the processor 130 can send a scan start signal, including information about the start of the scan, and a clock control signal for outputting gate signals through at least two gate lines at a time to the gate drive unit 121, and the gate drive unit 121 can output gate signals with different timings through two gate lines at a time according to the scan start signal and the clock control signal.

[0080] Then, the processor 130 can control the control unit 120 (e.g., the data drive unit 122) to apply data voltages to multiple pixels based on different output timings of individual gate signals output to multiple switching elements at a time through at least two gate lines.

[0081] As an example, refer to Figure 3According to an embodiment of the present disclosure, the gate driving unit 121 can be connected to the first to eighth gate lines, and the processor 130 can control the gate driving unit 121 to output gate signals with different output timings through two gate lines at one time.

[0082] Specifically, the processor 130 can control the control unit 120 to output a first gate signal CKV1 to a plurality of switching elements connected to the first gate line at a first timing, so that the first data voltage is charged into a plurality of pixels connected to the first gate line, and control the control unit 120 to output a second gate signal CKV2 to a plurality of switching elements connected to the second gate line at a second timing, so that a portion of the first data voltage and a portion of the second data voltage are charged into a plurality of pixels connected to the second gate line.

[0083] More specifically, the processor 130 can control the gate driving unit 121 to output a gate signal CKV1 to a plurality of switching elements connected to the first gate line at a first timing, and control the gate driving unit 121 to output a second gate signal CKV2 to a plurality of switching elements connected to the second gate line at a second timing later than the first timing. Here, the second timing can be an earlier timing than the third timing, which will be described later, where a gate signal CKV3 is output through a third gate line.

[0084] In this configuration, multiple switching elements connected to the first gate line and the second gate line can be turned on by gate signals CKV1 and CKV2 output through the gate lines. Specifically, the multiple switching elements connected to the first gate line can be turned on by the gate signal CKV1 output through the first gate line at a first timing point, and correspondingly, the pixel electrode electrically connected to the first gate line can be electrically connected to the data line connected to the data driving unit 122 at the first timing point. Then, the data driving unit 122 can apply a first data voltage to the pixel electrode electrically connected to the first gate line during a predetermined time period starting from the first timing point according to a drive control signal, and correspondingly, the pixel electrode electrically connected to the first gate line can be charged by the first data voltage applied by the data driving unit 122.

[0085] Furthermore, multiple switching elements connected to the second gate line can be turned on by the gate signal CKV2 output through the second gate line at the second timing, and correspondingly, the pixel electrode electrically connected to the second gate line can be electrically connected to the data line connected to the data driving unit 122 for a predetermined time period starting from the second timing.

[0086] Furthermore, as described above, the data driving unit 122 applies a first data voltage to the pixel electrode electrically connected to the data line during a predetermined time period starting from the first timing according to the driving control signal, and correspondingly, a portion of the first data voltage applied by the data driving unit 122 can be charged in the pixel electrode electrically connected to the second gate line.

[0087] Subsequently, the processor 130 can control the gate driving unit 121 to output the gate signal CKV3 to a plurality of switching elements connected to the third gate line through the third gate line at the third timing, and control the gate driving unit 121 to output the gate signal CKV4 to a plurality of switching elements connected to the fourth gate line through the fourth gate line at the fourth timing.

[0088] Here, multiple switching elements connected to the third and fourth gate lines can be turned on by gate signals CKV3 and CKV4 output through the gate lines.

[0089] Specifically, multiple switching elements connected to the third gate line can be turned on by the gate signal CKV3 output through the third gate line at a third timing point, and correspondingly, the pixel electrode electrically connected to the third gate line can be electrically connected to the data line connected to the data driving unit 122 at the third timing point. Then, the data driving unit 122 can apply a second data voltage to the pixel electrode electrically connected to the third gate line during a predetermined time period starting from the third timing point according to the driving control signal, and correspondingly, the pixel electrode electrically connected to the third gate line can be charged by the second data voltage applied by the data driving unit 122.

[0090] Simultaneously, as described above, during a predetermined time period starting from the second timing, the pixel electrode electrically connected to the second gate line can be electrically connected to the data line connected to the data driving unit 122. As an example, during a first time period starting from the second timing, the pixel electrode electrically connected to the second gate line can be electrically connected to the data line providing a first data voltage, and can be electrically connected to the data line providing a second data voltage during a second time period starting from the third timing. Here, the sum of the first and second times can be the aforementioned predetermined time. Therefore, the pixel electrode electrically connected to the second gate line can be charged by the first data voltage during the first time period and can be charged by the second data voltage during the second time period.

[0091] In other words, multiple pixels connected to the second gate line can be charged by the first data voltage during the first time period based on the second timing mentioned above, and can be charged by the second data voltage during the second time period.

[0092] Therefore, multiple pixels connected to the second gate line can be charged by a third value between the first value and the second value, wherein multiple pixels connected to the first gate line are charged with the first data voltage at the first value, and multiple pixels connected to the third gate line are charged with the second data voltage at the second value. Here, the third value can be an intermediate value between the first value and the second value, but is not limited to this.

[0093] Similarly, during a predetermined time period starting from the fourth timing, the pixel electrode electrically connected to the fourth gate line can be electrically connected to the data line connected to the data driving unit 122. As an example, during a first time period starting from the fourth timing, the pixel electrode electrically connected to the fourth gate line can be electrically connected to the data line providing a second data voltage, and can be electrically connected to the data line providing a third data voltage during a second time period starting from the fifth timing. Therefore, the pixel electrode electrically connected to the fourth gate line can be charged by the second data voltage during the first time period and can be charged by the third data voltage during the second time period.

[0094] Thus, the gate driving unit 121 can output a gate signal CKV5 to multiple switching elements connected to the fifth gate line at the fifth timing point, and output a gate signal CKV6 to multiple switching elements connected to the sixth gate line at the sixth timing point. Therefore, the third data voltage output by the data driving unit 122 can charge multiple pixels electrically connected to the fifth gate line, and a portion of the third data voltage and a portion of the fourth data voltage output by the data driving unit 122 can charge multiple pixels electrically connected to the sixth gate line.

[0095] Then, the gate driving unit 121 can output a gate signal CKV7 to a plurality of switching elements connected to the seventh gate line at a seventh timing point, and output a gate signal CKV8 to a plurality of switching elements connected to the eighth gate line at an eighth timing point. Therefore, the fourth data voltage output by the data driving unit 122 can charge a plurality of pixels electrically connected to the seventh gate line, and a portion of the fourth data voltage and a portion of the fifth data voltage output by the data driving unit 122 can charge a plurality of pixels electrically connected to the eighth gate line.

[0096] Simultaneously, based on the difference between the data voltage applied to the pixel electrode and the common voltage applied to the common electrode, the liquid crystal particles included in each pixel can change their orientation. Accordingly, the light transmittance of each pixel changes according to the application of the aforementioned data voltage, and the display panel 110 implements grayscale according to the change in light transmittance.

[0097] As described above, compared to conventional display devices that output gate signals via one gate line at a time, the present disclosure allows for the output of gate signals via at least two gate lines at a time, thus enabling high-speed driving and, consequently, uninterrupted reproduction of HFR images. For example, in the case of conventional display devices operating at 60 Hz, there is a problem that image data requiring a 120 Hz drive frequency cannot be smoothly reproduced. However, in the present disclosure, even with the basic drive frequency of the display device set to 60 Hz, the device can operate at a drive frequency of 120 Hz or higher by outputting gate signals via at least two gate lines at a time, and accordingly, uninterrupted reproduction of HFR images requiring drive frequencies such as 120 Hz can be achieved.

[0098] Furthermore, in this disclosure, the output timing of the gate signal output in each gate line is controlled to be different when the gate signal is output through at least two gate lines at a time, thus enabling compensation for resolution degradation. In other words, compared to the case where the gate signal is output through at least two gate lines at the same timing, in this disclosure, resolution degradation can be compensated for by image quality interpolation between pixel lines.

[0099] Meanwhile, the above explanation describes an embodiment of outputting gate signals through two gate lines at a time. However, in this disclosure, depending on the frame rate, fps, etc. of the image data, gate signals can be output through at least three gate lines at a time.

[0100] in addition, Figure 3 The output timing of the gate signal and the output timing of the data voltage shown are examples, and the timing of the gate signal output by the gate drive unit 121 and the timing of the data voltage output by the data drive unit 122 can be synchronized with... Figure 3 They are different. That is to say, the timing of the gate signal output by the gate driving unit 121 and the timing of the data voltage output by the data driving unit 122 can be set or changed in various ways according to the embodiments.

[0101] Meanwhile, the processor 130 can control the gate driving unit 121 to output gate signals through one gate line or at least two gate lines at a time, depending on the mode of the display device.

[0102] Specifically, in the first mode, in order to process image data at a first driving frequency, the processor 130 can control the control unit 120 (e.g., the gate driving unit 121) to sequentially output gate signals through one gate line at a time, and in the second mode, in order to process image data at a second driving frequency higher than the first driving frequency, the processor 130 can control the control unit 120 (e.g., the gate driving unit 121) to output gate signals through at least two gate lines at a time.

[0103] Here, the operation of the display device 100 in the second mode is as follows: Figure 3 As explained in the document.

[0104] In the following text, reference will be made to Figure 4 This describes the operation of the display device 100 according to the first mode.

[0105] The processor 130 can process image data received from the outside at a basic drive frequency.

[0106] Specifically, the processor 130 can process image data at a driving frequency preset in the display device 100. Here, the preset driving frequency can be, for example, 60 (Hz), but is not limited to this.

[0107] Therefore, the processor 130 can control the panel driving unit 120 to sequentially output gate signals one gate line at a time. Here, the panel driving unit 120 can be the aforementioned gate driving unit 121.

[0108] Specifically, the processor 130 can send a scan start signal, including information about the start of the scan, and a clock control signal for controlling the output timing of the gate signal one gate line at a time to the gate drive unit 121. The gate drive unit 121 can adjust the output timing of the gate signal one gate line at a time according to the scan start signal and the clock control signal, thereby sequentially outputting the gate signal one gate line at a time.

[0109] Then, when operating in the first mode, the processor 130 can control the control unit 120 to apply data voltages to multiple pixels based on the output timing of gate signals that are sequentially output to multiple switching elements one gate line at a time.

[0110] As an example, refer to Figure 4 According to the embodiments of the present disclosure, the gate driving unit 121 can be connected to the first to eighth gate lines, and the processor 130 can control the gate driving unit 121 to output gate signals one gate line at a time.

[0111] In this case, the gate drive unit 121 can output the gate signal CKV1 to a plurality of switching elements connected to the first gate line at the first timing.

[0112] Therefore, the multiple switching elements connected to the first gate line can be turned on by the gate signal output through the first gate line. Then, as the switching elements are turned on, the pixel electrode included in the pixel can be electrically connected to the data line connected to the data driving unit 122.

[0113] Therefore, the first data voltage output by the data driving unit 122 can be applied to the pixel electrode connected to the conducting switching element through multiple data lines.

[0114] Subsequently, the gate drive unit 121 can output the gate signal CKV2 to a plurality of switching elements connected to the second gate line at the second timing.

[0115] Here, multiple switching elements connected to the second gate line can be turned on by a gate signal output through the gate line. Then, as the switching elements are turned on, the pixel electrode included in the pixel can be electrically connected to the data line connected to the data driving unit 122.

[0116] Therefore, the second data voltage output by the data driving unit 122 can be applied to the pixel electrode connected to the conducting switching element through multiple data lines.

[0117] In other words, when operating in the first mode, the processor 130 can control the control unit 120 to output a first gate signal to a plurality of switching elements connected to the first gate line through the first gate line at a first timing, so that the first data voltage is charged into a plurality of pixels connected to the first gate line, and control the control unit 120 to output a second gate signal to a plurality of switching elements connected to the second gate line through the second gate line at a second timing, so that the second data voltage is charged into a plurality of pixels connected to the second gate line.

[0118] In a similar manner, the gate driving unit 121 can output a gate signal CKVn to a plurality of switching elements connected to the nth gate line at the nth timing, and the nth data voltage output by the data driving unit 122 can be applied to the pixel electrode connected to the turned-on switching element through a plurality of data lines.

[0119] at the same time, Figure 4 The output timing of the gate signal and the output timing of the data voltage shown are examples, and the timing of the gate signal output by the gate drive unit 121 and the timing of the data voltage output by the data drive unit 122 can be synchronized with... Figure 4 They are different. That is to say, the timing of the gate signal output by the gate driving unit 121 and the timing of the data voltage output by the data driving unit 122 can be set or changed in various ways according to the embodiments.

[0120] As the first to nth data voltages are applied, the transmittance of each pixel changes, and the display panel 110 realizes grayscale according to the change in transmittance.

[0121] At the same time, the display device 100 can be set to a mode according to user instructions received through the input unit.

[0122] Specifically, if a user instruction is received via the input unit to set the mode of the display device 100 to a first mode, the processor 130 can operate in the first mode and process image data at a first driving frequency; if a user instruction is received via the input unit to set the mode of the display device 100 to a second mode, the processor 130 can operate in the second mode and process image data at a second driving frequency higher than the first driving frequency.

[0123] Here, the feature of processing at the first driving frequency can be that the gate driving unit 121 outputs the gate signal sequentially through one gate line at a time, while the feature of processing at the second driving frequency can be that the gate driving unit 121 outputs the gate signal through at least two gate lines at different timing points.

[0124] Meanwhile, the input unit can be not only a keyboard and mouse, but also a touch screen. Furthermore, the input unit is a communication unit, and if a signal corresponding to a user instruction for setting or changing the mode of the display device 100 is received from an external device via the communication unit, the processor 130 can set the mode of the display device 100 to a first mode or a second mode based on the user instruction. For this purpose, the processor 130 can display a user interface (UI) for setting the mode of the display device on the screen of the display panel 110.

[0125] At the same time, the processor 130 can automatically set or change the mode of the display device 100.

[0126] As an example, if image data is received from an external source, the processor 130 can perform an Automatic Content Recognition (ACR) function and determine the type of the image data. Here, the ACR function is a technique for identifying image data by extracting image or sound information from the content. As an example, the ACR function could be a technique that compares the extracted image or sound information from the content with pre-stored image or sound information to obtain information such as the content's title and type. For this purpose, the display device 100 may have already stored image or sound information for multiple contents. Alternatively, the processor 130 can extract image or sound information from the image data and send the extracted image or sound information to an external device (e.g., a server), receiving information from the external device regarding the title, type, etc., of the content determined based on the image or sound information from the image data.

[0127] Then, if the type of image data is determined to be a first type by the ACR function, the processor 130 can operate in the first mode and process the image data at a first drive frequency. If the type of image data is determined to be a second type, the processor 130 can operate in the second mode and process the image data at a second drive frequency.

[0128] Here, the first type of image can be a general broadcast image, etc., and the second type of image can be a game image or a sports image, but the images are not limited to these.

[0129] Meanwhile, the processor 130 can set or change the mode of the display device 100 based on the number of frames per second (fps) of the image data received from the outside.

[0130] Therefore, when image data is received from an external source, the processor 130 can determine the number of frames per second (fps) of the image data. As an example, the processor 130 can determine the fps of the image data based on the metadata of the image data.

[0131] Then, if the frame rate of the image data is a first value, the processor 130 can operate in a first mode and process the image data at a first driving frequency; if the frame rate of the image data is a second value, the processor 130 can operate in a second mode and process the image data at a second driving frequency.

[0132] Here, the first value can be 60 (fps) and the second value can be 120 (fps), but these values ​​are not limited to these. Therefore, information about the first and second values ​​can already be stored in the display device 100.

[0133] At the same time, the processor 130 can change the fps (or frame rate) of the image data received from the outside and process the image data through high-speed drive.

[0134] As an example, if first image data with a first value of fps is received from the outside, the processor 130 can convert the image data into second image data with a second value of fps and process the second image data at a second driving frequency.

[0135] Here, the first value can be 60 (fps) and the second value can be 120 (fps), but these values ​​are not limited to these.

[0136] For this purpose, the display device 100 may also include a frame rate converter (FRC) for converting the fps or frame rate of image data.

[0137] Furthermore, if the frame rate (fps) of the image data is determined to have a first value based on the metadata of the image data received from the outside, the processor 130 can convert the fps of the image data into a second value via FRC and process the image data at a second drive frequency.

[0138] at the same time, Figure 2 The gate driving unit 121 in the middle can also be implemented as follows: Figure 5The array-on-gate driver (GOA) is shown. Here, GOA refers to a data driving circuit fabricated on a substrate surrounding the pixel that performs the functions described above for the gate driving unit 121, and the GOA can output gate signals one gate line at a time or at least two gate lines at a time, depending on the control of the processor 130.

[0139] When the GOA outputs a gate signal along the gate line, the pixel electrode of pixel 10 (the capacitor to the left of reference numeral 10) can be electrically connected to the data line, and correspondingly, a data voltage can be applied to the pixel electrode through the data line. Therefore, depending on the pixel electrode and the common electrode (the capacitor to the right of reference numeral 10), the arrangement of the liquid crystal particles in pixel 10 can be different, the light transmittance of pixel 10 can vary according to the arrangement of the liquid crystal particles, and pixel 10 can achieve grayscale levels that vary according to the light transmittance.

[0140] Figure 6 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0141] exist Figure 2 For ease of explanation, the display panel 110 and the panel driving unit 120 are shown separately, but the panel driving unit 120 may be included in, for example, Figure 6 In the display panel 110 shown.

[0142] in addition, Figure 2 The processor 130 in the middle can not only be implemented as a component, but also like Figure 6 The image control unit 131 and drive control unit 132 are implemented as separate components.

[0143] Here, the image control unit 131 can receive image data from an external source and determine the drive frequency used to process the image data. To this end, the image control unit 131 can determine the type of image data using the aforementioned ACR function, or determine the frame rate or fps of the image data based on the metadata of the image data.

[0144] Then, the image control unit 131 can determine the driving frequency of the display device 100 based on the type of image data, the frame rate or fps of the image data, and control the drive control unit 132 to process the image data at the driving frequency.

[0145] Alternatively, the image control unit 131 may determine the driving frequency of the display device 100 based on the mode of the display device 100 selected according to the user instruction, and control the drive control unit 132 to process image data at the driving frequency.

[0146] The drive control unit 132 can process image data at a basic drive frequency or a high-speed drive frequency according to the control of the image control unit 131. Here, the basic drive frequency can be the first drive frequency mentioned above, and the high-speed drive frequency can be the second drive frequency mentioned above.

[0147] Specifically, when the image control unit 131 receives a control signal and image data for processing image data at a first driving frequency, the image processing unit of the drive control unit 132 can process the image data into image data corresponding to the first driving frequency. Then, the signal generation unit of the drive control unit 132 can generate image signals corresponding to multiple pixels in the horizontal line based on the image data corresponding to the first driving frequency, and send the signals to the source IC of the display panel 110 (which can be the aforementioned data driving unit).

[0148] In addition, the gate timing control unit of the drive control unit 132 can send a signal to the gate unit of the display panel 110 (which may be the gate driving unit mentioned above) for outputting a gate signal through one gate line at a time, thereby processing image data at a first driving frequency.

[0149] When the image control unit 132 receives a control signal and image data for processing image data at a second driving frequency from the image control unit 131, the image processing unit of the drive control unit 132 can process the image data into image data corresponding to the second driving frequency. Then, the signal generation unit of the drive control unit 132 can generate an image signal corresponding to multiple pixels in the horizontal line based on the image data corresponding to the second driving frequency, and send the signal to the source IC of the display panel 110.

[0150] Furthermore, the gate timing control unit of the drive control unit 132 can send signals to the gate units of the display panel 110 for outputting gate signals through at least two gate lines at a time, thereby processing image data at a second drive frequency. Here, each gate signal can have different output timings as described above.

[0151] Figure 7 This is a detailed block diagram illustrating a display device according to an embodiment of the present disclosure.

[0152] Reference Figure 7 The display panel 100 according to embodiments of this disclosure may include a display panel 110, a panel driving unit 120, a storage unit 140, an input unit 150, a communication unit 160, a microphone 170, a speaker 180, a signal processing unit 190, and a processor 130. Hereinafter, portions that are repeated from the above description are omitted, or the description is simplified.

[0153] Storage unit 140 can store the operating system (OS) used to control the overall operation of the components of display device 100, as well as instructions or data related to the components of display device 100.

[0154] Therefore, the processor 130 can control multiple hardware or software components of the display device 100 by using various instructions or data stored in the storage unit 140, load instructions or data received from at least one other component into volatile memory and process them, and store various data in non-volatile memory.

[0155] The input unit 150 can receive various user instructions. The processor 130 can execute functions corresponding to the user instructions input through the input unit 150.

[0156] For example, the input unit 150 can receive user commands for setting the mode of the display device 100. Furthermore, the input unit 150 can receive user commands for performing actions such as powering on, changing channels, and adjusting volume. The processor 130 can then power on the display device 100 or perform actions such as changing channels or adjusting volume based on the input user commands.

[0157] Therefore, the input unit 150 can be implemented as an input panel. The input panel can take the form of a touchpad, a keypad including various function keys, numeric keys, special keys, character keys, etc., or a touch screen.

[0158] The communication unit 160 can communicate with external devices and send and receive various types of data. For example, the communication unit 160 can communicate with electronic devices not only through near-field communication networks (local area networks (LANs)), the Internet, and mobile communication networks, but also through various communication methods such as Bluetooth (BT), Bluetooth Low Energy (BLE), Wi-Fi, Zigbee, and NFC.

[0159] Therefore, the communication unit 160 may include various communication modules for performing network communication. For example, the communication unit 160 may include a Bluetooth chip, a Wi-Fi chip, a wireless communication chip, etc.

[0160] Specifically, the communication unit 160 can perform communication with external devices and receive image data from external devices. Here, the external device can be a server, smartphone, computer, laptop computer, etc., but is not limited to these.

[0161] Microphone 170 can receive user voice. Here, user voice can be voice used to perform specific functions of display device 100. If user voice is received through microphone 170, processor 130 can analyze user voice using a speech-to-text (STT) algorithm and execute the function corresponding to user voice.

[0162] As an example, if a user voice for setting the mode of the display device 100 is received via microphone 170, the processor 130 can operate in a first mode and process image data at a first drive frequency according to the user voice, or operate in a second mode and process image data at a second drive frequency.

[0163] The speaker 180 can output various sounds. For example, the speaker 180 can output sound corresponding to image data.

[0164] The signal processing unit 190 performs signal processing on the image data received through the communication unit 160. Specifically, the signal processing unit 190 can perform operations such as decoding, scaling, and frame rate conversion on the image constituting the image data, and process the image data into a signal that can be output from the display device 100. In addition, the signal processing unit 190 can perform signal processing such as decoding on the audio signal, and process the audio signal into a signal that can be output from the speaker 180.

[0165] Figure 8 This is a flowchart illustrating a control method for a display device according to an embodiment of the present disclosure.

[0166] In operation S810, the display device 100 can output gate signals through multiple gate lines.

[0167] Specifically, in the first mode, in order to process image data at a first driving frequency, the display device 100 can sequentially output gate signals to multiple gate lines at one time through one gate line, and in the second mode, in order to process image data at a second driving frequency, the display device 100 can sequentially output gate signals to multiple gate lines at at least two gate lines at one time.

[0168] Here, in the second mode, the individual gate signals output to multiple gate lines at a time via at least two gate lines can have different output timings.

[0169] Then, in operation S820, the display device 100 can apply data voltage to multiple pixels connected to multiple switching elements to which gate signals are output via multiple data lines.

[0170] Specifically, when operating in the first mode, the display device 100 can apply data voltage to multiple pixels based on timing by sequentially outputting gate signals to multiple switching elements one gate line at a time.

[0171] Then, when operating in the second mode, the display device 100 can apply data voltages to multiple pixels based on different output timings that sequentially output individual gate signals to multiple switching elements through at least two gate lines at a time.

[0172] At the same time, the mode of the display device 100 can be determined not only based on the user command received through the input unit, but also based on the type of image data, the fps of the image data, or the frame rate of the image data.

[0173] Furthermore, according to an embodiment, the display device 100 can convert the frame rate of image data and process the image data at a high-speed drive frequency.

[0174] Furthermore, the methods described above according to various embodiments of this disclosure can be implemented in the form of software or applications that can be installed on conventional display devices.

[0175] Furthermore, the methods described above according to various embodiments of this disclosure can be implemented simply by software or hardware upgrades of conventional display devices.

[0176] Furthermore, the various embodiments of this disclosure described above can be executed by an embedded server located on the display device or an external server of the display device.

[0177] Additionally, a non-transitory computer-readable medium may be provided that stores a program for sequentially executing a control method for a display device according to the present disclosure.

[0178] Non-transitory computer-readable media refers to media that store data semi-permanently and can be read by a machine, rather than media that temporarily store data (such as registers, caches, and memory). Specifically, the various applications or programs mentioned above can be stored on non-transitory computer-readable media such as CDs, DVDs, hard drives, Blu-ray discs, USB drives, memory cards, ROMs, etc.

[0179] Furthermore, although this disclosure has been shown and described with reference to preferred embodiments, it is not limited to the specific embodiments described above, and it will be apparent to those skilled in the art that various modifications can be made without departing from the spirit of this disclosure as claimed in the appended claims. Moreover, such modifications are intended not to be construed as independent of the technical ideas or prospects of this disclosure.

Claims

1. A display device, comprising: Panel driving unit; The display panel includes multiple pixels connected to multiple gate lines and multiple data lines via multiple switching elements, wherein the multiple gate lines include a first gate line, a second gate line, and a third gate line; as well as The processor is configured to: control the panel driving unit to output gate signals through the plurality of gate lines, and control the panel driving unit to apply data voltages to the plurality of pixels connected to the plurality of switching elements to which the gate signals are output through the plurality of data lines. The processor is configured as follows: In the first mode, the panel driving unit is controlled to sequentially output gate signals to the plurality of gate lines one gate line at a time, thereby processing image data at a first driving frequency. In the second mode, the panel driving unit is controlled to output gate signals to the plurality of gate lines at least twice at a time, thereby processing image data at a second driving frequency higher than the first driving frequency. In the second mode, Each gate signal is output to the plurality of gate lines at a time via at least two gate lines, and the output timings of each gate signal are different from the others. The method of outputting a gate signal to the plurality of gate lines at a time through at least two gate lines includes: At a first timing point, a first gate signal is output to a plurality of switching elements connected to the first gate line via the first gate line. At the second timing point, a second gate signal is output to a plurality of switching elements connected to the second gate line via the second gate line, and At the third timing point, a third gate signal is output to a plurality of switching elements connected to the third gate line via the third gate line. In this configuration, a plurality of pixels connected to the second gate line are charged with a third value, which is based on and differs from both the first and second values. Conversely, a plurality of pixels connected to the first gate line are charged with the first value, and a plurality of pixels connected to the third gate line are charged with the second value. The processor is further configured to: Based on the image data received from the external source, the Automatic Content Recognition (ACR) function is executed to determine the type of the image data. Based on the determination that the image data is of a first type, the system operates in the first mode and processes the image data at the first driving frequency. The first type of image data includes broadcast image data. Based on the determination that the image data is of the second type, the image data is operated in the second mode and processed at the second driving frequency. The second type of image data includes game image data or sports image data.

2. The display device according to claim 1, in, The processor is configured to: When operating in the first mode, the panel driving unit is controlled to apply data voltages to the plurality of pixels based on the output timing of gate signals that are sequentially output to the plurality of switching elements one gate line at a time. When operating in the second mode, the panel driving unit is controlled to apply data voltages to the plurality of pixels based on different output timings of the respective gate signals that are output to the plurality of switching elements at least once via at least two gate lines.

3. The display device according to claim 1, wherein, The processor is configured to: When operating in the first mode, the panel driving unit is controlled to output a first gate signal to a plurality of switching elements connected to the first gate line through the first gate line at a first timing, so that a first data voltage is charged into a plurality of pixels connected to the first gate line. And the panel driving unit is controlled to output a second gate signal to a plurality of switching elements connected to the second gate line through the second gate line at a second timing, so that a second data voltage is charged into a plurality of pixels connected to the second gate line.

4. The display device according to claim 1, wherein, The processor is configured to: When operating in the second mode, the panel driving unit is controlled to output a first gate signal to a plurality of switching elements connected to the first gate line through the first gate line at a first timing, so that a first data voltage is charged into a plurality of pixels connected to the first gate line. And the panel driving unit is controlled to output a second gate signal to a plurality of switching elements connected to the second gate line through the second gate line at a second timing, so that the first data voltage and the second data voltage are charged into a plurality of pixels connected to the second gate line.

5. The display device according to claim 4, in, The plurality of pixels connected to the second gate line are charged by the first data voltage during a first time period and by the second data voltage during a second time period based on the second timing.

6. The display device according to claim 4, wherein, The processor is configured to: The panel driving unit is controlled to output a third gate signal to a plurality of switching elements connected to the third gate line at a third timing point, so that the second data voltage is charged into a plurality of pixels connected to the third gate line.

7. The display device according to claim 6, in, The third value is between the first value and the second value, wherein a plurality of pixels connected to the first gate line are charged with the first data voltage at the first value, and a plurality of pixels connected to the third gate line are charged with the second data voltage at the second value.

8. The display device according to claim 1, in, The processor is configured to: Based on the image data received from the outside, determine the number of frames per second (fps) of the image data, and The image data is processed in the first mode and at the first driving frequency, with the first fps value being the first fps value, and the image data is processed in the second mode and at the second driving frequency, with the second fps value being the second fps value.

9. The display device according to claim 1, in, The processor is configured to: Based on first image data with a first fps value received from the outside, the image data is converted into second image data with a second fps value, and the second image data is processed at the second driving frequency.

10. A control method for a display device, the control method comprising: Gate signals are output through multiple gate lines, including a first gate line, a second gate line, and a third gate line; as well as Data voltages are applied to multiple pixels connected to multiple switching elements to which the gate signal is output via multiple data lines. The output of the gate signal includes: In the first mode, image data is processed at a first driving frequency by sequentially outputting gate signals one gate line at a time to the plurality of gate lines; and In the second mode, gate signals are output to the plurality of gate lines at least twice at a time, thereby processing image data at a second driving frequency higher than the first driving frequency. In the second mode, Each gate signal is output to the plurality of gate lines at a time via at least two gate lines, and the output timings of each gate signal are different from the others. The method of outputting a gate signal to the plurality of gate lines at a time through at least two gate lines includes: At a first timing point, a first gate signal is output to a plurality of switching elements connected to the first gate line via the first gate line. At the second timing point, a second gate signal is output to a plurality of switching elements connected to the second gate line via the second gate line, and At the third timing point, a third gate signal is output to a plurality of switching elements connected to the third gate line via the third gate line. In this configuration, a plurality of pixels connected to the second gate line are charged with a third value, which is based on and differs from both the first and second values. Conversely, a plurality of pixels connected to the first gate line are charged with the first value, and a plurality of pixels connected to the third gate line are charged with the second value. The control method further includes: Based on the image data received from the external source, the Automatic Content Recognition (ACR) function is executed to determine the type of the image data. Based on the determination that the image data is of a first type, the system operates in the first mode and processes the image data at the first driving frequency. The first type of image data includes broadcast image data. Based on the determination that the image data is of the second type, the image data is operated in the second mode and processed at the second driving frequency. The second type of image data includes game image data or sports image data.

11. The control method for a display device according to claim 10, in, Applying the data voltage includes: When operating in the first mode, a data voltage is applied to the plurality of pixels based on the output timing of the gate signals sequentially output to the plurality of switching elements one gate line at a time; and When operating in the second mode, a data voltage is applied to the plurality of pixels based on different output timings of the respective gate signals that are output to the plurality of switching elements at least once via at least two gate lines.

12. The control method for a display device according to claim 10, in, Outputting the gate signal includes: When operating in the first mode, at a first timing point, a first gate signal is output to a plurality of switching elements connected to the first gate line through the first gate line, so that a first data voltage is charged into a plurality of pixels connected to the first gate line. At a second timing point, a second gate signal is output to a plurality of switching elements connected to the second gate line through the second gate line, so that a second data voltage is charged into a plurality of pixels connected to the second gate line.

13. The control method for a display device according to claim 10, in, Outputting the gate signal includes: When operating in the second mode, at a first timing point, a first gate signal is output to a plurality of switching elements connected to the first gate line through the first gate line, so that a first data voltage is charged into a plurality of pixels connected to the first gate line. At a second timing point, a second gate signal is output to a plurality of switching elements connected to the second gate line through the second gate line, so that the first data voltage and the second data voltage are charged into a plurality of pixels connected to the second gate line.

14. The control method for a display device according to claim 13, in, The plurality of pixels connected to the second gate line are charged by the first data voltage during a first time period and by the second data voltage during a second time period based on the second timing.

Images