Imaging method and imaging device with unit cell selection verification

Abstract

Techniques for facilitating unit cell selection verification systems and methods are provided. In one example, a method includes detecting electromagnetic radiation by each detector of a focal plane array (FPA). Each detector is selectively coupled to a readout circuit of the FPA via a selection circuit of the FPA. The method further includes: applying a predetermined signal pattern to a portion of the selection circuit during a frame period, wherein the portion is associated with a subset of the detectors of the FPA, and performing a readout of the FPA to obtain a corresponding output signal associated with each corresponding detector of the FPA. The method also includes determining whether the portion of the selection circuit is operating correctly based on at least the output signal associated with the detector of the subset from the readout. Related systems and apparatus are also provided.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 018,446, filed on April 30, 2020, and entitled “UNIT CELL SELECTION VERIFICATION SYSTEMS AND METHODS,” the entire contents of which are hereby incorporated by reference.

[0003] This application is related to U.S. Provisional Patent Application No. 63 / 031,383, filed on May 28, 2020, and entitled “READOUT ADDRESSING VERIFICATION SYSTEMS AND METHODS,” the entire contents of which are hereby incorporated by reference. Technical Field

[0004] One or more embodiments relate generally to imaging, and more particularly, to, for example, unit cell selection verification systems and methods. Background Art

[0005] An imaging system may include an array of detectors, each detector being used as a portion of a pixel to produce a two-dimensional image. There are a variety of image detectors, such as visible light image detectors, infrared image detectors, or other types of image detectors that may be disposed in an image detector array for capturing an image. As an example, a plurality of sensors may be disposed in an image detector array to detect electromagnetic (EM) radiation of a desired wavelength. In some cases, such as for infrared imaging, the readout of image data captured by the detector may be performed in a time-division multiplexed manner by a readout integrated circuit (ROIC). The readout image data may be transmitted to other circuits, such as for processing, storage, and / or display. In some cases, the combination of a detector array and a ROIC may be referred to as a focal plane array (FPA). Advances in processing technology for FPAs and image processing have led to increased capabilities and complexity of the resulting imaging systems. Summary of the invention

[0006] In one or more embodiments, a method includes detecting electromagnetic radiation by each detector of a focal plane array. Each detector is selectively coupled to a readout circuit of the focal plane array via a selection circuit of the focal plane array. The method further includes: applying a predetermined signal pattern to a portion of the selection circuit during a frame period, wherein the portion of the selection circuit is associated with a subset of the detectors of the focal plane array, and performing a readout of the focal plane array to obtain a respective output signal associated with each respective detector of the focal plane array. The method further includes determining whether the portion of the selection circuit is operating properly based at least on the output signal associated with the detectors of the subset from the readout.

[0007] In one or more embodiments, an imaging device includes a focal plane array. The focal plane array includes a detector array, a readout circuit, and a selection circuit. The detector array includes a plurality of detectors, each of which is configured to detect electromagnetic radiation. The readout circuit is configured to perform a readout during a frame period to obtain a corresponding output signal associated with each corresponding detector of the detector array. The selection circuit is configured to selectively couple the detector array to the readout circuit. The imaging device also includes a control signal generator configured to apply a predetermined signal pattern to a portion of the selection circuit during the frame period, wherein the portion of the selection circuit is associated with a subset of the detectors of the detector array. The imaging device also includes a verification device configured to determine whether the portion of the selection circuit is operating correctly based at least on an output signal associated with the detectors of the subset from the readout.

[0008] The scope of the present disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of the embodiments of the present disclosure, as well as the realization of additional advantages thereof, will be provided to those skilled in the art by considering the following detailed description of one or more embodiments. Reference will be made to the accompanying drawings, which will first be briefly described. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A block diagram of an exemplary imaging system is shown in accordance with one or more embodiments of the present disclosure.

[0010] Figure 2 A block diagram of an exemplary image sensor assembly is shown in accordance with one or more embodiments of the present disclosure.

[0011] Figure 3 An exemplary image sensor assembly is shown in accordance with one or more embodiments of the present disclosure.

[0012] Figure 4A circuit including a detector string and associated selection circuitry is shown in accordance with one or more embodiments of the present disclosure.

[0013] Figure 5 The present invention shows one or more embodiments of the present invention. Figure 4 An exemplary timing diagram of a selection circuit.

[0014] Figure 6 Circuitry associated with a readout circuit is shown in accordance with one or more embodiments of the present disclosure.

[0015] Figure 7 An exemplary system for facilitating functional verification of unit cell selection in accordance with one or more embodiments of the present disclosure is shown.

[0016] Figure 8 A flow chart is shown of an exemplary process for facilitating functional verification of unit cell selection in accordance with one or more embodiments of the present disclosure.

[0017] Embodiments of the present disclosure and their advantages may be best understood by reference to the following detailed description. It should be noted that the sizes of the various components and the distances between these components are not drawn to scale in the accompanying drawings. It should be appreciated that the same reference numerals are used to identify the same elements shown in one or more of the accompanying drawings. DETAILED DESCRIPTION

[0018] The detailed description set forth below is intended to be a description of various configurations of the subject technology, and is not intended to represent the only configuration in which the subject technology can be practiced. The accompanying drawings are incorporated herein and constitute a part of the detailed description. For the purpose of providing a thorough understanding of the subject technology, the detailed description includes specific details. However, it will be clear and obvious to those skilled in the art that the subject technology is not limited to the specific details set forth herein, and one or more embodiments can be used to practice. In one or more examples, structures and components are shown in block diagram form to avoid blurring the concept of the subject technology. One or more embodiments disclosed in the subject are illustrated by one or more drawings and / or described in conjunction with one or more drawings, and are set forth in the claims.

[0019] Various techniques are provided to facilitate unit cell selection verification systems and methods. In some embodiments, a unit cell of a unit cell array includes a detector and a selection circuit associated with the detector. Thus, the unit cell array includes a detector array formed by detectors (e.g., also referred to as detector pixels, detector elements, or simply pixels) and a portion of a selection circuit. The selection circuit associated with the detector is part of the selection circuit. Each detector pixel detects image data associated with a component of incident EM radiation and generates a detection signal (e.g., an electrical signal) indicative of the detected image data. The signal may include a photocurrent generated by the detector element in response to the incident EM radiation. For purposes of explanation, the selection circuit is considered to be an interface between the detector and the readout circuit because the selection circuit selectively connects the detector to the readout circuit. Thus, the selection circuit may also be referred to as an interface circuit. In other aspects, the selection circuit may be considered to be part of the readout circuit.

[0020] The readout of these detection signals involves selecting / addressing the unit cell (e.g., selection of the detector). For example, the unit cells may be selected row by row to allow the unit cells to be read out row by row. In some embodiments, the selection circuit associated with a given unit cell may include a switch. Each switch of the unit cell may be controlled using a corresponding control signal. The switch may be appropriately turned on (e.g., closed) and off (e.g., opened) to bias the detector, capture data from the associated detector, and provide the data to the readout circuit. In some aspects, the switch may be implemented using transistors. In one example, the unit cell has three transistors, and the state of each transistor (e.g., on or off state) is based on the control signal applied to the transistor. Unit cell selection verification may be performed to verify that the selection circuit of each unit cell (e.g., each switch) is operating correctly.

[0021] Various embodiments of the methods and systems disclosed herein may be included in or implemented as various devices and systems, such as visible light imaging systems, infrared imaging systems, imaging systems with visible light and infrared imaging capabilities, mobile digital cameras, video surveillance systems, video processing systems, or other systems or devices that may need to obtain image data in one or more portions of the EM spectrum.

[0022] Now referring to the accompanying drawings, Figure 1 A block diagram of an exemplary imaging system 100 (e.g., an infrared camera) according to one or more embodiments of the present disclosure is shown. However, all of the depicted components may not be required, and one or more embodiments may include additional components not shown in the figure. The arrangement and type of components may be changed without departing from the spirit or scope of the claims as set forth herein. Additional components, different components, and / or fewer components may be provided.

[0023] According to embodiments of the present disclosure, imaging system 100 may be used to capture and process images. Imaging system 100 may represent any type of imaging system that detects one or more ranges (e.g., bands) of EM radiation and provides representative data (e.g., one or more still image frames or video image frames). Imaging system 100 may include a housing that at least partially surrounds components of imaging system 100, thereby facilitating compactness and protection of imaging system 100. For example, Figure 1 The solid box marked as 100 in FIG. 1 may represent the housing of the imaging system 100. Figure 1 The housing may contain more, fewer, and / or different components of the imaging system 100 than the components depicted within the solid box in . In embodiments, the imaging system 100 may include a portable device and may be incorporated into, for example, a vehicle or non-mobile device in which images need to be stored and / or displayed. The vehicle may be a land-based vehicle (e.g., a car, a truck), a sea-based vehicle, an aircraft (e.g., an unmanned aerial vehicle (UAV)), a spacecraft, or generally any type of vehicle that may contain the imaging system 100 (e.g., mounted therein, mounted thereon, etc.). In another example, the imaging system 100 may be coupled to various types of fixed locations (e.g., a home security mount, a campsite or outdoor mount, or other locations) via one or more types of mounts.

[0024] According to one embodiment, the imaging system 100 includes a processing component 105, a memory component 110, an image capture component 115, an image interface 120, a control component 125, a display component 130, a sensing component 135, and / or a network interface 140. According to various embodiments, the processing component 105 includes a processor, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a single-core processor, a multi-core processor, a microcontroller, a programmable logic device (PLD) (e.g., a field programmable gate array (FPGA)), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) device, or one or more of other logic devices that can be configured by hardwiring, executing software instructions, or a combination of both to perform various operations discussed herein for embodiments of the present disclosure. The processing component 105 can be configured to interface and communicate with various other components of the imaging system 100 (e.g., 110, 115, 120, 125, 130, 135, etc.) to perform such operations. For example, processing component 105 can be configured to process captured image data received from imaging capture component 115, store the image data in memory component 110, and / or retrieve stored image data from memory component 110. In one aspect, processing component 105 can be configured to perform various system control operations (e.g., control the communications and operations of various components of imaging system 100) and other image processing operations (e.g., data conversion, video analysis, etc.).

[0025] In one embodiment, the memory component 110 includes one or more memory devices configured to store data and information, including infrared image data and information. The memory component 110 may include one or more memory devices of various types, including volatile and non-volatile memory devices, such as random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), non-volatile random access memory (NVRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, hard disk drive and / or other types of memory. As described above, the processing component 105 can be configured to execute software instructions stored in the memory component 110 to perform method and process steps and / or operations. The processing component 105 and / or the image interface 120 can be configured to store images or digital image data captured by the image capture component 115 in the memory component 110. The processing component 105 can be configured to store processed still images and / or video images in the memory component 110.

[0026] In some embodiments, a separate machine-readable medium 145 (e.g., a memory such as a hard drive, an optical disk, a digital video disk, or a flash memory) can store software instructions and / or configuration data that can be executed or accessed by a computer (e.g., a logic device or a processor-based system) to perform various methods and operations, such as those associated with processing image data. In one aspect, the machine-readable medium 145 can be portable and / or located separately from the imaging system 100, wherein the stored software instructions and / or data are provided to the imaging system 100 by coupling the machine-readable medium 145 to the imaging system 100 and / or by the imaging system 100 downloading from the machine-readable medium 145 (e.g., via a wired link and / or a wireless link). It should be appreciated that the various modules can be integrated in software and / or hardware as part of the processing component 105, wherein the code (e.g., software or configuration data) for the modules is stored in, for example, the memory component 110.

[0027] The imaging system 100 may represent an imaging device, such as a video and / or still camera, to capture and process images and / or video of a scene 160. In this regard, the image capture component 115 of the imaging system 100 may be configured to capture images (e.g., still and / or video images) of the scene 160 in a particular spectrum or modality. The image capture component 115 includes an image detector circuit 165 (e.g., a thermal infrared detector circuit) and a readout circuit 170 (e.g., an ROIC). In some cases, the image capture component 115 does not have a shutter, so that the image detector circuit 165 is exposed to the scene surrounded by the field of view of the image capture component 115. For example, the image capture component 115 may include an IR imaging sensor (e.g., an IR imaging sensor array) configured to detect IR radiation in the near, mid, and / or far IR spectrum and provide an IR image (e.g., IR image data or signal) representing IR radiation from the scene 160. For example, the image detector circuit 165 may capture (e.g., detect, sense) IR radiation having a wavelength in the range of about 700 nm to about 2 mm or a portion thereof. For example, in some aspects, image detector circuit 165 can be sensitive to (e.g., better detect) short wave IR (SWIR) radiation, mid wave IR (MWIR) radiation (e.g., EM radiation with wavelengths of 2 μm to 5 μm), and / or long wave IR (LWIR) radiation (e.g., EM radiation with wavelengths of 7 μm to 14 μm), or any desired IR wavelength (e.g., typically in the range of 0.7 μm to 14 μm). In other aspects, image detector circuit 165 can capture radiation from one or more other bands of the EM spectrum, such as visible light, ultraviolet light, etc.

[0028] Image detector circuit 165 may capture image data associated with scene 160. To capture an image, image detector circuit 165 may detect image data of scene 160 (e.g., in the form of EM radiation) and generate pixel values ​​of the image based on scene 160. An image may be referred to as a frame or image frame. In some cases, image detector circuit 165 may include a detector array (e.g., also referred to as a pixel array) that may detect radiation of a certain wavelength band, convert the detected radiation into an electrical signal (e.g., voltage, current, etc.), and generate pixel values ​​based on the electrical signal. Each detector in the array may capture a corresponding portion of the image data and generate a pixel value based on the corresponding portion captured by the detector. The pixel value generated by the detector may be referred to as an output of the detector. As a non-limiting example, each detector may be a photodetector such as an avalanche photodiode, an infrared photodetector, a quantum well infrared photodetector, a microbolometer, or other detector capable of converting EM radiation (e.g., EM radiation of a certain wavelength) into pixel values. The array of detectors may be arranged in rows and columns.

[0029] An image may be or may be considered to be a data structure that includes pixels and is a representation of image data associated with scene 160, each pixel having a pixel value representing EM radiation emitted or reflected from a portion of the scene and received by a detector that generates the pixel value. Depending on the context, a pixel may refer to a detector of image detector circuitry 165 that generates an associated pixel value or a pixel (e.g., pixel position, pixel coordinates) of an image formed by the generated pixel values.

[0030] In one aspect, the pixel value generated by the image detector circuit 165 can be represented according to a digital count value, which is generated based on an electrical signal obtained from converting the detected radiation. For example, where the image detector circuit 165 includes or is otherwise connected to an analog / digital converter (ADC) circuit, the ADC circuit can generate a digital count value based on the electrical signal. For an ADC circuit that can use 14 bits to represent the electrical signal, the digital count value can be in the range of 0 to 16,383. In such a case, the pixel value of the detector can be a digital count value output from the ADC circuit. In other cases (e.g., in the absence of an ADC circuit), the pixel value can be analog in nature, having a value that is or indicates the value of the electrical signal. As an example, for infrared imaging, a greater amount of IR radiation incident on and detected by the image detector circuit 165 (e.g., an IR image detector circuit) is associated with a higher digital count value and a higher temperature.

[0031] The readout circuit 170 may serve as an interface between the image detector circuit 165 that detects image data and the processing component 105 that processes the detected image data read out by the readout circuit 170, with data communication from the readout circuit 170 to the processing component 105 being facilitated by the image interface 120. The image capture frame rate may refer to the rate (e.g., the number of images per second) at which images are sequentially detected by the image detector circuit 165 and provided to the processing component 105 by the readout circuit 170. The readout circuit 170 may read out pixel values ​​generated by the image detector circuit 165 according to an integration time (e.g., also referred to as an integration period).

[0032] In various embodiments, the combination of image detector circuit 165 and readout circuit 170 may be, may include, or may provide together an FPA. In some aspects, image detector circuit 165 may be a thermal image detector circuit including an array of microbolometers, and the combination of image detector circuit 165 and readout circuit 170 may be referred to as a microbolometer FPA. In some cases, the array of microbolometers may be arranged in rows and columns. The microbolometer may detect IR radiation and generate pixel values ​​based on the detected IR radiation. For example, in some cases, the microbolometer may be a thermal IR detector that detects IR radiation in the form of thermal energy and generates pixel values ​​based on the amount of thermal energy detected. The microbolometer may absorb incident IR radiation and produce a corresponding temperature change in the microbolometer. The change in temperature is associated with a corresponding change in the resistance of the microbolometer. In the case where each microbolometer is used as a pixel, a two-dimensional image or picture representation of the incident IR radiation may be generated by converting the resistance change of each microbolometer into a time-multiplexed electrical signal. The translation may be performed by the ROIC. Microbolometer FPAs can include IR sensing materials such as amorphous silicon (a-Si), vanadium oxide (VO x ), combinations thereof, and / or other detection material(s). In one aspect, for a microbolometer FPA, the integration time may be or may indicate a period of time over which the microbolometer is biased. In this case, a longer integration time may be associated with a higher gain in the IR signal, but not with more IR radiation being collected. The IR radiation may be collected by the microbolometer in the form of heat energy.

[0033] In some cases, the imaging capture component 115 may include one or more filters that are suitable for passing radiation of some wavelengths but substantially blocking radiation of other wavelengths. For example, the imaging capture component 115 may be an IR imaging device that includes one or more filters (e.g., MWIR filters, thermal IR filters, and narrowband filters) that are suitable for passing IR radiation of some wavelengths while substantially blocking IR radiation of other wavelengths. In this example, the imaging capture component 115 may be customized with such filters to increase sensitivity to the desired IR wavelength band. On the one hand, when the IR imaging device is customized for capturing thermal IR images, the IR imaging device may be referred to as a thermal imaging device. Other imaging devices including IR imaging devices that are customized for capturing infrared IR images outside the thermal range may be referred to as non-thermal imaging devices.

[0034] In one specific non-limiting example, the image capture component 115 may include an IR imaging sensor having an FPA with a detector responsive to IR radiation, including near infrared (NIR), short wave IR (SWIR), MWIR, long wave IR (LWIR), and / or very long wave IR (VLWIR) radiation. In some other embodiments, alternatively or additionally, the image capture component 115 may include a complementary metal oxide semiconductor (CMOS) sensor or a charge coupled device (CCD) sensor that may be found in any consumer camera (e.g., a visible light camera).

[0035] Other imaging sensors that may be implemented in the image capture component 115 include photonic hybrid device (PMD) imaging sensors or other time-of-flight (ToF) imaging sensors, light detection and ranging (LIDAR) imaging devices, millimeter imaging devices, positron emission tomography (PET) scanners, single photon emission computed tomography (SPECT) scanners, ultrasound imaging devices, or other imaging devices operating in a specific modality and / or spectrum. It should be noted that for some of these imaging sensors that are configured to capture images in a specific modality and / or spectrum (e.g., infrared spectrum, etc.), for example, when compared to typical CMOS-based or CCD-based imaging sensors or other imaging sensors, imaging scanners, or imaging devices of different modalities, they are more likely to produce images with low-frequency shadows.

[0036] The image provided by the image capture component 115 or the digital image data corresponding to the image can be associated with a corresponding image size (also referred to as pixel size). Image size or pixel size generally refers to the number of pixels in the image, which can be expressed, for example, as the width multiplied by the height of a two-dimensional image, or otherwise suitable for the relevant size or shape of the image. Therefore, an image with an original resolution can be resized to a smaller size (e.g., with a smaller pixel size) in order to, for example, reduce the cost of processing and analyzing the image. A filter (e.g., non-uniformity estimation) can be generated based on the analysis of the resized image. Then, before being applied to the image, the filter can be resized to the original resolution and size of the image.

[0037] In some embodiments, the image interface 120 may include appropriate input ports, connectors, switches, and / or circuits configured to interface with an external device (e.g., remote device 150 and / or other device) to receive an image (e.g., digital image data) generated by or otherwise stored at the external device. The received image or image data may be provided to the processing component 105. In this regard, the received image or image data may be converted into a signal or data suitable for processing by the processing component 105. For example, in one embodiment, the image interface 120 may be configured to receive analog video data and convert it into suitable digital data to provide to the processing component 105.

[0038] In some embodiments, the image interface 120 may include various standard video ports that may be connected to a video player, a camera, or other device capable of generating a standard video signal, and may convert the received video signal into digital video / image data suitable for processing by the processing component 105. In some embodiments, the image interface 120 may also be configured to interface with and receive images (e.g., image data) from the image capture component 115. In other embodiments, the image capture component 115 may interface directly with the processing component 105.

[0039] In one embodiment, the control component 125 includes a user input and / or interface device suitable for generating a user input control signal, such as a rotatable knob (e.g., a potentiometer), a button, a slide bar, a keyboard, and / or other device. The processing component 105 can be configured to sense a control input signal from a user via the control component 125, and respond to any sensed control input signal received therefrom. As generally understood by those skilled in the art, the processing component 105 can be configured to interpret such a control input signal as a value. In one embodiment, the control component 125 can include a control unit (e.g., a wired or wireless handheld control unit) having a button suitable for connecting to a user interface and receiving a user input control value. In one embodiment, the buttons of the control unit can be used to control various functions of the imaging system 100, such as autofocus, menu activation and selection, field of view, brightness, contrast, noise filtering, image enhancement, and / or various other features of the imaging system or camera.

[0040] In one embodiment, display component 130 includes an image display device (e.g., a liquid crystal display (LCD)) or various other types of commonly known video displays or monitors. Processing component 105 can be configured to display image data and information on display component 130. Processing component 105 can be configured to retrieve image data and information from memory component 110 and display any retrieved image data and information on display component 130. Display component 130 can include display circuitry that can be used by processing component 105 to display image data and information. Display component 130 can be adapted to receive image data and information directly from image capture component 115, processing component 105, and / or image interface 120, or the image data and information can be transmitted from memory component 110 via processing component 105.

[0041] In one embodiment, the sensing component 135 includes one or more sensors of various types, depending on the application or implementation requirements, as will be understood by those skilled in the art. The sensors of the sensing component 135 provide data and / or information to at least the processing component 105. In one aspect, the processing component 105 can be configured to communicate with the sensing component 135. In various implementations, the sensing component 135 can provide information about environmental conditions, such as external temperature, lighting conditions (e.g., day, night, dusk and / or dawn), humidity levels, specific weather conditions (e.g., sunny, rainy and / or snowy), distances (e.g., laser rangefinders or time-of-flight cameras), and / or whether a tunnel or other type of enclosure has been entered or left. The sensing component 135 can represent conventional sensors for monitoring various conditions (e.g., environmental conditions) that may have an impact (e.g., on the appearance of the image) on the image data provided by the image capture component 115, as generally known to those skilled in the art.

[0042] In some implementations, sensing component 135 (e.g., one or more sensors) may include means for relaying information to processing component 105 via wired and / or wireless communications. For example, sensing component 135 may be adapted to receive information from satellites via local broadcast (e.g., radio frequency (RF)) transmissions, via mobile or cellular networks, and / or via information beacons in infrastructure (e.g., transportation or highway information beacon infrastructure), or various other wired and / or wireless technologies. In some embodiments, processing component 105 may use information retrieved from sensing component 135 (e.g., sensory data) to modify the configuration of image capture component 115 (e.g., adjust light sensitivity levels, adjust the orientation or angle of image capture component 115, adjust aperture, etc.).

[0043] In some embodiments, the various components of the imaging system 100 may be distributed over the network 155 and communicate with each other. In this regard, the imaging system 100 may include a network interface 140 configured to facilitate wired and / or wireless communications between the various components of the imaging system 100 via the network 155. In such embodiments, components may also be replicated if required for a particular application of the imaging system 100. That is, components configured for the same or similar operations may be distributed over the network. In addition, if desired, all or part of any of the various components may be implemented using appropriate components of a remote device 150 (e.g., a conventional digital video recorder (DVR), a computer configured for image processing, and / or other device) that communicates with the various components of the imaging system 100 via the network interface 140 over the network 155. Thus, for example, all or part of the processing component 105, all or part of the memory component 110, and / or all or part of the display component 130 may be implemented or replicated at the remote device 150. In some embodiments, the imaging system 100 may not include an imaging sensor (e.g., image capture component 115), but rather receive images or image data from an imaging sensor that is located separately and remotely from the processing component 105 and / or other components of the imaging system 100. It should be appreciated that many other combinations of distributed implementations of the imaging system 100 are possible without departing from the scope and spirit of the present disclosure.

[0044] Furthermore, in various embodiments, the various components of the imaging system 100 may or may not be combined and / or implemented as desired or depending on the application or requirements. In one example, the processing component 105 may be combined with the memory component 110, the image capture component 115, the image interface 120, the display component 130, the sensing component 135, and / or the network interface 140. In another example, the processing component 105 may be combined with the image capture component 115 such that certain functions of the processing component 105 are performed by circuitry (e.g., a processor, microprocessor, logic device, microcontroller, etc.) within the image capture component 115.

[0045] Figure 2 A block diagram of an exemplary image sensor assembly 200 is shown in accordance with one or more embodiments of the present disclosure. However, not all of the depicted components may be required, and one or more embodiments may include additional components not shown in the figure. Changes in the arrangement and types of components may be made without departing from the spirit or scope of the claims as set forth herein. Additional components, different components, and / or fewer components may be provided. In embodiments, the image sensor assembly 200 may be an FPA, for example, implemented as Figure 1 Imaging capture component 115.

[0046] The image sensor assembly 200 includes a unit cell array 205, column multiplexers 210 and 215, column amplifiers 220 and 225, a row multiplexer 230, a control bias and timing circuit 235, a digital-to-analog converter (DAC) 240, and a data output buffer 245. The unit cell array 205 includes an array of unit cells. In one aspect, each unit cell may include a detector (e.g., a pixel) and an interface circuit. The interface circuit of each unit cell may provide an output signal, such as an output voltage or an output current, in response to a detection signal (e.g., a detection current, a detection voltage) provided by the detector of the unit cell. The output signal may indicate a magnitude of EM radiation received by the detector. The column multiplexer 215, the column amplifier 220, the row multiplexer 230, and the data output buffer 245 may be used to provide an output signal from the unit cell array 205 as a data output signal on a data output line 250. The output signal on the data output line 250 may be provided to components downstream of the image sensor assembly 200, such as a processing circuit (e.g., Figure 1 105), memory (e.g., Figure 1 Memory component 110), a display device (e.g., Figure 1 The display component 130) and / or other components to facilitate processing, storage and / or display of the output signal. The data output signal can be an image formed by the pixel values ​​of the image sensor assembly 200. In this regard, the column multiplexer 215, the column amplifier 220, the row multiplexer 230 and the data output buffer 245 can collectively provide the ROIC (or portion thereof) of the image sensor assembly 200. In one aspect, the interface circuit can be considered to be part of the ROIC, or can be considered to be an interface between the detector and the ROIC. In an embodiment, the components of the image sensor assembly 200 can be implemented so that the unit cell array 205 is mixed (e.g., combined, joined, matched) with the ROIC.

[0047] The column amplifier 225 may generally represent any column processing circuit suitable for a given application (analog and / or digital), and is not limited to amplifier circuits for analog signals. In this regard, the column amplifier 225 may be more generally referred to as a column processor in such an aspect. The signal received by the column amplifier 225 may be processed according to the analog or digital nature of the signal, such as an analog signal on an analog bus and / or a digital signal on a digital bus. As an example, the column amplifier 225 may include a circuit for processing digital signals. As another example, the column amplifier 225 may be a path (e.g., unprocessed) that a digital signal from the unit cell array 205 passes through to reach the column multiplexer 215. As another example, the column amplifier 225 may include an ADC for converting an analog signal into a digital signal (e.g., to obtain a digital count value). These digital signals may be provided to the column multiplexer 215.

[0048] Each unit cell can receive a bias signal (e.g., a bias voltage, a bias current) to bias the detector of the unit cell to compensate for different response characteristics of the unit cell due to, for example, temperature changes, manufacturing variations, and / or other factors. For example, the control bias and timing circuit 235 can generate bias signals and provide them to the unit cells. By providing appropriate bias signals to each unit cell, the unit cell array 205 can be effectively calibrated to provide accurate image data in response to light (e.g., IR light) incident on the detector of the unit cell. In one aspect, the control bias and timing circuit 235 can be, can include, or can be part of a logic circuit.

[0049] In one aspect, the control bias and timing circuit 235 can generate a bias value, a timing control voltage, and a switch control voltage. In some cases, the DAC 240 can convert a bias value received as a data input signal on the data input signal line 255 or as part thereof into a bias signal (e.g., an analog signal on (one or more) analog signal lines 260) that can be provided to a separate unit cell through the operation of the column multiplexer 210, the column amplifier 220, and the row multiplexer 230. For example, the DAC 240 can drive a digital control signal (e.g., provided as a bit) to an appropriate analog signal level for the unit cell. In some technologies, a digital control signal of 0 or 1 can be driven to an appropriate logic low voltage level or an appropriate logic high voltage level, respectively. In another aspect, the control bias and timing circuit 235 can generate a bias signal (e.g., an analog signal) and provide the bias signal to the unit cell without utilizing the DAC 240. In this regard, some embodiments do not include the DAC 240, the data input signal line 255, and / or the (one or more) analog signal line 260. In one embodiment, the control bias and timing circuit 235 may be Figure 1 The processing component 105 and / or the imaging capture component 115 may include Figure 1 The processing component 105 and / or the imaging capture component 115 may be Figure 1 A portion of the processing component 105 and / or the imaging capture component 115, or may be otherwise coupled to Figure 1 processing component 105 and / or imaging capture component 115.

[0050] In some embodiments, the bias value may be or may be derived as a control signal (e.g., to turn on or off a switch of a selection circuit) for addressing the unit cell array 205. In this regard, the bias value may refer to an analog signal at an appropriate logic high level or an appropriate logic low level to turn on or off a switch of a selection circuit, or the bias value may refer to a digital control signal (e.g., a bit) for deriving an appropriate logic high level or an appropriate logic low level.

[0051] In one embodiment, the image sensor assembly 200 can be implemented as part of an imaging system (e.g., 100). In addition to the various components of the image sensor assembly 200, the imaging system can also include one or more processors, memories, logic devices, displays, interfaces, optical devices (e.g., lenses, mirrors, beam splitters), and / or other components that may be appropriate in various embodiments. In one aspect, the data output signal on the data output line 250 can be provided to a processor (not shown) for further processing. For example, the data output signal can be an image formed by pixel values ​​of unit cells from the image sensor assembly 200. The processor can perform operations such as non-uniformity correction (NUC), spatial and / or temporal filtering, and / or other operations. The image (e.g., a processed image) can be stored in a memory (e.g., external or local to the imaging system) and / or displayed on a display device (e.g., external to the imaging system and / or integrated with the imaging system).

[0052] It should be noted that Figure 2 , the unit cell array 205 is depicted as 8×8 (e.g., 8 rows and 8 columns of unit cells). However, the unit cell array 205 may have other array sizes. As non-limiting examples, the unit cell array 205 may include 512×512 (e.g., 512 rows and 512 columns of unit cells), 1024×1024, 2048×2048, 4096×4096, 8192×8192, and / or other array sizes. In some cases, the array size may have a row size (e.g., the number of detectors in a row) that is different from the column size (e.g., the number of detectors in a column). Examples of frame rates may include 30 Hz, 60 Hz, and 120 Hz. In one aspect, each unit cell of the unit cell array 205 may represent a pixel.

[0053] Each row of unit cell array 205 may be addressed using control signal(s) from row multiplexer 230. In some cases, row multiplexer 230 may receive control signal(s) from control bias and timing circuit 235. Figure 2A single line from the row multiplexer 230 to each row of the unit cell array 205 is shown, such as a single control line 265 associated with the row 270 of the unit cell array, but a single line may represent multiple control lines. Each of these lines may be associated with a control signal. In some embodiments, three control signals may be used to control each row.

[0054] In one embodiment, components of image sensor assembly 200 may be implemented such that a detector array is hybrid (e.g., combined) with a readout circuit. Figure 3 An exemplary image sensor assembly 300 is shown in accordance with one or more embodiments of the present disclosure. However, all of the depicted components may not be required, and one or more embodiments may include additional components not shown in the figures. Changes may be made to the arrangement and types of components without departing from the spirit or scope of the claims as set forth herein. Additional components, different components, and / or fewer components may be provided. In embodiments, image sensor assembly 300 may be image sensor assembly 200, may include image sensor assembly 200, or may be a part of image sensor assembly 200.

[0055] Image sensor assembly 300 includes device wafer 305, readout circuit 310, and contacts 315 that bond (e.g., mechanically and electrically bond) device wafer 305 to readout circuit 310. Device wafer 305 may include a detector (e.g., unit cell array 205). Contacts 315 may bond device wafer 305 and the detector of readout circuit 310. Contacts 315 may include conductive contacts of the detector of device wafer 305, conductive contacts of readout circuit 310, and / or metal bonds between conductive contacts of the detector and conductive contacts of readout circuit 310. In one embodiment, device wafer 305 may be bump bonded to readout circuit 310 using bonding bumps (e.g., indium bumps). Bonding bumps may be formed on device wafer 305 and / or readout circuit 310 to allow connection between device wafer 305 and readout circuit 310. In one aspect, hybridizing device wafer 305 to readout circuitry 310 may refer to bonding device wafer 305 (eg, a detector of device wafer 305 ) to readout circuitry 310 to mechanically and electrically bond device wafer 305 and readout circuitry 310 .

[0056] Figure 4 A circuit 400 including a detector string 405 and associated selection circuitry is shown in accordance with one or more embodiments of the present disclosure. Figure 5 Describing the circuit 400, Figure 5 1. A method for facilitating reading out a detector string 405 (eg, a detector array including the detector string 405) according to one or more embodiments of the present disclosure is shown. Figure 45. In one embodiment, a unit cell of the unit cell array 205 includes a detector of the detector string 405 and a portion of a selection circuit (eg, also referred to as an interface circuit) associated with the detector.

[0057] The detector string 405 of circuit 400 includes detectors 405A-D (e.g., infrared sensors). Each of contacts 410A-E is shared by the detectors of the detector string 405. For example, detectors 405A and 405B share contact 410A, and detectors 405B and 405C share contact 410B. By sharing contacts, the number of contacts of the detector is reduced, and the area required for the contacts is therefore reduced. In an embodiment, the detector string 405 can be a row or column in a detector array, or can be a part of a row or column in a detector array. In some cases, contacts 410A-E can be shared between adjacent columns or rows (e.g., also referred to as adjacent columns or rows) of an array. It should be noted that references to columns or rows can include partial columns or partial rows, and column and row terms can be interchangeable, depending on the application. For the purpose of explanation, the detector string 405 is a column (or part thereof) of an array, and each of detectors 405A-D is a part of different rows of an array. In this regard, the detector string 405 has N rows. The ellipse between detectors 405C and 405D indicates that there are one or more additional detectors between detectors 405C and 405D, or that there is no detector between detectors 405C and 405D. The number of columns and rows of the detector array may vary depending on, for example, the desired application, with circuit 400 being replicated to form the desired number of additional columns. Although the detector array is shown as a variable resistor and may be an array of microbolometers, other types of detectors may be utilized.

[0058] The selection circuit of circuit 400 includes switches 415A-D, switches 420A-F, and switches 425A-E. In some embodiments, switches 415A-D, switches 420A-F, and / or switches 425A-F may be implemented using transistors. Switches 415A-D are connected in parallel with detectors 405A-D. Figure 4 , each of switches 415A-D, switches 420A-F, and switches 425A-E is controlled by a control signal depicted adjacent to the associated switch. For example, control signal BS 3 The control signal EN may be asserted to turn on (eg, close) and deasserted to turn off (eg, open) the switch 415C. N-1 can be asserted to turn on and deasserted to turn off switch 420E, control signal SEL 1may be asserted to turn on and deasserted to turn off switch 425A, etc. In one aspect, the control signal (e.g., with appropriate timing) may be provided to the selection circuit by a readout circuit (e.g., readout circuit 170) and / or a processing circuit (e.g., processing component 105). Figure 2 For row 270 of unit cell array 205, row multiplexer 230 may provide a control signal on line(s) 265. For example, if row 270 includes detector 405A, the control signal provided on line(s) 265 may include BS 1 ,EN 1 and SEL 1 For the purpose of explanation, Figure 4 and 5 In the embodiment, each of the switches (e.g., 415A-D, 420A-F, and 425A-E) is turned on in response to a logic high control signal and turned off in response to a logic low signal. However, depending on the type of switching technology utilized, the switches may be turned off in response to a logic high control signal and turned on in response to a logic low control signal.

[0059] Control signal BS 1 To BS N 405A-D. Thus, switches 415A-D may be referred to as bolometer shorting (BS) switches. In some cases, switches 415A-D are used to isolate their respective detectors 405A-D. Such isolation may reduce parasitic capacitance and / or address performance issues. In some cases, by controlling the on / off state of switches 415A-D and applying appropriate timing (e.g., as described in reference to FIG. 4 ), the detectors 405A-D may be selectively shorted. Figure 5 As discussed above), reduced sensitivity to defects (eg, column-to-column short defects) may be provided, which may result in less noise, crosstalk, and / or reduced parasitic capacitance within the FPA.

[0060] Control signal EN 0 to EN N The switches 420A-F selectively connect the detectors 405A-D to the bias signals V DETCOM (For example, also referred to as a reference voltage). The control signal SEL 1 To SEL N can be used to control the corresponding switches 425A-D. The switches 425A-D selectively connect the detectors 405A-D to the node 435. The node 435 can be connected to the ROIC so that the switches 425A-D selectively connect the detectors 405A-D to the ROIC. For example, if the control signal SEL 1is asserted, switch 425A is closed (e.g., turned on), and detector 405A provides a signal to the ROIC (e.g., indicating radiation received by detector 405A). In a similar manner, detectors 405A-D may be selected row by row in a sequential manner using their corresponding set of control signals. Control signal EN 0 to EN N and SEL 1 To SEL N can be commonly set to control the corresponding switches 420A-F and 425A-E for selecting / addressing a row, while the control signal BS 1 To BS N Used to control the corresponding switches 415A-D (eg, for isolation purposes). Thus, the control signals may be referred to as column / row select signals, column / row address signals, or address signals.

[0061] Additional references Figure 5 describes the operating sequence of the circuit 400, Figure 5 4. A method for facilitating readout of a detector string 405 (eg, readout of a detector array including the detector string 405) according to one or more embodiments of the present disclosure is shown. Figure 4 The timing diagram 500 provides a normal signal pattern sequence of the selection circuit associated with each of the detectors in the detector string 405. In one aspect, the normal signal pattern sequence refers to the control signal BS as a function of time during normal operation. x ,EN x and SEL x state (e.g., logic high, logic low), where each row of detectors is read out in a sequential manner.

[0062] refer to Figure 4 and 5 , in order to initialize the detector array and the associated selection circuits for one frame period, the control signal EN 0 to EN N may be asserted (eg, at a logic high) to close the associated switches 420A to 420F and apply the reference voltage V to the detectors 405A to 405D. DETCOM , control signal BS 1 To BS N is asserted to close the associated switches 415A to 415D, and the control signal SEL 1 To SEL N is deasserted (eg, at logic low) to open the associated switches 425A to 425E. Figure 5 As shown in FIG. , time t=0 is set as the time when this initialization occurs. From about time t=t 0 Until about time t = t1 >t 0 , execute the global EN signal disconnect to turn the control signal EN 0 to EN N Transitions to the deasserted state. Control signal EN 0 to EN N is deasserted to open the associated switches 420A to 420F.

[0063] The operational sequence of circuit 400 then proceeds to facilitate readout of detector 405A (e.g., facilitate readout of the row of detectors that includes detector 405A). 2 >t 1 , control signal EN 1 is asserted to close switch 420B, and the control signal BS 1 is deasserted to open switch 415A. With switch 420B closed, detector 405A is coupled to reference voltage V DETCOM At approximately time t = t 3 >t 2 , control signal SEL 1 is asserted to close switch 425A. After switches 420B and 425A are closed and switch 415A is open (and the remaining switches are controlled using their corresponding control signals, such as Figure 5 In some cases, the output signal may be a current flowing through switch 420B, detector 405A, and switch 425A.

[0064] The operational sequence of circuit 400 then proceeds to facilitate readout of detector 405B (e.g., facilitate readout of the row of detectors that includes detector 405B). 4 >t 3 , control signal EN 1 and BS 2 is deasserted to open switches 420B and 415B, respectively, to remove (eg, disconnect, decouple) reference voltage V from detector 405A. DETCOM and remove the short circuit on detector 405B. Then the control signal EN 2 is asserted to close switch 420C. At approximately time t=t 5 >t 4 , control signal SEL 1 is deasserted to open switch 425A, and the control signal SEL 2420C. Detector 405B is asserted to close switch 425B. With switch 425A open and switch 425B closed, detector 405B can be read. In this regard, detector 405B provides a signal (e.g., current flowing through switch 425B, detector 405B, and switch 420C) to the circuitry of the ROIC. With switch 415A open, detector 405A is used to isolate detector 405B from a potential short circuit (e.g., a column-to-column defect) at node 430.

[0065] The operational sequence of circuit 400 then continues to facilitate readout of detector 405C (e.g., facilitate readout of the row of detectors that includes detector 405C). 6 >t 5 , control signal EN 2 and BS 3 is deasserted to open switches 420C and 415C, respectively, and control signal EN 3 and BS 1 is asserted to close switches 420D and 415A, respectively. At approximately time t=t 7 >t 6 , control signal SEL 2 is deasserted to open switch 425B, and the control signal SEL 3 420D. Detector 405C may be read out when switch 425B is open and switch 425C is closed. In this regard, detector 405C provides a signal (e.g., current flowing through switch 425C, detector 405C, and switch 420D) to the circuitry of the ROIC. Detector 405B is used to isolate detector 405C from a potential short circuit at node 430 and / or contact 410A when switch 415B is open.

[0066] In a similar manner, other detectors including detector 405D may be selected for readout, for example, row-by-row readout in a sequential manner. In this regard, at approximately time t 8 , detector 405D has been read and the control signals are deasserted and asserted appropriately. Figure 5 The frame period may have approximately t 8 The duration of t = t 8 Thereafter (e.g., after executing detectors 405A to 405D (including Figure 4 After readout of any detector between detectors 405C and 405D not explicitly shown in the figure), the detector array and selection circuits can be initialized for the next frame period. The control signal EN 0 to EN Nis reasserted (e.g., as part of the global EN signal turning on), while the control signal SEL 1 To SEL N is deasserted and controls the BS signal 1 To BS N is in the asserted state, so the timing diagram 500 can be repeated for the next readout of the detector array (e.g., the next frame). In some embodiments, by closing switches 415A-D, 420A-F, and 425A-E in this manner, detrimental parasitic resistance and capacitance characteristics can be minimized and potential defects can be isolated, thereby providing improved detector array performance.

[0067] exist Figure 5 In FIG. 4 , when two detectors are enabled, there is a brief non-overlap time. For example, when both detectors 405A and 405B are enabled (eg, current flows through switch 425A, detectors 405A and 405B, and switch 420C), control signal EN 1 The deassertion of the control signal SEL 2 The non-overlapping time between the assertions of the control signal EN results in a short period of time. Similarly, such non-overlapping time exists between the assertions of the control signal EN 2 The deassertion of the control signal SEL 3 Between subsequent assertions of the control signal EN 3 The deassertion of the control signal SEL 4 Between subsequent assertions of the control signal EN N-1 The deassertion of the control signal SEL N between subsequent assertions of , and so on. It should be noted that Figure 5 The timing diagram associated with one exemplary embodiment is shown, and other embodiments may not include the duration when both detectors are enabled.

[0068] On the one hand, Figure 4 The selection circuit of the circuit 400 shown in FIG. Figure 5 The particular switching scheme associated with the timing diagram 500 shown in (e.g., the timing of the on or off state of each switch) can help reduce sensitivity to defects (e.g., column-to-column short defects), reduce noise, reduce crosstalk, and / or reduce parasitic capacitance within the FPA. In some cases, a previously readout detector and associated portions of its selection circuitry can be used to isolate the detector currently being readout.

[0069] Figure 6 600 is shown in association with a readout circuit (eg, ROIC) according to one or more embodiments. In one embodiment, the circuit 600 is coupled to a selection circuit and includes Figure 4The detector array of the detector string 405 is a microbolometer array. In this regard, the node 605 can be connected to Figure 4 435 of the detector array. In some cases, circuit 600 provides temperature compensation for the detector array. It should be noted that in other embodiments and as will be appreciated by those skilled in the art, circuit 600 can be associated with readouts of other detector arrays, and / or circuits different from circuit 600 can be associated with readouts of other detector arrays. For purposes of explanation, the detector array is an array of microbolometers. However, the detector array can include other types of infrared detector arrays (e.g., thermal infrared detector arrays, infrared detector arrays outside the thermal infrared spectrum) or detector arrays associated with wavelengths outside the infrared spectrum.

[0070] Circuit 600 includes power supply voltage 610, thermal short microbolometer 615, resistors 620 and 625, transistor 630, amplifier 635, and DAC 640. Power supply voltage 610 may provide a reference voltage V DETCOM In some aspects, circuit 600 provides substrate temperature compensation and temperature coefficient of resistance (TCR) mismatch compensation for a detector array.

[0071] The active microbolometer of the microbolometer array (e.g., one of detectors 405A-D or other detectors) can be a thermally isolated microbolometer that receives incident infrared radiation, which is selected from the circuit 400 provided above. The active microbolometer is driven by a reference voltage V DETCOM and load current I BIAS Bias. Amplifier 635 provides a gate bias to transistor 630, and DAC 640 is used to set an amplifier reference voltage and control amplifier 635 to set the appropriate gate bias for transistor 630. Alternatively, amplifier 635 can be eliminated and DAC 640 is used to directly set the appropriate gate bias for transistor 630. The load circuit or bias circuit includes a supply voltage 610, a resistor 625, a microbolometer 615 (e.g., a thermally shorted (to substrate) load microbolometer), transistor 630, and amplifier 635 with DAC 640, which is used to establish a load current I BIAS .

[0072] Microbolometer 615 acts as a substrate temperature compensation load. Supply voltage 610 is set to optimize the operating point of circuit 600 by setting the nominal voltage drop across microbolometer 615. The output voltage V of circuit 600 is provided at node 645. OUT In some cases, the output voltage V may be transformed, amplified, or converted by an amplification or integration process and / or other signal processing techniques. OUT For example, the amplifier can amplify the voltage at node 645 to provide an output voltage VOUT .

[0073] As the level of incident infrared radiation increases, the temperature of the active microbolometer (e.g., one of the detectors of detector string 405) increases. The temperature increase reduces the resistance of the active microbolometer and reduces the voltage drop across the active microbolometer, and thus increases the voltage level at the drain terminal of transistor 630 (i.e., at node 645). The change in the voltage drop across the active microbolometer results in an output voltage V OUT Thus, an increase or decrease in the incident infrared radiation level is respectively transmitted through the output voltage V OUT The increase or decrease of the voltage level is reflected.

[0074] The power supply voltage 610 is used to regulate the load current and thereby adjust the output voltage V OUT The operating point of the circuit 600 is optimized by setting the appropriate gate bias of the transistor 630 and the appropriate voltage level of the power supply voltage 610 at a desired point within the output circuit voltage level range. The output voltage V OUT For example, supply voltage 610 may be a single voltage level set for the entire microbolometer array. Amplifier 635 and DAC 640 may then be used to provide a unique voltage bias to each corresponding thermally shorted microbolometer 615 in the FPA to provide a bias to the load voltage or load current I BIAS This corrects for individual offset errors in the output signal from each thermally isolated microbolometer (e.g., an active microbolometer). By adjusting the offset of each microbolometer circuit, the output voltage V OUT The nominal output voltage level is adjusted to fall within the desired range.

[0075] In one aspect, resistors 620 and 625 can be used to account for a relative mismatch in TCR between an active microbolometer and microbolometer 615 (e.g., a load microbolometer). Resistor 620 is a variable resistor to provide adjustment (e.g., fine tuning) of a composite TCR value of the active microbolometer portion of the circuit relative to the load microbolometer portion of the circuit. Resistor 625 provides adjustment (e.g., coarse tuning) for circuit 600. Thus, by providing resistor 620, temperature compensation can be provided for a mismatch in relative TCR between the active microbolometer and the load microbolometer. In this regard, for a voltage divider network of resistors, resistor 620 adjusts the composite TCR of the active microbolometer and resistor 620 relative to microbolometer 615 and resistor 625. As an example, the circuit values ​​of these circuit elements may range from about 50 kΩ to about 200 kΩ and from about 150 kΩ to about 600 kΩ, respectively, for active microbolometers and microbolometer 615. Exemplary circuit values ​​of resistors 620 and 625 may, for example, vary from about 0 Ω to about 10 kΩ and from about 0 Ω to about 30 kΩ, respectively, but these ranges are not limiting and may vary within a wider range of values.

[0076] Resistors 620 and 625 are typically resistors that have different TCRs (e.g., typically lower) than their corresponding microbolometers (e.g., active microbolometers and microbolometer 615). For example, resistor 620 may have a low TCR, and the active microbolometer may have a higher TCR relative to microbolometer 615. By appropriately selecting the resistance value of resistor 620, the combination of resistor 620 and the active microbolometer provides a TCR that is closer to the TCR of microbolometer 615 (or closer to the TCR of the combination of microbolometer 615 and resistor 625 if resistor 625 is present) than the TCR of the active microbolometer alone. As a result, the performance and behavior of each microbolometer within the array is greatly improved over the substrate temperature range.

[0077] although Figure 4-6 Portions of the circuitry of an FPA and timing diagrams associated with readout of a detector array of the FPA are shown, but it should be noted that such circuitry and timing diagrams are provided as non-limiting examples. Different architectures (and associated timing diagrams) may be utilized to implement the circuitry of the FPA, such as different architectures of the detector array, the selection circuitry of the readout circuitry, and / or other components of the FPA. Additional examples of circuitry of an FPA and associated timing diagrams are provided, for example, in U.S. Patent No. 7,679,048, which is incorporated herein by reference in its entirety.

[0078] In some embodiments, techniques for verifying unit cell selection functionality are provided. In some aspects, a unit cell array includes a detector array and a selection circuit for selecting one or more detectors of the detector array. Each unit cell of the unit cell array includes a detector and a portion of the selection circuit. The selection circuit may include a switch whose state (e.g., an on or off state) can be controlled using a control signal to select / address multiple portions of the detector array, such as addressing / selecting a detector for row-by-row readout. Thus, the techniques provided herein for verifying the functionality of the selection circuit may involve verifying the functionality of each of the switches that form the selection circuit.

[0079] During normal operation of the unit cell array, a combination of states of switches of a portion of the unit cells being addressed (e.g., a row of unit cells) is controlled (e.g., turned on or off) according to a specific signal pattern sequence for readout, compared to non-addressed unit cells. Normal operation may refer to detecting radiation to generate detection signals, followed by reading out these detection signals, without unit cell selection verification as provided herein. The specific signal pattern sequence may be referred to as a normal signal pattern sequence because the signal pattern sequence is followed to address the unit cells for readout during normal operation. For example, returning to reference Figure 4 and 5 , at a given point in time, the states (e.g., logic high or logic low) of the BS, EN, and SEL control signals are in a particular signal pattern (e.g., a particular combination of logic high and logic low) to facilitate biasing and readout of the addressed unit cells compared to the states of these signals in the non-addressed unit cells. Figure 4 and 5 In the example of , the signal pattern applied to the unit cell can be provided as a 3-tuple (BS, EN, SEL). Figure 4 The signal pattern of switches 415B, 420C and 425B associated with detector 405B in the embodiment can be represented by the triple (BS 2 ,EN 2 , SEL 2 ) is provided. It should be noted that although for explanation purposes, three control signals are used to perform unit cell selection, in other embodiments, less than three control signals or more than three control signals may be used to perform unit cell selection. The number of control signals is typically based on the architecture of the detector array and / or readout circuit.

[0080] To verify the functionality of the unit cell selection circuit, a control signal provided to the selection circuit (e.g., each switch of the selection circuit) via a control line (e.g., a digital control line) may be controlled (e.g., set), and an output signal from the unit cell may be monitored. Figure 2, control signals may be provided by row multiplexer 230 to row 270 of unit cell array 205 via control line(s) 265. In embodiments, techniques may test (e.g., directly test) and verify functionality of each switch of a selection circuit, which in some cases covers a large percentage of the chip area and total switch count associated with the readout circuitry. In one aspect, the switches may be implemented using transistors. Such transistors may be referred to as imaging sensor unit cell transistors, unit cell interface transistors, or unit cell transistors. As an example, a malfunctioning switch may exhibit characteristics of being stuck in an on state (e.g., the switch essentially acts as a short circuit) or stuck in an off state (e.g., the switch essentially acts as an open).

[0081] In some embodiments, for each frame, a predetermined signal pattern may be applied to a portion of the selection circuit (e.g., associated with a row of the detector array). The predetermined signal pattern may refer to the state of each control signal to be applied to the portion of the selection circuit (e.g., logic low or logic high). In some aspects, for the portion of the selection circuit being tested, the predetermined signal pattern may be applied to the portion of the selection circuit within a single frame period (e.g., the entire frame period). For example, applying a logic high or logic low to a switch simulates the situation where the switch falls into an open state or an off state, respectively. Other portions of the selection circuit (e.g., portions that are not currently being tested) are addressed normally, where a normal sequence of signal patterns is applied to the readout of these other portions. In this regard, the portion of the selection circuit being tested may be associated with a verification operation, while the remaining portion of the selection circuit may be associated with a normal operation. In some aspects, a set of predetermined signal patterns may be applied to the portion of the selection circuit to verify whether the portion of the selection circuit (e.g., the switch of the selection circuit portion) is operating normally before continuing to verify other portions of the selection circuit (e.g., the switch of the other selection circuit portion).

[0082] In one aspect, using three control signals BS, EN, and SEL, the same 8 (ie, 2 3 ) combinations to test each part of the selection circuit. Table 1 shows an example of a predetermined signal pattern applied row by row to a unit cell array having 2,160 rows to verify the functionality of each of the three switches associated with each row of the unit cell array. For each frame, a predetermined signal pattern is applied to a row of unit cells. In order to apply eight predetermined signal patterns to each row of the unit cell array, the unit cell array captures 17,280 frames. In this regard, the test of the selection circuit of the 2,160-row unit cell array spans 17,280 frame periods. The other rows of unit cells are addressed normally, with normal signal pattern sequences being applied to the readout of these other rows.

[0083] Table 1: Example of a sequence of applied predetermined signal patterns

[0084]

[0085]

[0086] As an example in Table 1, for frame 1, the row 1 of the unit cell array applies the predetermined signal pattern #0 (BS=0, EN=0, SEL=0). As other examples in Table 1, for frames 2 to 8, the row 1 of the unit cell array applies the predetermined signal pattern #2 (BS 1 =0,EN 1 =0,SEL 1 =1) to predetermined signal pattern #7 (BS1=1, EN1=1, SEL1=1). Each of subsequent frames 9 to 17,280 may be associated with the application of one of eight predetermined signal patterns for a given row of the unit cell array.

[0087] Referring to row 1 of the unit cell array, row 1 may include detector 405A and other detectors in the same row as detector 405A. For frame 1, row 1 of the unit cell array is expected to provide no signal (e.g., a nominal zero output) by applying a predetermined signal pattern #0 to the portion of the selection circuit associated with row 1 of the unit cell array. In this regard, for detector 405A in row 1, control signal BS 1 ,EN 1 and SEL 1 is at logic low, and switches 415A, 420B, and 425A are closed. Similarly, the other detectors in row 1 also receive these control signals, and their corresponding switches are in the off state. If the unit cell of row 1 provides a non-zero signal instead of the expected nominal zero signal, the unit cell can be determined to be operating abnormally / incorrectly. The remaining predetermined signal patterns (e.g., predetermined signal patterns #1 to #7) can be applied to the unit cells of row 1 in consecutive frames (e.g., frames 2 to 8) to further verify the functionality of the unit cells of row 1. Applying each of the predetermined signal patterns on a given row of unit cells can allow verification of the functionality of each unit cell of the row (e.g., each switch of each unit cell). In this regard, the functionality of each individual switch can be verified.

[0088] Unit cells that are determined to be operating improperly / incorrectly may be indicated as being in an error state. The error state may be due to a bad connection (e.g., a control line carrying a control signal to a switch may be faulty) and / or one or more of the switches may always be stuck on (e.g., the switch essentially always remains shorted) or stuck off (e.g., the switch essentially always remains open). In the above example, if any switch is determined to be operating improperly, troubleshooting and / or mitigation actions (e.g., repairs) may be performed on row 1 of unit cells (or a particular portion / component of row 1 of unit cells).

[0089] On the other hand, rather than applying all predetermined signal patterns to the portion of the selection circuit associated with a given row of the detection array in consecutive frames, the same predetermined signal pattern can be applied to multiple portions of the selection circuit associated with different rows in consecutive frames. Table 2 shows an example of a predetermined signal pattern applied using this scheme to verify the functionality of each of the three switches associated with each row of the unit cell array row by row. The other rows are addressed normally.

[0090] Table 2: Example of a sequence of applied predetermined signal patterns

[0091]

[0092]

[0093]

[0094] It should be noted that Tables 1 and 2 provide exemplary schemes for verifying unit cell selection functionality, and other schemes can be used to verify selection functionality as long as the functionality of each switch (e.g., each transistor) of the selection circuit is verified. In some cases, the scheme may enable testing of two different rows in two temporally adjacent frames (e.g., in Tables 1 and 2, frames 3 and 4 are temporally adjacent frames). In other cases, the scheme may define the minimum distance between rows that can be tested in temporally adjacent frames. For example, if frame 1 is associated with test row 1, frame 2 may need to be associated with test row 1,080 or higher. The scheme used may be based on the application. For example, testing row 1 for eight consecutive frames (e.g., row 1 provides little or no image data for eight consecutive frames) may be undesirable in some applications.

[0095] In some aspects, such as when obtaining test data from the selection circuit is too disruptive for imaging and / or inconsistent with the error tolerance period associated with some applications, the unit cell selection verification can be performed as a power-on test. Alternatively or additionally, the schemes for performing unit cell selection verification (such as those shown in Tables 1 and 2) can be designed to avoid test data interfering with imaging and / or other application-related criteria. For example, in some cases, avoiding testing the same row in temporally adjacent frames can help avoid disruption to imaging.

[0096] As an example, for an FPA having 2,160 rows and operating at a frame rate of 240 Hz, the time to perform unit cell selection verification according to Table 1 or Table 2 is 72 seconds. As another example, for an FPA having 2,160 rows and operating at a frame rate of 60 Hz, the time to perform unit cell selection verification according to Table 1 or Table 2 is 288 seconds.

[0097] Figure 7 An exemplary system 700 for facilitating functional verification of unit cell selection according to one or more embodiments of the present disclosure is shown. However, all of the depicted components may not be required, and one or more embodiments may include additional components not shown in the figures. The arrangement and type of components may be varied without departing from the spirit or scope of the claims as set forth herein. Additional components, different components, and / or fewer components may be provided.

[0098] The system 700 includes a control signal generator 705, an FPA 710, an image processing device 715, and a unit cell selection verification device 720 (e.g., also referred to as a selection verification device or verification device). The FPA 710 includes a detector array and an ROIC. In one embodiment, the control signal generator 705 and the unit cell selection verification device 720 can be implemented by the processing component 105 and / or the imaging capture component 115.

[0099] The control signal generator 705 may generate control signals for the FPA 710. The control signals may include control signals for selecting / addressing unit cells (e.g., for readout) of the FPA 710. In one aspect, for a given subset (e.g., a row) of unit cells, the control signal generator 705 may apply a set of predetermined signal patterns to the subset of unit cells to verify functionality of the subset of unit cells. In some cases, for a given frame, the control signal generator 705 may apply the predetermined signal patterns to a subset of unit cells to verify functionality of the subset of unit cells. In one example, e.g., with respect to Table 1, the control signal generator 705 may apply each predetermined signal pattern in the set of predetermined signal patterns to the same row of unit cells on temporally adjacent frames before continuing to apply each predetermined signal pattern in the set of predetermined signal patterns to the next row of unit cells on temporally adjacent frames. In another example, the control signal generator 705 may apply the same predetermined signal pattern to each row of unit cells over temporally adjacent frames before continuing to apply the next predetermined signal pattern to each row over temporally adjacent frames, e.g., with respect to Table 2. Other ways in which the set of predetermined signal patterns may be applied to verify functionality of unit cells of the unit cell array may be performed depending on the application.

[0100] The image processing device 715 may generate an image based on the output signals from the FPA 710. For unit cells that are not currently being tested (e.g., a normal signal pattern sequence is applied), the output signals may be based on detection signals (e.g., detection current / voltage) generated by the detectors of these unit cells based on detected radiation (e.g., detected IR radiation). For unit cells that are being tested, the output signals from these unit cells may or may not depend on the detection signals generated by the detectors of these unit cells, depending on the predetermined signal pattern applied. In one aspect, output signals that are independent of the detection signals may still be considered to be associated with the detectors (or more generally associated with the unit cells that include these detectors) because the output signals are obtained when the ROIC is addressed to read out from the detectors. In one case, the image processing device 715 may include the output signals from the unit cells being tested in the image, which may be provided for display, storage, and / or further processing. In this case, a portion of the image provided by the image processing device 715 may not be associated with the image data. Depending on the number of rows and columns in the unit cell array, a portion of the image associated with the unit cell being tested may not generally be noticed by an observer of the image. For example, when the unit cell being tested constitutes one row of an array having hundreds or thousands of rows, an observer may not typically notice that one of the rows does not include image data.

[0101] In other cases, the image processing device 715 does not incorporate the output signals from the unit cells being tested into the generated image. As an example, for a unit cell array having 2,160 rows, the image generated by the image processing device 715 can simply exclude the output signals associated with the unit cells being tested from the image (e.g., not including these output signals in the image), so that the image effectively has 2,159 rows of image data. As another example, the image processing device 715 can generate pixel values ​​for the unit cells being tested based on the output signals (e.g., detection signals) of one or more of the untested unit cells, and generate an image based on the output signals of the untested unit cells and these generated pixel values. Such pixel values ​​can be referred to as interpolated pixel values. The untested unit cells whose detection signals are used to generate pixel values ​​can be unit cells adjacent to the unit cells being tested. As an example, these unit cells can be spatially adjacent to the unit cells being tested, such as unit cells in adjacent rows of the unit cells being tested (e.g., when the test is performed row by row). Alternatively or additionally, as another example, the unit cells may be temporal neighbors of the unit cell being tested. For example, consider that row 86 of the unit cell array is tested in frame 74 and is not tested in frames 72, 73, 75, and 76. For frame 74, the pixel value of row 86 may be determined based on the detection signal from row 86 for one or more of frames 72, 73, 75, and 76. Other ways of generating images while testing a subset of unit cells may be utilized and may be based on the application (e.g., whether the application is sensitive to a row of missing / lost image data).

[0102] The unit cell selection verification device 720 may receive output signals from the FPA 710. In some cases, the unit cell selection verification device 720 may receive output signals from all unit cells of the FPA 710. In other cases, the unit cell selection verification device 720 may receive output signals only from unit cells of the FPA 710 to be verified (e.g., receive output signals only from unit cells under test).

[0103] The unit cell selection verification device 720 may determine whether the unit cell under test is operating properly in response to the predetermined signal pattern applied. For example, referring to Table 1, for frame 9, the unit cell selection verification device 720 determines whether row 2 of the FPA 710 is operating properly by determining whether a signal (e.g., a nominal zero signal) is not received from each unit cell of row 2 in response to the predetermined signal pattern (BS=0, EN=0, SEL=0) applied to row 2 of the FPA 710. For frame 15, the unit cell selection verification device 720 determines whether row 2 of the FPA 710 is operating properly based on whether the output signal associated with row 2 of the FPA 710 matches the output signal expected in response to the predetermined signal pattern (BS=1, EN=1, SEL=0) applied to row 2 of the FPA 710. In this regard, the unit cell selection verification device 720 may verify the functionality of row 2 by comparing the output signal of row 2 with the output signal expected in response to the application of the predetermined signal pattern. With further reference to row 2, the unit cell selection verification device 720 may collectively use at least frames 9 through 16 to determine whether row 2 of the FPA 710 is operating properly. In one aspect, the output signal associated with that portion of the selection circuitry may be captured in the output stream and compared to the factory characterized safe operating range predictions to verify the functionality of that portion of the selection circuitry.

[0104] The knowledge of the applied predetermined signal pattern (e.g., for a given frame) facilitates image generation by the image processing device 715 and unit cell selection verification by the unit cell selection verification device 720. In some embodiments, the image processing device 715 and / or the unit cell selection verification device 720 may receive an indication of the predetermined signal pattern applied to the FPA 710 for a given frame from the control signal generator 705. In other embodiments, the control signal generator 705 may not need to communicate the indication of the predetermined signal pattern to the unit cell selection verification device 720. For example, proper synchronization and operation of the control signal generator 705 and the unit cell selection verification device 720 regarding, for example, a frame number and an associated predetermined signal pattern applied to that frame number may avoid the need to communicate the indication of the predetermined signal pattern to the image processing device 715 and / or the unit cell selection verification device 720 by the control signal generator 705.

[0105] In some aspects, verification of the unit cell selection function may be aborted without applying all predetermined signal patterns to all portions of the selection circuitry. As one example, verification may be aborted when greater than a threshold number of portions and / or switches of the selection circuitry in the FPA 710 as a whole are determined to be operating incorrectly. As another example, verification may be aborted when greater than a threshold number of portions and / or switches in a localized area of ​​the FPA 710 are determined to be operating incorrectly. In this latter example, a high density of incorrectly operating selection circuitry in a localized area may indicate damage to the FPA 710 in that localized area. In some cases, a user of the FPA 710 (e.g., a camera that includes the FPA 710) may be alerted to the situation so that the user may troubleshoot and / or perform mitigation actions (e.g., cleaning the localized area as a possible repair).

[0106] Figure 8 FIG. 8 is a flow chart showing an exemplary process 800 for facilitating functional verification of unit cell selection according to one or more embodiments of the present disclosure. Figure 7 Process 800 is described with respect to system 700 of FIG. However, process 800 may be performed with respect to other systems for facilitating functional verification of unit cell selection. It should be noted that Figure 8 One or more operations in may be combined, omitted, and / or performed in a different order as desired.

[0107] At block 805, electromagnetic radiation is detected by a detector array of FPA 710. In one aspect, the detector array is an infrared detector array (eg, a microbolometer array) that detects IR radiation (eg, thermal IR radiation).

[0108] At block 810, the control signal generator 705 applies a predetermined signal pattern to a portion of the selection circuitry of the FPA 710. In an embodiment, the portion of the selection circuitry may include a portion associated with a row of the detector array (e.g., associated with addressing / reading out a row of the detector array). Figure 4 and 5 , the predetermined signal pattern can be provided as a 3-tuple (BS, EN and SEL). Each of the three control signals is applied to the corresponding switches to configure the switches to an on or off state. For example, for frame 1 of Table 1 and referring to Figure 4 and 5 , predetermined signal pattern (BS 1 =0,EN 1 =0,SEL 1 =0) is applied to detector 405A and other detectors in the same row as detector 405A. Switches 415A, 420B, and 425A associated with detector 405A respond to a predetermined signal pattern (BS1 =0,EN 1 =0,SEL 1 =0) and open.

[0109] At block 815, the readout circuitry of the FPA 710 performs a readout of the FPA 710 to obtain an output signal. While the portion of the selection circuitry has the predetermined signal pattern applied, the remaining portions of the selection circuitry (e.g., the remaining rows) are controlled normally (e.g., addressed normally via a normal sequence of signal patterns) to allow readout of detection signals generated by detectors associated with these remaining portions. For a given detector, a detection signal (e.g., a detection voltage, a detection current) may be generated based on electromagnetic radiation detected by the detector. Depending on the predetermined signal pattern applied, the output signal associated with the portion of the selection circuitry may be independent of the electromagnetic radiation detected by the detector associated with the portion of the selection circuitry. For the remaining portions of the selection circuitry, the output signal may be or may be based on the detection signal generated by the associated detector.

[0110] At block 820, the unit cell selection verification device 720 determines / verifies whether the portion of the selection circuit is operating correctly based on the output signal associated with the portion of the selection circuit. The unit cell selection verification device 720 may compare the output signal with the expected output signal corresponding to the predetermined signal pattern applied at block 815. For example, when the predetermined signal pattern (BS=0, EN=0, SEL=0) is applied to the portion of the selection circuit, no signal (e.g., a nominal zero signal) from the portion of the selection circuit is expected. In some cases, the output signal associated with the portion of the selection circuit may be captured in the output stream and compared with the factory-characterized safe operating range prediction results. It should be noted that such verification at block 820 may be referred to as partial verification of the portion of the selection circuit. In this regard, the unit cell selection verification device 720 may verify / determine whether the portion is operating correctly based on the output signal obtained from a given portion of the selection circuit in response to the application of each of a set of predetermined signal patterns as shown, for example, in Tables 1 and 2.

[0111] At block 825, the image processing device 715 generates an image based on the output signal from the FPA 710. The image may be provided for display, storage, and / or further processing. In one case, the image processing device 715 may include the output signal associated with the portion of the selection circuit. In this case, a portion of the image provided by the image processing device 715 may not be associated with the image data. In other cases, the image processing device 715 does not incorporate the output signal associated with the portion of the selection circuit into the generated image.

[0112] In some embodiments, process 800 is performed during a single frame period. The next frame period can be associated with applying a different predetermined signal pattern to the same portion of the selection circuit (e.g., as in the scheme shown in Table 1), applying the same predetermined signal pattern to different portions of the selection circuit (e.g., as in the scheme shown in Table 2), or applying a different predetermined signal pattern to different portions of the selection circuit. In some aspects, process 800 can be repeatedly performed until all predetermined signal patterns have been applied to all portions of the selection circuit (e.g., all transistors of the selection circuit). In some aspects, verification of unit cell selection functionality can be aborted without all predetermined signal patterns having been applied to all portions of the selection circuit, such as if it is determined that a large number of switches of the selection circuit are not functioning properly.

[0113] Using various embodiments, techniques may be applied to implement safety measures to support functional safety of imagers (e.g., infrared cameras). In some aspects, a large portion of the selection circuitry of an FPA may have its functionality quickly tested. In some cases, safety measures may verify that a unit cell selection circuit (e.g., a unit cell switch) operates normally. Thus, such techniques may allow each unit cell switch to be tested (e.g., directly tested) and allow for direct statements of functional safety coverage, such as direct statements involving proof of compliance with safety standards. For example, such techniques may help reduce the time and documentation involved in certification compliance with safety standards (e.g., vehicle safety standards). In some aspects, unit cell selection verification may be performed as a power-on test, such as when obtaining test data from a selection circuit is too destructive for imaging and / or inconsistent with a fault tolerance period associated with some applications (e.g., vehicle applications). For example, for vehicle applications, a camera mounted to a vehicle may test its selection circuitry during power-on of the vehicle and / or camera.

[0114] Where applicable, the various embodiments provided by the present disclosure can be implemented using hardware, software, or a combination of hardware and software. Also where applicable, without departing from the spirit of the present disclosure, the various hardware components and / or software components set forth herein can be combined into composite components comprising software, hardware, and / or both. Where applicable, without departing from the spirit of the present disclosure, the various hardware components and / or software components set forth herein can be divided into subcomponents comprising software, hardware, or both. In addition, where applicable, it is expected that software components can be implemented as hardware components, and vice versa.

[0115] Software according to the present disclosure, such as non-transitory instructions, program code and / or data, can be stored on one or more non-transitory machine-readable media. It is also contemplated that the software identified herein can be implemented using one or more general or special-purpose computers and / or computer systems, networked and / or otherwise. Where applicable, the order of the various steps described herein can be changed, combined into composite steps and / or divided into sub-steps to provide the features described herein.

[0116] The foregoing description is not intended to limit the present disclosure to the precise form disclosed or to the specific field of use. The above embodiments illustrate but do not limit the present invention. It is contemplated that various alternative embodiments and / or modifications of the present invention are possible in light of the present disclosure, whether explicitly described or implied herein. Therefore, the scope of the present invention is limited only by the following claims.

Claims

1. A method for selective functional verification of an imaging device, the method comprising: detecting electromagnetic radiation by each detector of a focal plane array of the imaging device, wherein each detector is selectively coupled to a readout circuit of the focal plane array via selection circuitry of the focal plane array; During the first frame period: applying a first predetermined signal pattern to a first portion of the selection circuit, wherein the first portion of the selection circuit is associated with a first subset of detectors of the focal plane array; and performing a first readout of the focal plane array to obtain a respective output signal associated with each respective detector of the focal plane array; determining whether the first portion of the selection circuitry is operating properly based at least on output signals from the first readout associated with the first subset of detectors; and An image is generated based at least on output signals of detectors of the focal plane array that are not in the first subset of detectors.

2. The method according to claim 1, wherein: The first predetermined signal pattern is one of a plurality of predetermined signal patterns, and wherein an output signal of each detector in the first subset in response to at least one of the plurality of predetermined signal patterns is independent of electromagnetic radiation.

3. The method according to claim 2, wherein: The determining includes determining whether the first portion of the selection circuit is operating properly based at least on output signals from the first sensed detectors responsive to the first subset of each of the plurality of predetermined signal patterns.

4. The method according to claim 1, wherein: The focal plane array comprises an array of unit cells, wherein each unit cell in the array of unit cells comprises a detector of the focal plane array and a portion of the selection circuit, wherein the portion comprises a plurality of switches, and wherein the first subset of detectors comprises a row of detectors.

5. The method according to claim 1, further comprising, during the second frame period: applying a second predetermined signal pattern to the first portion of the selection circuit; and performing a second readout of the focal plane array to obtain a respective output signal associated with each respective detector of the focal plane array, in, The determining includes determining whether the first portion of the selection circuit is operating properly based on at least output signals associated with the first subset of detectors from the first readout and the second readout.

6. The method according to claim 5, wherein: The second frame period is adjacent to the first frame period in time.

7. The method according to claim 5, wherein: The second frame period is not adjacent to the first frame period in time.

8. The method according to claim 1, further comprising, during the second frame period: applying a second predetermined signal pattern to a second portion of the selection circuit, wherein: the second portion of the selection circuit being associated with a second subset of detectors of the focal plane array; performing a second readout of the focal plane array to obtain a respective output signal associated with each respective detector of the focal plane array; as well as A determination is made as to whether the second portion of the selection circuit is operating properly based at least on output signals from the second readout associated with the second subset of detectors.

9. The method according to claim 8, wherein: The second frame period is adjacent to the first frame period in time.

10. The method of claim 1, further comprising determining pixel values ​​of the first subset of detectors based on output signals of one or more of the detectors not in the first subset of detectors, wherein: The image is based on the pixel values ​​and output signals of detectors that are not in the first subset of detectors.

11. The method according to claim 10, wherein: The one or more of the detectors include one or more detectors adjacent to one or more detectors in the first subset of detectors.

12. The method according to claim 1, further comprising, during the first frame period: configuring a first plurality of switches to selectively short circuit one or more of the detectors of the focal plane array; configuring a second plurality of switches to selectively provide bias signals to one or more of the detectors of the focal plane array; as well as A third plurality of switches is configured to selectively couple one or more of the detectors of the focal plane array to the readout circuitry.

13. The method according to claim 12, wherein: The first predetermined signal pattern includes a first signal level associated with the first control signal, a second signal level associated with the second control signal, and a third signal level associated with the third control signal; Configuring the first plurality of switches includes configuring a first set of switches associated with a first subset of the detectors using the first control signal; Configuring the second plurality of switches includes using the second control signal to configure a second set of switches associated with a first subset of the detectors; and Configuring the third plurality of switches includes using the third control signal to configure a third set of switches associated with the first subset of the detectors.

14. The method according to claim 12, wherein: Each switch of the first plurality of switches, each switch of the second plurality of switches, and each switch of the third plurality of switches includes a transistor.

15. An imaging device, comprising: A focal plane array, the focal plane array comprising: a detector array comprising a plurality of detectors, wherein each detector is configured to detect electromagnetic radiation; a readout circuit configured to perform a first readout during a first frame period, to obtain a respective output signal associated with each respective detector of said detector array; and a selection circuit configured to selectively couple the detector array to the readout circuit; a control signal generator configured to apply a first predetermined signal pattern to a first portion of the selection circuit during the first frame period, wherein the first portion of the selection circuit is associated with a first subset of detectors of the detector array; verification means configured to determine whether the first portion of the selection circuit is operating correctly based at least on output signals from the first readout associated with the detectors of the first subset; and Image processing means are configured to generate an image based at least on output signals of detectors of the detector array that are not in the first subset of detectors.

16. The imaging device according to claim 15, wherein: The first predetermined signal pattern is one of a plurality of predetermined signal patterns, and wherein the verification device is configured to determine whether the first part of the selection circuit is operating correctly based on the output signal of the detector responsive to the first subset of each of the plurality of predetermined signal patterns.

17. The imaging device according to claim 15, wherein: The focal plane array comprises a unit cell array, wherein each unit cell of the unit cell array comprises a detector of the detector array and a portion of the selection circuit, and wherein the portion comprises a plurality of switches.

18. The imaging device according to claim 15, wherein: The control signal generator is further configured to apply a second predetermined signal pattern to the first portion of the selection circuit during a second frame period; The readout circuit is further configured to perform a second readout during the second frame period to obtain a respective output signal associated with each respective detector of the detector array; and The verification means is configured to determine whether the first part of the selection circuit is operating correctly based on at least output signals from the first and second readouts associated with the detectors of the first subset.

19. The imaging device according to claim 15, wherein: The control signal generator is further configured to apply a second predetermined signal pattern to a second portion of the selection circuit during a second frame period, wherein the second portion of the selection circuit is associated with a second subset of detectors of the detector array; The readout circuit is further configured to perform a second readout during the second frame period to obtain a respective output signal associated with each respective detector of the detector array; and The verification device is further configured to determine whether the second portion of the selection circuit is operating correctly based on at least the output signals from the second readout associated with the detectors of the second subset.

20. The imaging device according to claim 15, wherein The image processing device is also configured to determine pixel values ​​of the first subset of detectors based on output signals of one or more detectors in the first subset of detectors that are not in the first subset of detectors, and wherein the image is based on the pixel values ​​and the output signals of the detectors that are not in the first subset of detectors.

21. The imaging device according to claim 15, wherein The selection circuit comprises: a first plurality of transistors, wherein each transistor of the first plurality of transistors is configured to selectively short-circuit a corresponding one of the plurality of detectors; a second plurality of transistors, wherein each transistor of the second plurality of transistors is configured to selectively provide a bias signal to a corresponding one of the plurality of detectors; and A third plurality of transistors, wherein each switch in the third plurality of transistors is configured to selectively couple a corresponding one of the plurality of detectors to the readout circuit.

22. The imaging device according to claim 21, wherein: The first predetermined signal pattern includes a first signal level associated with the first control signal, a second signal level associated with the second control signal, and a third signal level associated with the third control signal; the first plurality of transistors comprising a first set of transistors associated with a first subset of the detectors; the second plurality of transistors comprising a second set of transistors associated with a first subset of the detectors; the third plurality of transistors comprising a third set of transistors associated with a first subset of the detectors; During the first frame period: the first set of transistors being configured to receive the first control signal; The second set of transistors is configured to receive the second control signal; and The third set of transistors is configured to receive the third control signal.

Images