An array substrate, a display panel, a display device and a method for manufacturing an array substrate

Abstract

The present invention provides an array substrate, comprising a plurality of sub-pixel units located in an area defined by the intersection of a plurality of data lines and a plurality of scanning lines, wherein the electrode structure of the sub-pixel unit comprises: at least one first branch electrode along a first direction, the width of the first branch electrode along a second direction is a, the spacing between the first branch electrode and an adjacent electrode is c, and the width of a first spacing area is a+c; at least one second branch electrode along the first direction, the width of the second branch electrode along the second direction is b, the spacing between the second branch electrode and an adjacent electrode is d, and the width of the second spacing area is b+d, a is not equal to b and / or c is not equal to d; the first branch electrode and the second branch electrode are arranged alternately. The embodiment of the present invention can ensure that when the width of the first branch electrode and the width of the second branch electrode increase or decrease due to fluctuations in exposure, the transmittance of the first spacing area and the second spacing area changes in the opposite direction, so that the overall transmittance of the pixel remains relatively small.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel, a display device and a method for manufacturing the array substrate. Background Art

[0002] The exposure machine of the high-generation LCD panel production line has a projection unit composed of multiple projection lenses. There is a connection part between the multiple projection lenses. By adjusting the position and focus of each projection unit, the exposure amount and center of each connection part are the same, the uniformity of exposure energy is achieved, and the exposure is completed. The ideal exposure energy distribution is as follows Figure 1 As shown in FIG. 1 , the exposure of lens 1 and lens 2 at the joint position is complementary, and the combined exposure is the same as the center of the lens. However, in practice, there is a deviation in the imaging of the multiple projection lenses at the joint position, which will lead to differences in the critical dimension (CD) of the pattern formed on the substrate after the photoresist is exposed through the mask, such as Figure 2 , thereby forming lens mura on the exposed substrate.

[0003] In the related art, when a pixel electrode or a common electrode is formed by exposing a photoresist through a mask, the width of the pixel electrode or the common electrode formed at a position corresponding to the connecting portion on the substrate varies due to fluctuations in exposure amount.

[0004] In the Advanced Super Dimension Switch display mode, a fringe electric field is formed between the pixel electrode and the common electrode to control the deflection of the liquid crystal. If the width of the pixel electrode and the common electrode changes, the voltage applied to the liquid crystal will change, affecting the deflection of the liquid crystal molecules, thereby affecting the pixel transmittance, so that obvious mirror stripes will appear on the substrate when displaying, seriously affecting the display effect. Summary of the invention

[0005] Embodiments of the present invention provide an array substrate, a display panel and a method for manufacturing the array substrate, which are used to solve the problem that the display panel has mirror stripes during display, which seriously affects the display effect.

[0006] A first aspect of the present invention provides an array substrate, comprising a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixel units, wherein the plurality of sub-pixel units are located in an area defined by intersections of the plurality of data lines and the plurality of scan lines, and wherein an electrode structure of the sub-pixel unit comprises:

[0007] At least one first branch electrode along the first direction, the width of the first branch electrode along the second direction is a, the spacing between the first branch electrode and an adjacent electrode is c, and the width of the first spacing area is a+c;

[0008] At least one second branch electrode along the first direction, the width of the second branch electrode along the second direction is b, the spacing between the second branch electrode and the adjacent electrode is d, the width of the second spacing area is b+d, a is not equal to b and / or c is not equal to d;

[0009] The first electrodes and the second electrodes are arranged alternately.

[0010] Optionally, when the width a+c of the first spacing region is the same as the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode; or

[0011] When the width a+c of the first spacing region is different from the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is the same as the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode; or

[0012] When the width a+c of the first spacing area is different from the width b+d of the second spacing area, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is the same as the spacing d between the second branch electrode and the adjacent electrode.

[0013] Optionally, when the width a+c of the first spacing region is the same as the width b+d of the second spacing region, if the width of the first branch electrode along the second direction and the width of the second branch electrode along the second direction increase or decrease at the same time, the transmittance changes of the first spacing region and the second spacing region are opposite.

[0014] Optionally, |ab| is in the range of 0.1-1 micrometers, and / or, |cd| is in the range of 0.1-1 micrometers.

[0015] Optionally, the range of a is 1.8-3.0 microns, and the range of b is 1.8-3.0 microns.

[0016] Optionally, the range of c is 3.0-7.0 microns, and the range of d is 3.0-7.0 microns.

[0017] Optionally, a width a+c of the first spacing region is in a range of 6.6-8.0 microns, and a width b+d of the second spacing region is in a range of 6.6-8.0 microns.

[0018] Optionally, the electrode structure of the sub-pixel unit includes a plurality of domains, the plurality of domains include at least one first domain and at least one second domain, the first domain includes at least one first branch electrode along the third direction and at least one second branch electrode along the third direction, the first branch electrodes and the second branch electrodes are alternately arranged; the second domain includes:

[0019] At least one third branch electrode along a fourth direction, and at least one fourth branch electrode along the fourth direction, the third branch electrodes and the fourth branch electrodes are arranged alternately, the first branch electrode and the third branch electrode are electrically connected, and the fourth branch electrode and the second branch electrode are electrically connected.

[0020] Optionally, the third direction and the fourth direction form an acute angle or an obtuse angle.

[0021] Optionally, the electrode structure of the sub-pixel unit is a sub-pixel electrode or a common electrode.

[0022] A second aspect of the present invention provides a display panel, comprising the above-mentioned array substrate.

[0023] A third aspect of the present invention provides a method for manufacturing an array substrate, comprising:

[0024] forming a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixel units, wherein the plurality of data lines extend along a first direction, the plurality of scan lines extend along a second direction, and the plurality of sub-pixel units are located in an area defined by intersections of the plurality of data lines and the plurality of scan lines;

[0025] forming at least one first branch electrode along the first direction, wherein the width of the first branch electrode along the second direction is a, the spacing between the first branch electrode and an adjacent electrode is c, and the width of the first spacing region is a+c;

[0026] At least one second branch electrode is formed along the first direction, the width of the second branch electrode along the second direction is b, the spacing between the second branch electrode and the adjacent electrode is d, the width of the second spacing area is b+d, a is not equal to b and / or c is not equal to d; the first branch electrodes and the second branch electrodes are arranged alternately.

[0027] The embodiments of the present invention have the following beneficial effects:

[0028] The embodiment of the present invention can ensure that when the exposure fluctuation causes the width of the first electrode and the width of the second electrode to increase or decrease, the transmittance of the first spacing area and the second spacing area change oppositely, so that the overall transmittance of the pixel maintains a small fluctuation. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the exposure energy of the exposure machine at the connecting part under an ideal condition in the prior art;

[0030] Figure 2 It is a schematic diagram of the exposure energy of the exposure machine at the connecting part under actual conditions in the prior art;

[0031] Figure 3 This is a simulation diagram of the effect of the change in electrode characteristic line width on the transmittance at L127 grayscale;

[0032] Figure 4 A schematic diagram of the structure of a display substrate provided by an embodiment of the present invention;

[0033] Figure 5 A schematic diagram of the electrode structure of a sub-pixel unit provided in an embodiment of the present invention;

[0034] Figure 6 A schematic diagram of the arrangement of a first electrode and a second electrode provided by an embodiment of the present invention;

[0035] Figure 7 Another schematic diagram of arrangement of a first electrode and a second electrode provided by an embodiment of the present invention;

[0036] Figure 8 A schematic diagram of the width range of the first spacing area and the second spacing area provided in an embodiment of the present invention;

[0037] Fig. 9 A top view of an array substrate provided by an embodiment of the present invention;

[0038] Fig.10 for Fig. 9 Schematic diagram of the cross-sectional structure along line A-A';

[0039] Fig.11 for Fig. 9 Schematic diagram of the cross-sectional structure along line B-B';

[0040] Fig.12 is a transmittance simulation diagram of the array substrate of the present invention at the L127 gray scale;

[0041] Fig.13 is a transmittance simulation diagram of the array substrate of the present invention at the L255 gray scale;

[0042] Fig.14It is a comparison chart of transmittance of the prior art and the present invention at the L255 gray scale. DETAILED DESCRIPTION

[0043] In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0044] High-generation line exposure machines use lens splicing for exposure. Since the exposure amount at the lens joint position fluctuates, the characteristic line width of the graphics on the substrate will fluctuate accordingly.

[0045] In the ADS display mode, if the width of the pixel electrode and the common electrode changes, the pixel transmittance will be affected in two ways. On the one hand, if the width of the pixel electrode and the common electrode changes, the voltage applied to the liquid crystal will change, affecting the deflection of the liquid crystal molecules, thereby affecting the pixel transmittance; on the other hand, the pixel electrode and the common electrode themselves will also affect the transmittance, and the transmittance of the area where the pixel electrode or the common electrode is located is smaller than the gap (Space) between the electrodes. Within a certain range, the smaller the characteristic line width of the pixel electrode or the common electrode, that is, the smaller the proportion of the pixel electrode or the common electrode, the higher the pixel transmittance; however, when the characteristic line width of the pixel electrode or the common electrode continues to decrease and the Space increases, the average electric field in the Space area between the pixel electrode or the common electrode will also weaken, resulting in insufficient deflection of the liquid crystal in the Space area between the electrodes, which will also cause a decrease in transmittance.

[0046] Figure 3 Schematic diagram of the effect of the characteristic line width change of the electrode on the transmittance at L127 grayscale. The ordinate is grayscale and the abscissa is the characteristic line width change, i.e., the electrode width of the branch electrode. Figure 3The curve for the interval area (Pitch) of 6.6um is a curve of the width and grayscale change after adjusting the width of different branch electrodes for the 6.6um electrode structure. The value of 0 at the origin of the coordinate represents the width of the branch electrode, that is, the characteristic line width CD is 2.2um, and the Space width is 4.4um, that is, the distance between the branch electrode and the adjacent branch electrode, and the sum of CD and Space is the size of the interval area. For the curve with an interval area (Pitch) of 8um, the value of 0 represents the characteristic line width CD of 2.6um and the Space width of 5.4um. For the curve with an interval area (Pitch) of 7.6um, the value of 0 represents the characteristic line width CD of 2.4um and the Space width of 5.2um. It can be seen from the attached figure that when the Pitch is 7.6, the characteristic line width increases from 1.8um to 3.0um, the transmittance first increases and then decreases, and the CD value is bounded by 2.4um, decreasing to the left, for example 2.2um, or increasing to the right, for example 2.6um. The grayscale shows a relatively symmetrical trend, which reflects that the transmittance first increases and then decreases compared to the other two curves.

[0047] There are two points Pitch 1 and Pitch 2 on the curve with a pitch of 7.6um. The characteristic line width CD of Pitch 1 is 2.6um, and the gray scale decreases relative to the characteristic line width of 2.4um, that is, the transmittance decreases; the characteristic line width CD of Pitch 2 is 2.2um, and the gray scale also decreases relative to the characteristic line width of 2.4, that is, the transmittance also decreases.

[0048] From another perspective, for the curve with a pitch of 7.6um, if the characteristic line widths of the electrodes of Pitch 1 and Pitch 2 fluctuate positively and negatively at the same time, they are complementary in terms of displayed grayscale. For example, if the characteristic line width of Pitch 1 fluctuates positively from 2.6um to 2.8um, its transmittance will decrease. At the same time, if the characteristic line width of Pitch 2 fluctuates positively from 2.2um to 2.4um, its transmittance will increase, which is complementary in terms of displayed grayscale.

[0049] Similarly, if the characteristic line widths of Pitch 1 and Pitch 2 experience negative fluctuations at the same time, they are also complementary in the displayed grayscale. Therefore, when manufacturing an array substrate or a display panel, for example, when preparing a pixel electrode, after the pixel electrode pattern mask is set, when manufacturing the pixel electrode, there will often be process fluctuations, such as the widths of multiple branch electrodes included in the pixel electrode are larger or smaller than the actual set value, that is, positive fluctuations or negative fluctuations occur, which makes the overall transmittance of the display panel fluctuate greatly, and it is easy to produce lens mura (lens group stripes) caused by changes in electrode width. Therefore, for an electrode structure with a pitch of 7.6um, whether it is a positive fluctuation or a negative fluctuation, the transmittance can compensate each other, and the final improvement is to keep the overall transmittance of the electrode to a small fluctuation, which can improve the lens mura problem. It should be noted that the current description is based on the pixel electrode, and the common electrode can also be designed into such a structure, which is not limited here.

[0050] Similarly, if the Space of Pitch 1 and Pitch 2 fluctuate positively and negatively at the same time, the displayed grayscale is also complementary.

[0051] Based on the problems existing in the prior art, and Figure 3 Based on the simulation results, an embodiment of the present invention provides an array substrate.

[0052] Figure 4 A schematic diagram of the structure of a display substrate provided in an embodiment of the present invention, Figure 5 The electrode structure diagram of the sub-pixel unit provided in the embodiment of the present invention is shown in FIG. Figure 4 and Figure 5 The array substrate includes a plurality of data lines 10, a plurality of scan lines 20 and a plurality of sub-pixel units 30, wherein the plurality of sub-pixel units are located in an area defined by the intersection of the plurality of data lines and the plurality of scan lines, and the electrode structure of the sub-pixel unit includes:

[0053] At least one first branch electrode 31 along the first direction, the width of the first branch electrode along the second direction is a, the spacing between the first branch electrode and the adjacent electrode is c, and the width of the first spacing area is a+c;

[0054] At least one second branch electrode 32 along the first direction, the width of the second branch electrode along the second direction is b, the spacing between the second branch electrode and the adjacent electrode is d, the width of the second spacing area is b+d, a is not equal to b and / or c is not equal to d;

[0055] The first electrodes and the second electrodes are arranged alternately.

[0056] The array substrate further includes a transistor 40 , a gate of the transistor 40 is connected to the scan line, a source of the transistor is connected to the data line, and when the electrode structure included in the pixel unit is a pixel electrode, a drain of the transistor is connected to the pixel electrode.

[0057] In the present invention, the electrode structure includes at least one first branch electrode and at least one second branch electrode, which are arranged alternately, and the width of the first branch electrode and the second branch electrode is adjusted, and / or the spacing between the first branch electrode and the adjacent electrode, and the spacing between the second branch electrode and the adjacent electrode are adjusted, so that the overall pixel transmittance is kept relatively small during the process manufacturing process, and when used in a display panel, the display quality of the display panel is improved. Optionally, when a process fluctuation occurs, such as a positive fluctuation or a resurgence fluctuation, the electrode width of the first branch electrode and the electrode width of the second branch electrode are adjusted, and / or the spacing between the first branch electrode and the adjacent electrode, and the spacing between the second branch electrode and the adjacent electrode are adjusted to achieve transmittance complementarity, or for example, if the electrode width is adjusted, the corresponding transmittance of the branch electrode with a large width is relatively reduced, and the transmittance of the branch electrode with a smaller width is relatively high. When a positive process deviation occurs, the transmittance of the branch electrode with a larger width tends to decrease, and the transmittance of the branch electrode with a smaller width tends to increase, so that the transmittance fluctuation of the overall electrode structure is just kept small, which can improve the lens mura problem.

[0058] Figure 6 A schematic diagram of the arrangement of a first electrode and a second electrode provided in an embodiment of the present invention is shown in FIG. Figure 6 As shown, the width of the first electrode is a, and the spacing between the first electrode and the adjacent electrode is c; the width of the second electrode is b, and the spacing between the second electrode and the adjacent electrode is d.

[0059] Figure 7 Another schematic diagram of the arrangement of the first electrode and the second electrode provided in an embodiment of the present invention is shown in FIG. Figure 7 , wherein every two first electrodes and every two second electrodes are arranged alternately.

[0060] Optionally, when the width a+c of the first spacing region is the same as the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode; or

[0061] When the width a+c of the first spacing region is different from the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is the same as the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode; or

[0062] When the width a+c of the first spacing area is different from the width b+d of the second spacing area, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is the same as the spacing d between the second branch electrode and the adjacent electrode.

[0063] By setting the width of the first spacing region, the width of the first branch electrode, and the width of the second branch electrode, the requirements for the electrode structure of the sub-pixel in different application scenarios can be met.

[0064] Figure 8 A schematic diagram of the width range of the first spacing area and the second spacing area provided in an embodiment of the present invention; Figure 8 , the following examples of the values ​​of b and d relative to a and c are given.

[0065] The first value may be: when the width a+c of the first spacing region is the same as the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode, and b>a,d <c;

[0066] The second value may be: when the width a+c of the first spacing region is the same as the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode, and b<a,d> c;

[0067] The third value may be: when the width a+c of the first spacing area is different from the width b+d of the second spacing area, the width a of the first branch electrode along the second direction is the same as the width b of the second branch electrode along the second direction, the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode, and d <c;

[0068] The fourth value may be: when the width a+c of the first spacing area is different from the width b+d of the second spacing area, the width a of the first branch electrode along the second direction is the same as the width b of the second branch electrode along the second direction, the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode, and d <c;

[0069] The fifth value may be: when the width a+c of the first spacing area is different from the width b+d of the second spacing area, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is the same as the spacing d between the second branch electrode and the adjacent electrode, and b>a;

[0070] The sixth value may be: when the width a+c of the first spacing region is different from the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is the same as the spacing d between the second branch electrode and the adjacent electrode, and b <a。

[0071] Optionally, |ab| is in the range of 0.1-1 micrometers, and / or, |cd| is in the range of 0.1-1 micrometers. By setting |ab| in the range of 0.1-1 micrometers, and / or, |cd| in the range of 0.1-1 micrometers, it is possible to prevent the transmittance from being non-complementary when the characteristic line width changes due to a large difference in the value range, thereby reducing or increasing the transmittance.

[0072] Optionally, the range of a is 1.8-3.0 microns, and the range of b is 1.8-3.0 microns.

[0073] By setting the range of a to 1.8-3.0 microns and the range of b to 1.8-3.0 microns, not only can the transmittance of the area where Pitch 1 and Pitch 2 are located be high, but also the electric field strength of the area where Pitch 1 and Pitch 2 are located be guaranteed.

[0074] Optionally, the range of c is 3.0-7.0 microns, and the range of d is 3.0-7.0 microns.

[0075] By setting the range of c to 3.0-7.0 microns and the range of d to 3.0-7.0 microns, it is possible to ensure that the transmittance of the areas where Pitch 1 and Pitch 2 are located is high. Optionally, the width a+c of the first spacing area is in the range of 6.6-8.0 microns, and the width b+d of the second spacing area is in the range of 6.6-8.0 microns.

[0076] By setting the width of the first spacing region, the width of the first branch electrode, and the width of the second branch electrode, the requirements for the electrode structure of the sub-pixel in different application scenarios can be met.

[0077] refer to Fig. 9 , Fig. 9A top view of an array substrate provided by an embodiment of the present invention. Fig.10 for Fig. 9 Schematic diagram of the cross-sectional structure along line A-A'; Fig.11 for Fig. 9 Schematic diagram of the cross-sectional structure along line BB'.

[0078] refer to Figures 9 to 11 The array substrate includes a first transparent electrode layer, a gate insulating layer GI, a protective layer PVX, a source and drain electrode layer, and a second transparent electrode layer, wherein the electrode structure of the second transparent electrode layer corresponding to a sub-pixel unit includes Pitch 1 and Pitch 2, and the widths of Pitch 1 and Pitch 2 are both 7.6um, wherein the width of the inner branch electrode of Pitch 1 is 2.6um, and the width of Space is 5.0um; the width of the inner branch electrode of Pitch 2 is 2.2um, and the width of Space is 5.4um. The figure shows that 1ITO is a pixel electrode, 2ITO is a common electrode, 1ITO and the gate or gate line are in the same layer, and the stacking order of the film layers in the figure can be adjusted according to the actual process, and no limitation is made here. It should be noted that the widths of Pitch 1 and Pitch 2 are both 7.6um, wherein the width of the inner branch electrode of Pitch 1 is 2.0um, and the width of Space is 5.6um; the width of the inner branch electrode of Pitch 2 is 2.8um, and the width of Space is 4.8um. The parameters provided in the present invention all include parameter limits within a test error range, for example, a measurement error of + / - 0.1 um.

[0079] Reference again Figure 3 Compared with the maximum characteristic line width of transmittance W / S=2.4 / 5.2, Pitch 1 has a slightly larger characteristic line width W / S=2.6 / 5.0, and Pitch 2 has a slightly smaller characteristic line width W / S=2.2 / 5.4; when the electrode characteristic line width increases, Pitch 1 will cause the pixel transmittance to decrease, while Pitch 2 will cause the pixel transmittance to increase, and finally compensate each other, so that the overall pixel transmittance fluctuates less.

[0080] The pitch of the array substrate of the present invention is selected to be 7.6um. When making the display panel electrode pattern, since the mask plate design is fixed, for example, the first electrode is selected to be 2.2 and the second electrode is selected to be 2.6, when the process fluctuates, the process fluctuation is positive or negative. For example, if it is a positive fluctuation, 2.2 corresponds to a movement to the right, and the grayscale brightness or transmittance increases. However, at this time, 2.6 corresponds to a movement to the right, and the grayscale brightness or transmittance decreases.

[0081] Fig.10This is a simulated transmittance diagram of the array substrate of the present invention at the L127 grayscale. The characteristic line width of the array substrate provided by the embodiment of the present invention varies within the range of ±0.2um, and the change in pixel transmittance is much smaller than that of conventional designs, which can effectively improve the mirror group fringes. Fig.10 In the existing design, when the electrode structures are the same, for example, the line width and space of the branch electrodes included in the electrode structure are the same, referring to the upper curve of the two curves, it can be seen that when the branch electrode structure fluctuates, taking the branch electrode at the origin as a reference, for example, a positive fluctuation, the grayscale will change from 127 to 126, and when a negative fluctuation occurs, the grayscale will change from 127 to 126; and referring to the design of the present invention, referring to the lower curve of the two curves, taking the branch electrode at the origin as a reference, whether it is a positive fluctuation or a negative fluctuation of the process, the grayscale difference is not large, all around 126 grayscale, and the grayscale difference is less than 1 grayscale value; it means that the present invention can achieve a relatively small fluctuation in the overall grayscale and transmittance of the electrode structure.

[0082] It should be noted that Multi Pitch does not include the case where Pitch 1 and Pitch 2 have the same width, and the width a of the first electrode and the width b of the second electrode are also equal.

[0083] Fig.13 The transmittance simulation diagram of the array substrate of the present invention at the L255 grayscale. At the L255 grayscale, as the characteristic line width of the electrode of the present invention continues to increase with the characteristic line width of the branch electrode, for example, when adjusted above 0.4um, the corresponding transmittance no longer increases, and a downward trend appears. Therefore, the width of the first branch electrode and the width of the second branch electrode of the present invention are not infinitely adjustable, and both transmittance and lens mura improvement need to be considered at the same time. For example, the widths of Pitch 1 and Pitch 2 are both 7.6um, wherein the width of the inner branch electrode of Pitch 1 is 2.0um, and the width of Space is 5.6um; the width of the inner branch electrode of Pitch 2 is 2.8um, and the width of Space is 4.8um. Continue to make adjustments. For example, if the width of Pitch 1 and Pitch 2 are both 7.6um, if the width of the branch electrode of pitch1 is adjusted by 0.6um, that is, from 2.4-0.6um=1.8um, the space is 5.8um. ​​If the width of the branch electrode of pitch2 is adjusted by 0.6um, that is, 2.4+0.6um is 3um, the space is 4.6um. At this time, refer to Fig.13 It can be seen that the transmittance will lose more transmittance when adjusting the range of 0.6um than when adjusting the range of 0.2um or 0.4um. Fig.14For example, the present invention adjusts the branch electrode by 0.2um or 0.4um, although it will also reduce some transmittance, compared with the adjustment of 0.6um, the transmittance loss is relatively small, that is, the present invention comprehensively considers the balance between transmittance and improvement of lens mura to make adjustments. Figure 3 The present invention aims to improve the mirror stripes without affecting the L255 transmittance, so the characteristic line width variation range is selected to be ±0.2um, so that the transmittance is basically not affected at the L255 grayscale, and only decreases by 0.03%.

[0084] Optionally, the array substrate according to claim 1, characterized in that the electrode structure of the sub-pixel unit includes a plurality of domains, the plurality of domains include at least one first domain and at least one second domain, the first domain includes at least one first branch electrode along the third direction and at least one second branch electrode along the third direction, the first branch electrodes and the second branch electrodes are alternately arranged; the second domain includes:

[0085] At least one third branch electrode along a fourth direction, and at least one fourth branch electrode along the fourth direction, the third branch electrodes and the fourth branch electrodes are arranged alternately, the first branch electrode and the third branch electrode are electrically connected, and the fourth branch electrode and the second branch electrode are electrically connected.

[0086] refer to Fig. 9 , Fig. 9 A top view of an array substrate provided in an embodiment of the present invention; Fig. 9 As shown, the electrode structure included in the array substrate includes 2 domain areas.

[0087] The branch electrodes in the first domain and the second domain form an obtuse angle.

[0088] By adjusting the angle between the direction of the strip pixel electrode in each display area and the reference direction, and controlling the display of multiple domains through a TFT to produce different liquid crystal deflection angles, the color deviation and the viewing angle can be improved. The color deviation can be improved without reducing the transmittance, and the viewing angle can be improved at the same time, thereby ultimately improving the quality of the flat panel display.

[0089] An embodiment of the present invention further provides a display panel, comprising the above-mentioned display device.

[0090] The display device includes but is not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will appreciate that the structure of the above-mentioned display device does not constitute a limitation on the display device, and the display device may include more or less of the above-mentioned components, or a combination of certain components, or different component arrangements. In an embodiment of the present invention, the display device includes but is not limited to a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.

[0091] The display device may be any product or component with a display function, such as a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device further includes a flexible circuit board, a printed circuit board and a backplane.

[0092] An embodiment of the present invention further provides a method for manufacturing an array substrate, comprising:

[0093] forming a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixel units, wherein the plurality of sub-pixel units are located in an area defined by intersections of the plurality of data lines and the plurality of scan lines;

[0094] forming at least one first branch electrode along the first direction, wherein the width of the first branch electrode along the second direction is a, the spacing between the first branch electrode and an adjacent electrode is c, and the width of the first spacing region is a+c;

[0095] At least one second branch electrode is formed along the first direction, the width of the second branch electrode along the second direction is b, the spacing between the second branch electrode and the adjacent electrode is d, the width of the second spacing area is b+d, a is not equal to b and / or c is not equal to d; the first branch electrodes and the second branch electrodes are arranged alternately.

[0096] Figure 6 A schematic diagram of the arrangement of a first electrode and a second electrode provided in an embodiment of the present invention is shown in FIG. Figure 6 As shown, the width of the first electrode is a, and the spacing between the first electrode and the adjacent electrode is c; the width of the second electrode is b, and the spacing between the second electrode and the adjacent electrode is d.

[0097] Figure 7 Another schematic diagram of the arrangement of the first electrode and the second electrode provided in an embodiment of the present invention is shown in FIG. Figure 7 , wherein every two first electrodes and every two second electrodes are arranged alternately.

[0098] Optionally, when the width a+c of the first spacing region is the same as the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode; or

[0099] When the width a+c of the first spacing region is different from the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is the same as the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode; or

[0100] When the width a+c of the first spacing area is different from the width b+d of the second spacing area, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is the same as the spacing d between the second branch electrode and the adjacent electrode.

[0101] By setting the width of the first spacing region, the width of the first branch electrode, and the width of the second branch electrode, the requirements for the electrode structure of the sub-pixel in different application scenarios can be met.

[0102] Figure 8 A schematic diagram of the width range of the first spacing area and the second spacing area provided in an embodiment of the present invention; Figure 8 , the following examples of the values ​​of b and d relative to a and c are given.

[0103] The first value may be: when the width a+c of the first spacing region is the same as the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode, and b>a,d <c;

[0104] The second value may be: when the width a+c of the first spacing region is the same as the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode, and b<a,d> c;

[0105] The third value may be: when the width a+c of the first spacing area is different from the width b+d of the second spacing area, the width a of the first branch electrode along the second direction is the same as the width b of the second branch electrode along the second direction, the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode, and d <c;

[0106] The fourth value may be: when the width a+c of the first spacing area is different from the width b+d of the second spacing area, the width a of the first branch electrode along the second direction is the same as the width b of the second branch electrode along the second direction, the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode, and d <c;

[0107] The fifth value may be: when the width a+c of the first spacing area is different from the width b+d of the second spacing area, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is the same as the spacing d between the second branch electrode and the adjacent electrode, and b>a;

[0108] The sixth value may be: when the width a+c of the first spacing region is different from the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is the same as the spacing d between the second branch electrode and the adjacent electrode, and b <a。

[0109] Optionally, |ab| is in the range of 0.1-1 micrometers, and / or, |cd| is in the range of 0.1-1 micrometers. By setting |ab| in the range of 0.1-1 micrometers, and / or, |cd| in the range of 0.1-1 micrometers, it is possible to prevent the transmittance from being non-complementary when the characteristic line width changes due to a large difference in the value range, thereby reducing or increasing the transmittance.

[0110] Optionally, the range of a is 1.8-3.0 microns, and the range of b is 1.8-3.0 microns.

[0111] By setting the range of a to 1.8-3.0 microns and the range of b to 1.8-3.0 microns, not only can the transmittance of the area where Pitch 1 and Pitch 2 are located be high, but also the electric field strength of the area where Pitch 1 and Pitch 2 are located be guaranteed.

[0112] Optionally, the range of c is 3.0-7.0 microns, and the range of d is 3.0-7.0 microns.

[0113] By setting the range of c to 3.0-7.0 microns and the range of d to 3.0-7.0 microns, it is possible to ensure that the transmittance of the area where Pitch 1 and Pitch 2 are located is high.

[0114] Optionally, a width a+c of the first spacing region is in a range of 6.6-8.0 microns, and a width b+d of the second spacing region is in a range of 6.6-8.0 microns.

[0115] By setting the width of the first spacing region, the width of the first branch electrode, and the width of the second branch electrode, the requirements for the electrode structure of the sub-pixel in different application scenarios can be met.

[0116] refer to Fig. 9 , Fig. 9 A top view of an array substrate provided by an embodiment of the present invention. Fig.10 for Fig. 9 Schematic diagram of the cross-sectional structure along line A-A'; Fig.11 for Fig. 9 Schematic diagram of the cross-sectional structure along line BB'.

[0117] refer to Figures 9 to 11 The array substrate includes a first gate transparent electrode layer, a gate insulating layer GI, a protective layer PVX, a source and drain electrode layer and a second transparent electrode layer, wherein the electrode structure of the second transparent electrode layer corresponding to a sub-pixel unit includes Pitch 1 and Pitch 2, and the width of Pitch 1 and Pitch 2 are both 7.6um, wherein the width of the inner branch electrode of Pitch 1 is 2.6um, and the width of Space is 5.0um; the width of the inner branch electrode of Pitch 2 is 2.2um, and the width of Space is 5.4um.

[0118] Reference again Figure 3 Compared with the maximum characteristic line width of transmittance W / S=2.4 / 5.2, Pitch 1 has a slightly larger characteristic line width W / S=2.6 / 5.0, and Pitch 2 has a slightly smaller characteristic line width W / S=2.2 / 5.4; when the electrode characteristic line width increases, Pitch 1 will cause the pixel transmittance to decrease, while Pitch 2 will cause the pixel transmittance to increase, and finally compensate each other, so that the overall pixel transmittance fluctuates less.

[0119] The pitch of the array substrate of the present invention is selected to be 7.6um. When making the display panel electrode pattern, since the mask plate design is fixed, for example, the first electrode is selected to be 2.2 and the second electrode is selected to be 2.6, when the process fluctuates, the process fluctuation is positive or negative. For example, if it is a positive fluctuation, 2.2 corresponds to a movement to the right, and the grayscale brightness or transmittance increases. However, at this time, 2.6 corresponds to a movement to the right, and the grayscale brightness or transmittance decreases.

[0120] Fig.10 This is a simulated transmittance diagram of the array substrate of the present invention at the L127 grayscale. The characteristic line width of the array substrate provided by the embodiment of the present invention varies within the range of ±0.2um, and the change in pixel transmittance is much smaller than that of conventional designs, which can effectively improve the mirror group fringes. Fig.10 , Single Pitch is a transmittance diagram when Pitch 1 and Pitch 2 have the same width, and the width a of the first electrode and the width b of the second electrode are also equal, that is, the electrode structure used in the related art. MultiPitch is a structure designed by the present invention, including Figure 8 Examples of various values ​​are shown.

[0121] It should be noted that Multi Pitch does not include the case where Pitch 1 and Pitch 2 have the same width, and the width a of the first electrode and the width b of the second electrode are also equal.

[0122] Fig.11 The transmittance simulation diagram of the array substrate of the present invention at L255 grayscale. At L255 grayscale, as the characteristic line width of the electrode of the present invention continues to increase with the characteristic line width of Pitch1, for example, above 0.4um, the corresponding transmittance no longer increases, and the corresponding Pitch2 adopts a smaller characteristic line width at L255 grayscale, the transmittance continues to decrease. Therefore, at L255 grayscale, this Multi Pitch design will slightly reduce the maximum transmittance and affect the performance of the Panel, and as the difference in characteristic line width increases, the transmittance decreases more significantly, such as Figure 3 The present invention aims to improve the mirror stripes without affecting the L255 transmittance, so the characteristic line width variation range is selected to be ±0.2um, so that the transmittance is basically not affected at the L255 grayscale, and only decreases by 0.03%.

[0123] Optionally, the electrode structure of the sub-pixel unit includes a plurality of domains, the plurality of domains include at least one first domain and at least one second domain, the first domain includes at least one first branch electrode 31 along the third direction D3 and at least one second branch electrode 32 along the third direction, the first branch electrode 31 and the second branch electrode 32 are arranged alternately; the second domain includes:

[0124] At least one third branch electrode 33 along the fourth direction D4, and at least one fourth branch electrode 34 along the fourth direction D4, the third branch electrode and the fourth branch electrode are arranged alternately, the first branch electrode and the third branch electrode are electrically connected, the fourth branch electrode and the second branch electrode are electrically connected, optionally, the electrode width of the third branch electrode is the same as the electrode width of the first branch electrode, the spacing between the third branch electrode and the adjacent electrode is the same as the spacing between the first branch electrode and the adjacent electrode, the electrode width of the fourth branch electrode is the same as the electrode width of the second branch electrode, the spacing between the fourth branch electrode and the adjacent electrode is the same as the spacing between the second branch electrode and the adjacent electrode, of course, the branch electrode widths or pitches corresponding to different domain line areas are different, which is also within the protection scope of this case, for example, the first branch electrode and the third branch electrode have different widths and different pitches. Continue to refer to Fig. 9 Each pixel structure also includes a connection area 50, wherein the branch electrode in the connection area is used to connect the first branch electrode and the third branch electrode, and the second branch electrode and the fourth electrode. When used in a liquid crystal display panel, the liquid crystal in this area rotates chaotically, and black lines will appear in this area. Fig. 9 , in this case the data line can be extended in a straight line or as Fig. 9 The data line includes an extension method that matches the pixel structure, that is, it includes a data line portion extending along the third direction and a data line portion extending along the fourth direction, but the entire data line is still arranged and extended along the first direction.

[0125] refer to Fig. 9 , Fig. 9 A top view of an array substrate provided in an embodiment of the present invention; Fig. 9 As shown, the pixel structure included in the array substrate includes two domains, and the branch electrodes in the first domain and the second domain form an obtuse angle.

[0126] It should be noted that the branch electrodes in the first domain area and the second domain area may also be at an acute angle, which is not limited here.

[0127] By adjusting the angle between the direction of the strip pixel electrode in each display area and the reference direction, and controlling the display of multiple domains through a TFT to produce different liquid crystal deflection angles, the color deviation and the viewing angle can be improved. The color deviation can be improved without reducing the transmittance, and the viewing angle can be improved at the same time, thereby ultimately improving the quality of the flat panel display.

[0128] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0129] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiments.

[0130] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0131] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0132] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0133] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, comprising a plurality of data lines, a plurality of scan lines and a plurality of sub-pixel units, wherein the plurality of sub-pixel units are located in an area defined by the intersection of the plurality of data lines and the plurality of scan lines, characterized in that: The electrode structure of the sub-pixel unit includes: At least one first branch electrode along the first direction, the width of the first branch electrode along the second direction is a, the spacing between the first branch electrode and an adjacent electrode is c, and the width of the first spacing area is a+c; At least one second branch electrode along the first direction, the width of the second branch electrode along the second direction is b, the spacing between the second branch electrode and the adjacent electrode is d, the width of the second spacing area is b+d, a is not equal to b and / or c is not equal to d; The first electrodes and the second electrodes are arranged alternately; Wherein, |ab| is in the range of 0.1-1 micrometer, and / or, |cd| is in the range of 0.1-1 micrometer, the range of a is 1.8-3.0 micrometer, the range of b is 1.8-3.0 micrometer, the range of c is 3.0-7.0 micrometer, the range of d is 3.0-7.0 micrometer, the width a+c of the first spacing area is in the range of 6.6-8.0 micrometer, and the width b+d of the second spacing area is in the range of 6.6-8.0 micrometer; When the width of the first branch electrode and the width of the second branch electrode increase or decrease due to fluctuation in exposure, the transmittance of the first spacing region and the second spacing region change in the opposite direction.

2. The array substrate according to claim 1, characterized in that: When the width a+c of the first spacing region is the same as the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode; or When the width a+c of the first spacing region is different from the width b+d of the second spacing region, the width a of the first branch electrode along the second direction is the same as the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is different from the spacing d between the second branch electrode and the adjacent electrode; or When the width a+c of the first spacing area is different from the width b+d of the second spacing area, the width a of the first branch electrode along the second direction is different from the width b of the second branch electrode along the second direction, and the spacing c between the first branch electrode and the adjacent electrode is the same as the spacing d between the second branch electrode and the adjacent electrode.

3. The array substrate according to claim 2, characterized in that: When the width a+c of the first spacing region is the same as the width b+d of the second spacing region, if the width of the first branch electrode along the second direction and the width of the second branch electrode along the second direction increase or decrease at the same time, the transmittance changes of the first spacing region and the second spacing region are opposite.

4. The array substrate according to claim 1, characterized in that: The electrode structure of the sub-pixel unit includes a plurality of domains, the plurality of domains include at least one first domain and at least one second domain, the first domain includes at least one first branch electrode along the third direction and at least one second branch electrode along the third direction, the first branch electrode and the second branch electrode are arranged alternately; the second domain includes: At least one third branch electrode along a fourth direction, and at least one fourth branch electrode along the fourth direction, the third branch electrodes and the fourth branch electrodes are arranged alternately, the first branch electrode and the third branch electrode are electrically connected, and the fourth branch electrode and the second branch electrode are electrically connected.

5. The array substrate according to claim 4, characterized in that: The third direction and the fourth direction form an acute angle or an obtuse angle.

6. The array substrate according to claim 1, characterized in that: The electrode structure of the sub-pixel unit is a sub-pixel electrode or a common electrode.

7. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 6.

8. A display device, characterized in that: Comprising the display panel as claimed in claim 7.

9. A method for manufacturing an array substrate, characterized in that: Used to manufacture the array substrate according to any one of claims 1 to 6, comprising: forming a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixel units, wherein the plurality of sub-pixel units are located in an area defined by intersections of the plurality of data lines and the plurality of scan lines; forming at least one first branch electrode along the first direction, wherein the width of the first branch electrode along the second direction is a, the spacing between the first branch electrode and an adjacent electrode is c, and the width of the first spacing region is a+c; At least one second branch electrode is formed along the first direction, the width of the second branch electrode along the second direction is b, the spacing between the second branch electrode and the adjacent electrode is d, the width of the second spacing area is b+d, a is not equal to b and / or c is not equal to d; the first branch electrodes and the second branch electrodes are arranged alternately.

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