An ESD protection circuit applied to a high-frequency circuit

Abstract

The application discloses an ESD protection circuit applied to a high-frequency circuit and belonging to the field of electronic circuits, comprising a positive static discharge path, a negative static discharge path and a harmonic bidirectional discharge path; the positive static discharge path is used for forming a positive path for discharging a power supply end when positive static leakage occurs in the circuit; the negative static discharge path is used for forming a negative path for discharging a ground end when negative static leakage occurs in the circuit; and the harmonic bidirectional discharge path is used for forming a consumption path for the ground when positive jump or negative jump high-frequency harmonic leakage occurs in the circuit. The application can solve the ESD problem of the high-frequency circuit application occasion and filter the interference of high-frequency signals.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to an ESD protection circuit for high-frequency circuits. Background Technology

[0002] ESD (electrostatic discharge) is a phenomenon that cannot be ignored in electronic circuits. It is characterized by high voltage, high speed, random occurrence, great destructiveness, and hidden damage location, and can generate a large current of tens of amperes in a very short time. If the current directly passes through the electronic components inside the chip, it will cause serious consequences, leading to degraded device performance or even loss of function. Circuits carrying high-frequency signals are often susceptible to interference from the external environment. This interference includes power supply noise and radio frequency harmonics in the environment. Improper handling can cause signal distortion and malfunction of the circuit.

[0003] To address the aforementioned issues, there is an urgent need for an ESD protection circuit that can be applied to high-frequency circuits. Summary of the Invention

[0004] The purpose of this invention is to provide an ESD protection circuit for high-frequency circuits to solve the problems in the prior art.

[0005] To solve the above-mentioned technical problems, the present invention provides an ESD protection circuit for high-frequency circuits, including a positive electrostatic discharge path, a negative electrostatic discharge path, and a harmonic bidirectional discharge path.

[0006] The positive electrostatic discharge path is used to form a positive path for discharge to the power supply terminal when positive electrostatic leakage occurs in the circuit.

[0007] The negative electrostatic discharge path is used to form a negative path for discharge to ground when negative electrostatic leakage occurs in the circuit.

[0008] The harmonic bidirectional discharge path is used to form a dissipation path to ground when the circuit experiences high-frequency harmonic leakage due to positive or negative transitions.

[0009] In one embodiment, the ESD protection circuit applied to the high-frequency circuit further includes a second discharge path based on the harmonic bidirectional discharge path, thereby enhancing the discharge capability for high-frequency harmonic leakage current.

[0010] In one embodiment, the forward electrostatic discharge path consists of four diodes arranged closely on a layout, with their positive terminals all connected to the main signal path and their negative terminals all connected to the internal reference ground.

[0011] In one embodiment, the negative electrostatic discharge path consists of four large-sized diodes arranged closely on a layout, with their negative terminals all connected to the main signal path and their positive terminals all connected to the internal reference ground.

[0012] In one embodiment, the harmonic bidirectional discharge path includes NMOS transistors M0 and M1 and resistor R0. The gate terminal of the NMOS transistor M0, which is connected to the equivalent large capacitor, is connected to the positive terminals of the four diodes in the forward electrostatic discharge path. The source and drain terminals are connected to the first terminal of resistor R0, and the second terminal of resistor R0 is connected to the internal reference ground.

[0013] The gate of NMOS transistor M1 is connected to the first terminal of resistor R0, the source is connected to the second terminal of resistor R0, and the drain is connected to the gate of NMOS transistor M0.

[0014] In one embodiment, the second discharge path includes NMOS transistors M2 and M3; the gate terminal of NMOS transistor M3 is connected to the first terminal of resistor R0, the source terminal is connected to the second terminal of resistor R0, the drain terminal is connected to the source terminal of NMOS transistor M2, the gate terminal of NMOS transistor M2 is connected to an external control signal CTRL, and the drain terminal is connected to the gate terminal of NMOS transistor M0.

[0015] In one embodiment, the ESD protection circuit applied to the high-frequency circuit further includes a protection resistor R1, a main path protection diode D4, and an NMOS transistor M4 with an equivalent small capacitor connection; one end of the protection resistor R1 is connected to the drain terminal of the NMOS transistor M2, and the other end is connected to both the positive terminal of the main path protection diode D4 and the drain terminal of the NMOS transistor M4; the gate terminal and source terminal of the NMOS transistor M4 are both connected to the second end of the resistor R0; the negative terminal of the main path protection diode D4 is connected to the negative terminals of the four diodes in the negative electrostatic discharge path.

[0016] In one embodiment, the positive electrostatic leakage includes positive electrostatic leakage from the pad to the wafer circuit to be protected; the negative electrostatic leakage includes negative electrostatic leakage from the pad to the wafer circuit to be protected; and the high-frequency harmonic leakage includes signal transmission harmonics, environmental interference noise, or power supply crosstalk harmonics from the pad to the wafer circuit to be protected.

[0017] In one embodiment, the power supply voltage range for the ESD protection circuit applied to high-frequency circuits is 2.7V to 5.5V.

[0018] The ESD protection circuit for high-frequency circuits provided by this invention includes a positive electrostatic discharge path, a negative electrostatic discharge path, and a harmonic bidirectional discharge path. The positive electrostatic discharge path forms a positive path to the power supply terminal when positive electrostatic leakage occurs in the circuit. The negative electrostatic discharge path forms a negative path to ground when negative electrostatic leakage occurs in the circuit. The harmonic bidirectional discharge path forms a dissipation path to ground when high-frequency harmonic leakage occurs due to positive or negative transitions. This invention can solve ESD problems in high-frequency circuit applications and filter out interference from high-frequency signals. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of an ESD protection circuit structure for high-frequency circuits provided by the present invention. Detailed Implementation

[0020] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of an ESD protection circuit for high-frequency circuits proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0021] This invention provides an ESD protection circuit for high-frequency circuits, the structure of which is as follows: Figure 1 As shown, the circuit includes a positive electrostatic discharge path, a negative electrostatic discharge path, and a harmonic bidirectional discharge path. The positive electrostatic discharge path is used to form a positive path for discharging to the power supply terminal when positive electrostatic leakage occurs in the circuit; the negative electrostatic discharge path is used to form a negative path for discharging to the ground terminal when negative electrostatic leakage occurs in the circuit; the harmonic bidirectional discharge path is used to form a dissipation path to ground when high-frequency harmonic leakage occurs due to positive or negative transitions in the circuit. The ESD protection circuit applied to high-frequency circuits also includes a second discharge path based on the harmonic bidirectional discharge path, enhancing the discharge capability for high-frequency harmonic leakage.

[0022] The positive electrostatic discharge (ESD) includes positive ESD from the pads to the wafer circuit to be protected; the negative ESD includes negative ESD from the pads to the wafer circuit to be protected; and the high-frequency harmonic discharge includes signal transmission harmonics, environmental interference noise, or power supply crosstalk harmonics from the pads to the wafer circuit to be protected. The ESD protection circuit is used in applications with a power supply voltage range of 2.7V to 5.5V.

[0023] Please continue reading. Figure 1The positive electrostatic discharge path consists of four diodes closely arranged on the circuit board (i.e., diodes D0, D1, D2, and D3). The positive terminals of diodes D0, D1, D2, and D3 are all connected to the main signal path, and the negative terminals are all connected to the internal reference ground, which can guide excessive positive electrostatic current to the designated power supply branch. The negative electrostatic discharge path consists of four large-size diodes closely arranged on the circuit board (i.e., diodes D5, D6, D7, and D8). The negative terminals of diodes D5, D6, D7, and D8 are connected to the main signal path, and the positive terminals are connected to the internal reference ground, which can guide excessive negative electrostatic current to the designated ground branch. In the harmonic bidirectional discharge path, the equivalent large current... In the capacitive NMOS transistor M0, a resistor R0 is connected to the internal reference ground and to the gate of another NMOS transistor M1. The resistor R0 is 50 ohms. The capacitor absorbs excessive harmonic pulses and then dissipates them through the ground loop. Excessive pulses also cause NMOS transistor M1 to conduct slightly, effectively acting as a resistor and further dissipating the signal. In the second discharge path based on the aforementioned bidirectional harmonic discharge path, the equivalent large capacitor NMOS transistor M0 is connected to the gate of an NMOS transistor M3. The drain of NMOS transistor M3 is connected to the source of NMOS transistor M2. The gate of NMOS transistor M2 is connected to the external control signal CTRL, and the drain of NMOS transistor M2 is connected to the main signal path. Specifically, for example, when the power supply in the circuit is increased to 5.5V, the external control signal CTRL is turned on, providing an additional discharge path, which helps filter out high-frequency signal interference.

[0024] The ESD protection circuit applied to high-frequency circuits also includes a protection resistor R1, a main path protection diode D4, and an NMOS transistor M4 with an equivalent small capacitor connection. The protection resistor R1 serves as a current-limiting resistor in the circuit and is located between the input terminal and the main path protection diode D4. The main path protection diode D4 is located between the protection resistor R1 and the internal circuit to be protected, used to prevent signal breakdown in the circuit. The NMOS transistor M4 with an equivalent small capacitor connection is located between the protection resistor R1 and the internal reference ground, used for low-frequency filtering. The resistor R1 has a strength of 62 ohms.

[0025] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An ESD protection circuit for high-frequency circuits, characterized in that, This includes positive electrostatic discharge paths, negative electrostatic discharge paths, and harmonic bidirectional discharge paths. The positive electrostatic discharge path is used to form a positive path for discharge to the power supply terminal when positive electrostatic leakage occurs in the circuit. The negative electrostatic discharge path is used to form a negative path for discharge to ground when negative electrostatic leakage occurs in the circuit. The harmonic bidirectional discharge path is used to form a dissipation path to ground when the circuit experiences high-frequency harmonic leakage due to positive or negative transitions. The ESD protection circuit applied to high-frequency circuits also includes a second discharge path based on the harmonic bidirectional discharge path, which enhances the discharge capability for high-frequency harmonic leakage current. The harmonic bidirectional discharge path includes NMOS transistors M0 and M1 and resistor R0. The gate terminal of the NMOS transistor M0, which is connected in an equivalent large capacitor configuration, is connected to the positive terminal of the four diodes in the forward electrostatic discharge path. The source and drain terminals are connected to the first terminal of resistor R0, and the second terminal of resistor R0 is connected to the internal reference ground. The negative terminals of the four diodes in the forward electrostatic discharge path are connected to the power supply terminal. The gate terminal of NMOS transistor M1 is connected to the first terminal of resistor R0, the source terminal is connected to the second terminal of resistor R0, and the drain terminal is connected to the gate terminal of NMOS transistor M0. The second discharge path includes NMOS transistors M2 and M3; the gate terminal of NMOS transistor M3 is connected to the first terminal of resistor R0, the source terminal is connected to the second terminal of resistor R0, the drain terminal is connected to the source terminal of NMOS transistor M2, the gate terminal of NMOS transistor M2 is connected to the external control signal CTRL, and the drain terminal is connected to the gate terminal of NMOS transistor M0. The ESD protection circuit applied to high-frequency circuits further includes a protection resistor R1, a main path protection diode D4, and an NMOS transistor M4 with an equivalent small capacitor connection. One end of the protection resistor R1 is connected to the drain of the NMOS transistor M2, and the other end is connected to both the anode of the main path protection diode D4 and the drain of the NMOS transistor M4. The gate and source terminals of the NMOS transistor M4 are both connected to the second terminal of the resistor R0. The cathode of the main path protection diode D4 is connected to the cathodes of the four diodes in the negative electrostatic discharge path, and the anodes of the four diodes in the negative electrostatic discharge path are all connected to the internal reference ground.

2. The ESD protection circuit for high-frequency circuits as described in claim 1, characterized in that, The forward electrostatic discharge path consists of four diodes closely arranged on the layout.

3. The ESD protection circuit for high-frequency circuits as described in claim 1, characterized in that, The negative electrostatic discharge path consists of four large-sized diodes closely arranged on the layout.

4. The ESD protection circuit for high-frequency circuits as described in claim 1, characterized in that, The positive electrostatic leakage includes positive electrostatic leakage from the pad to the wafer circuit to be protected; the negative electrostatic leakage includes negative electrostatic leakage from the pad to the wafer circuit to be protected; the high-frequency harmonic leakage includes signal transmission harmonics, environmental interference noise, or power supply crosstalk harmonics from the pad to the wafer circuit to be protected.

5. The ESD protection circuit for high-frequency circuits as described in claim 1, characterized in that, The power supply voltage range for the ESD protection circuit used in high-frequency circuits is 2.7V~5.5V.

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