Method and apparatus for encoding and decoding channels in a communication or broadcasting system

Abstract

The present disclosure relates to a 5G or quasi-5G communication system for supporting a higher data transmission rate than a 4G communication system such as LTE. The present invention relates to a method for encoding and decoding a channel in a communication or broadcasting system, comprising the following steps: determining an input bit size (CBS); determining a code rate (R); determining a block size (Z); comparing the determined CBS and code rate with a predetermined reference value; determining an LDPC sequence for performing LDPC encoding based on the comparison result; and performing LDPC encoding and decoding based on the LDPC sequence and the block size. In addition, the present invention includes the following steps: determining a code rate (R) indicated by a modulation and coding scheme (MCS) index; determining a transport block size; and determining a first base matrix or a second base matrix as a base matrix based on the transport block size and the code rate.

Description

Technical Field

[0001] The present disclosure relates to a method and apparatus for encoding / decoding a channel in a communication or broadcasting system. Background Art

[0002] In order to meet the increased demand for wireless data services since the deployment of the 4G communication system, efforts have been made to develop an improved 5G or quasi-5G communication system. Therefore, the 5G or quasi-5G communication system is also called a 'super 4G network' or a 'post-LTE system'.

[0003] 5G communication systems are considered to be implemented in higher frequency (millimeter wave) bands, such as the 60 GHz band, in order to achieve higher data rates. In order to reduce the propagation loss of radio waves and increase the transmission distance, beamforming, massive multiple-input multiple-output (MIMO), full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, and large antenna technologies are discussed in 5G communication systems.

[0004] In addition, in 5G communication systems, development of system network improvements based on advanced small cells, cloud radio access networks (RAN), ultra-dense networks, device-to-device (D2D) communication, wireless backhaul, mobile networks, cooperative communications, coordinated multi-point (CoMP), receiving-end interference cancellation, etc. is underway.

[0005] In 5G systems, hybrid FSK with QAM modulation (FQAM) and sliding window superposition coding (SWSC) have been developed as advanced coded modulation (ACM), and filter bank multi-carrier (FBMC), non-orthogonal multiple access (NOMA), and sparse code multiple access (SCMA) as advanced access technologies.

[0006] In a communication or broadcasting system, various channel noises, fading phenomena, and inter-symbol interference (ISI) may significantly degrade the performance of a link. Therefore, in order to implement high-speed digital communication or broadcasting systems that require large amounts of data processing and high reliability, such as next-generation mobile communications, digital broadcasting, and portable Internet, it is necessary to develop a technology for overcoming noise, fading, and ISI. As part of research for overcoming noise, etc., error correction codes have recently been actively studied as a method for improving the reliability of communication by effectively restoring distortion of information. Summary of the invention

[0007] Technical issues

[0008] The present disclosure provides a method and apparatus for encoding / decoding LDPC capable of supporting various input lengths and code rates.

[0009] The present disclosure provides a method and apparatus for encoding / decoding an LDPC code suitable for a case having a short information word length of about 100 bits and having a fixed code rate.

[0010] Solution to the problem

[0011] The present disclosure proposes a method for designing LDPC codes capable of supporting various lengths and code rates by simultaneously considering a boosting method and trapping set characteristics.

[0012] The present disclosure proposes a method for designing a dedicated LDPC code, which is suitable for a situation with a small number of information bits and a fixed code rate.

[0013] According to aspects of the present disclosure, a method for encoding a channel by a transmitting device includes: determining a code rate (R) indicated by a modulation and coding scheme (MCS) index; determining a transport block size; and determining one of a first base matrix or a second base matrix as a base matrix based on the transport block size and the code rate.

[0014] According to another aspect of the present disclosure, a method for decoding a channel by a receiving device includes: determining a code rate (R) indicated by a modulation and coding scheme (MCS) index; determining a transport block size; and determining one of a first base matrix or a second base matrix as a base matrix based on the transport block size and the code rate.

[0015] According to another aspect of the present disclosure, an apparatus for encoding a channel in a communication or broadcasting system includes: a transmitter / receiver; and a controller configured to determine a code rate (R) indicated by a modulation and coding scheme (MCS) index, determine a transport block size, and determine one of a first base matrix or a second base matrix as a base matrix based on the transport block size and the code rate.

[0016] According to another aspect of the present disclosure, an apparatus for decoding a channel in a communication or broadcasting system includes: a transmitter / receiver; and a controller configured to determine a code rate (R) indicated by a modulation and coding scheme (MCS) index, determine a transport block size, and determine one of a first base matrix or a second base matrix as a base matrix based on the transport block size and the code rate.

[0017] Advantageous Effects of the Invention

[0018] The present disclosure may support LDPC codes with variable length and variable rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram showing the structure of an LDPC codeword of the system.

[0020] Figure 2is a schematic diagram showing a graphical method of LDPC codes.

[0021] Figure 3a and Figure 3b is an exemplary diagram showing the cyclic characteristics of a QC-LDPC code.

[0022] Figure 4 is a block diagram showing a configuration of a transmitting device according to an embodiment of the present disclosure.

[0023] Figure 5 is a block diagram showing a configuration of a receiving device according to an embodiment of the present disclosure.

[0024] Figure 6a and Figure 6b is a message structure diagram illustrating a message passing operation between specific check nodes and variable nodes for LDPC encoding.

[0025] Figure 7 is a block diagram showing a detailed configuration of an LDPC encoder according to an embodiment of the present disclosure.

[0026] Figure 8 is a block diagram showing the configuration of a decoding device according to an embodiment of the present disclosure.

[0027] Fig. 9 is a schematic diagram showing the structure of an LDPC decoder according to another embodiment of the present disclosure.

[0028] Fig.10 is a schematic diagram showing the structure of a transport block according to another embodiment of the present disclosure.

[0029] Fig.11 is a schematic diagram illustrating an exemplary LDPC encoding process according to an embodiment of the present disclosure.

[0030] Fig.12 is a schematic diagram illustrating an exemplary LDPC decoding process according to an embodiment of the present disclosure.

[0031] Fig.13 is a schematic diagram illustrating another exemplary LDPC encoding process according to an embodiment of the present disclosure.

[0032] Fig.14 is a schematic diagram illustrating another exemplary LDPC decoding process according to an embodiment of the present disclosure.

[0033] Fig.15 is a schematic diagram illustrating another exemplary LDPC encoding process according to an embodiment of the present disclosure.

[0034] Fig.16 is a schematic diagram illustrating another exemplary LDPC decoding process according to an embodiment of the present disclosure.

[0035] Fig.17 is a schematic diagram illustrating another exemplary LDPC encoding process according to an embodiment of the present disclosure.

[0036] Fig.18 is a schematic diagram illustrating another exemplary LDPC decoding process according to an embodiment of the present disclosure.

[0037] Fig.19a , Fig.19b , Fig.19c , Fig.19d , Fig.19e , Fig.19f , Figure 19g , Figure 19h , Fig.19i and Fig.19j is a schematic diagram showing an exemplary LDPC code base matrix according to an embodiment of the present disclosure.

[0038] Fig.20a , Fig.20b , Fig.20c , Fig.20d , Fig.20e , Fig.20f , Figure 20g , Figure 20h , Fig.20i and Fig.20j is a schematic diagram showing an exemplary LDPC code base matrix according to an embodiment of the present disclosure.

[0039] Fig.21 is a diagram illustrating an exemplary method for determining a base matrix according to a CBS and a code rate by a transmitter.

[0040] Fig. 22 is a schematic diagram showing an exemplary range of allocating a base matrix according to CBS and coding rate.

[0041] Fig.23a and Figure 23b is a schematic diagram of an exemplary method for determining a base matrix according to a CBS and a code rate by a transmitter and a receiver, respectively.

[0042] Fig.24a and Figure 24b is a schematic diagram of other exemplary methods for determining a base matrix according to CBS and a code rate by a transmitter and a receiver, respectively.

[0043] Fig.25 FIG. 4 is a schematic diagram showing another exemplary range of allocating a base matrix according to CBS and coding rate.

[0044] Fig.26a and Figure 26bis a schematic diagram of other exemplary methods for determining a base matrix according to CBS and a code rate by a transmitter and a receiver, respectively.

[0045] Fig. 27 FIG. 4 is a schematic diagram showing another exemplary range of allocating a base matrix according to CBS and coding rate.

[0046] Fig.28a and Fig.28b is a diagram illustrating other exemplary methods for determining a base matrix according to a TBS index and the number of resource blocks by a transmitter and a receiver, respectively.

[0047] Fig.29 is a diagram showing an example of appending CRC bits to a given transport block.

[0048] Fig.30 is an exemplary diagram of changing the number of CRC bits to be appended to a transport block according to an LDPC base matrix to be applied to encoding according to an embodiment.

[0049] Fig.31 is an exemplary diagram of changing the number of CRC bits to be appended to a transport block according to an LDPC base matrix to be applied to encoding according to another embodiment.

[0050] Fig.32 is an exemplary diagram of determining the number of CRC bits appended to a transport block according to an LDPC base matrix and thus performing a CRC check by a receiver according to an embodiment.

[0051] Fig.33 It is shown based on Figures 19a to 19j An exemplary diagram of the LDPC coding performance of the base matrix.

[0052] Fig.34 It is shown based on Figures 20a to 20j An exemplary diagram of the LDPC coding performance of the base matrix.

[0053] Fig.35 is another exemplary diagram of changing the number of CRC bits to be appended to a transport block according to an LDPC base matrix to be applied to encoding according to an embodiment.

[0054] Fig.36 is another exemplary diagram of determining the number of CRC bits appended to a transport block according to an LDPC base matrix and thus performing a CRC check by a receiver according to an embodiment.

[0055] Fig.37 is an exemplary schematic diagram of a method for segmenting a transport block according to an embodiment.

[0056] Fig.38is an exemplary diagram of a method for determining the number of transport block CRC and code block CRC bits and whether to perform segmentation according to a TBS according to an embodiment.

[0057] Fig.39 is another exemplary diagram of a method for determining the number of transport block CRC and code block CRC bits and whether to perform segmentation according to a TBS according to an embodiment.

[0058] Fig.40 2 is an exemplary diagram of determining the number of transport block CRC and code block CRC bits and whether to perform segmentation according to the TBS according to an embodiment and thus performing CRC check by the receiver.

[0059] Fig.41 FIG. 4 is a schematic diagram showing another exemplary range of allocating a base matrix according to TBS and coding rate.

[0060] Fig.42 is another exemplary diagram regarding a method for determining a base matrix according to a TBS and a code rate by a transmitter.

[0061] Fig.43 is another exemplary diagram regarding a method for determining a base matrix according to a TBS and a code rate by a receiver.

[0062] Fig.44 is another exemplary diagram regarding a method for determining a base matrix according to a TBS and a code rate by a transmitter.

[0063] Fig.45 is another exemplary diagram regarding a method for determining a base matrix according to a TBS and a code rate by a receiver.

[0064] Fig.46 FIG. 4 is a schematic diagram showing another exemplary range of allocating a base matrix according to TBS and coding rate.

[0065] Fig.47 is another exemplary diagram regarding a method for determining a base matrix according to a TBS and a code rate by a transmitter.

[0066] Fig.48 is another exemplary diagram regarding a method for determining a base matrix according to a TBS and a code rate by a receiver. DETAILED DESCRIPTION

[0067] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, in the following description of the present disclosure, when the detailed description of known functions and configurations incorporated herein makes the subject matter of the present disclosure quite unclear, the detailed description may be omitted. The terms to be described below are terms defined in consideration of the functions in the present disclosure, and may differ according to the user, the user's intention or habit. Therefore, the definition of the term should be determined based on the content throughout the entire specification.

[0068] The main gist of the present disclosure is applicable to other systems with similar technical backgrounds through minor modifications without substantially departing from the scope of the present disclosure, and this is possible based on the determination of those skilled in the art to which the present disclosure belongs.

[0069] By reference to the embodiments described in detail below in conjunction with the accompanying drawings, the advantages and characteristics of the present disclosure and their implementation will be apparent. However, the present disclosure is not limited to the embodiments set forth below, but can be implemented in various different forms. The following embodiments are provided only to fully disclose the present disclosure and inform those skilled in the art of the scope of the present disclosure, and the present disclosure is limited only by the scope of the attached claims. Throughout the entire specification, the same or similar reference numerals represent the same or similar elements.

[0070] Low-density parity check (hereinafter referred to as LDPC) codes were originally proposed by Gallager in the 1960s, but have long been forgotten due to the complexity that was difficult to implement at the technical level at the time. However, Berrou, Glavieux, and Thitimajshima proposed turbo codes in 1993, which showed performance close to Shannon's channel capacity. Therefore, extensive analysis has been conducted on the performance and characteristics of turbo codes, and channel coding based on iterative decoding and graphs has been widely studied. As a result, LDPC codes were re-studied in the late 1990s, and it was found that if iterative decoding based on the sum-product algorithm is applied to decode the Tanner graph corresponding to the LDPC code, the LDPC code also has performance close to Shannon's channel capacity.

[0071] LDPC codes are usually defined as parity check matrices and can be represented using a bipartite graph often called a Tanner graph.

[0072] Figure 1 is a schematic diagram showing the structure of a system LDPC codeword.

[0073] according to Figure 1 , for LDPC codes, the receiver includes K ldpc bit or K ldpc The information word 102 of N symbols is taken as input and LDPC encoded so as to generateldpc bit or N ldpc For the convenience of description, it will be assumed that the received codeword includes K ldpc bit information word 102 as input, and generates a ldpc The code word of bits is 100. That is, if the ldpc Information word of input bits 102 performs LDPC encoding, then generates a codeword 100. That is, the information word and the code word are bit strings including a plurality of bits, and the information word bit and the code word bit refer to the bits constituting the information word and the code word, respectively. Generally, if the code word includes bits such as The information word is called the system code. The parity bit may be 104, and the number of the parity bits may be N. parity Can be N parity = N ldpc -K ldpc .

[0074] The LDPC code is a linear block code and includes a process of determining a codeword that satisfies the condition given in the following equation 1:

[0075] [Formula 1]

[0076]

[0077] in .

[0078] In Equation 1, H refers to the parity check matrix, C refers to the codeword, and c i is the i-th bit of the codeword, and N ldpc refers to the length of the LDPC codeword. In addition, h i refers to the i-th column of the parity check matrix H.

[0079] The parity check matrix H consists of N ldpc Column, N ldpc Equal to the number of bits of the LDPC codeword. Equation 1 represents the i-th column h of the parity check matrix i and the i-th codeword position c i The sum of the products is "0", and thus indicates that the i-th column h i and the i-th codeword position c i Related.

[0080] Reference Figure 2 A method for representing LDPC codes by graphing is described.

[0081] Figure 2 is a parity check matrix H showing an LDPC code including four rows and eight columns. 1and its corresponding Tanner diagram. Figure 2 , since the parity check matrix H 1 has eight columns, thus generating a codeword of length 8. 1 The generated code is an LDPC code, and each column corresponds to eight bits after encoding.

[0082] refer to Figure 2 , based on the parity check matrix H 1 The Tanner graph of the LDPC code for encoding and decoding includes eight variable nodes, namely x 1 202, x 2 204, x 3 206, x 4 208, x 5 210, x 6 212, x 7 214 and x 8 216, and four check nodes 218, 220, 222, and 224. Thus, the parity check matrix H of the LDPC code 1 The i-th column and j-th row correspond to the variable node x i And the jth check node. In addition, in the parity check matrix H of the LDPC code 1 The value 1 (i.e., non-zero value) at the intersection between the jth column and the jth row of indicates that there is a connection variable node x on the Tanner graph. i and the edge of the j-th check node, such as Figure 2 shown.

[0083] In the Tanner graph of the LDPC code, the degree of the variable node and the check node refers to the number of edges connected to each node and is equal to the number of non-zero entries in the column or row corresponding to the corresponding node in the parity check matrix of the LDPC code. For example, Figure 2 Variable node x 1 202, x 2 204, x 3 206, x 4 208, x 5 210, x 6 212, x 7 214 and x 8 The degrees of each of check nodes 216 are 4, 3, 3, 3, 2, 2, 2, 2, and the degrees of each of check nodes 218, 220, 222, and 224 are 6, 5, 5, 5, respectively. Figure 2 The variable nodes in Figure 2 The parity check matrix H in 1The number of non-zero entries in each column is equal to the above mentioned series of degrees 4, 3, 3, 3, 2, 2, 2, 2, and corresponds to Figure 2 The check nodes in Figure 2 The parity check matrix H in 1 The number of non-zero entries in the various rows of is the series of degrees 6, 5, 5, 5 mentioned above.

[0084] Can be done through Figure 2 The LDPC code is iteratively decoded using an iterative decoding algorithm based on the sum-product algorithm on the bipartite graph enumerated in . As used herein, the sum-product algorithm is a message passing algorithm, and the message passing algorithm refers to an algorithm configured to exchange messages through edges on the bipartite graph to calculate and update output messages from messages input to variable nodes or check nodes.

[0085] In this way, the value of the i-th coded bit can be determined based on the message of the i-th variable node. Regarding the value of the i-th coded bit, hard decision or soft decision is possible. Therefore, the i-th bit (i.e., c i ) corresponds to the performance of the i-th variable node on the Tanner graph, and this can be determined based on the position and number of 1s in the i-th column of the parity check matrix. In other words, the N ldpc The performance of each codeword bit can depend on the position and number of 1s in the parity check matrix, and this means that the performance of the LDPC code is greatly affected by the parity check matrix. Therefore, a method for designing a good parity check matrix is ​​needed to design an LDPC code with excellent performance.

[0086] As a parity check matrix used in a communication or broadcasting system, a quasi-cyclic LDPC code (or QC-LDPC code; hereinafter referred to as a QC-LDPC code) is most commonly used, which generally uses a quasi-cyclic type parity check matrix for ease of implantation.

[0087] The QC-LDPC code is characterized in that the parity check matrix it has includes a zero matrix or a cyclic permutation matrix in the form of a small square matrix. As used herein, a permutation matrix refers to a square matrix configured so that each entry is 0 or 1 and each row or column includes only one 1. In addition, a cyclic permutation matrix refers to a matrix obtained by cyclically shifting the entries of the identity matrix to the right.

[0088] The QC-LDPC code will now be described in detail.

[0089] First, the circulant permutation matrix of size L×L is defined in Equation 2 .here, refers to the entry in the i-th row and j-th column of the matrix P (where 0 ≤ i, j < L).

[0090] [Formula 2]

[0091]

[0092] It can be understood that, regarding the permutation matrix P defined above, (0≤i<L) is obtained by cyclically shifting the entries of the L×L identity matrix to the right. i The circulant permutation matrix is ​​obtained.

[0093] The parity check matrix H of the simplest QC-LDPC code can be defined as follows:

[0094] [Formula 3]

[0095]

[0096] If Defined as a zero matrix of size L×L, each index in the circulant permutation matrix or zero matrix in the above formula 3 is has a value selected from {-1, 0, 1, 2, ..., L-1}. In addition, it can be understood that the parity check matrix H of the above formula 3 has n Column blocks and m row blocks, and therefore have a size of mL×nL.

[0097] Obviously, if the parity check matrix of the above formula 3 has a full rank, the size of the information word bit of the QC-LDPC code corresponding to the parity check matrix is ​​(nm)L. For the convenience of description, the size corresponding to the information word bit is ( n - m ) column blocks are called information word column blocks, and the columns corresponding to the remaining parity bits are m The column blocks are called parity column blocks (for the convenience of description, the value of L is also called block size).

[0098] Generally, a binary matrix of size m×n obtained by replacing each cyclic permutation matrix and 0 matrix in the parity check matrix of the above formula 3 with 1 and 0 respectively is called a mother matrix or base matrix M(H) of the parity check matrix H, and an integer matrix of size m×n obtained by selecting the index of each cyclic permutation matrix or 0 matrix as defined in the following formula 4 is called an exponential matrix E(H) of the parity check matrix H.

[0099] [Formula 4]

[0100]

[0101] Therefore, one integer included in the exponential matrix corresponds to one circulant permutation matrix in the parity check matrix, and for the convenience of description, the exponential matrix can also be expressed as a sequence including integers (the sequence can also be called an LDPC sequence or an LDPC code sequence to distinguish it from other sequences). In general, a parity check matrix can be expressed not only as an exponential matrix, but also as a sequence having the same algebraic characteristics. Although in the present disclosure the parity check matrix is ​​expressed as, for example, an exponential matrix or sequence indicating the position of 1 in the parity check matrix, there are various methods for describing the sequence so that the position of 1 or 0 included in the parity check matrix can be identified. Therefore, the method of expression is not limited to those described herein, and can be expressed as various sequences having the same algebraic effect.

[0102] In addition, although it is possible to perform LDPC encoding and decoding by directly generating a parity check matrix by a transmitting / receiving device on the device, according to the implementation-related features, LDPC encoding and decoding can also be performed by using an exponential matrix or sequence having the same algebraic effect as the parity check matrix. Therefore, it should be noted that although encoding and decoding based on a parity check matrix are described in this disclosure for the convenience of description, the encoding and decoding can be implemented by various methods that can exhibit the same effect as the parity check matrix. For this reason, for the convenience of description, an exponential matrix or an LDPC sequence may also be referred to as a parity check matrix.

[0103] For reference, as used herein, the same algebraic effect means that at least two different representations can be described or converted to be logically or mathematically identical to each other.

[0104] Although it is assumed in the description of the present disclosure that only one circulant permutation matrix corresponds to one block for the sake of convenience, the present disclosure is also applicable to the case where multiple circulant permutation matrices are included in one block. For example, if two circulant permutation matrices The sum of is included in the position of the i-th row block and the j-th column block as shown in Formula 5 below, and its exponential matrix can be expressed as shown in Formula 6 below. It can be understood from Formula 6 that the matrix has two integers corresponding to the i-th row and j-th column, and the i-th row and j-th column correspond to the row block and column block including the sum of multiple circulant permutation matrices.

[0105] [Formula 5]

[0106]

[0107] [Formula 6]

[0108]

[0109] In the above embodiments, the QC-LDPC code may generally have multiple cyclic permutation matrices corresponding to a single row block and a single column block in the parity check matrix. Although for the convenience of description, it will be assumed in the description of the present disclosure that one cyclic permutation matrix corresponds to one block, the gist of the present disclosure is not limited thereto. For reference, a matrix having a size of L×L configured so that multiple cyclic permutation matrices overlap with a single row block and a single column block in this manner is referred to as a cyclic matrix or cyclic.

[0110] Meanwhile, similar to the definition used in the above-mentioned Formula 3, the mother matrix or base matrix about the parity check matrix and the exponential matrix in Formulas 5 and 6 refers to a binary matrix obtained by replacing each circulant permutation matrix and 0 matrix with 1 and 0, respectively. The sum of a plurality of circulant permutation matrices included in one block (i.e., the circulant matrix) may also be simply replaced with 1.

[0111] Since the performance of LDPC codes is determined by the parity check matrix, it is necessary to design a parity check matrix with excellent performance for LDPC codes. In addition, a method for LDPC encoding or decoding that can support various input lengths and code rates is also required.

[0112] Lifting refers to a method for not only efficiently designing QC-LDPC codes, but also generating parity check matrices with various lengths from a given exponential matrix or generating LDPC codewords therefrom. That is, lifting refers to a method for efficiently designing a very large parity check matrix by configuring an L value that determines the size of a circulant permutation matrix or a 0 matrix from a given small mother matrix according to a specific rule, or generating parity check matrices with various lengths or generating LDPC codewords by applying an L value suitable for a given exponential matrix or a sequence corresponding thereto.

[0113] The existing boosting methods and features of QC-LDPC codes designed by this boosting will now be briefly described with reference to the following reference [Myung2006]:

[0114] References [Myung2006]

[0115] S. Myung, K. Yang, and Y. Kim, “Lifting Methods for Quasi-Cyclic LDPC Codes,” IEEE Communications Letters, Vol. 10, June 2006, pp. 489–491.

[0116] First, assume that if an LDPC code C0 is given, up to S A QC-LDPC code is C1 , ..., C S , and the values ​​of the sizes of the row blocks and column blocks corresponding to the parity check matrix of each QC-LDPC code are L k In this way, C 0 Corresponding to code C 1 , ..., C S The mother matrix of the minimum LDPC code is used as the parity check matrix, and corresponds to the size of the row block and column block L 0 The value is 1. For the convenience of description, each code C k The parity check matrix An exponential matrix with size m×n , and each index Selected from {-1, 0, 1, 2, ..., L k - 1}.

[0117] Existing lifting methods are based on C 0 -> C 1 ->...-> C S The steps are performed and are characterized by satisfying such as L k+1 = q k+1 L k (q k+1 is a positive integer, k = 0, 1, ..., S-1). In addition, as long as the parity check matrix is ​​stored according to the characteristics of the lifting process , we can use the following formula 7 to express all QC-LDPC codes C according to the lifting scheme: 0 , C 1 , ..., C S :

[0118] [Formula 7]

[0119]

[0120] or

[0121] [Formula 8]

[0122]

[0123] In this way, not only for 0 Design a larger QC-LDPC code C 1 , ..., C S Such a method is called lifting and is used to obtain the value of C from a large code by using an appropriate method such as Equation 7 or Equation 8. k Generate code C i The (i=k-1, k-2, …, 1, 0) method is also called boosting.

[0124] According to the lifting scheme defined in Equation 7 or Equation 8, corresponding to each QC-LDPC code C k The size of the row block or column block in the parity check matrix is ​​L k have a multiple relationship with each other, and the exponential matrix is ​​also determined by a specific scheme. This existing lifting scheme improves the algebraic or graphical characteristics of each parity check matrix designed based on lifting, thus facilitating the design of a QC-LDPC code with improved error floor characteristics.

[0125] However, the disadvantage of the existing lifting scheme is that due to the k The values ​​are multiples of each other, so the length of each code is severely limited. k+1 =2 L k The minimum lifting scheme is applied to each L k In this case, the size of the parity check matrix of each QC-LDPC code may be 2 k m×2 k That is, if ten lifting steps (S = 10) are applied, a total of ten sizes of parity check matrices can be generated, and this means that QC-LDPC codes with ten lengths can be supported.

[0126] Therefore, the existing lifting scheme has a slightly disadvantageous feature in designing QC-LDPC codes that support various lengths. However, in view of various types of data transmission, commonly used communication systems require a very high level of length compatibility. Therefore, the LDPC coding technology based on the existing lifting scheme has the problem of being difficult to apply to communication systems.

[0127] In order to solve the above problems, the present invention adopts the following improvement method:

[0128] Generally speaking, the improvement can also be considered in terms of changing the L value. Figure 4 After the values ​​of the entries of the exponential matrix in are calculated, the exponential matrix is ​​used for LDPC encoding and decoding. For example, assuming Figure 4 The exponential matrix in is , and the exponential matrix changed according to the L value is , then the conversion formula defined in equation 9 can usually be applied:

[0129] [Formula 9]

[0130]

[0131] In the above formula 9, It can be defined as various types, and for example, f(x, L) = x (mod L) can be simply applied based on modular operations. Various functions such as those in the following formula 10 can also be defined and used:

[0132] [Formula 10]

[0133]

[0134] In the above formula 10, mod(a,b) refers to performing a modulo b operation on a, and D is a constant that is a predefined positive integer.

[0135] For reference, although for ease of description, it is assumed that the conversion formula used to apply the conversion formula in the above equation 9 is f The reference of is 0, but this reference value can be configured differently according to the block size L value to be supported.

[0136] Figure 4 is a block diagram showing a configuration of a transmitting device according to an embodiment of the present disclosure.

[0137] Specifically, if Figure 4 As shown, in order to process variable length input bits, the transmitting device 400 may include a segmenter 410, a zero padder 420, an LDPC encoder 430, a rate matcher 440, a modulator 450, etc. The rate matcher 440 may include an interleaver 441, a puncture / repetition / zero remover 442, etc.

[0138] Figure 4 The constituent elements shown in are merely exemplary constituent elements for performing encoding and modulation on variable length input bits. If necessary, they may be omitted or modified. Figure 4 Some of the constituent elements shown in FIG. 1 are shown in FIG. 5 , and other constituent elements may be added.

[0139] At the same time, the transmitting device 400 can determine the necessary parameters (for example, input bit length, modulation code rate (MOdCod), parameters for zero padding (or shortening), code rate / codeword length of the LDPC code, parameters for interleaving, parameters for repetition, puncturing, etc., modulation scheme, etc.), can perform encoding based on the determined parameters, and can transmit the encoding result to the receiving device 500.

[0140] In view of the fact that the number of input bits is variable, if the number of input bits is greater than a preconfigured value, the input bits may be segmented into lengths equal to or less than the preconfigured value. In addition, each segmented block may correspond to one LDPC coding block. If the number of input bits is less than or equal to the preconfigured value, the input bits are not segmented. The input bits may correspond to one LDPC coding block.

[0141] At the same time, the transmitting device 400 may have various parameters for encoding, interleaving and modulation pre-stored therein. As used herein, the parameters for encoding may be the code rate of the LDPC code, the length of the codeword, and information about the parity check matrix. The parameters for interleaving may be information about the interleaving rule, and the parameters for modulation may be information about the modulation scheme. The information about puncturing may be the puncturing length. The information about repetition may be the repetition length. If the parity check matrix proposed in the present disclosure is used, the information about the parity check matrix may store the index value of the circulant matrix.

[0142] In this case, the respective constituent elements constituting the transmitting device 400 may perform operations by using these parameters.

[0143] Although not shown, if necessary, the transmitting device 400 may further include a controller (not shown) for controlling the operation of the transmitting device 400. Therefore, the operation of the transmitting device described above and the operation of the transmitting device described in the present disclosure may be controlled by the controller, and the controller according to the present disclosure may be defined as a circuit, an application specific integrated circuit, or at least one processor.

[0144] Figure 5 is a block diagram showing a configuration of a receiving device according to an embodiment of the present disclosure.

[0145] Specifically, if Figure 5 As shown in , in order to process multiple variable length information, the receiving device 500 may include: a demodulator 510, a rate dematcher 520, an LDPC decoder 530, a zero remover 540, a desegmenter 550, etc. The rate dematcher 520 may include a log-likelihood ratio (LLR) inserter 522, an LLR combiner 523, a deinterleaver 524, etc.

[0146] Figure 5 The components shown in the figure are only used to perform the corresponding Figure 5 The functions of the constituent elements shown in the figure are exemplary constituent elements. If necessary, they may be omitted or modified. Figure 5 Some of the constituent elements shown in FIG. 1 are shown in FIG. 5 , and other constituent elements may be added.

[0147] The parity check matrix of the present disclosure can be read by a memory, or can be given in advance by a transmitting device or a receiving device, or can be directly generated by a transmitting device or a receiving device. In addition, the transmitting device can store or generate a sequence, an index matrix, etc. corresponding to the parity check matrix, and can apply it to encoding. Obviously, the receiving device can also store or generate a sequence, an index matrix, etc. corresponding to the parity check matrix, and can apply it to decoding.

[0148] In the following, reference will be made to Figure 5 Describe the receiver operation in detail.

[0149] The demodulator 510 demodulates the signal received from the transmitting device 400 .

[0150] Specifically, the demodulator 510 , which is a constituent element of the modulator 450 corresponding to the transmitting device 400 , may demodulate a signal received from the transmitting device 400 , thereby generating a value corresponding to a bit transmitted by the transmitting device 400 .

[0151] To this end, the receiving device 500 may pre-store therein information on the modulation scheme used by the transmitting device 400 for modulation according to the mode. Therefore, the demodulator 510 may demodulate the signal received from the transmitting device 400 according to the mode, thereby generating a value corresponding to the LDPC codeword bit.

[0152] Meanwhile, a value corresponding to a bit transmitted by the transmitting device 400 may be a log likelihood ratio (LLR) value.

[0153] Specifically, the LLR value may be expressed as the logarithm of the ratio between the likelihood that the bit transmitted by the transmitting device 400 will be 0 and the likelihood that the bit will be 1. Alternatively, the LLR value may be the bit value itself. In addition, the LLR value may be a representative value determined according to the range to which the likelihood that the bit transmitted by the transmitting device 400 will be 0 or 1 belongs.

[0154] The demodulator 510 includes a process of performing multiplexing (not shown) on the LLR values. Specifically, the demodulator 510 is a constituent element corresponding to the bit demultiplexer (not shown) of the transmitting device 400, and can perform operations corresponding to those of the bit demultiplexer (not shown).

[0155] To this end, the receiving device 500 may pre-store therein information about the parameters used for demultiplexing and block interleaving by the transmitting device 400. Therefore, the multiplexer (not shown) may reversely perform the demultiplexing and block interleaving operations performed by the bit demultiplexer (not shown) on the LLR values ​​corresponding to the cell words, thereby multiplexing the LLR values ​​corresponding to the cell words bit by bit.

[0156] The rate dematcher 520 may insert the LLR value into the LLR value output from the demodulator 510. In this case, the rate dematcher 520 may insert the pre-agreed LLR value between the LLR values ​​output from the demodulator 510.

[0157] Specifically, the rate dematcher 520 is a constituent element corresponding to the rate matcher 440 of the transmitting apparatus 400 , and may perform operations corresponding to the operations of the interleaver 441 and the zero removal and puncturing / repetition / zero remover 442 .

[0158] First, the rate dematcher 520 performs deinterleaving to correspond to the interleaver 441 of the transmitter. The output value from the deinterleaver 524 can insert the LLR value corresponding to the zero bit in the position filled with the zero bit in the LDPC codeword by the LLR inserter 522. In this case, the LLR value corresponding to the filled zero bit (that is, the shortened zero bit) can be ∞ or -∞. However, ∞ or -∞ is a theoretical value and can basically be the maximum value or minimum value of the LLR value used by the receiving device 500.

[0159] To this end, the receiving device 500 may pre-store therein information about the parameters used by the transmitting device 400 to fill the zero bits. Therefore, the rate dematcher 520 may determine the positions filled with zero bits in the LDPC codeword, and may insert LLR values ​​corresponding to the shortened zero bits in the corresponding positions.

[0160] In addition, the LLR inserter 522 of the rate dematcher 520 may insert an LLR value corresponding to the punctured bit in the position of the punctured bit in the LDPC codeword. In this case, the LLR value corresponding to the punctured bit may be 0.

[0161] To this end, the receiving apparatus 500 may pre-store therein information about parameters used for puncturing by the transmitting apparatus 400. Therefore, the LLR inserter 522 may insert LLR values ​​corresponding to LDPC parity bits in positions where LDPC parity bits are punctured.

[0162] The LLR combiner 523 may combine (add) the LLR values ​​output from the LLR inserter 522 and the demodulator 510. Specifically, the LLR combiner 523 is a constituent element corresponding to the puncture / repeat / zero remover 442 of the transmitting device 400, and may perform an operation corresponding to the repetition unit 442. First, the LLR combiner 523 may combine the LLR value corresponding to the repeated bit with another LLR value. The other LLR value may be an LLR value of a bit (i.e., an LDPC parity bit selected as a repetition target) based on which the transmitting device 400 generates the repeated bit.

[0163] That is, as described above, the transmitting apparatus 400 selects some bits from the LDPC parity bits, repeats them between the LDPC information word bits and the LDPC parity bits, and transmits them to the receiving apparatus 500 .

[0164] Therefore, the LLR values ​​about the LDPC parity bits may include LLR values ​​about repeated LDPC parity bits and LLR values ​​about non-repeated LDPC parity bits (ie, LDPC parity bits generated by encoding). Therefore, the LLR combiner 523 may combine the same LDPC parity bits with the LLR values.

[0165] To this end, the receiving device 500 may pre-store therein information about parameters used for repetition by the transmitting device 400. Therefore, the LLR combiner 523 may determine an LLR value about the repeated LDPC parity bits and may combine it with an LLR value about the LDPC parity bits used as a basis for repetition.

[0166] In addition, the LLR combiner 523 may combine the LLR value corresponding to the bit that has undergone retransmission or incremental redundancy (IR) with another LLR value. The other LLR value here may be an LLR value for a bit selected to generate an LDPC codeword bit, the LLR value being the basis for generating the bit that has been retransmitted or IR by the transmitting device 400.

[0167] That is, as described above, if NACK occurs for HARQ, the transmitting device 400 may transmit some or all of the codeword bits to the receiving device 500 .

[0168] Therefore, the LLR combiner 523 may combine LLR values ​​regarding bits received through retransmission or IR with LLR values ​​regarding LDPC codeword bits received through a previous codeword or frame.

[0169] To this end, the receiving device 500 may pre-store therein information about the parameters used by the transmitting device 400 to generate the retransmission or IR bits. Therefore, the LLR combiner 523 may determine the LLR value about the number of retransmission or IR bits, and may combine it with the LLR value of the LDPC parity bit that is the basis for generating the retransmission bits.

[0170] The deinterleaver 524 may deinterleave the LLR values ​​output from the LLR combiner 523 .

[0171] Specifically, the deinterleaver unit 524 is a constituent element corresponding to the interleaver 441 of the transmitting device 400 , and can perform an operation corresponding to the operation of the interleaver 441 .

[0172] To this end, the receiving device 500 may pre-store therein information about the parameters used for interleaving by the transmitting device 400. Therefore, the deinterleaver 524 may reversely perform the interleaving operation performed by the interleaver 441 on the LLR values ​​corresponding to the LDPC codeword bits, thereby deinterleaving the LLR values ​​corresponding to the LDPC codeword bits.

[0173] The LDPC decoder 530 may perform LDPC decoding based on the LLR value output from the rate dematcher 520 .

[0174] Specifically, the LDPC decoder 530 is a constituent element corresponding to the LDPC encoder 430 of the transmitting apparatus 400 , and may perform an operation corresponding to the operation of the LDPC encoder 430 .

[0175] To this end, the receiving apparatus 500 may pre-store therein information about parameters used by the transmitting apparatus 400 to perform LDPC encoding according to the mode. Therefore, the LDPC decoder 530 may perform LDPC decoding according to the mode based on the LLR value output from the rate dematcher 520.

[0176] For example, the LDPC decoder 530 may perform LDPC decoding based on the LLR values ​​output from the rate dematcher 520 according to an iterative decoding scheme based on a sum-product algorithm, and may output error-corrected bits as a result of the LDPC decoding.

[0177] The zero remover 540 may remove zero bits from the bits output by the LDPC decoder 530 .

[0178] Specifically, the zero remover 540 is a constituent element corresponding to the zero filler 420 of the transmitting device 400 , and may perform an operation corresponding to the operation of the zero filler 420 .

[0179] To this end, the receiving device 500 may pre-store therein information about parameters used by the transmitting device 400 to fill zero bits. Therefore, the zero remover 540 may remove the zero bits that have been filled by the zero filler 420 from the bits output by the LDPC decoder 530.

[0180] The desegmenter 550 is a constituent element corresponding to the segmenter 410 of the transmitting device 400 , and may perform an operation corresponding to that of the segmenter 410 .

[0181] To this end, the receiving device 500 may pre-store therein information about parameters used for segmentation by the transmitting device 400. Therefore, the desegmenter 550 may concatenate segments about bits output from the zero remover 540 (ie, variable-length input bits), thereby restoring bits before segmentation.

[0182] Although not shown, if necessary, the receiving device 400 may further include a controller (not shown) for controlling the operation of the receiving device 400. Therefore, the operation of the receiving device described above and the operation of the receiving device described in the present disclosure may be controlled by the controller, and the controller according to the present disclosure may be defined as a circuit, an application specific integrated circuit, or at least one processor.

[0183] At the same time, it is possible to Figure 2The bipartite graph listed in uses an iterative decoding algorithm based on the sum-product algorithm to decode the LDPC code, and the sum-product algorithm is a message passing algorithm.

[0184] In the following, reference will be made to Figure 6a and Figure 6b Describe the message passing operations typically used during LDPC decoding.

[0185] Figure 6a and Figure 6b The message passing operations in specific check nodes and variable nodes for LDPC decoding are shown.

[0186] Figure 6a The check node m 600 and connected to the verification node m 600 has a plurality of variable nodes 610, 620, 630 and 640. In addition, the Tn',m From the variable node n ' 610 is passed to the verification node m 600 messages, and En,m It means from the check node m 600 is passed to the variable node n 630 message. Here, it will connect to the verification node m The set of all variable nodes of 600 is defined as N(m) , and will be passed from N(m) Exclude variable nodes n 630 and the obtained set is defined as N (m)\n .

[0187] In this case, the message update rule based on the sum-product algorithm can be defined by the following equation 11:

[0188] [Formula 11]

[0189]

[0190] in, Sign(E n,m ) It's news E n,m The symbol of It means the message E n,m At the same time, the function It can be defined by the following formula 12:

[0191] [Formula 12]

[0192]

[0193] at the same time, Figure 6b Show variable nodes x 650 and connected to the variable node x 650 has multiple check nodes 660, 670, 680 and 690. In addition, the E y',x It means from the check node y ' 660 passed to the variable node x 650 messages, and T y,x From the variable node x 650 is passed to the variable node y 680 message. Here, it will be connected to the variable node x The set of all variable nodes of 650 is defined as M(x) , will be passed from M(x) Exclude check nodes y 680 and the obtained set is defined as M (x)\y In this case, the message update rule based on the sum-product algorithm can be defined by Equation 13:

[0194] [Formula 13]

[0195]

[0196] in E x It refers to the variable node x The initial message value of .

[0197] In addition, determine the node x The bit value of can be defined by the following formula 14:

[0198] [Formula 14]

[0199]

[0200] In this case, the P x The value corresponding to the node x The encoding bits.

[0201] References Figure 6a and Figure 6b The described scheme is a conventional decoding method, and therefore its further detailed description will be omitted here. Figure 6a and Figure 6bIn addition to the method described above, other methods may also be used to determine the message values ​​passed between variable nodes and check nodes, and a detailed description in this regard may be found in "Frank RKschischang, Brendan J. Frey and Hans-Andrea Loeliger, "Factor Graphs and the Sum-Product Algorithm", IEEE TRANSACTIONS ON INFORMATION THEORY, Vol. 47, February 2, 2001, pp. 498-519).

[0202] Figure 7 is a block diagram showing a detailed configuration of an LDPC encoder according to an embodiment of the present disclosure.

[0203] Up to K ldpc bits may constitute K for the LDPC encoder 700 ldpc LDPC information word bit I = (i 0 ,i 1 ,..., ). LDPC encoder 700 can ldpc LDPC information word bits are systematically LDPC encoded, thereby generating N ldpc LDPC codeword of one digit =(c 0 ,c 1 ,..., c Nldpc-1 )=(i 0 ,i 1 ,..., i Kldpc-1 ,p 0 ,p 1 ,...,p Nldpc-Kldpc-1 ).

[0204] As described above with reference to Equation 1, a process of determining a codeword so that the product of the LDPC codeword and the parity check matrix becomes a zero vector is included.

[0205] according to Figure 7 , the encoding device 700 includes an LDPC encoder 710. The encoding device 700 may have a reference Figure 4The LDPC encoder 710 may perform LDPC encoding on the input bits based on a parity check matrix or an exponential matrix or sequence corresponding thereto, thereby generating an LDPC codeword. In this case, the LDPC encoder 710 may perform LDPC encoding by using a parity check matrix differently defined according to a code rate (i.e., a code rate of an LDPC code).

[0206] Meanwhile, the encoding device 700 may further include a memory (not shown) for pre-storing the code rate of the LDPC code, the codeword length, and information about the parity check matrix, and the LDPC encoder 710 may perform LDPC encoding by using such information. If the parity check matrix proposed in the present disclosure is used, the information about the parity check matrix may store information about the index value of the circulant matrix.

[0207] Figure 8 is a block diagram showing the configuration of a decoding device according to an embodiment of the present disclosure.

[0208] according to Figure 8 , the decoding device 800 may include an LDPC decoder 810. The decoding device 800 may have a reference Figure 5 Alternatively, the decoding device 800 may additionally include some of the constituent elements of the transmitting device, or may not include some of them.

[0209] The LDPC decoder 810 performs LDPC decoding on the LDPC codeword based on the parity check matrix or an exponential matrix or sequence corresponding thereto.

[0210] For example, the LDPC decoder 810 may pass a log likelihood ratio (LLR) value corresponding to an LDPC codeword bit through an iterative decoding algorithm to perform LDPC decoding, thereby generating an information word bit.

[0211] The LLR value is a channel value corresponding to an LDPC codeword bit and may be represented in various methods.

[0212] For example, the LLR value may be expressed as the logarithm of the ratio between the likelihood that a bit transmitted from the transmitting side through the channel will be 0 and the likelihood that the bit will be 1. Alternatively, the LLR value may be the bit value itself determined by hard decision, or may be a representative value determined according to the range to which the likelihood that a bit transmitted from the transmitting side will be 0 or 1 belongs.

[0213] In this case, the transmitting side can be Figure 7 The LDPC encoder 710 in generates the LDPC codeword.

[0214] In this case, the LDPC decoder 810 may perform LDPC decoding by using a parity check matrix differently defined according to a code rate (ie, a code rate of an LDPC code).

[0215] Fig. 9 is a schematic diagram showing the structure of an LDPC decoder according to another embodiment of the present disclosure.

[0216] Meanwhile, the LDPC decoder 810 may perform LDPC decoding by using the iterative decoding algorithm as described above, and in this case, the LDPC decoder 810 may perform LDPC decoding in the same manner as Fig. 9 It should be noted that the iterative decoding algorithm is known, and therefore, Fig. 9 The detailed configurations shown are merely examples.

[0217] according to Fig. 9 The decoding device 900 includes an input processor 901, a memory 902, a variable node operator 904, a controller 906, a check node operator 908, an output processor 910, etc.

[0218] The input processor 901 stores the input value. Specifically, the input processor 901 may store the LLR value of the reception signal received through the wireless channel.

[0219] The controller 904 determines the number of values ​​input to the variable node operator 904, its address value in the memory 902, the number of values ​​input to the check node operator 908, its address value in the memory 902, etc. based on the size of the block of the received signal received through the wireless channel (i.e., the length of the codeword) and the parity check matrix corresponding to the code rate.

[0220] The memory 902 stores input data and output data of the variable node operator 904 and the check node operator 908 .

[0221] The variable node operator 904 receives a plurality of pieces of data input from the memory 902, and performs a variable node operation based on the address information of the input data and the information about the number of the input data input from the controller 906. The variable node operator 904 then stores the variable node operation result in the memory 902 based on the information about the address of the output data and the information about the number of the output data received from the controller 906. In addition, the variable node operator 904 inputs the variable node operation result to the output processor 910 based on the data received from the input processor 901 and the memory 902. Figure 6a and Figure 6b Describes the variable node operation.

[0222] The check node operator 908 receives multiple pieces of data from the memory 902 and performs variable node operations based on the address information of the input data input from the controller 906 and the information about the number of pieces of input data. Then, the check node operator 908 stores the variable node operation results in the memory 902 based on the information about the address of the output data received from the controller 906 and the information about the number of pieces of output data. The check node operation has been described with reference to Figure 6a and Figure 6b The output processor 910 makes a hard decision as to whether the information bit of the transmitted-side codeword will be 0 or 1 based on the data input from the variable node operator 904, and then outputs the result of the hard decision, and the output value of the output processor 910 ultimately becomes the decoded value. In this case, the hard decision can be made based on the sum of all the message values (initial message values and all the message values input from the check nodes) input to a single variable node in

[0223] and Figure 6a and Figure 6b .

[0224] Meanwhile, the decoding device 900 may further include a memory (not shown) for pre-storing the code rate of the LDPC code, the codeword length, and the information about the parity check matrix, and the LDPC decoder 810 may perform LDPC decoding by using such information. However, this is merely an example, and the corresponding multiple pieces of information may be provided from the transmission side.

[0225] Fig.10 is a block diagram showing the structure of a transport block according to another embodiment of the present disclosure.

[0226] With reference to Fig.10 , <Null> bits may be added to make the lengths of the segments the same.

[0227] In addition, <Null> bits may be added to conform to the information length of the LDPC code.

[0228] A method of applying various block sizes based on the QC-LDPC code has been described in connection with communication and broadcast systems that support LDPC codes of various lengths. Next, a method for further improving the coding performance will be proposed in connection with the proposed method.

[0229] Generally, as in the case of the lifting method described with reference to Equations 9 and 10, if an appropriate sequence is converted from a single LDPC exponent matrix, sequence, etc. and used for a very diverse block size L, there are many advantages because only one sequence or a small number of sequences need to be implemented in the system. However, if the types of block sizes to be supported increase, it becomes very difficult to design LDPC codes that have good performance for all block sizes.

[0230] The present disclosure proposes a method and apparatus for performing LDPC encoding / decoding by using multiple index matrices (or LDPC sequences) corresponding to each base matrix on two determined base matrices. The two base matrices are fixed, and according to the block size included in each block size group, the index matrix or sequence of the LDPC code defined on the base matrix is ​​lifted, thereby performing variable-length LDPC encoding and decoding. This scheme is characterized in that the entries or numbers of the index matrices or LDPC sequences constituting the multiple LDPC codes can have different values, but the positions of the corresponding entries or numbers are accurately limited according to the base matrix.

[0231] Thus, the exponential matrix or LDPC sequence refers to the index of each cyclic permutation matrix, that is, a cyclic shift value with respect to a bit. If the positions of all entries or numbers are configured identically, it becomes easy to identify the positions of the bits corresponding to the cyclic permutation matrix. For reference, since the exponential matrix or LDPC sequence proposed in the present disclosure corresponds to the cyclic shift values ​​of the bits corresponding to the block size Z, the cyclic shift values ​​may be variously referred to as shift matrices, shift value matrices, shift sequences, shift value sequences, etc.

[0232] In addition, the present disclosure proposes a method for improving performance by appropriately selecting two base matrices according to the information word length or code rate of the LDPC code and applying them to the system. If there are two base matrices, the system complexity will be increased to a certain extent and the advantage of substantially improving the coding performance will be balanced.

[0233] Generally, it is difficult to optimize LDPC codes for all lengths and code rates based on a single base matrix. Therefore, a method and apparatus for encoding and decoding can be implemented that supports stable and good performance for various lengths and code rates by using two or more base matrices and index matrices based on the base matrices, even if there is a certain degree of increased complexity.

[0234] For a more detailed description, the block size Z to be supported may be classified into a plurality of block size groups (or sets) as shown in the following Equation 15. The block size Z may refer to a value related to the size Z×Z of a circulant permutation matrix or circulant matrix associated with a parity check matrix of an LDPC code.

[0235] [Formula 15]

[0236] Z1 = {2, 4, 8, 16, 32, 64, 128, 256}

[0237] Z2 = {3, 6, 12, 24, 48, 96, 192, 384}

[0238] Z3 = {5, 10, 20, 40, 80, 160, 320}

[0239] Z4 = {7, 14, 28, 56, 112, 224}

[0240] Z5 = {9, 18, 36, 72, 144, 288}

[0241] Z6 = {11, 22, 44, 88, 176, 352}

[0242] Z7 = {13, 26, 52, 104, 208}

[0243] Z8 = {15, 30, 60, 120, 240}

[0244] As described above, the present disclosure proposes a method and apparatus for performing LDPC encoding / decoding by using a plurality of index matrices (or LDPC sequences) corresponding to respective base matrices on two determined base matrices.

[0245] The above formula 15 is only an example. All block size Z values ​​included in the block size group in the above formula 15 can be used. As defined in the following formula 16, block size values ​​in a subset of the block size group included in formula 15 can be appropriately used. Appropriate values ​​can be added to or excluded from the block size group (or set) in formula 15 or formula 16 and used.

[0246] [Formula 16]

[0247] Z1'= {8, 16, 32, 64, 128, 256}

[0248] Z2'= {12, 24, 48, 96, 192, 384}

[0249] Z3'= {10, 20, 40, 80, 160, 320}

[0250] Z4' = {14, 28, 56, 112, 224}

[0251] Z5'= {9, 18, 36, 72, 144, 288}

[0252] Z6'= {11, 22, 44, 88, 176, 352}

[0253] Z7' = {13, 26, 52, 104, 208}

[0254] Z8'= {15, 30, 60, 120, 240}

[0255] The block size groups in the above equations 15 and 16 are characterized in that they not only have different granularities, but also the ratios between adjacent block sizes are the same integer. In other words, the block sizes included in one group are divisors or multiples of each other. Assume that the block sizes corresponding to p Each exponential matrix of a group (p = 1, 2, …, 8) is , corresponding to the p The exponential matrix of the Z values ​​in the group is , and by using f p (x,Z) = x (mod Z) To apply the sequence conversion method as in Formula 9. That is, for example, if the block size Z is determined to be Z=28, then as defined in the following Formula 17, the exponential matrix (or LDPC sequence) corresponding to the fourth block size group including Z=28 is , we can get the exponential matrix (or LDPC sequence) about Z=28 Each entry .

[0256] [Formula 17]

[0257]

[0258] The conversion in the above equation 17 can also be expressed in the following equation 18 as:

[0259] [Formula 18]

[0260]

[0261] For reference, although it is assumed in the above description that the lifting or exponential matrix conversion scheme according to Equation 9 or Equations 15 to 18 is applied to the entire exponential matrix corresponding to the parity check matrix, it may also be applied to a partial exponential matrix.

[0262] For example, in many cases, the submatrix corresponding to the parity bits of the parity check matrix usually has a special structure for efficient encoding. In this case, lifting may change the encoding method or complexity. Therefore, lifting may not be applied to the part of the submatrix corresponding to the parity in the parity check matrix in the exponential matrix in order to maintain the same encoding method or complexity, or the manner in which lifting is applied to the submatrix corresponding to the information word bit may be different from the manner in which lifting is applied to the exponential matrix. In other words, the lifting scheme applied to the sequence corresponding to the information word bit in the exponential matrix and the lifting scheme applied to the sequence corresponding to the parity check bit can be configured differently. If necessary, lifting may not be applied to part or all of the sequence corresponding to the parity check bit to use a fixed value without sequence conversion.

[0263] Figures 11 to 18 15 to 18, which is a flow chart of an embodiment of an LDPC encoding and decoding process based on a base matrix and an exponential matrix (or an LDPC sequence) of an LDPC code designed by the design method according to the above-mentioned Equations 15 to 18.

[0264] Fig.11 is a schematic diagram illustrating an exemplary LDPC encoding process according to an embodiment of the present disclosure.

[0265] The encoding device or transmitting device (hereinafter referred to as the transmitting device) first determines the length of the information word, such as Fig.11 As shown in step 1110 in . In the present disclosure, if necessary, the length of the information word is also referred to as a code block size (CBS).

[0266] Next, the transmitting device may determine an LDPC index matrix or sequence that conforms to the determined CBS, as shown in step 1120 .

[0267] In addition, in step 1130, the transmitting device performs LDPC encoding based on the exponential matrix or sequence.

[0268] The LDPC decoding process is also Fig.12 .

[0269] Fig.12 is a schematic diagram illustrating an exemplary LDPC decoding process according to an embodiment of the present disclosure.

[0270] If the CBS is determined in step 1210 , then in step 1220 , the decoding device or the receiving device (hereinafter referred to as the receiving device) may determine an appropriate index matrix or sequence.

[0271] In addition, in step 1230, the receiving apparatus may perform LDPC decoding by using an index matrix or sequence.

[0272] Fig.13 and Fig.14 A flowchart of another embodiment of the LDPC encoding and decoding process based on a designed base matrix or exponential matrix is ​​shown in FIG.

[0273] Fig.13 is a schematic diagram illustrating another exemplary LDPC encoding process according to an embodiment of the present disclosure.

[0274] The transmitting device determines the size of the transport block to be transmitted, i.e., the transport block size (TBS), such as Fig.13 As shown in step 1310 in .

[0275] If the length of the maximum information word that can be encoded at one time for a channel code given by the system is the maximum CBS size (hereinafter referred to as the maximum CBS), and if the size of the TBS is greater than the maximum CBS, it is necessary to perform encoding after segmenting the transport block into multiple information word blocks (or code blocks). The maximum CBS may be determined in advance according to the system, or may be changed according to the channel conditions or the characteristics of the data to be transmitted. For example, it is assumed that two base matrices of LDPC codes are to be used in the system, it is assumed that the rules for using each base matrix are determined according to the MCS, and it is assumed that the maximum CBS of the first base matrix is ​​greater than the maximum CBS of the second base matrix. In this case, if the MCS to be applied by the transceiver is determined, the base matrix to be used for LDPC encoding is determined, and if the base matrix is ​​determined, the appropriate maximum CBS value is also determined. In addition, if the maximum CBS changes according to the channel conditions or the characteristics of the data to be transmitted, the maximum CBS may be determined by the base station, and the terminal may receive the information from the base station.

[0276] Therefore, in step 1320, the transmitting device may determine whether the TBS is greater than the maximum CBS, less than the maximum CBS, or equal to the maximum CBS.

[0277] In addition, if the TBS is greater than the maximum CBS, the transmitting device may segment the transport block to determine a new CBS in step 1330. The transmitting device may determine the size of the CBS to be segmented and may segment the transport block according to the size. In addition, in step 1340, the transmitting device may determine an LDCP index matrix or sequence.

[0278] On the other hand, if TBS is less than or equal to the maximum CBS, the transmitting device omits the segmentation operation, determines TBS as CBS, and then determines an appropriate LDPC index matrix or sequence according to the TBS or CBS value in step 1340. Thereafter, in step 1350, the transmitting device may perform LDPC encoding based on the determined index matrix or sequence.

[0279] As a specific example, it will be assumed that the TBS is determined to be 9216 in step 1310, and the maximum CBS given by the system is 8448. In this case, the transmitting device can determine in step 1320 that the TBS is greater than the maximum CBS, and can appropriately perform segmentation in step 1330. Therefore, as a result of the segmentation, two information word blocks (or code blocks) with CBS=4608 are obtained. Therefore, the transmitting device can determine an index matrix or sequence suitable for CBS=4608 in step 1340, and can perform LDPC encoding in step 1350 by using the determined index matrix or sequence.

[0280] The LDPC decoding process is also Fig.14 is shown similarly.

[0281] Fig.14 is a schematic diagram illustrating another exemplary LDPC decoding process according to an embodiment of the present disclosure.

[0282] The receiving device determines the size of a transport block to be transmitted, ie, a transport block size (TBS), as shown in step 1410 .

[0283] If the length of the maximum information word that can be encoded at one time for a channel code given by the system is the maximum CBS size (hereinafter referred to as the maximum CBS), and if the size of the TBS is greater than the maximum CBS, it is necessary to perform decoding after segmenting the transport block into a plurality of information word blocks (or code blocks). The maximum CBS may be determined in advance according to the system, or may be changed according to channel conditions. In addition, if the maximum CBS changes according to channel conditions, the maximum CBS may be determined by the base station, and the terminal may receive the information from the base station.

[0284] Therefore, in step 1420, the receiving device may determine whether the TBS is greater than the maximum CBS, less than the maximum CBS, or equal to the maximum CBS.

[0285] In addition, if the TBS is greater than the maximum CBS, the receiving device may determine the size of the CBS to be segmented in step 1430. In addition, in step 1440, the receiving device may appropriately determine the LDCP index matrix or sequence according to the size of the CBS.

[0286] On the other hand, if TBS is less than or equal to the maximum CBS, the receiving device determines TBS as CBS in step 1440, and then determines an appropriate LDPC index matrix or sequence based on the TBS or CBS value. Thereafter, in step 1450, the receiving device may perform LDPC decoding based on the determined index matrix or sequence.

[0287] As a specific example, it will be assumed that the TBS is determined to be 9216 in step 1410, and the maximum CBS given by the system is 8448. Therefore, the receiving device may determine in step 1420 that the TBS is greater than the maximum CBS, and may determine the size of the CBS to be segmented, such as 4608, in step 1430.

[0288] If it is determined in step 1420 that TBS is less than or equal to the maximum CBS, it is determined that TBS is equal to CBS. Thereafter, the receiving apparatus may determine an index matrix or sequence of the LDPC code in step 1440, and may perform LDPC decoding by using the determined index matrix or sequence in step 1450.

[0289] Fig.15 and Fig.16 A flowchart of another embodiment of the LDPC encoding and decoding process based on a designed base matrix or exponential matrix is ​​shown in FIG.

[0290] Fig.15 is a schematic diagram illustrating another exemplary LDPC encoding process according to an embodiment of the present disclosure.

[0291] As in Fig.15 In step 1510 of , the transmitting device determines a transport block size (TBS) to be transmitted.

[0292] Additionally, in step 1520, the transmitting device may determine whether the TBS is greater than the maximum CBS, less than the maximum CBS, or equal to the maximum CBS.

[0293] If the TBS is greater than the maximum CBS, then in step 1530, the transmitting device may segment the transport block in order to determine a new CBS.

[0294] On the other hand, if the TBS is less than or equal to the maximum CBS, the transmitting device may omit the segmentation operation and may determine the TBS as the CBS.

[0295] In addition, in step 1540 , the transmitting device may determine a block size (Z) value to be applied to LDPC encoding based on the CBS.

[0296] Thereafter, in step 1550, the transmitting device appropriately determines the LDPC index matrix or sequence according to the TBS, CBS or block size (Z) value.

[0297] In addition, the transmitting device performs LDPC encoding based on the determined block size and index matrix or sequence in step 1560. For reference, if necessary, step 1550 may include a process of converting the determined LDPC index matrix or sequence based on the determined block size.

[0298] The LDPC decoding process is also Fig.16 is shown similarly.

[0299] Fig.16 is a schematic diagram illustrating another exemplary LDPC decoding process according to an embodiment of the present disclosure.

[0300] Therefore, if the TBS has been determined in step 1610, then in step 1620, the receiving device may determine whether the TBS is greater than the maximum CBS, less than the maximum CBS, or equal to the maximum CBS.

[0301] If the TBS is greater than the maximum CBS, then in step 1630, the receiving device determines the size of the CBS to be segmented.

[0302] If it is determined in step 1620 that the TBS is less than or equal to the maximum CBS, then it is determined that the TBS is the same as the CBS.

[0303] In addition, the receiving apparatus determines a block size (Z) value to be applied to LDPC decoding in step 1640 , and then determines an LDPC index matrix or sequence suitable for TBS, CBS, or the block size (Z) value in step 1650 .

[0304] Thereafter, the receiving device may perform LDPC decoding by using the determined block size and index matrix or sequence in step 1660. For reference, if necessary, step 1650 may include a process of converting the LDPC index matrix of the determined sequence based on the determined block size.

[0305] Although already combined with Figures 11 to 16 The above embodiment is described with respect to the case where the index matrix or sequence of the LDPC code is determined by one of TBS, CBS, or block size (Z) in steps 1120 , 1220 , 1340 , 1440 , 1550 , and 1650 , but various other methods may also exist.

[0306] Fig.17 and Fig.18 A flowchart of another embodiment of the LDPC encoding and decoding process based on a designed base matrix or exponential matrix is ​​shown in FIG.

[0307] Fig.17 is a schematic diagram illustrating another exemplary LDPC encoding process according to an embodiment of the present disclosure.

[0308] exist Fig.17 In step 1710, the transmitting device determines the CBS size to be transmitted.

[0309] In addition, in step 1720, the transmitting device determines the value of the number of columns Kb corresponding to the CBS in the LDPC index matrix and the block size (Z) according to the CBS size. In the case of the index matrix of the LDPC code, the number of columns corresponding to the information word bits is usually fixed. However, in order to provide various CBS or optimized performance, not all columns corresponding to the information word bits may be used, but they may be appropriately shortened (using zero padding) according to the CBS and used. The Kb value may be determined in consideration of this shortening.

[0310] In step 1730 , the transmitting device appropriately determines an LDPC index matrix or sequence according to the CBS, the number of column blocks (Kb) corresponding to the CBS, or a block size (Z) value.

[0311] In addition, in step 1740, the transmitting device may perform a process of converting the determined LDPC index matrix or sequence based on the determined block size and index matrix or sequence. In step 1750, the transmitting device performs LDPC encoding based on the determined block size and index matrix or sequence.

[0312] The LDPC decoding process is also Fig.18 is shown similarly.

[0313] Fig.18 is a schematic diagram illustrating another exemplary LDPC decoding process according to an embodiment of the present disclosure.

[0314] As in Fig.18 In step 1810, the receiving device determines the CBS size of the received data.

[0315] In addition, in step 1820 , the receiving apparatus determines a value of the number of columns Kb corresponding to the CBS in the LDPC index matrix and a block size (Z) according to the CBS size.

[0316] In step 1830 , the receiving apparatus appropriately determines an LDPC index matrix or sequence according to the CBS, the number of column blocks (Kb) corresponding to the CBS, or a block size (Z) value.

[0317] In addition, in step 1840, the receiving device may perform a process of converting the determined LDPC index matrix or sequence based on the determined block size and index matrix or sequence. In step 1850, the receiving device performs LDPC decoding based on the determined block size and index matrix or sequence.

[0318] For reference Figures 11 to 18The embodiments of the LDPC encoding and decoding process described above based on the base matrix and the exponential matrix (or LDPC sequence) of the LDPC code can support LDPC encoding and decoding at various code rates and various lengths by appropriately shortening a portion of the information word bits of the LDPC code and puncturing a portion of the code word bits. For example, if the information word bits used for determining Figures 11 to 18 A portion of the information word bits in a base matrix or exponential matrix for LDPC encoding and decoding is shortened, if the information word bits corresponding to the first two columns are always punctured, and if a portion of the parity is punctured, various information word lengths (or code block lengths) and various code rates can be supported.

[0319] Furthermore, when supporting variable information word length or variable code rate by using shortening of LDPC codes, zero padding thereof, etc., the performance of the code can be improved according to the shortening sequence or shortening method. If the shortening sequence has been preconfigured, the coding performance can be improved by appropriately rearranging the order of part or all of a given base matrix. In addition, the performance can also be improved by appropriately determining the block size or number of column blocks to which shortening is to be applied for a specific information word length (or code block length CBS).

[0320] For example, assuming that the number of columns required for LDPC encoding and decoding in a given LDPC base matrix, exponential matrix or sequence is Kb, then if the Kb and block size (Z) values ​​corresponding thereto are determined by applying appropriate rules according to CBS in the following manner (e.g., A = 640, B = 560, C = 192), better performance can be achieved:

[0321] if(CBS > A)

[0322] Kb=10;

[0323] elseif(CBS > B)

[0324] Kb=9;

[0325] elseif(CBS > C)

[0326] Kb=8;

[0327] Else

[0328] Kb=6;

[0329] End

[0330] In the case of the above example, if the Kb value is determined in the above manner, the block size (Z) value can be determined as the minimum value that satisfies Z×Kb>=CBS. The higher the degree of freedom in determining the Kb value, the more beneficial it is to improve performance, but the worse it is in terms of system implementation complexity. Therefore, it is necessary to apply an appropriate level of rules to improve performance and system implementation efficiency. The method of determining Kb and block size values ​​is only an example, and various methods are applicable.

[0331] Hereinafter, a method for improving performance by appropriately selecting two base matrices according to the information word length or code rate of the LDPC code and applying them to the system proposed in the present disclosure will be described in detail. Although the present disclosure will be described with respect to two base matrices for ease of description, the present disclosure can generally be expanded by similar methods with respect to three or more base matrices.

[0332] Reference will be made to the embodiments of the present disclosure based on Fig.19a and Fig.20a The gist of the present disclosure is described by using a system for performing LDPC encoding and decoding with different base matrices shown. That is, the characteristics of each index matrix or LDPC sequence corresponding to the block size set corresponding to Equation 15 or Equation 16 are that they correspond to Fig.19a or Fig.20a The basis matrix in .

[0333] Fig.19a , Fig.19b , Fig.19c , Fig.19d , Fig.19e , Fig.19f , Figure 19g , Figure 19h , Fig.19i and Fig.19j is a schematic diagram showing an exemplary LDPC code base matrix according to an embodiment of the present disclosure.

[0334] Fig.19a The basis matrix in is divided into parts, which are Figures 19b to 19j is enlarged and shown in FIG. Fig.19a A matrix corresponding to the schematic diagrams corresponding to the figure numbers described in the respective sections. Thus, Figures 19b to 19j can be combined to form a single basis matrix. Fig.20a The basis matrix in is divided into parts, which are Figures 20b to 20j is enlarged and shown in FIG. Fig.20a A matrix corresponding to the schematic diagrams corresponding to the figure numbers described in the respective sections. Thus, Figures 20b to 20j can be combined to form a single basis matrix.

[0335] For reference, it can also be expressed by using the sequences given in the following equations 19 and 20, respectively: Fig.19a and Fig.20a Equations 19 and 20 represent the position of entry 1 relative to each row in the above basic matrix.

[0336] [Formula 19]

[0337] 0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, 23

[0338] 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, 24

[0339] 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25

[0340] 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, 25

[0341] 0, 1, 26

[0342] 0, 1, 3, 12, 16, 21, 22, 27

[0343] 0, 6, 10, 11, 13, 17, 18, 20, 28

[0344] 0, 1, 4, 7, 8, 14, 29

[0345] 0, 1, 3, 12, 16, 19, 21, 22, 24, 30

[0346] 0, 1, 10, 11, 13, 17, 18, 20, 31

[0347] 1, 2, 4, 7, 8, 14, 32

[0348] 0, 1, 12, 16, 21, 22, 23, 33

[0349] 0, 1, 10, 11, 13, 18, 34

[0350] 0, 3, 7, 20, 23, 35

[0351] 0, 12, 15, 16, 17, 21, 36

[0352] 0, 1, 10, 13, 18, 25, 37

[0353] 1, 3, 11, 20, 22, 38

[0354] 0, 14, 16, 17, 21, 39

[0355] 1, 12, 13, 18, 19, 40

[0356] 0, 1, 7, 8, 10, 41

[0357] 0, 3, 9, 11, 22, 42

[0358] 1, 5, 16, 20, 21, 43

[0359] 0, 12, 13, 17, 44

[0360] 1, 2, 10, 18, 45

[0361] 0, 3, 4, 11, 22, 46

[0362] 1, 6, 7, 14, 47

[0363] 0, 2, 4, 15, 48

[0364] 1, 6, 8, 49

[0365] 0, 4, 19, 21, 50

[0366] 1, 14, 18, 25, 51

[0367] 0, 10, 13, 24, 52

[0368] 1, 7, 22, 25, 53

[0369] 0, 12, 14, 24, 54

[0370] 1, 2, 11, 21, 55

[0371] 0, 7, 15, 17, 56

[0372] 1, 6, 12, 22, 57

[0373] 0, 14, 15, 18, 58

[0374] 1, 13, 23, 59

[0375] 0, 9, 10, 12, 60

[0376] 1, 3, 7, 19, 61

[0377] 0, 8, 17, 62

[0378] 1, 3, 9, 18, 63

[0379] 0, 4, 24, 64

[0380] 1, 16, 18, 25, 65

[0381] 0, 7, 9, 22, 66

[0382] 1, 6, 10, 67

[0383] [Formula 20]

[0384] 0, 1, 2, 3, 6, 9, 10, 11

[0385] 0, 3, 4, 5, 6, 7, 8, 9, 11, 12

[0386] 0, 1, 3, 4, 8, 10, 12, 13

[0387] 1, 2, 4, 5, 6, 7, 8, 9, 10, 13

[0388] 0, 1, 11, 14

[0389] 0, 1, 5, 7, 11, 15

[0390] 0, 5, 7, 9, 11, 16

[0391] 1, 5, 7, 11, 13, 17

[0392] 0, 1, 12, 18

[0393] 1, 8, 10, 11, 19

[0394] 0, 1, 6, 7, 20

[0395] 0, 7, 9, 13, 21

[0396] 1, 3, 11, 22

[0397] 0, 1, 8, 13, 23

[0398] 1, 6, 11, 13, 24

[0399] 0, 10, 11, 25

[0400] 1, 9, 11, 12, 26

[0401] 1, 5, 11, 12, 27

[0402] 0, 6, 7, 28

[0403] 0, 1, 10, 29

[0404] 1, 4, 11, 30

[0405] 0, 8, 13, 31

[0406] 1, 2, 32

[0407] 0, 3, 5, 33

[0408] 1, 2, 9, 34

[0409] 0, 5, 35

[0410] 2, 7, 12, 13, 36

[0411] 0, 6, 37

[0412] 1, 2, 5, 38

[0413] 0, 4, 39

[0414] 2, 5, 7, 9, 40

[0415] 1, 13, 41

[0416] 0, 5, 12, 42

[0417] 2, 7, 10, 43

[0418] 0, 12, 13, 44

[0419] 1, 5, 11, 45

[0420] 0, 2, 7, 46

[0421] 10, 13, 47

[0422] 1, 5, 11, 48

[0423] 0, 7, 12, 49

[0424] 2, 10, 13, 50

[0425] 1, 5, 11, 51

[0426] from Fig.19a The basis matrix and Fig.20a It can be clearly seen from the basis matrices in that they have different weight distributions or degree distributions.

[0427] Generally, it is well known in theory that the performance of an LDPC code with ideal conditions (assuming infinite length) is proportional to the average density of weights. However, in the case where the LDPC code used in an actual system has a finite (restricted) length, the result is different from the theoretical analysis. Therefore, if the length range to be supported in an actual communication or broadcasting system is different, designing a base matrix with a different distribution is beneficial to support good performance.

[0428] In addition, without applying the shortening method, Fig.20a The basis matrix in can basically be compared Fig.19a The base matrix in supports a lower bit rate, and from this we can understand that Fig.19a and Fig.20a The basis matrix in is considered and designed to support different lengths and code rates. In fact, it can be understood that Fig.20a The weight density of the basis matrix in is significantly lower than Fig.19a The weight density of the basis matrix in . This is because, in Fig.20a In this case, it has been determined that the design exhibits good performance at shorter lengths.

[0429] First, refer to Fig.21 The flowchart in is used in conjunction with the method and device for LDPC encoding and decoding based on two or more different base matrices described above to describe a method for selecting a base matrix or an index matrix corresponding thereto.

[0430] Fig.21 is a diagram illustrating an exemplary method for determining a base matrix according to a CBS and a code rate by a transmitter.

[0431] If a modulation and coding scheme (MCS) for transmission is determined by the system, the transmitter may determine a CBS and an initial transmission code rate corresponding thereto in steps 2110 and 2120, respectively.

[0432] Then, in step 2130, the transmitter may compare the determined CBS value with a predetermined reference value K Th The determined code rate R can be compared with a predetermined reference value R Th A comparison is made to determine whether a certain condition is met.

[0433] According to a result of determining whether the CBS value and the code rate satisfy a specific condition, the transmitter determines whether to perform LDPC encoding based on the first base matrix or the second base matrix.

[0434] Specifically, Fig.21 The determination condition in the example may correspond to CBS being less than K Th value and the code rate is less than R Th situation.

[0435] Therefore, if CBS is less than K Th value, and if the code rate is less than R Th , the transmitter can perform LDPC encoding based on the second base matrix in step 2150, and in other cases, can perform LDPC encoding based on the first matrix in step 2140 (although for ease of description, it is assumed in the description of this disclosure that the code rate is the initial transmission code rate, the code rate can generally be defined by the system as various types).

[0436] K in this disclosure Th The value can be called the CBS threshold, and R Th It can be called the bit rate threshold. Th Value and R Th The value may be configured by the base station or may be configured in advance. The base station may notify the terminal of the above value through RRC signaling or the like.

[0437] If this basis matrix selection method is applied, one case of selecting the basis matrix is Fig. 22 It is shown in the figure to briefly describe it.

[0438] Fig. 22 The range of selecting the first base matrix and the second base matrix is ​​shown, where the X-axis represents CBS and the Y-axis represents the initial transmission code rate. The first base matrix in the present disclosure may correspond to the reference Fig.19a The base matrix described in the present disclosure may correspond to the base matrix of reference Fig.20a However, the embodiments of the present disclosure are not limited thereto, and the first base matrix may correspond to the reference Fig.20a The second basis matrix can correspond to the reference Fig.19a In addition, the first base matrix and the second base matrix in the present disclosure may correspond to two different base matrices configured separately.

[0439] If you use Fig.21 and Fig. 22The method shown is to select the basis matrix, and the selection criteria are simple, so that the system can implement the basis matrix efficiently. However, as briefly described above, the optimal weight distribution of LDPC codes may vary greatly in coding performance, and by using Fig.21 and Fig. 22 The simple method shown does not easily support good performance at a certain length and a certain code rate. In other words, two basis matrices (such as Fig.19a and Fig.20a The basis matrix in ) applies shortening and puncturing to support various lengths and code rates, and uses Fig.21 and Fig. 22 The method shown may have difficulty in applying shortening and puncturing techniques corresponding to a good weight distribution.

[0440] To be precise, Fig.19a The design of the base matrix in is based on the case where the maximum initial transmission code rate is relatively high and the CBS is large, while Fig.20a The design of the basis matrix in is based on the fact that the maximum initial transmission code rate is relatively lower than Fig.19a Therefore, if the CBS is small and if the code rate is high, it is difficult to Fig.21 and Fig. 22 The method shown supports good performance.

[0441] In order to solve this problem, the present disclosure proposes Figures 23a to 26b The method presented in this disclosure Fig.21 Flowchart and Fig.23a , Figure 23b and Fig.24a , Figure 24b The biggest difference between the flowcharts of is that the criterion for determining the size of the CBS may vary according to the code rate, or the criterion for determining the size of the code rate may vary according to the size of the CBS.

[0442] Fig.23a and Figure 23b is a schematic diagram of an exemplary method for determining a base matrix according to CBS and a code rate by a transmitter and a receiver, respectively.

[0443] refer to Fig.23a The transmission operation shown determines the CBS and the initial transmission code rate in steps 2310 and 2311, respectively.

[0444] Afterwards, in step 2312, the transmitter may determine whether the CBS value satisfies a specific condition. For example, the transmitter may compare the determined CBS value with a predetermined reference value, and may configure the reference value differently according to the code rate. Therefore, the reference value may generally be expressed as a function of R, such as K Th(R).

[0445] Thus, after determining whether a specific condition is satisfied in step 2312, the transmitter may determine whether to perform LDPC encoding based on the first base matrix or the second base matrix according to the determination result. The details are similar to those in reference Fig.21 The description is similar.

[0446] The receiver can be operated as in Figure 23b As shown in . The CBS and the initial transmission code rate are determined in steps 2320 and 2321 respectively.

[0447] Then, in step 2322, the receiver may determine whether the CBS value satisfies a specific condition. For example, the receiver may compare the determined CBS value with a predetermined reference value K Th (R) is compared, and the reference value can be configured differently according to the code rate. The details are as described above.

[0448] Therefore, after determining whether a specific condition is satisfied, the receiver can determine whether to perform LDPC decoding based on the first base matrix or the second base matrix according to the result of the determination, the details of which are the same as those in reference Fig.21 The description is similar.

[0449] Fig.24a and Figure 24b is a schematic diagram of an exemplary method for determining a base matrix according to a CBS and a code rate by a transmitter and a receiver, respectively.

[0450] refer to Fig.24a The transmission operation shown determines the CBS and the initial transmission code rate in steps 2410 and 2411, respectively.

[0451] Afterwards, in step 2412, the transmitter may determine whether the CBS value satisfies a specific condition. For example, the transmitter may compare the determined CBS value with a predetermined reference value, and may configure the reference value differently according to the CBS value. Therefore, the reference value may generally be expressed as a function of K, such as R Th (K).

[0452] Therefore, after determining whether a specific condition is satisfied in step 2412, the transmitter may determine whether to perform LDPC encoding based on the first base matrix or the second base matrix according to the result of the determination. Fig.21 The description is similar.

[0453] The receiver can be operated as in Figure 24b As shown in . The CBS and the initial transmission code rate are determined in steps 2420 and 2421 respectively.

[0454] After that, in step 2422, the receiver can determine whether the transmission code rate meets a specific condition. For example, the receiver can compare the determined transmission code rate with a predetermined reference value R Th (K) and can configure the reference value differently according to the CBS value. The details are as described above.

[0455] Therefore, after determining whether the specific condition is met, the receiver can determine whether to perform LDPC decoding based on the first basis matrix or based on the second basis matrix according to the determined result. The details are similar to those described in the reference Fig.21 description.

[0456] Fig.25 and Fig.26a 、 26b show specific examples of applying the basis matrix according to the CBS or the transmission code rate value in the flowchart shown in Fig.23a 、 Figure 23b and Fig.24a 、 Figure 24b shown.

[0457] Fig.25 shows the range of allocating the basis matrix in the case of defining K Th (R) as a constant function according to the range of R or defining the value of R Th (K) as a constant function according to the K value.

[0458] For example, the CBS threshold K Th (R) can be configured such that if 0 < R < the first coding rate threshold R Th1 , then it has the first CBS threshold K Th1 ; if R Th1 < R < the second code rate threshold R Th2 , then it has the second CBS threshold K Th2 , and if R > R Th2 , then it has the value 0.

[0459] Therefore, the transmitter and the receiver can use the second basis matrix in the range where the CBS is less than K Fig.23a and Figure 23b . The range of using the second basis matrix is as shown in [a] of Th (R) as shown in Fig.25 .

[0460] The range where the CBS is less than K Th (R) can specifically be the range where the size of the CBS is less than K Th1 when R is less than R Th1 2510, and can be the range where R is greater than R Th1and is less than R Th2 In the case where the size of CBS is less than K Th2 range.

[0461] Alternatively, the code rate threshold R Th (K) can be configured as: If 0 <K<K Th1 , then it has the value R Th1 ; if K Th1 <K<K Th2 , then it has the value R Th2 , and if K>K Th2 , then it has the value 0.

[0462] In this case, the transmitter and receiver can be based on Fig.24a and Figure 24b When R is less than R Th (K) The second basis matrix is ​​used in the range of Fig.25 As shown in [a].

[0463] In addition, the embodiments of the present disclosure are not limited thereto, and the CBS threshold may be configured according to three code rate thresholds, or the code rate threshold may be determined by three CBS thresholds. Fig.25 [b] shows the range of using the basis matrix.

[0464] In addition, the CBS threshold may be determined as a linear function of the bit rate, or the bit rate threshold may be determined as a linear function of the CBS. Fig. 27 [a] or Fig. 27 The range shown in [b] uses the basis matrix. The details will be described later.

[0465] Fig.25 FIG. 4 is a schematic diagram showing another exemplary range of allocating a base matrix according to CBS and coding rate.

[0466] First reference Fig.25 [a], the reference value of CBS has K Th1 and K Th2 two values, and has a reference value R about the code rate corresponding to the reference value of each CBS Th1 and R Th2 .

[0467] Fig.26a and Figure 26b The combination is shown in Fig.25 Case [a] is another example of a flowchart regarding system operation.

[0468] Fig.26a and Figure 26bSchematic diagrams of other exemplary methods for determining a base matrix according to CBS and a code rate by a transmitter and a receiver, respectively.

[0469] refer to Fig.26a , in step 2610, the transmitter may determine the CBS and the code rate R.

[0470] In addition, in step 2611, the transmitter may compare the determined CBS value with the first CBS reference value K Th1 Make a comparison.

[0471] If the CBS value is greater than K Th1 , then in step 2612, the transmitter performs LDPC encoding based on the first basis matrix.

[0472] If the CBS value is not greater than K Th1 , then in step 2613, the transmitter may again compare the CBS value with the second CBS reference value K Th2 Make a comparison.

[0473] If the CBS value is greater than K Th2 , then in step 2614, the transmitter may compare the code rate determined in step 2610 with the first code rate reference value R Th1 If the code rate is greater than R Th1 , then in step 2612, the transmitter may perform LDPC encoding based on the first base matrix; otherwise, in step 2615, the transmitter may perform LDPC encoding based on the second base matrix.

[0474] If in step 2613, the determined CBS value is not greater than K Th2 , then in step 2616, the transmitter may compare the code rate determined in step 2610 with the second code rate reference value R Th2 If the code rate is greater than R Th2 , then in step 2612, the transmitter performs LDPC encoding based on the first base matrix; otherwise, in step 2615, the transmitter performs LDPC encoding based on the second base matrix.

[0475] like Figure 26b As shown in , the operation in the receiver can also be similar to Fig.26a operation.

[0476] In step 2620, the receiver may determine the CBS and the code rate R.

[0477] In addition, in step 2621, the receiver may compare the determined CBS value with the first CBS reference value K Th1 Make a comparison.

[0478] If the CBS value is greater than K Th1, then in step 2622, the receiver performs LDPC decoding based on the first base matrix.

[0479] If the CBS value is not greater than K Th1 , then in step 2623, the receiver may again compare the CBS value with the second CBS reference value K Th2 Make a comparison.

[0480] If the CBS value is greater than K Th2 , then in step 2624, the receiver may compare the code rate determined in step 2620 with the first code rate reference value R Th1 If the code rate is greater than R Th1 , then in step 2622, the receiver may perform LDPC decoding based on the first base matrix; otherwise, in step 2625, the receiver may perform LDPC decoding based on the second base matrix.

[0481] If in step 2623, the determined CBS value is not greater than K Th2 , then in step 2626, the receiver may compare the code rate determined in step 2620 with the second code rate reference value R Th2 If the code rate is greater than R Th2 , then in step 2622, the receiver performs LDPC decoding based on the first base matrix; otherwise, in step 2625, the receiver performs LDPC encoding based on the second base matrix.

[0482] Although for ease of description reference has been made Fig.25 and Fig.26a , Figure 26b The example in describes LDPC encoding and decoding based on the first base matrix and the second base matrix, but if necessary, two or more index matrices, LDPC sequences, etc. may be used to perform LDPC encoding in step 2612 or step 2615 and LDPC decoding in step 2622 or step 2625. In addition, although the CBS may be used to determine the LDPC base matrix, index matrix, or sequence, if necessary, the TBS value may be used to determine the LDPC base matrix, index matrix, or sequence, and the CBS and TBS may be considered to determine the LDPC base matrix, index matrix, or sequence.

[0483] Fig.25 [b] is a schematic diagram showing an example of configuring three reference values ​​for CBS and three reference values ​​for code rate. If LDPC encoding and decoding are performed based on multiple base matrices or LDPC index matrices or sequences corresponding thereto in this way, more reference values ​​are configured, which can generally support more optimized performance, but there is a disadvantage of increased system complexity. Therefore, it is necessary to appropriately configure the reference values ​​according to system requirements.

[0484] Fig.25 and Fig.26a , Figure 26b The illustrated LDPC encoding and decoding process can be summarized as follows:

[0485] First, the transmitter or receiver performs a process of determining the CBS (K) in the system and a process of determining the code rate (R). In addition, a process of determining the block size (Z) is also necessary for encoding and decoding of LDPC codes, which can be defined by a parity check matrix of the type in Equations 3 to 6.

[0486] In addition, the transmitter or the receiver may confirm whether the CBS or the code rate satisfies a predetermined condition, and may determine whether to use the first base matrix or the second base matrix according to the result of the confirmation.

[0487] Specifically, the transmitter or the receiver performs a comparison between the determined CBS and a predetermined first CBS reference value K. Th1 Or the second CBS reference value K Th2 The process of comparing at least one of the

[0488] Afterwards, if CBS(K) is not greater than the first CBS reference value K Th1 , the transmitter or receiver may perform a comparison between the determined code rate (R) and a predetermined first code rate reference value R Th1 and the second code rate reference value R Th2 The process of comparing at least one of the

[0489] In addition, the transmitter or the receiver performs a process of determining an LDPC base matrix, an exponential matrix, or a sequence according to a comparison result of a code rate (R) and a reference value.

[0490] LDPC encoding and decoding are performed based on the finally determined LDPC base matrix, index matrix or sequence and block size (Z). In the process of determining the LDPC base matrix, index matrix or sequence, the boost defined in Equation 17 or Equation 18 may be additionally applied.

[0491] The method proposed in the present disclosure may predefine the reference value as a specific value, but the reference value may also be defined in various ways. For example, the range of CBS and bit rate may be configured as follows: Fig. 27 [a] and Fig. 27 [b] shows various types to support better performance.

[0492] exist Fig. 27 In the case of [a], a reference value is configured for CBS, but the reference value of the code rate has a linear function form with respect to the CBS value K, as defined in the following equation 21:

[0493] [Formula 21]

[0494]

[0495] It can be clearly seen from the above formula 21 that the reference value R of the bit rate Th Relative to the CBS value K decreases. Fig. 27 The same as R in [a] Th2 is predetermined and configured as a linear function, corresponding to the slope value in Eq. A It can be defined as in the following formula 22:

[0496] [Formula 22]

[0497]

[0498] The above-mentioned Formula 22 is only an example and may be defined as various values.

[0499] exist Fig. 27 In the case of [b], the linear function and the constant function can be appropriately combined according to the following formula 23:

[0500] [Formula 23]

[0501]

[0502] refer to Figure 21 to Figure 27 The present disclosure described proposes a method for determining an appropriate LDPC base matrix, index matrix or sequence based on CBS, TBS, code rate, etc. In the process of determining the LDPC base matrix, index matrix or sequence, a method of selecting the LDPC base matrix, index matrix or sequence according to a predetermined reference value defined as Equation 21 to Equation 23 is applied. For the reference value, the code rate reference value can vary according to the CBS or TBS. On the contrary, the CBS (or TBS) reference value can vary according to the code rate. In addition, the reference value can be simply determined by the CBS, TBS or code rate, and can be determined in different ways according to system requirements. For example, the reference value can be adjusted according to the amount of overhead of the frame used to transmit data in the system, and can be appropriately changed according to the modulation order, so that the performance is further improved.

[0503] The method of selecting the LDPC base matrix, index matrix or sequence does not necessarily have to be determined by using CBS, TBS, code rate, etc. For example, it is possible to support the use of MCS or its index I MCS , TBS or its index I TBS Or from physical resource block number N PRBThe method of selecting an LDPC sequence having the same effect as the case in the LTE standard by using the TBS table defined in the present disclosure. According to the LTE standard, it is actually very easy to determine an accurate or approximate code rate based on the MCS index, TBS index, or TBS table defined from the physical resource block. Therefore, the reference value of the CBS, TBS, or code rate proposed by the present disclosure can be obtained by using the physical resource block number N used in the MCS index, TBS index, or TBS table. PRB To express.

[0504] The method for using MCS or its index I based on the MCS will be described with reference to a simple embodiment. MCS , TBS or its index I TBS Or physical resource block number N PRB A method of determining an LDPC base matrix or sequence and performing LDPC encoding and decoding.

[0505] As an example, if the MCS is determined in the communication system, the coding device can determine information about the approximate code rate of the channel code. In addition, if the base station allocates appropriate physical resource blocks, the TBS can also be determined. After determining the TBS, the coding device determines the block size for LDPC coding. Therefore, the LDPC base matrix, sequence, etc. for LDPC coding can be determined based on the MCS information and the block size.

[0506] As another example, if the communication system determines the MCS, the encoding device may determine the TBS index I TBS In addition, if the base station determines the appropriate physical resource block number N PRB , the encoding device can be based on the TBS index I TBS and physical resource block number N PRB Determine TBS. After determining the TBS, the encoding device determines the block size for LDPC encoding, and can determine the LDPC base matrix, sequence, etc. for LDPC encoding based on the TBS index, the physical resource block number, and the block size.

[0507] After determining the LDPC base matrix, sequence, etc. in this way, the encoding device can perform LDPC encoding based on the block size. In order to perform LDPC encoding, a process of converting the LDPC sequence according to the block size may also be included.

[0508] Through a similar process, the above LDPC encoding method can also be applied to the LDPC decoding process.

[0509] Another embodiment of the present disclosure is Fig.28a and Fig.28b Shown in.

[0510] Fig.28a and Fig.28bSchematic diagrams of other exemplary methods for determining a base matrix according to a TBS index and the number of resource blocks by a transmitter and a receiver are respectively shown.

[0511] First reference Fig.28a In step 2810, the transmitter may determine (I TBS , N PRB ). Here, (I TBS , N PRB ) can be called index information.

[0512] In addition, in step 2811, the transmitter confirms the determined (I TBS , N PRB ) value is included in the predefined set S. Set S refers to the value of (I TBS , N PRB ) in step 2811 may be performed by a 1:1 comparison between the value determined in step 2810 and the index or value included in the set S. TBS , N PRB ) value is included in the predefined set S. It is also possible to apply I TBS or N PRB A method by which a value is compared with each predetermined reference value, thereby determining a range of values.

[0513] The transmitter may determine the index information through steps 2810 and 2811, and may determine the index information based on the determined (I TBS ,N PRB ) In step 2812 or 2813, an appropriate LDPC base matrix, LDPC index matrix or LDPC sequence is determined, thereby performing LDPC encoding.

[0514] Specifically, if the index information is included in the index set, the transmitter may perform encoding based on the second base matrix in step 2813. If the index information is not included in the index set, the transmitter may perform encoding based on the first base matrix in step 2812.

[0515] The operation of the receiver can be almost similar to Fig.28a The operation of the transmitter in is performed, such as Fig.28b Shown.

[0516] In step 2820, the receiver may determine (I TBS , N PRB ). Here, (I TBS , N PRB ) can be called index information.

[0517] In addition, in step 2821, the receiver confirms the determined (I TBS , N PRB ) value is included in the predefined set S. Set S refers to the value of (I TBS , N PRB ) in step 2821 may be performed by a 1:1 comparison between the value determined in step 2820 and the index or value included in the set S. TBS , N PRB ) value is included in the predefined set S. It is also possible to apply I TBS or N PRB A method by which a value is compared with each predetermined reference value, thereby determining a range of values.

[0518] The receiver may determine the index information through steps 2820 and 282, and may determine the index information based on the determined (I TBS ,N PRB ) In step 2812 or 2813, an appropriate LDPC base matrix, LDPC index matrix or LDPC sequence is determined, thereby performing LDPC decoding.

[0519] Specifically, if the index information is included in the index set, the receiver may perform decoding based on the second base matrix in step 2823. If the index information is not included in the index set, the receiver may perform decoding based on the first base matrix in step 2822.

[0520] A method of changing the length of cyclic redundancy check (CRC) bits appended to a transport block according to a determined LDPC base matrix, exponential matrix, or sequence will now be described as another embodiment of the present disclosure.

[0521] Usually, if Fig.29 CRC bits are shown appended to a transport block in order to determine whether an error has occurred when a receiver decodes the data in the transport block.

[0522] Fig.29 is a diagram showing an example of appending CRC bits to a given transport block.

[0523] refer to Fig.29 , the transmitter can be CRC The length of the CRC 2920 is added to the transport block 2910. The CRC bits play an important role in detecting errors in the recovered data, but are an overhead from the system perspective. Therefore, determining the appropriate number of bits is a key issue in reducing system overhead.

[0524] For CRC bits, generally, the more bits are added, the lower the false alarm rate (FAR) may be (FAR refers to the probability that the system cannot identify the error even though the actual recovered data has an error). Therefore, it is necessary to determine the appropriate number of CRC bits according to the FAR level required by the system. Specifically, for a system using LDPC codes, the LDPC code itself can reduce the FAR to some extent. Only by determining the CRC bits with this feature in mind can the system efficiency be maximized.

[0525] For LDPC codes, due to the characteristics of the decoding process, it is possible to determine whether an error has occurred through a fault check in the parity check matrix. Therefore, it is necessary to determine the number of CRC bits in consideration of the FAR characteristics of the LDPC code used in the communication system to which the LDPC code is applied.

[0526] For example, the transmitter determines an LDPC base matrix or sequence corresponding to the LDPC encoding based on the TBS, the MCS information, or a portion of the MCS information. Afterwards, the transmitter confirms which LDPC base matrix or sequence is determined, and if the determined LDPC base matrix or sequence is not the first LDPC base matrix or the LDPC sequence corresponding to the first base matrix, the transmitter determines the number of CRC bits N CRC is a predefined number X. If the first LDPC base matrix has been selected, the transmitter can determine the number of CRC bits N CRC is a predefined number Y.

[0527] In addition, when determining N CRC The transmitter then applies CRC coding to the transport block, thereby generating N CRC CRC bits. In addition, the transmitter appends the generated CRC bits to the transport block, and then appropriately performs LDPC encoding. It is necessary to determine a block size (Z) value for LDPC encoding, and the block size value can be variably determined according to the TBS value or the determined LDPC base matrix or sequence. In this way, the number of CRC bits can be configured differently according to the LDPC base matrix or sequence corresponding to the LDPC encoding.

[0528] The decoding process corresponding to the encoding process can be performed similarly.

[0529] The receiver may first receive a signal including information about the LDPC-encoded transport block and CRC bits. The receiver determines the LDPC base matrix or sequence corresponding to the LDPC decoding based on the TBS, MCS information, or a portion of the MCS information from the received signal. Thereafter, the receiver confirms which LDPC base matrix or sequence has been determined, and if the confirmed LDPC base matrix or sequence is not the first LDPC base matrix or the LDPC sequence corresponding to the first base matrix, the receiver determines the number of CRC bits N CRCis a predefined number X. If the first LDPC base matrix has been selected, the receiver can determine the number of CRC bits N CRC is a predefined number Y.

[0530] In addition, the receiver performs LDPC decoding on the received LDPC-encoded transport blocks and CRC bits according to the determined LDPC base matrix or sequence. A block size (Z) value needs to be determined for LDPC decoding, and the receiver can variably determine the block size value according to the TBS value or the determined LDPC base matrix or sequence. Afterwards, the receiver determines the block size value according to N CRC CRC check is performed by the fact that a CRC is attached to the LDPC-decoded transport block, thereby detecting an error.

[0531] Fig.30 is an exemplary diagram of another embodiment, illustrating a method in which a transmitter variably determines the number of CRC bits to be appended to a transport block according to the characteristics of the LDPC code described above.

[0532] In step 3010, the TBS is determined, and in step 3020, the transmitter determines the LDPC base matrix or sequence.

[0533] In addition, in step 3030, the transmitter determines which LDPC base matrix or sequence was determined in step 3020. If the first LDPC base matrix or sequence is not selected, the transmitter determines the number of CRC bits N CRC is the predetermined number X.

[0534] If the first LDPC base matrix or sequence is selected, the transmitter determines an appropriate value for the number of CRC bits based on the TBS.

[0535] Specifically, in step 3050, the transmitter determines whether TBS is greater than a predetermined reference value K Th,CRC Reference value K Th,CRC It can be expressed as a CBS threshold related to CRC, which is a reference value for determining the length of CRC. Th,CRC , then in step 3060, the transmitter may determine N CRC is the predetermined number Y 1 If TBS is greater than the reference value, then in step 3070, the transmitter determines N CRC is the predetermined number Y 2 In this case, Y 1 and Y 2 Have different integer values.

[0536] In determining N CRC Thereafter, in step 3080, the transmitter applies CRC coding to the transport block, thereby generating N CRC CRC bits.

[0537] In addition, the transmitter appends the generated CRC bits to the transport block, and then appropriately performs LDPC encoding.A block size (Z) value needs to be determined for LDPC encoding, and the block size value may be variably determined according to a TBS value or a determined LDPC base matrix or sequence.

[0538] Fig.31 Another embodiment of a method for variably determining, by a transmitter, the number of CRC bits to be appended to a transport block in view of characteristics of an LDPC code is shown in FIG.

[0539] Fig.31 is an exemplary diagram of changing the number of CRC bits to be appended to a transport block according to an LDPC base matrix to be applied to encoding according to another embodiment.

[0540] If the MCS is determined in step 3100, the TBS and the code rate may be determined according to the MCS in steps 3110 and 3120, respectively.

[0541] In step 3130, the transmitter may determine an LDPC base matrix or sequence for performing encoding according to the TBS and the code rate. As a method for determining the LDPC base matrix or sequence, the Figure 21 to Figure 27 After determining the LDPC base matrix or sequence in step 3130, the process of determining the number of CRC bits is the same as Fig.30 The process after step 3030 in is the same.

[0542] In step 3190, the transmitter applies CRC coding to the transport block, thereby generating N CRC CRC bits are generated, the generated CRC bits are appended to the transport block, and then LDPC encoding is appropriately performed. A block size (Z) value needs to be determined for LDPC encoding, and the block size value may be variably determined according to the TBS value or the determined LDPC base matrix or sequence.

[0543] Fig.32 is an exemplary diagram of a method in which a receiver determines the number of CRC bits appended to a transport block in view of characteristics of an LDPC code and thus performs a CRC check.

[0544] The receiver may receive a signal regarding the LDPC encoded transport block and CRC bits.

[0545] Thereafter, in step 3210, TBS is determined, and in step 3220, an LDPC base matrix or sequence is determined. In step 3230, the receiver determines which LDPC base matrix or sequence has been determined. If the first LDPC base matrix or sequence is not selected, the receiver determines the number of CRC bits NCRC is the predetermined number X.

[0546] If the first LDPC base matrix or sequence is selected, the receiver determines an appropriate value for the number of CRC bits based on the TBS.

[0547] Specifically, in step 3250, the receiver confirms whether TBS is greater than a predetermined reference value K Th,CRC Reference value K Th,CRC It can be expressed as a CBS threshold related to CRC, which is a reference value for determining the length of CRC. Th,CRC , then in step 3260, the receiver may determine N CRC is the predetermined number Y 1 If TBS is greater than the reference value, then in step 3270, the receiver determines N CRC is the predetermined number Y 2 In this case, Y 1 and Y 2 have different integer values.

[0548] In step 3280, the receiver performs LDPC decoding 3280 on the received LDPC coded transport block and CRC bits according to the LDPC base matrix or sequence determined in step 3220. Next, the receiver performs LDPC decoding 3280 on the received LDPC coded transport block and CRC bits according to the LDPC base matrix or sequence determined in step 3220. CRC Due to the fact that CRC bits are attached to the LDPC decoded transport block, a CRC check is performed in the final step 3290, thereby detecting errors.

[0549] A block size (Z) value for LDPC decoding needs to be determined, and the block size value may be variably determined according to a TBS value or a determined LDPC base matrix or sequence.

[0550] Fig.33 and Fig.34 It is shown that when based on Fig.19a and Fig.20a Schematic diagram of FAR performance according to each code rate and CBS when LDPC encoding and decoding are applied to the base matrix in Equations 15 to 18.

[0551] Assume that the FAR required by the system is FAR T , the CRC bits need to be at least FAR is achieved only by CRC T In this paper, ( x ) means equal to or greater than x The smallest integer among the integers.

[0552] However, as in Fig.33 and Fig.34As shown in , the advantage of LDPC codes is that since a certain degree of FAR can be overcome by itself during decoding through functions such as fault detection, CRC bits can be reduced to a certain extent. Theoretically, assuming that the maximum value of FAR that LDPC codes can overcome is FAR LDPC , it can be reduced to at least ( -log 2 (FAR LDPC )) That is, when using Fig.19a and Fig.20a The base matrix of LDPC encoding and decoding technology in the system, the system required FAR T It can be obtained by simply using N as defined in the following formula 24 or formula 25 CRC CRC bits to achieve:

[0553] [Equation 24]

[0554]

[0555] [Formula 25]

[0556]

[0557] As a specific example, if By system configuration, , and therefore a total of 20 CRC bits are required. However, since Fig.33 If 128≤K≤192, the maximum FAR value is close to 0.026. Therefore, if the required number of CRC bits is calculated based on equation 24 or equation 25, we can get Therefore, this means that if the reference value K of TBS Th exist Fig.32 is configured as 192, then Y 1 The value can be configured to be equal to or less than Obviously, this is just an example, according to FAR T 、FAR LDPC or other system requirements, various values ​​are applicable. Fig.33 If TBS=512, then FAR has an approximate value of about 0.0013. If the size of TBS is always 512, then only N CRC =11 CRC bits are sufficient to obtain the FAR required by the system.

[0558] It can be confirmed that Fig.34 In the example, if the necessary CRC bits are calculated from the TBS by a similar method, about 12 to 15 bits are required. However, if the TBS size is small and the code rate is high, the FAR tends to increase. Fig.20a The LDPC encoding and decoding of the base matrix is ​​suitable for supporting relatively small TBS. Therefore, if enough CRC bits are used, the overhead increases while the system stability improves. Taking this into account, it is necessary to determine the appropriate number of CRC bits.

[0559] For example, if in Fig.32 Lieutenant General K Th Configured to 512, and if X=16, Y 1 =16,Y 2 =12, then not only can the required FAR of the system be fully achieved, but also the overhead can be reduced. As another example, even if X=24 is fixed by other system requirements, Y 1 =24, or by configuring 2 =12 to get the overhead reduction effect.

[0560] It should also be understood that due to Fig.33 and Fig.34 The FAR performance in shows different characteristics depending on the code rate, and thus different numbers of CRC bits can be applied in combination with a method for variably determining the number of CRC bits according not only to the TBS and LDPC base matrices but also to the code rate.

[0561] exist Fig.35 Another embodiment of a method in which a transmitter variably determines the number of CRC bits to be appended to a transport block in view of characteristics of an LDPC code is shown in FIG.

[0562] Fig.35 is another exemplary diagram of changing the number of CRC bits to be appended to a transport block according to an LDPC base matrix to be applied to encoding according to an embodiment.

[0563] After determining the TBS in step 3510, in step 3511, the transmitter can determine the LDPC base matrix or sequence used to perform encoding.

[0564] Obviously, in the process of determining the LDPC base matrix or sequence in step 3511, the LDPC base matrix or sequence can be determined not only according to TBS but also according to other additional conditions. In addition, as a method for determining the LDPC base matrix or sequence, Figure 21 to Figure 27 One or a portion of the methods shown.

[0565] In step 3512 , the transmitter confirms which LDPC base matrix or sequence was determined in step 3511 .

[0566] If the LDPC base matrix or sequence determined in step 3511 is not the first LDPC base matrix or sequence, then in step 3513, the transmitter may use a predetermined first CB reference value K Th1,CRC Compare with TBS. First CBS reference value K Th1,CRC It can also be called the first threshold value related to CRC, which is a reference value for determining CRC. In addition, the transmitter determines the number of CRC bits N in steps 3514 and 3515 according to the comparison result. CRC In this case, X 1 and X 2 are different integers.

[0567] Specifically, if TBS is greater than K Th1,CRC , then in step 3514, the transmitter can determine that the number of CRC bits is X 1 If TBS is not greater than K Th1,CRC , then in step 3515, the transmitter can determine that the number of CRC bits is X 2 .

[0568] If the LDPC base matrix or sequence determined in step 3511 is the first LDPC base matrix or sequence, then in step 3516, the transmitter may compare the TBS with a predetermined second CBS reference value K Th2,CRC The second CBS reference value K Th2,CRC It can also be called the second threshold value related to CRC, which is a reference value for determining CRC. In addition, the transmitter determines the number of CRC bits N in steps 3517 and 3518 according to the comparison results. CRC In this case, Y 1 and Y 2 are different integers.

[0569] Specifically, if TBS is greater than K Th2,CRC , then in step 3517, the transmitter can determine that the number of CRC bits is Y 1 If TBS is not greater than K Th2,CRC , then in step 3518, the transmitter can determine that the number of CRC bits is Y 2 .

[0570] In addition, in step 3519, the transmitter applies CRC coding to the transport block, thereby generating N CRC CRC bits. In addition, the generated CRC bits are attached to the transport block, and LDPC encoding is performed appropriately. A block size (Z) value for LDPC encoding needs to be determined, and the block size value can be variably determined according to the TBS value.

[0571] Fig.36is another exemplary diagram of an embodiment of a method for determining, by a receiver, the number of CRC bits appended to a transport block in view of characteristics of an LDPC code.

[0572] The receiver may receive a signal regarding the LDPC encoded transport block and CRC bits.

[0573] The TBS is determined in step 3610, and the receiver determines an LDPC base matrix or sequence in step 3611. In step 3612, the receiver determines which LDPC base matrix or sequence was determined in step 3611.

[0574] If the LDPC base matrix or sequence determined in step 3611 is not the first LDPC base matrix or sequence, then in step 3613, the receiver may use a predetermined first CBS reference value K Th1,CRC Compare with TBS. First CBS reference value K Th1,CRC It may also be referred to as the first threshold related to CRC, which is a reference value for determining CRC.

[0575] In addition, the receiver determines the number of CRC bits N in steps 3614 and 3615 based on the comparison results. CRC In this case, X 1 and X 2 are different integers.

[0576] Specifically, if TBS is greater than K Th1,CRC , then in step 3614, the receiver can determine that the number of CRC bits is X 1 If TBS is not greater than K Th1,CRC , then in step 3615, the receiver can determine that the number of CRC bits is X 2 .

[0577] If the LDPC base matrix or sequence determined in step 3611 is the first LDPC base matrix or sequence, then in step 3616, the receiver may compare the TBS with a predetermined second CBS reference value K Th2,CRC The second CBS reference value K Th2,CRC It can also be called the second threshold value related to CRC, which is a reference value for determining CRC. In addition, the receiver determines the number of CRC bits N in steps 3617 and 3618 according to the comparison results. CRC In this case, Y 1 and Y 2 are different integers.

[0578] Specifically, if TBS is greater than K Th2,CRC , then in step 3617, the receiver can determine that the number of CRC bits is Y 1 If TBS is not greater than KTh2,CRC , then in step 3618, the receiver can determine that the number of CRC bits is Y 2 .

[0579] In addition, in step 3620, the receiver performs LDPC decoding on the received LDPC-coded transport block and CRC bits according to the LDPC base matrix or sequence determined in step 3611. CRC The fact that CRC bits are attached to the LDPC decoded transport block causes a CRC check to be performed in the final step 3619, thereby detecting errors.

[0580] For reference, in Fig.35 and Fig.36 In, X 1 =X 2 and Y 1 = Y 2 One of the two may be true, and X 1 =X 2 and Y 1 = Y 2 In addition, if necessary, configuration can be performed to satisfy K Th1,CRC = K Th2,CRC If the configuration is performed so that K Th1 = K Th2 , X 1 =X 2 and Y 1 = Y 2 , then all steps 3520 or 3612, and steps 3560 to 3580 or steps 3616 to 3618 can be omitted. Fig.35 and Fig.36 Only the case of determining TBS in steps 3510 and 3610 is shown, but it can be changed to a step of determining CBS instead of TBS.

[0581] Although referenced Figures 29 to 36 Only the CRC bits appended to the transport block are described, but the CRC bits appended to the code block can generally be determined by applying a similar method.

[0582] Fig.37 is an exemplary schematic diagram of a method for segmenting a transport block according to an embodiment.

[0583] For example, if Fig.37The TBS in the transport block is usually large, so it is divided into multiple code blocks and then channel encoded and decoded. In this way, it can be assumed that the system is configured so that: if segmentation is applied to the transport block to divide it into multiple code blocks, it is necessary to append code block CRC (CB-CRC) bits to each of all code blocks or to each of some code blocks.

[0584] refer to Fig.37 , if the length of the transport block and the transport CRC bits obtained after performing CRC encoding on the transport block exceeds a specific length, the transmitter may segment the transport block into a plurality of code blocks.

[0585] In addition, after segmenting the transport block into a plurality of code blocks, the transmitter performs CRC encoding on each of all code blocks or on each of some code blocks so that code block CRC bits are attached to the code blocks that have undergone CRC encoding.

[0586] Likewise, during the decoding process, the receiver receives signals regarding LDPC-encoded transport blocks and transport block CRC bits, performs LDPC decoding on each code block, performs error detection on the code block CRC, and performs error detection on the transport block CRC based on the results.

[0587] In this case, by adding a code block CRC, a beneficial effect of further reducing the FAR of the transport block can be expected, and thus the number of transport block CRC (TB-CRC) bits can be reduced. Fig.37 As in the example, the number of bits of the transport block CRC is called N TB,CRC , and the number of code block CRC bits is called N CB,CRC .

[0588] Fig.38 FIG. 4 is an exemplary diagram of a method for determining the number of transport block CRC and code block CRC bits according to a TBS and whether segmentation is performed according to an embodiment.

[0589] refer to Fig.38 After determining the TBS in step 3810, in step 3820, the transmitter may determine whether it is necessary to apply transport block segmentation based on the size of the TBS so as to divide it into a plurality of code blocks.

[0590] If segmentation is required, then in step 3830, the transmitter determines the number N of CRC bits to append to the transport block. TB,CRC Yes X 1 , and the number N of CRC bits to be appended to the code block CB,CRC It is Y.

[0591] On the other hand, if it is determined in step 3820 that segmentation is not required, then in step 3840, the transmitter determines N TB,CRC Yes X2 In this case, X 1 Can always be less than X 2 Or it can be equal to X 2 .

[0592] The above processing also applies to the decoding process.

[0593] Fig.38 The encoding process in can be summarized as follows. The transmitter determines the transport block size (TBS), determines whether segmentation is applied to the transport block, and determines the number of CRC bits N to be appended to the transport block according to whether segmentation is applied. TB,CRC .

[0594] In addition, the transmitter determines the number of CRC bits N TB,CRC CRC encoding is performed on the transport block, and then LDPC encoding is performed on the transport block and the code block of CRC bits. It should be noted that the number of CRC bits to be appended to the transport block when segmentation is applied is less than or equal to the number of CRC bits to be appended to the transport block when segmentation is not applied.

[0595] A specific example will be described in this regard. Assume that if segmentation is not required according to the TBS value, the transmitter always adds 24 (= X 2 ) transport block CRC bits to achieve the required FAR for the system. In addition, assuming that if segmentation is performed according to the TBS value, the transmitter appends 16 (=Y) code block CRC bits, the FAR required by the receiver of the system can be reduced by configuring the number of transport block CRC bits to 8 (=X 1 ) to meet the requirement. Theoretically, if the number of segment code blocks is N seg (>1), and if N CB,CRC CRC bits are appended to each code block, the FAR required by the system can be achieved by determining the number of CRC bits to satisfy the following equation 26:

[0596] [Equation 26]

[0597]

[0598] According to the above formula 26, if X 2 =24, and if Y=8, then in configuration X 1 =8, regardless of N seg The above formula is always valid regardless of the value of (>1). It can be understood that even if Y=8, X 1 =16,X 2 =24, the above formula is always valid.

[0599] In this way, X can be pre-configured 2On the other hand, the Y value can be determined according to the number of segments. For example, the Y value can be configured to decrease inversely proportional to the increasing number of segments.

[0600] Fig.39 is another exemplary schematic diagram of a method for determining the number of transport block CRC and code block CRC bits according to a TBS and whether segmentation is performed according to an embodiment.

[0601] refer to Fig.39 , steps 3910 to 3930 are similar to those in reference Fig.38 The steps 3810 to 3830 described in are the same as those described in the previous section, and their repeated description will be omitted here.

[0602] On the other hand, it is clear that if the transport blocks are not segmented, the transmitter can Fig.35 Step 3500 in step 3940 is combined with the process of determining the CRC bits in step 3940, so that Fig.38 Unlike the case where the CRC bit is determined as X2, the CRC bit is determined more specifically.

[0603] The decoding process is very similar to the inverse process of the encoding process described above. The decoding process can be summarized as follows.

[0604] The receiver may receive a signal regarding the LDPC encoded transport block and CRC bits.

[0605] The receiver may determine a transport block size (TBS) from the received signal and may determine whether to apply segmentation to the transport block.

[0606] The receiver determines the number N of CRC bits to append to the transport block based on whether segmentation is applied. TB,CRC .

[0607] The receiver performs LDPC decoding on the received coded transport block and the code block of CRC bits. After LDPC decoding is completed, the receiver determines the number of CRC bits N TB,CRC CRC error detection is performed on the LDPC decoded transport blocks and CRC bits.

[0608] If the transport block is segmented into multiple code blocks, it also includes calculating the number of CRC bits N appended to each code block CB,CRC The process and given that N CB,CRC The process of detecting errors in the code block using CRC bits.

[0609] Likewise, when segmentation is applied, the number of CRC bits appended to the transport block may be less than or equal to the number of CRC bits appended to the transport block when segmentation is not applied.

[0610] exist Fig.40 The decoding process is schematically shown in FIG.

[0611] Fig.40 is an exemplary diagram of determining the number of transport block CRC and code block CRC bits according to the TBS and whether segmentation is performed and thus performing CRC check by a receiver according to an embodiment.

[0612] The TBS is determined in step 4010, and in step 4020, the receiver may determine whether it is necessary to apply transport block segmentation so as to divide it into a plurality of code blocks according to the size of the TBS.

[0613] If segmentation is required, then in step 4030, the receiver determines the number N of CRC bits to append to the transport block. TB,CRC Yes X 1 , and the number N of CRC bits to be appended to the code block CB,CRC It is Y.

[0614] If it is determined in step 4020 that segmentation is not required, then in step 4040, the receiver determines N TB,CRC Yes X 2 However, the embodiments of the present disclosure are not limited thereto, and the receiver may be configured according to Fig.35 3500 in the formula to determine N TB,CRC .

[0615] In this case, X 1 Need to always be less than X 2 or equal to X 2 After determining the number of CRC bits as described above, the receiver performs LDPC decoding on each code block according to the received signal as in steps 4050 and 4060.

[0616] If segmentation has been applied to the transport block so that it is divided into a plurality of code blocks, then in step 4070, the receiver respectively considers N CB,CRC CRC bits perform CRC detection on the LDPC decoded code blocks. If all code blocks have passed the CRC detection, then in step 4071, the receiver combines the code blocks and considers N TB,CRC The CRC bits perform a CRC check on the recovered transport block.

[0617] If segmentation is not applied to the transport block, then the receiver only considers N TB,CRC The CRC bits perform LDPC decoding on the recovered transport block and perform CRC detection.

[0618] Hereinafter, another embodiment of a method for selecting a base matrix or an exponential matrix to be applied to LDPC coding according to CBS or TBS and a code rate will be described. Fig.41 Describe the criteria used to select the first basis matrix and the second basis matrix.

[0619] refer to Fig.41 , Fig.41 The range of selecting the first base matrix and the area of ​​selecting the second base matrix according to TBS and code rate are shown. The first base matrix in the present disclosure may correspond to the reference Fig.19a The base matrix described in the present disclosure may correspond to the base matrix of reference Fig.20a However, the embodiments of the present disclosure are not limited thereto, and the first base matrix may correspond to the reference Fig.20a The basis matrix described, and the second basis matrix can correspond to the reference Fig.19a In addition, the first base matrix and the second base matrix in the present disclosure may correspond to two different base matrices configured separately.

[0620] In order to describe the corresponding Fig.41 The operation of the transmitter, in Fig.42 An exemplary schematic diagram of a flow chart regarding a transmitter is shown in FIG.

[0621] If the MCS for transmission is determined by the system, the transmitter may determine the TBS and the transmission code rate corresponding thereto in steps 4210 and 4220, respectively.

[0622] In step 4230, the transmitter may compare the determined code rate (R) value with a predetermined first code rate reference value R Th1 A comparison is made to determine whether a certain condition is met.

[0623] according to Fig.41 , if the code rate (R) value is less than the first code rate reference value R Th1 , then in step 4240, the transmitter may perform encoding based on a second LDPC base matrix (or LDPC sequence).

[0624] If the code rate (R) value is greater than the first code rate reference value R Th1 , then in step 4250, the transmitter may compare the TBS size with the first TBS reference value K Th1 A comparison is made to determine whether a certain condition is met.

[0625] exist Fig.42 If the TBS size is greater than the first TBS reference value K Th1 , then in step 4290, the transmitter may perform encoding based on a first LDPC base matrix (or LDPC sequence).

[0626] On the other hand, if the TBS size is less than or equal to the first TBS reference value K Th1 , the transmitter can compare the code rate (R) value with the predetermined second code rate reference value R Th2If the determined code rate (R) value is less than or equal to the second code rate reference value R Th2 , then in step 4240, the transmitter may perform encoding based on a second LDPC base matrix (or LDPC sequence).

[0627] If the determined code rate (R) is greater than the second code rate reference value R Th2 , then in step 4270, the transmitter may compare the TBS size with the second TBS reference value K Th2 A comparison is made to determine whether a certain condition is met.

[0628] If the TBS size is greater than the second TBS reference value K Th2 , then in step 4290, the transmitter may perform encoding based on a first LDPC base matrix (or LDPC sequence).

[0629] If the TBS value is equal to or less than the second TBS reference value K Th2 , the transmitter can compare the determined code rate (R) value with the predetermined third code rate value R Th3 A comparison is made to determine whether a certain condition is met.

[0630] If the determined code rate (R) value is less than or equal to the third code rate reference value R Th3 , then in step 4240, the transmitter may perform encoding based on the second LDPC base matrix (or LDPC sequence). If the determined code rate (R) is greater than the third code rate reference value R Th3 , then in step 4290, the transmitter may perform encoding based on a first LDPC base matrix (or LDPC sequence).

[0631] The receiver determines the base matrix or LDPC sequence to be used for LDPC encoding through a process similar to the operation of the transmitter.

[0632] Fig.43 is another exemplary schematic diagram of a method in which a receiver determines a base matrix according to TBS and a code rate.

[0633] First, since the receiver can obtain information about the MCS or information about the TBS from the received signal, the receiver can determine the TBS and the transmission code rate in steps 4310 and 4320, respectively.

[0634] In step 4330, the receiver may compare the determined code rate (R) value with a predetermined first code rate reference value R Th1 A comparison is made to determine whether a certain condition is met.

[0635] If the code rate (R) value is less than the first code rate reference value R Th1, then in step 4340, the receiver may perform decoding based on the second LDPC base matrix (or LDPC sequence). If the code rate (R) value is greater than the first code rate reference value R Th1 , then in step 4350, the receiver may compare the TBS size with the first TBS reference value K Th1 A comparison is made to determine whether a certain condition is met.

[0636] If the TBS size is greater than the first TBS reference value K Th1 , then in step 4390, the receiver may perform decoding based on the first LDPC base matrix (or LDPC sequence).

[0637] If the TBS size is less than or equal to the first TBS reference value K Th1 , the receiver can compare the code rate (R) value with the predetermined second code rate reference value R Th2 If the determined code rate (R) value is less than or equal to the second code rate reference value R Th2 , then in step 4340, the receiver may perform decoding based on a second LDPC base matrix (or LDPC sequence).

[0638] If the determined code rate (R) is greater than the second code rate reference value R Th2 , then in step 4370, the receiver may compare the TBS size with the second TBS reference value K Th2 A comparison is made to determine whether a certain condition is met.

[0639] If the TBS size is greater than the second TBS reference value K Th2 , then in step 4390, the receiver may perform decoding based on the first LDPC base matrix (or LDPC sequence).

[0640] If the TBS value is equal to or less than the second TBS reference value K Th2 , the receiver can compare the determined code rate (R) value with the predetermined third code rate value R Th3 A comparison is made to determine whether a certain condition is met.

[0641] It can be understood that if the determined code rate (R) value is less than or equal to the third code rate reference value R Th3 , then in step 4340, the receiver performs decoding based on the second LDPC base matrix (or LDPC sequence). It can be understood that if the determined code rate (R) is greater than the third code rate reference value R Th3 , the receiver performs decoding based on the first LDPC base matrix (or LDPC sequence).

[0642] Depending on the length of the TBS, the TB segmentation operation can be added to Fig.42 and Fig.43 The transmitter and receiver are shown in operation.

[0643] Fig.44 is another exemplary schematic diagram of a method in which a transmitter determines a base matrix according to TBS and a code rate.

[0644] refer to Fig.44 , as an embodiment of the present disclosure, as in Fig.42 As in step 4230, the transmitter may compare the code rate (R) value with the predetermined first code rate reference value R Th1 Make a comparison.

[0645] As a result of the comparison, if R is less than or equal to the first code rate reference value R Th1 , then in step 4410, the transmitter determines whether the determined TBS is less than or equal to the first TBS reference value K Th1 If it is determined that the TBS is less than or equal to the first TBS reference value, the transmitter performs LDPC encoding based on a second base matrix or sequence without segmentation.

[0646] However, if it is determined in step 4410 that the determined TBS is greater than the first TBS reference value K Th1 , then in step 4420, the transmitter appropriately segments the given TB to generate multiple code blocks, and performs LDPC encoding on each code block based on a second LDPC base matrix or sequence.

[0647] If the code rate R is greater than the first code rate R Th1 , then as in Fig.42 As in step 4250, the transmitter may compare the TBS value with a predetermined first TBS reference value K Th1 Make a comparison.

[0648] If the TBS value is greater than the first TBS reference value, then in step 4430, the transmitter may determine whether the determined TBS is less than or equal to a third TBS reference value K Th3 .

[0649] If the determined TBS is less than or equal to the third TBS reference value, the transmitter performs LDPC encoding based on the first LDPC base matrix or sequence without TB segmentation.

[0650] However, if it is confirmed that the determined TBS is greater than the third TBS reference value K Th3 , then in step 4440, the transmitter appropriately segments the given TB to generate multiple code blocks, and performs LDPC encoding on each code block based on a first LDPC base matrix or sequence.

[0651] On the other hand, if it is determined in step 4250 that the TBS value is less than or equal to the first TBS reference value, the transmitter may perform steps 4260 to 4280, and the details thereof are the same as those of the reference value. Fig.42 The description is the same.

[0652] Fig.45 is another exemplary schematic diagram of a method in which a receiver determines a base matrix according to TBS and a code rate.

[0653] refer to Fig.45 , as in Fig.43 As in step 4330, the receiver may compare the determined code rate (R) value with a predetermined first code rate reference value R Th1 Make a comparison.

[0654] As a result of the comparison, if R is less than the first code rate reference value R Th1 , then in step 4510, the receiver determines whether the determined TBS is less than or equal to the first TBS reference value K Th1 If it is determined that the TBS is less than or equal to the first TBS reference value, the receiver performs LDPC decoding based on a second LDPC base matrix or sequence without applying segmentation to the received TB block.

[0655] However, if it is determined in step 4510 that the determined TBS is greater than the first TBS reference value K Th1 , then in step 4520, the receiver appropriately segments the received TB to generate multiple received code blocks, and performs LDPC decoding on each received code block based on a second LDPC base matrix or sequence.

[0656] If the code rate R is greater than the first code rate R Th1 , then as in Fig.43 As in step 4350, the receiver may compare the TBS value with the predetermined first TBS reference value K Th1 Make a comparison.

[0657] If the TBS value is greater than the first TBS reference value, then in step 4530, the receiver may determine whether the determined TBS is less than or equal to a third TBS reference value K. Th3 .

[0658] If the determined TBS is less than or equal to the third TBS reference value, the receiver performs LDPC decoding based on the first LDPC base matrix or sequence without TB segmentation.

[0659] However, if it is confirmed that the determined TBS is greater than the third TBS reference value K Th3, the receiver appropriately segments the received TB to generate multiple received code blocks, and performs LDPC decoding on each received code block based on the first LDPC base matrix or sequence.

[0660] On the other hand, if it is confirmed in step 4350 that the TBS value is less than or equal to the first TBS reference value, the transmitter may perform steps 4260 to 4280, and the details thereof are the same as those of the reference value. Fig.42 The description is the same.

[0661] For reference, received TBs and received code blocks may refer to received signals corresponding to transmitted TBs and code blocks, or may refer to values ​​(eg, LLRs or quantized values ​​of received signals) stored from received signals so that a receiver can perform decoding.

[0662] The operation of the transmitter can be summarized as follows. The transmitter first determines the size of the TB (TBS) to be transmitted and the transmission code rate (R). After that, the transmitter performs a comparison between the code rate (R) and the first code rate reference value R. Th1 , the second code rate reference value R Th2 and the third code rate reference value R Th3 The process of comparing TBS with the first TBS reference value K Th1 , the second TBS reference value K Th2 and the third TBS reference value K Th3 A process of comparing at least one of the first LDPC base matrix (or sequence) and the second LDPC base matrix (or sequence) and performing LDPC encoding is performed according to the code rate (R) and the size of TBS.

[0663] The operation of the receiver can be summarized as follows. The receiver first determines the size of the transmitted TB (TBS) and the transmission code rate (R) based on the received signal. After that, the receiver performs a comparison between the code rate R and the first code rate reference value R. Th1 , the second code rate reference value R Th2 and the third code rate reference value R Th3 The process of comparing TBS with the first TBS reference value K Th1 , the second TBS reference value K Th2 and the third TBS reference value K Th3 A process of comparing at least one of them, and a process of determining one from the first LDPC base matrix (or sequence) and the second LDPC base matrix (or sequence) according to the code rate R and the size of TBS and performing LDPC decoding.

[0664] Fig.41The case where encoding and decoding are performed based on the first LDPC base matrix (or sequence) and the second LDPC base matrix (or sequence) in the second LDPC base matrix (or sequence) corresponds to the case where one of the conditions in the following equation 27 is satisfied. Otherwise, encoding and decoding are performed based on the first LDPC base matrix (or sequence).

[0665] [Formula 27]

[0666] Condition 1) R ≤ R Th1

[0667] Condition 2) R ≤ R Th2 And TBS ≤ K Th1

[0668] Condition 3) R ≤ R Th3 And TBS ≤ K Th2

[0669] In addition, the case where LDPC encoding and decoding are performed after TB segmentation is additionally applied corresponds to the case where one of the equations in the following Equation 28 is satisfied.

[0670] [Equation 28]

[0671] Condition 1) R ≤ R Th1 And TBS > K Th1

[0672] Condition 2) R > R Th1 And TBS > K Th3

[0673] The feature is that if condition 1) is satisfied in the above equation 28, TB segmentation is performed, and then encoding and decoding are performed based on the second LDPC base matrix (or sequence). If condition 2) is satisfied, encoding and decoding are performed based on the first LDPC base matrix (or sequence).

[0674] It should be noted that as including the first code rate reference value R Th1 , the second code rate reference value R Th2 , the third code rate reference value R Th3 , the first TBS reference value K Th1 , the second TBS reference value K Th2 and the third TBS reference value K Th3 The above-mentioned reference values ​​may use values ​​pre-configured by the system, or may use values ​​that vary according to system conditions.

[0675] For example, one can use a Th1 = 3824, K Th2 = 176, K Th3 = 8424, R Th1 = 0.25, RTh2 =0.67, R Th3 = 5 / 6. Alternatively, a fixed value can be used for K Th1 , K Th2 , K Th3 , R Th2 and R Th3 , such as K Th1 =3824, K Th2 = 176, K Th3 = 8424, R Th2 = 0.67, R Th3 = 5 / 6, and a value that varies depending on conditions such as the amount of allocated system resources or the limited buffer size of the receiver may be used as R Th1 value.

[0676] Will refer to Fig.46 Another embodiment of a method of selecting a base matrix or an exponential matrix applied to LDPC coding according to TBS and a code rate is described.

[0677] refer to Fig.46 , Fig.46 The range of selecting the first base matrix and the area of ​​selecting the second base matrix according to TBS and code rate are shown. The first base matrix in the present disclosure may correspond to the reference Fig.19a The base matrix described in the present disclosure may correspond to the base matrix of reference Fig.20a However, the embodiments of the present disclosure are not limited thereto, and the first base matrix may correspond to the reference Fig.20a The basis matrix described, and the second basis matrix can correspond to the reference Fig.19a In addition, the first base matrix and the second base matrix in the present disclosure may correspond to two different base matrices configured separately.

[0678] Fig.46 This means that the system does not consider the case of having a specific TBS and a specific bit rate (R). In other words, Fig.46 The undefined area in may not be used depending on the system, and may also be freely determined by the transmitter and receiver without considering the standard.

[0679] As Fig.46 For example, if the system does not use the case corresponding to TBS and bit rate range, then different from Figure 42 to Figure 45 The operation flow chart of the transmitter and receiver shown in Fig.47 and Fig.48 As shown in FIG. 1 , the determined TBS and code rate R and the third TBS reference value K may be omitted. Th3 and the third code rate reference value R Th3 The process of making comparisons.

[0680] Fig.46 The case where encoding and decoding are performed based on the first LDPC base matrix (or sequence) and the second LDPC base matrix (or sequence) in the second LDPC base matrix (or sequence) corresponds to the case where one of the conditions in the following Equation 29 is satisfied.

[0681] [Equation 29]

[0682] Condition 1) R ≤ R Th1

[0683] Condition 2) R ≤ R Th2 And TBS ≤ K Th2

[0684] In addition, the case where encoding and decoding are performed based on the first LDPC base matrix (or sequence) corresponds to the case where one of the conditions in the following Equation 30 is satisfied.

[0685] [Formula 30]

[0686] Condition 1) R > R Th3

[0687] Condition 2) R > R Th2 And TBS > K Th3

[0688] Condition 3) R > R Th1 And TBS > K Th2

[0689] It should be noted that the region defined in the above equations 29 and 30 does not include the region satisfying R Th2 <R≤R Th3 And TBS ≤ K Th3 area.

[0690] In addition, when one of the conditions in the above formula 28 is satisfied, LDPC encoding and decoding are performed after TB segmentation is additionally applied. It is characterized in that if condition 1) is satisfied in the above formula 28, TB segmentation is performed, and then encoding and decoding are performed based on the second LDPC base matrix (or sequence). If condition 2) is satisfied, encoding and decoding are performed based on the first LDPC base matrix (or sequence).

[0691] The LDPC encoding and decoding methods described above are characterized in that they are based on an LDPC base matrix (or sequence) determined according to a CBS or TBS and a transmission code rate (R). However, the transmission code rate can be defined in various ways, which will now be described. Although the transmission code rate is referred to as R in this article for ease of description, it is clear that the transmission code rate (e.g., R_T, R_init, etc.) can be represented in various ways depending on the system.

[0692] Hereinafter, a process of determining a transmission code rate for LDPC encoding and decoding and a process of determining main parameters related to an LDPC code will be described.

[0693] The parameters used for description are briefly defined as follows:

[0694] -R nominal : A code rate associated with the MCS. It may be signaled in the control information or may be determined based on information signaled in the control information.

[0695] -R limit : A code rate that can be determined based on user equipment (UE) category information. Generally, it refers to the minimum code rate for rate matching determined by the buffer size. Determined by a given buffer size may mean that repetition of codeword bits is not considered (for reference, the buffer size used here refers to the space in which the received signal can be appropriately converted and stored so that decoding can be performed on the received TB).

[0696] -R_init: refers to the code rate (R) defined in this disclosure to determine the LDPC base matrix. This value can be based on R nominal and R limit And sure.

[0697] -BG index: represents the index of the LDPC base matrix. It can be represented in various ways. For example, the first base matrix (or sequence) can be represented as BG#1, and the second base matrix (or sequence) can be represented as BG#2. It can be determined based on TBS and R_init.

[0698] -K cb : Maximum code block size corresponding to the selected basis matrix or BG index.

[0699] -C: by TBS and K cb Determine the number of code blocks.

[0700] -K': refers to the number of information bits per code block and is determined based on TBS and C values. The information word bits include CRC bits. It can be defined to include or exclude padding bits.

[0701] -N TBCRC : The number of CRC bits appended to the TB.

[0702] -Z C , K b : Parameters used for LDPC encoding and decoding, which are necessary values ​​for defining the parity check matrix.

[0703] Given below is an exemplary representation of a process of selecting a base matrix of an LDPC code based on the parameters defined above and a portion of the encoding or decoding process.

[0704] Process Example 1:

[0705] Step 1) Signal TBS and R in the control information nominal .

[0706] R nominal is the nominal code rate that is signaled in the control information to schedule the transmission of transport blocks.

[0707] Step 2) R can be determined from UE category information limit .

[0708] R limit It is the lower limit of the bit rate based on a limited circular buffer.

[0709] Step 3) Determine R init

[0710] Rinit = max(R nominal , R limit )

[0711] Step 4) Use TBS and R init Select base map

[0712] BG#1, for (TBS<=3840, R init > 0.67) or (TBS>3840, R init > 0.25)

[0713] BG#2, for (TBS<=3840, R init <= 0.67) or (TBS>3840, R init <= 0.25)

[0714] Step 5) Determine the maximum code block size K based on the BG index cb

[0715] K cb = 8448 for BG#1

[0716] K cb = 3840 for BG#2

[0717] Step 6) Use TBS and K cb Calculate the number of code blocks C

[0718] If TBS + N TBCRC < K cb , then C = 1;

[0719] Otherwise, C = (TBS + N TBCRC ) / (K cb - twenty four)

[0720] If TBS <= 3824, then N_ TBCRC = 16, otherwise, N_ TBCRC = 24.

[0721] Step 7) Calculate the number of information bits (including CRC bits) of the code block using TBS and C.

[0722] If C = 1, then K' = TBS + N TBCRC ;

[0723] Otherwise, K'= (TBS + N TBCRC ) / C + 24

[0724] Step 8) Use K' and BG index to perform K b choose

[0725] Step 9) Use K b Z with CBS c choose.

[0726] Step 10) Use Z c PCM selection with BG index

[0727] To describe another embodiment of the present disclosure, additional parameters are defined as follows:

[0728] -N soft : Refers to the total buffer size that the receiver can use. It can be determined based on UE category information.

[0729] -K C : Parameters related to the maximum allowed carrier aggregation (CA). It can be based on N soft And sure.

[0730] -K MIMO : Parameters related to transmit diversity determined by the transmit mode.

[0731] -M DL_HARQ : Maximum number of downlink HARQ (DL HARQ) processes

[0732] -M limit : A value related to the number of downlink HARQ (DL HARQ) processes. It can be a pre-committed value, signaled in control information, or based on N soft Value determined (8 in LTE)

[0733] -NIR : refers to the buffer size that the receiver can use per TB. It can be based on N soft , K C , K MIMO 、M DL_HARQ 、M limit The value is determined by at least two parameters.

[0734] -C1, C2: refers to the number of code blocks when using the first LDPC base matrix (or sequence) and the second LDPC base matrix (or sequence), respectively, which can be based on TBS and N IR And sure.

[0735] -K 1 ', K 2 ': refers to the number of information word bits of the code block when using the first LDPC base matrix (or sequence) and the second LDPC base matrix (or sequence), which can be based on TBS and N IR And sure.

[0736] -N cb1 、N cb2 : refers to the buffer size corresponding to a code block when using the first LDPC base matrix (or sequence) and the second LDPC base matrix (or sequence), which can be based on TBS and N IR If segmentation has been applied to a given TB, the code block refers to the code block after segmentation.

[0737] Given below is an exemplary representation of a process of selecting a base matrix of an LDPC code based on the parameters defined above and a portion of the encoding or decoding process.

[0738] Process Example 2:

[0739] Step 1) Signal TBS and R in the control information nominal .

[0740] Step 2) N can be determined by UE category soft .

[0741] Step 3) Based on the control information and N soft Determine K C , K MIMO 、M DL_HARQ and M limit .

[0742] Step 4) Use N soft , K C , K MIMO 、M DL_HARQ and M limit Calculate N IR .

[0743] NIR is the soft buffer size for the transmit block

[0744] N IR = floor(N soft / (K C· K MIMO· min(M DL_HARQ· M limit )))

[0745] Step 5) Calculate C1 and C2 using TBS

[0746] C 1 and C 2 are the number of code blocks based on BG#1 and BG#2 parameters respectively.

[0747] If TBS < 8424, then C 1 = 1; otherwise, C 1 = (TBS + 24) / 8424

[0748] If TBS < 3824, then C 2 = 1; otherwise, C 2 = (TBS + 24) / 3816

[0749] Step 6) Use N IR , C 1 and C 2 Calculate N cb1 and N cb2

[0750] N cb1 and N cb2 are the soft buffer sizes of code blocks based on BG#1 and BG#2 parameters, respectively.

[0751] N cb1 = floor(N IR / C1)

[0752] N cb2 = floor(N IR / C2)

[0753] Step 7) Use TBS, C 1 and C 2 Calculate the number of information bits (including CRC bits) of the code block K 1 ' and K 2 '

[0754] If C 1 = 1, then K 1 ' = TBS + N TBCRC Otherwise, K 1' = (TBS + N TBCRC ) / C 2 + 24

[0755] If C 2 = 1, then K 2 ' = TBS + N TBCRC Otherwise, K 2 ' = (TBS + N TBCRC ) / C 2 + 24

[0756] Step 8) Use K2' and N cb2 Calculate R limit

[0757] R limit is the lower limit of the bitrate based on a limited circular buffer using BG#2 parameters

[0758] R limit = K2' / N cb2

[0759] Step 9) Determine R init

[0760] R init = max(R nominal , R limit )

[0761] Step 10) Use TBS and R init Select base map

[0762] BG#1, for (TBS<=3840, R init >0.67) or (TBS>3840, R init >0.25)

[0763] BG#2, for (TBS<=3840, R init <=0.67) or (TBS>3840, R init <=0.25)

[0764] Step 11) Use the base graph index to determine C and K'

[0765] C = C 1 , K' = K 1 ', for BG#1

[0766] C = C 2 , K' = K 2 ', for BG#2

[0767] Step 12) Calculate the number of information bits (including CRC bits) of the code block using TBS and C.

[0768] If C = 1, then K' = TBS + N TBCRC

[0769] Otherwise, K 2 ' = (TBS + N TBCRC ) / C + 24

[0770] If TBS <= 3824 N_ TBCRC = 16, otherwise N_ TBCRC = 24.

[0771] Step 13) Use K' and BG index to perform K b choose

[0772] Step 14) Use K b Z with CBS c choose.

[0773] Step 15) Use Z c PCM selection with BG index

[0774] Compared with process example 1, the biggest difference of process example 2 is that it can be based on N cb2 and K 2 'Determine R limit In this way, based on N cb2 and K 2 'Determine R limit Afterwards, you can use R nominal and R limit To determine R init , and finally according to TBS and R init Determine the BG index or LDPC basis matrix (or sequence).

[0775] The following is a description of how to determine R init Various embodiments of more detailed methods of values.

[0776] R init Determine method 1

[0777] -R nominal is the nominal code rate that is signaled in the control information to schedule the transmission of transport blocks.

[0778] -R limit It is the lower limit of the bit rate based on the limited circular buffer

[0779] -R init = max(R nominal , R limit)

[0780] - Use basemap #1 for initial emission or subsequent re-emission of the same TB when

[0781] - TBS <= 3840 and R init > 0.67

[0782] - TBS > 3840 and R init > 0.25

[0783] - Use basemap #2 for initial emission and subsequent re-emissions of the same TB when

[0784] - TBS <= 3840 and R init <= 0.67

[0785] - TBS > 3840 and R init <= 0.25

[0786] R init Determine method 2

[0787] -R nominal is the nominal code rate that is signaled in the control information to schedule the transmission of transport blocks.

[0788] -R limit = K' / N cb,limit ,in

[0789] - K' is the number of input bits of the code block (including CRC bits and excluding padding bits), and

[0790] -N cb,limit is the finite (or full) circular buffer size used to transmit one code block calculated using the BG#2 parameters

[0791] -R init = max(R nominal , R limit )

[0792] - Use basemap #1 when used for initial emission or subsequent re-emission of the same TB)

[0793] - TBS <= 3840 and R init > 0.67

[0794] - TBS > 3840 and R init > 0.25

[0795] - Use basemap #2 for initial emission and subsequent re-emissions of the same TB in the following cases)

[0796] - TBS <= 3840 and R init <= 0.67

[0797] - TBS > 3840 and R init <= 0.25

[0798] R init Determine method 3

[0799] -R nominal is the nominal code rate that is signaled in the control information to schedule the transmission of transport blocks.

[0800] -R limit = K' / N cb,limit ,in

[0801] - K' is the number of input bits of the code block (including CRC bits and padding bits) and

[0802] -N cb,limit is the finite (or full) circular buffer size used to transmit one code block calculated using the BG#2 parameters

[0803] -R init = max(R nominal , R limit )

[0804] - Basemap #1 is used for initial emission and subsequent re-emission of the same TB in the following cases)

[0805] - TBS <= 3840 and R init > 0.67

[0806] - TBS > 3840 and R init > 0.25

[0807] - Basemap #2 is used for initial emission and subsequent re-emission of the same TB in the following cases)

[0808] - TBS <= 3840 and R init <= 0.67

[0809] - TBS > 3840 and R init <= 0.25

[0810] R init Determine method 4

[0811] -When TBS <= 3824, R init = R nominal

[0812] -R nominal is the nominal code rate and can be signaled in the control information to schedule the transmission of transport blocks.

[0813] -When TBS > 3824, R init = max(R nominal , R limit )

[0814] -R limit = K' / N cb,limit ,in

[0815] - K' is the number of input bits of the code block (including CRC bits and excluding padding bits), and

[0816] -N cb,limit is the finite (or full) circular buffer size used to transmit one code block calculated using the BG#2 parameters

[0817] - Use basemap #1 for initial emission and subsequent re-emissions of the same TB in the following cases)

[0818] - TBS <= 3840 and R init > 0.67

[0819] - TBS > 3840 and R init > 0.25

[0820] - Use basemap #2 for initial emission and subsequent re-emissions of the same TB in the following cases)

[0821] - TBS <= 3840 and R init <= 0.67

[0822] - TBS > 3840 and R init <= 0.25

[0823] R init Determine method 5

[0824] -When TBS <= 3824, R init = R nominal

[0825] -R nominal is the nominal code rate that is signaled in the control information to schedule the transmission of transport blocks.

[0826] -When TBS > 3824, R init = max(R nominal , R limit )

[0827] -R limit = K' / N cb,limit ,in

[0828] - K' is the number of input bits (including CRC bits and padding bits) of the code block, and

[0829] -N cb,limit is the finite (or full) circular buffer size used to transmit one code block calculated using the BG#2 parameters

[0830] - Use basemap #1 for initial emission and subsequent re-emissions of the same TB in the following cases)

[0831] - TBS <= 3840 and R init > 0.67

[0832] - TBS > 3840 and R init > 0.25

[0833] - Use basemap #2 for initial emission and subsequent re-emissions of the same TB in the following cases)

[0834] - TBS <= 3840 and R init <= 0.67

[0835] - TBS > 3840 and R init <= 0.25

[0836] R init Determine method 6

[0837] -If TBS <= 3824

[0838] -R init = R nominal , where R nominal is the nominal code rate that is signaled in the control information to schedule the transmission of transport blocks.

[0839] -When R init > 0.67, use basemap #1 for initial emission and subsequent re-emissions of the same TB

[0840] -When R init <= 0.67, use basemap #2 for initial emission and subsequent re-emissions of the same TB

[0841] -If TBS > 3824

[0842] -R init = max(R nominal , R limit),in

[0843] -R limit = K' / N cb,limit ,and

[0844] - K' is the number of input bits of the code block (including CRC bits and excluding padding bits), and

[0845] -N cb,limit is the finite (or full) circular buffer size used to transmit one code block calculated using the BG#2 parameters

[0846] -When R init > 0.25, use basemap #1 for initial emission and subsequent re-emissions of the same TB

[0847] -When R init <= 0.25, use basemap #2 for initial emission and subsequent re-emissions of the same TB

[0848] R init Determine method 7

[0849] -If TBS <= 3824

[0850] -R init = R nominal , where R nominal is the nominal code rate that is signaled in the control information to schedule the transmission of transport blocks.

[0851] -When R init > 0.67, use basemap #1 for initial emission and subsequent re-emissions of the same TB

[0852] -When R init <= 0.67, use basemap #2 for initial emission and subsequent re-emissions of the same TB

[0853] -If TBS > 3824

[0854] -R init = max(R nominal , R limit ),in

[0855] -R limit = K' / N cb,limit ,and

[0856] - K' is the number of input bits (including CRC bits and padding bits) of the code block, and

[0857] -N cb,limitis the finite (or full) circular buffer size used to transmit one code block calculated using the BG#2 parameters

[0858] -When R init > 0.25, use basemap #1 for initial emission and subsequent re-emissions of the same TB

[0859] -When R init <= 0.25, use basemap #2 for initial emission and subsequent re-emissions of the same TB

[0860] Next, the determination of R will be described. nominal Another specific embodiment of. Reference will now be made to the following formula 31:

[0861] [Equation 31]

[0862]

[0863] In the above formula 31, #RB refers to the number of resource blocks (RBs) used to transmit TBs, and can be transmitted as control information. RMCS is a code rate indicating the MCS, and is determined according to the MCS value. #OFDM_symbol refers to the number of OFDM symbols used to transmit TBs, and can be transmitted as control information. #sub_carrier_RB refers to the number of subcarriers allocated per RB. MOD refers to the modulation order, and is 2 in the case of QPSK, 4 in the case of 16QAM, 6 in the case of 64QAM, and 8 in the case of 256QAM. R can also be determined by additionally considering the reference signaling (RS). nominal value.

[0864] As another embodiment corresponding to the above equation 31, for determining R nominal At least one of the initially transmitted #OFDM_symbol, #sub_carrier_RB, RMCS, #RB, MOD, TBS may be stored by the transmitter and the receiver, and the LDPC base matrix (or sequence) may be determined based on at least one of the above.

[0865] As another embodiment, the LDPC base matrix (or sequence) to be used may be determined in advance and configured as a table, and the LDPC matrix to be used may be determined based on the table. In this case, since the table is configured based on MCS and #RB, the LDPC base matrix (or sequence) may be determined by a combination of MCS and #RB. However, depending on the situation, the LDPC base matrix (or sequence) may be determined to be different from a given table. For example, if a limited buffer is used, a restriction may be made in view of this situation so that the LDPC base matrix (or sequence) may be finally determined without considering the table as long as the following conditions are met:

[0866] - If both R limit > R th and R nominal < R th , encoding and decoding can always be performed based on the first LDPC base matrix (or sequence).

[0867] R th The value is a predetermined value, and for example, a value such as 0.25 can be used for this purpose.

[0868] Although the present disclosure has been described with respect to preferred embodiments, various changes and modifications may occur to those skilled in the art. Such changes and modifications are intended to be encompassed by the appended claims.

Claims

1. A method for low-density parity check (LDPC) coding performed by a transmitting device in a communication system, the method comprising: Determine a code rate based on a modulation and coding scheme MCS index; Determine the size of the transfer block; Determining one of a first base matrix or a second base matrix as a base matrix based on the size of the transport block and the code rate; Determine a parity check matrix based on the base matrix; as well as performing LDPC encoding of at least one code block based on the parity check matrix, the at least one code block being determined based on the transport block, Wherein, when the code rate is less than or equal to the first code rate threshold, the second base matrix is ​​determined as the base matrix, Wherein, when the code rate is less than or equal to a second code rate threshold and the size of the transport block is less than or equal to a transport block size threshold, the second base matrix is ​​determined as the base matrix, and The second bit rate threshold is greater than the first bit rate threshold.

2. The method according to claim 1, wherein: Performing the LDPC encoding includes: Determining a block size Z for boosting based on the size of the transport block; Determining a block size group Zi including the block size Z from a plurality of block size groups; and determining the parity check matrix based on the base matrix and the block size, The plurality of block size groups include a first block size group Z1, wherein the first block size group Z1 includes 2, 4, 8, 16, 32, 64, 128 and 256, The plurality of block size groups include a second block size group Z2, wherein the second block size group Z2 includes 3, 6, 12, 24, 48, 96, 192 and 384, The plurality of block size groups include a third block size group Z3, and the third block size group Z3 includes 5, 10, 20, 40, 80, 160 and 320, The plurality of block size groups include a fourth block size group Z4, and the fourth block size group Z4 includes 7, 14, 28, 56, 112 and 224, The plurality of block size groups include a fifth block size group Z5, and the fifth block size group Z5 includes 9, 18, 36, 72, 144 and 288. The plurality of block size groups include a sixth block size group Z6, and the sixth block size group Z6 includes 11, 22, 44, 88, 176 and 352, The plurality of block size groups include a seventh block size group Z7, and the seventh block size group Z7 includes 13, 26, 52, 104 and 208, Among them, the multiple block size groups include an eighth block size group Z8, and the eighth block size group Z8 includes 15, 30, 60, 120 and 240.

3. The method according to claim 1, wherein: Cyclic redundancy check CRC bits are appended to the transport block, Wherein, in the case where the size of the transport block is greater than a threshold value related to CRC, the size of the CRC bits is a first size, wherein, in a case where the size of the transport block is less than or equal to the threshold value related to CRC, the size of the CRC bits is a second size, and The first size and the second size are different.

4. A method for low-density parity check (LDPC) decoding performed by a receiving device in a communication system, the method comprising: Determine a code rate based on a modulation and coding scheme MCS index; Determine the size of the transfer block; Determining one of a first base matrix or a second base matrix as a base matrix based on the size of the transport block and the code rate; Determine a parity check matrix based on the base matrix; performing LDPC decoding based on the parity check matrix; as well as determining at least one code block based on the LDPC decoding, Wherein, when the code rate is less than or equal to the first code rate threshold, the second base matrix is ​​determined as the base matrix, Wherein, when the code rate is less than or equal to a second code rate threshold and the size of the transport block is less than or equal to a transport block size threshold, the second base matrix is ​​determined as the base matrix, and The second bit rate threshold is greater than the first bit rate threshold.

5. The method according to claim 4, wherein: Performing the LDPC decoding includes: Determining a block size Z for boosting based on the size of the transport block; Determining a block size group Zi including the block size Z from a plurality of block size groups; and determining the parity check matrix based on the base matrix and the block size, The plurality of block size groups include a first block size group Z1, wherein the first block size group Z1 includes 2, 4, 8, 16, 32, 64, 128 and 256, The plurality of block size groups include a second block size group Z2, wherein the second block size group Z2 includes 3, 6, 12, 24, 48, 96, 192 and 384, The plurality of block size groups include a third block size group Z3, and the third block size group Z3 includes 5, 10, 20, 40, 80, 160 and 320, The plurality of block size groups include a fourth block size group Z4, and the fourth block size group Z4 includes 7, 14, 28, 56, 112 and 224, The plurality of block size groups include a fifth block size group Z5, and the fifth block size group Z5 includes 9, 18, 36, 72, 144 and 288. The plurality of block size groups include a sixth block size group Z6, and the sixth block size group Z6 includes 11, 22, 44, 88, 176 and 352, The plurality of block size groups include a seventh block size group Z7, and the seventh block size group Z7 includes 13, 26, 52, 104 and 208, Among them, the multiple block size groups include an eighth block size group Z8, and the eighth block size group Z8 includes 15, 30, 60, 120 and 240.

6. The method according to claim 4, wherein: Cyclic redundancy check CRC bits are appended to the transport block, Wherein, in the case where the size of the transport block is greater than a threshold value related to CRC, the size of the CRC bits is a first size, wherein, in a case where the size of the transport block is less than or equal to the threshold value related to CRC, the size of the CRC bits is a second size, and The first size and the second size are different.

7. A device for low-density parity check (LDPC) coding in a communication system, the device comprising: Transceiver; as well as a controller coupled to the transceiver and configured to: Determine a code rate based on a modulation and coding scheme MCS index; Determine the size of the transfer block; Determining one of a first base matrix or a second base matrix as a base matrix based on the size of the transport block and the code rate; Determine a parity check matrix based on the base matrix; as well as performing LDPC encoding of at least one code block based on the parity check matrix, the at least one code block being determined based on the transport block, Wherein, when the code rate is less than or equal to the first code rate threshold, the second base matrix is ​​determined as the base matrix, Wherein, when the code rate is less than or equal to a second code rate threshold and the size of the transport block is less than or equal to a transport block size threshold, the second base matrix is ​​determined as the base matrix, and The second bit rate threshold is greater than the first bit rate threshold.

8. The device according to claim 7, wherein: The controller is configured to: Determining a block size Z for boosting based on the size of the transport block; Determining a block size group Zi including the block size Z from a plurality of block size groups; and determining the parity check matrix based on the base matrix and the block size, The plurality of block size groups include a first block size group Z1, wherein the first block size group Z1 includes 2, 4, 8, 16, 32, 64, 128 and 256, The plurality of block size groups include a second block size group Z2, wherein the second block size group Z2 includes 3, 6, 12, 24, 48, 96, 192 and 384, The plurality of block size groups include a third block size group Z3, and the third block size group Z3 includes 5, 10, 20, 40, 80, 160 and 320, The plurality of block size groups include a fourth block size group Z4, and the fourth block size group Z4 includes 7, 14, 28, 56, 112 and 224, The plurality of block size groups include a fifth block size group Z5, and the fifth block size group Z5 includes 9, 18, 36, 72, 144 and 288. The plurality of block size groups include a sixth block size group Z6, and the sixth block size group Z6 includes 11, 22, 44, 88, 176 and 352, The plurality of block size groups include a seventh block size group Z7, and the seventh block size group Z7 includes 13, 26, 52, 104 and 208, Among them, the multiple block size groups include an eighth block size group Z8, and the eighth block size group Z8 includes 15, 30, 60, 120 and 240.

9. The device according to claim 7, wherein: Cyclic redundancy check CRC bits are appended to the transport block, Wherein, in the case where the size of the transport block is greater than a threshold value related to CRC, the size of the CRC bits is a first size, wherein, in a case where the size of the transport block is less than or equal to the threshold value related to CRC, the size of the CRC bits is a second size, and The first size and the second size are different.

10. A device for low-density parity check (LDPC) decoding in a communication system, the device comprising: Transceiver; as well as a controller coupled to the transceiver and configured to: Determine a code rate based on a modulation and coding scheme MCS index; Determine the size of the transfer block; Determining one of a first base matrix or a second base matrix as a base matrix based on the size of the transport block and the code rate; Determine a parity check matrix based on the base matrix; performing LDPC decoding based on the parity check matrix; as well as determining at least one code block based on the LDPC decoding, Wherein, when the code rate is less than or equal to the first code rate threshold, the second base matrix is ​​determined as the base matrix, Wherein, when the code rate is less than or equal to a second code rate threshold and the size of the transport block is less than or equal to a transport block size threshold, the second base matrix is ​​determined as the base matrix, and The second bit rate threshold is greater than the first bit rate threshold.

11. The device according to claim 10, wherein: The controller is configured to: Determining a block size Z for boosting based on the size of the transport block; Determining a block size group Zi including the block size Z from a plurality of block size groups; and determining the parity check matrix based on the base matrix and the block size, The plurality of block size groups include a first block size group Z1, wherein the first block size group Z1 includes 2, 4, 8, 16, 32, 64, 128 and 256, The plurality of block size groups include a second block size group Z2, wherein the second block size group Z2 includes 3, 6, 12, 24, 48, 96, 192 and 384, The plurality of block size groups include a third block size group Z3, and the third block size group Z3 includes 5, 10, 20, 40, 80, 160 and 320, The plurality of block size groups include a fourth block size group Z4, and the fourth block size group Z4 includes 7, 14, 28, 56, 112 and 224, The plurality of block size groups include a fifth block size group Z5, and the fifth block size group Z5 includes 9, 18, 36, 72, 144 and 288. The plurality of block size groups include a sixth block size group Z6, and the sixth block size group Z6 includes 11, 22, 44, 88, 176 and 352, The plurality of block size groups include a seventh block size group Z7, and the seventh block size group Z7 includes 13, 26, 52, 104 and 208, Among them, the multiple block size groups include an eighth block size group Z8, and the eighth block size group Z8 includes 15, 30, 60, 120 and 240.

12. The device according to claim 10, wherein: Cyclic redundancy check CRC bits are appended to the transport block, Wherein, in the case where the size of the transport block is greater than a threshold value related to CRC, the size of the CRC bits is a first size, wherein, in a case where the size of the transport block is less than or equal to the threshold value related to CRC, the size of the CRC bits is a second size, and The first size and the second size are different.

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