Video output device, method, electronic device, storage medium and program

Abstract

The present disclosure provides a video output device, method, electronic device, storage medium, and program, belonging to the field of display technology. The device labels audio data based on the validity of video frames when switching between video stream formats on the same channel. This device then distinguishes valid and invalid audio data, plays only audio data from valid video frames, and filters invalid audio data, thereby ensuring the continuity of the audio data and eliminating audio playback noise.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and in particular relates to a video output device, method, electronic device, storage medium, and program. Background Art

[0002] In the display field, when switching different signal formats on the same channel, the signal source and the analyzer will need to be re-locked, and multiple re-locks are required to achieve a stable state.

[0003] During the relocking process, since the audio data and video data cannot determine the validity of the current data, they need to be compared with subsequent data to determine the validity of the subsequent data. This causes the playback of valid video frames to have a lag, and the audio data of invalid video frames affects the continuity of the audio data, generating noise. Summary of the Invention

[0004] The present disclosure provides a video output device, method, electronic device, storage medium, and program.

[0005] Some embodiments of the present disclosure provide a video output method, the method comprising:

[0006] a video parsing subcircuit configured to, when a signal format of a video stream received through a target channel changes, parse the video stream to obtain video frames and audio data and send them to the video detection subcircuit;

[0007] The video detection subcircuit is configured to, when the video frame is a valid video frame, add a valid tag to the audio data, write the audio data into the audio buffer, and send an enable signal to the output-side timing generation subcircuit;

[0008] The output-side timing generation subcircuit is configured to generate an output-side timing signal corresponding to the valid video frame based on the enable signal, and send the output-side timing signal to the video output subcircuit and the audio output subcircuit respectively;

[0009] The video output subcircuit is configured to output the valid video frame according to the output side timing signal;

[0010] The audio output sub-circuit is configured to read the audio data in the audio buffer according to the output-side timing signal, and encode the audio data with the valid tag added thereto and then output it.

[0011] Optionally, the video analysis subcircuit is further configured to:

[0012] Parsing the video stream to obtain audio auxiliary data;

[0013] The audio output subcircuit includes:

[0014] an audio sampling clock creation module, configured to construct an audio sampling clock according to the audio auxiliary data;

[0015] an audio encoding module, configured to read the audio data from the audio buffer based on the audio sampling clock when receiving the output-side timing signal;

[0016] Encoding the audio data to which the valid tag is added to obtain an audio analog signal;

[0017] The audio output module is configured to output the audio analog signal.

[0018] Optionally, the audio auxiliary data includes at least: a timing tree complex, a video clock, and audio clock parameters;

[0019] The audio sampling clock creation module is further configured to construct an audio sampling clock through a crystal oscillator based on the timing tree complex, the video clock, and the audio clock parameters.

[0020] Optionally, the audio sampling clock creation module is further configured to:

[0021] The audio sampling clock is constructed using the following formula:

[0022] Fs = (N*Ftmds) / (CTS*128);

[0023] Wherein, the Fs represents an audio sampling clock, the N represents an audio clock parameter, the Ftmds represents a video frame clock, and the CTS represents a timing tree complex.

[0024] Optionally, the video detection sub-circuit is further configured to:

[0025] Compare the video timing of the nth video frame with the video timing of the n+1th video frame to determine whether the nth video frame is a valid video frame.

[0026] Optionally, the video timing includes at least: a line synchronization signal, a field synchronization signal, and a valid display data selection signal;

[0027] The video detection sub-circuit is further configured to:

[0028] Analyze the line synchronization signal, the field synchronization signal, and the effective display data selection signal to obtain the total number of clocks per line, the number of effective pixels per line, the total number of lines per frame, and the number of effective lines per frame of the nth video frame and the (n+1)th video frame;

[0029] When the total number of clocks per row, the number of valid pixels per row, the total number of rows per frame, and the number of valid rows per frame of the nth video frame and the n+1th video frame are all equal, determining that the nth video frame is a valid video frame;

[0030] When any of the total number of clocks per row, the number of valid pixels per row, the total number of rows per frame, and the number of valid rows per frame of the nth video frame and the n+1th video frame are not equal, the nth video frame is determined to be an invalid video frame.

[0031] Optionally, the output-side timing generation sub-circuit is further configured to:

[0032] When the enable signal is received, an output-side timing signal is generated in the local clock domain.

[0033] Some embodiments of the present disclosure provide a video output method, the apparatus comprising:

[0034] When a signal format of a video stream received through a target channel changes, parsing the video stream to obtain video frames and audio data;

[0035] If the video frame is a valid video frame, adding a valid tag to the audio data and then writing the audio data into an audio buffer;

[0036] Generating an output side timing signal corresponding to the valid video frame;

[0037] The valid video frame is output according to the output side timing signal, the audio data in the audio buffer is read according to the output side timing signal, and the audio data with the valid tag added is encoded and then output.

[0038] Optionally, the method further includes:

[0039] Parsing the video stream to obtain audio auxiliary data;

[0040] The step of reading the audio data in the audio buffer according to the output-side timing signal and encoding the audio data with the valid tag added thereto and outputting the encoded audio data comprises:

[0041] constructing an audio sampling clock according to the audio auxiliary data;

[0042] When receiving the output-side timing signal, reading the audio data from the audio buffer based on the audio sampling clock;

[0043] Encoding the audio data to which the valid tag is added to obtain an audio analog signal;

[0044] The analog audio signal is output.

[0045] Optionally, the audio auxiliary data includes at least: a timing tree complex, a video clock, and audio clock parameters;

[0046] The step of constructing an audio sampling clock according to the audio auxiliary data comprises:

[0047] An audio sampling clock is constructed through a crystal oscillator based on the timing tree complex, the video clock, and the audio clock parameters.

[0048] Optionally, constructing an audio sampling clock through a crystal oscillator based on the timing tree complex, the video clock, and the audio clock parameters includes:

[0049] The audio sampling clock is constructed using the following formula:

[0050] Fs = (N*Ftmds) / (CTS*128);

[0051] Wherein, the Fs represents an audio sampling clock, the N represents an audio clock parameter, the Ftmds represents a video frame clock, and the CTS represents a timing tree complex.

[0052] Optionally, when the video frame is a valid video frame, after adding a valid tag to the audio data and before writing the audio data into the audio buffer, the method further includes:

[0053] Compare the video timing of the nth video frame with the video timing of the n+1th video frame to determine whether the nth video frame is a valid video frame.

[0054] Optionally, the video timing includes at least: a line synchronization signal, a field synchronization signal, and a valid display data selection signal;

[0055] The comparing the video timing of the nth video frame with the (n+1)th video frame to determine whether the nth video frame is a valid video frame includes:

[0056] Analyze the line synchronization signal, the field synchronization signal, and the effective display data selection signal to obtain the total number of clocks per line, the number of effective pixels per line, the total number of lines per frame, and the number of effective lines per frame of the nth video frame and the (n+1)th video frame;

[0057] When the total number of clocks per row, the number of valid pixels per row, the total number of rows per frame, and the number of valid rows per frame of the nth video frame and the n+1th video frame are all equal, determining that the nth video frame is a valid video frame;

[0058] When any of the total number of clocks per row, the number of valid pixels per row, the total number of rows per frame, and the number of valid rows per frame of the nth video frame and the n+1th video frame are not equal, the nth video frame is determined to be an invalid video frame.

[0059] Optionally, generating the output-side timing signal corresponding to the valid video frame includes:

[0060] When the enable signal is received, an output-side timing signal is generated in the local clock domain.

[0061] Some embodiments of the present disclosure provide a computing processing device, including:

[0062] a memory having computer readable code stored therein;

[0063] One or more processors, when the computer readable code is executed by the one or more processors, the computing processing device performs the video output method as described above.

[0064] Some embodiments of the present disclosure provide a computer program, comprising a computer-readable code, which, when executed on a computing and processing device, causes the computing and processing device to execute the video output method as described above.

[0065] Some embodiments of the present disclosure provide a non-transitory computer-readable medium storing the above-mentioned video output method.

[0066] The present disclosure provides a video output device, method, electronic device, storage medium and program. When switching the format of a video stream on the same channel, valid audio data and invalid audio data are calibrated by labeling the audio data according to the validity of the video frame. Only the audio data of the valid video frame is played, and the invalid audio data is filtered out, thereby ensuring the continuity of the audio data and eliminating noise in the audio playback.

[0067] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0069] Figure 1 Schematically shows a structural diagram of a video output device provided by some embodiments of the present disclosure;

[0070] Figure 2 Schematically illustrates one of the principle schematic diagrams of a video output device provided by some embodiments of the present disclosure;

[0071] Figure 3 The second schematic diagram schematically illustrates a principle of a video output device provided by some embodiments of the present disclosure;

[0072] Figure 4 A system diagram of a video output device provided by some embodiments of the present disclosure is schematically shown;

[0073] Figure 5 The following schematically illustrates a flow chart of a video output system provided by some embodiments of the present disclosure;

[0074] Figure 6 The third schematic diagram schematically illustrates a principle of a video output device provided by some embodiments of the present disclosure;

[0075] Figure 7 The following schematically illustrates a flow chart of a video output method provided by some embodiments of the present disclosure;

[0076] Figure 8 Schematically shows a block diagram of a computing processing device for executing the method according to some embodiments of the present disclosure;

[0077] Figure 9 The figure schematically shows a storage unit for holding or carrying program codes for implementing methods according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0078] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0079] Figure 1 The following schematically shows a structural diagram of a video output circuit provided by the present disclosure, wherein the circuit comprises:

[0080] The video parsing sub-circuit 101 is configured to, when a signal format of a video stream received through a target channel is changed, parse the video stream to obtain video frames and audio data and send them to the video detection sub-circuit.

[0081] It should be noted that the target channel refers to the information transmission channel for receiving the video stream. For example, the HDMI (High Definition Multimedia Interface) interface has three different TMDS (Time Minimized Differential Signal) channels and a clock channel. The signal format refers to the video stream format parameters, such as the video frame rate and color channels.

[0082] The execution subject of the embodiment of the present disclosure may be an electronic device or processor having functions such as data processing, data transmission, data output, and data storage. In the embodiment of the present disclosure, when the signal format of the video stream received by the processor through the same target channel changes, the video frame and the audio data corresponding to the video frame can be parsed from the video stream through the video parsing subcircuit, wherein the correspondence between the audio data and the video frame can be distinguished based on the timing of data reception. For example, the video frame received first at the timing corresponds to the audio data received first at the timing, the video frame received second at the timing corresponds to the audio data received second at the timing, and so on, to obtain the correspondence between the video frame and the audio data. Since the currently received video frame needs to be compared with the subsequently received video frame to determine the validity of the video frame and output the valid video frame, when the signal format changes, the validity of the video frame cannot be judged when the next sequential video frame is not obtained. Therefore, when the signal format is just switched, the video frame judgment will be delayed due to waiting for the subsequent video frame for valid video frame judgment. At this time, since there is no concept of valid or invalid audio data, if it is still output continuously, the audio data will be discontinuous, resulting in noise in the played audio.

[0083] The video detection subcircuit 102 is configured to, when the video frame is a valid video frame, add a valid tag to the audio data and write the audio data into the audio buffer, and send an enable signal to the output-side timing generation subcircuit.

[0084] It should be noted that a valid video frame refers to a video frame that actually needs to be output among the video frames, which can usually be determined by the video timing carried in the video stream, for example: based on only DE (valid display data selection signal), or based on HS (line synchronization signal), VS (field synchronization signal) and DE, or based on the parity of pixel data, etc.

[0085] In the embodiment of the present disclosure, the video detection subcircuit determines whether a valid video frame in the video stream is a valid video frame, and stores the video frame after determining whether it is valid into the memory, referring to Figure 2 , multiple storage areas can be set in the memory, each storage area stores a video frame and is written cyclically through the WDMA ((write memory control) module).

[0086] Taking into account the line blanking period and frame blanking period of the audio data stored in the video stream, there is essentially no concept of frame. When the signal format of the same channel is switched, the audio data will continue to play, resulting in discontinuous audio data and noise. Therefore, the embodiment of the present disclosure indicates whether the corresponding video frame is valid by extending the corresponding audio data by one bit based on whether the video frame is valid. For example, for 24-bit parallel audio data, AUDIO DATA = {24'B (AUDIO_RAW_DATA)} is expanded to AUDIO DATA = {VAL, 24'B (AUDIO_RAW_DATA)}, where AUDIODATAVAL is the audio data, 24'B (AUDIO_RAW_DATA is the audio signal in the audio data, and VAL is the extended data. Furthermore, VAL = 1 can be used to indicate that the video frame corresponding to the audio data is a valid video frame; VAL = 0 can be used to indicate that the video frame corresponding to the audio data is an invalid video frame. After adding a label to the audio data, it will be written to the audio buffer.

[0087] Furthermore, when the video detection subcircuit detects the presence of a valid video frame in the video stream, since the video frames received after the valid video frame are also valid video frames, the video detection subcircuit will generate an enable signal and send it to the output side timing generation subcircuit, so that the output side timing generation subcircuit can further generate an output side timing signal to drive the audio and video output.

[0088] The output side timing generation sub-circuit 103 is configured to generate an output side timing signal corresponding to the valid video frame based on the enable signal, and send the output side timing signal to the video output sub-circuit and the audio output sub-circuit respectively.

[0089] In the embodiment of the present disclosure, upon receiving an enable signal, the output-side timing generation subcircuit generates a timing signal for outputting audio and video data, and sends the timing signal to the video output subcircuit and the audio output subcircuit respectively.

[0090] Further, refer to Figure 3, the relationship between frame 1 and frame 2 is F=0, indicating that frame 1 is an invalid frame, and the relationship between frame 2 and frame 3 is F=1, indicating that frame 2 is a valid frame, and so on and so forth, all subsequent frames are valid frames. When writing frame 3 is completed, it can be obtained that frame 2 is a valid frame, and the read operation can be performed at this time. Because frame 2 is the first valid frame, the first read operation reads frame 2, a valid frame, and the read frame operation delays the write frame operation by 2 frames. That is, TDLY_VID (delay time of video frame) = 2*T, where T is the duration of a single frame of video input. The audio data enters the audio buffer for buffering. The time from when the audio data is written to the audio buffer to when it starts to be read from the audio buffer is TDLY_AUD (delay time of audio data). In order to ensure the synchronization of audio data and video data, it is necessary to ensure that the delay of audio data in the audio buffer is equal to the delay of video data in memory, that is, TDLY_AUD = TDLY_VID = 2*T. Specifically, the output side timing generation subcircuit can output timing signals with the same delay to ensure that the delays of the audio frames and video data output by the audio output subcircuit and the video output subcircuit are the same, so that the audio data and video frames remain synchronized.

[0091] The video output sub-circuit 104 is configured to output the valid video frame according to the output-side timing signal.

[0092] In the embodiment of the present disclosure, the video output subcircuit sends an output side timing signal to the memory read control module to read the valid video frame from the memory, and then sends the acquired valid video frame to the display screen through the transmitter for display.

[0093] The audio output sub-circuit 105 is configured to read the audio data in the audio buffer according to the output-side timing signal, and encode the audio data with the valid tag added thereto and then output it.

[0094] In the disclosed embodiment, the audio output subcircuit and the video output subcircuit receive the same output-side timing signal from the output-side timing generation subcircuit. The audio output subcircuit then generates a sampling clock in the local clock domain, reads audio data from the audio buffer based on the sampling clock, and sends the read audio data to the audio encoding module. The audio encoding module encodes only audio data with valid tags and converts the encoded audio data into an analog signal for output. This ensures that during signal format switching on the same channel, only stable audio data of valid video frames is output, ensuring audio data continuity, filtering invalid data, and eliminating audio data noise.

[0095] Reference Figure 4, showing a system schematic diagram of a video output method provided by an embodiment of the present disclosure, wherein HDMI_RX_IP is a video parsing subcircuit, DDR3 is memory, MIG is a memory controller, AXI_INTERCONNECT is a bus arbitration module, WDMA is a write memory control module, RDMA is a read memory control module, VEDIO DET is a video detection subcircuit, VTG is an output-side timing generation subcircuit, FRM TAG is an audio data tagging module, AUDIO FIFO is an audio buffer, ACR is an audio sampling clock creation module, OSC is a local clock, VBO is a transmitter, I2S is an audio encoding module, PANEL is a display, CODEC is a digital-to-analog conversion module, and SPEAKER is an audio player. VIDEO is a video frame, VS is a video timing, AUDIO is audio data, and CTS / N is audio auxiliary data.

[0096] Reference Figure 5 A video output method provided by an embodiment of the present disclosure may include the following process:

[0097] S1, the video parsing subcircuit parses the video data and audio data from the data stream;

[0098] S2: Video data flow process:

[0099] S21, the video detection module detects the timing signal of the video frame and outputs a video frame enable signal;

[0100] S22, the video frame is written into the memory through the memory write control module;

[0101] S23, the output side timing generation sub-circuit generates an output side timing signal according to the video frame enable signal;

[0102] S24, the memory read control module reads the valid video frame from the memory based on the output side timing signal;

[0103] S25, the valid video frame is sent to the display through the sending module;

[0104] S3: Audio data flow process:

[0105] S31, the video detection subcircuit detects the video timing and adds a valid label or an invalid label to the audio data;

[0106] S32, audio data is written into the audio buffer;

[0107] S33, the audio sampling clock creation module reconstructs the audio sampling clock according to the audio auxiliary data output by the video analysis subcircuit;

[0108] S34, audio data is read out of the audio buffer through the audio clock sampling clock.

[0109] S35, performing an encoding operation on the audio data when the tag in the extension bit of the audio data is a valid tag;

[0110] S36: The audio signal is transmitted to the audio player.

[0111] The present invention labels the audio data according to the validity of the video frame when the format of the video stream on the same channel is switched, thereby calibrating the valid and invalid audio data. Only the audio data of the valid video frame is played, and the invalid audio data is filtered out, thereby ensuring the continuity of the audio data and eliminating the noise of the audio playback.

[0112] Optionally, the video analysis sub-circuit 101 is further configured to:

[0113] The video stream is parsed to obtain audio auxiliary data.

[0114] In the disclosed embodiments, audio auxiliary data is auxiliary data carried in the video stream, used to interpret audio timing, and typically exists in the blanking period of the video stream. Video timing is information in the video stream used to interpret video timing, and also exists in the blanking period of the video stream.

[0115] The audio output sub-circuit 105 includes:

[0116] The audio sampling clock creation module is configured to construct an audio sampling clock according to the audio auxiliary data.

[0117] In the disclosed embodiments, the audio data sampling rates include 44100, 48000, and 192000. During HDMI transmission, the audio data is transmitted uncompressed and broken up into individual packets. To obtain the audio data for each video frame, it is necessary to reconstruct the audio sampling clock to obtain the sampling rate of the audio data in the local sampling time domain.

[0118] Optionally, the audio auxiliary data includes at least: a timing tree complex, a video clock, and audio clock parameters.

[0119] The audio sampling clock creation module is further configured to construct an audio sampling clock through a crystal oscillator based on the timing tree complex, the video clock, and the audio clock parameters.

[0120] The audio sampling clock is constructed using the following formula:

[0121] Fs = (N*Ftmds) / (CTS*128).

[0122] Wherein, the Fs represents an audio sampling clock, the N represents an audio clock parameter, the Ftmds represents a video frame clock, and the CTS represents a timing tree complex.

[0123] In the disclosed embodiment, the main parameters for audio sampling clock reconstruction are: TMDS Clock (video frame clock), CTS (clock tree synthesis) and audio clock parameter N. The TMDS CLOCK is known, and CTS and N are parsed from the video stream by the video parsing subcircuit.

[0124] The audio encoding module is configured to read the audio data from the audio buffer based on the audio sampling clock when receiving the output side timing signal; and encode the audio data with the valid tag added to obtain an audio analog signal.

[0125] In the disclosed embodiments, the audio sampling clock is used to describe the length of each audio data read. By constructing an audio sampling clock based on the audio auxiliary data in the video stream, the timing of the read audio data and valid video frames can be synchronized. However, since the read audio data still contains audio data synchronized with invalid video frames, the audio encoding module can use the tags carried in the audio data to identify whether the audio data corresponds to a valid video frame. In other words, only audio data with valid tags will be encoded.

[0126] The audio output module is configured to output the audio analog signal.

[0127] In the embodiment of the present disclosure, the data conversion module sends the audio analog signal to the audio player, and the audio player plays the audio analog signal.

[0128] Optionally, the video detection sub-circuit 102 is further configured to:

[0129] Compare the video timing of the nth video frame with the video timing of the n+1th video frame to determine whether the nth video frame is a valid video frame.

[0130] In the disclosed embodiment, the n+1th video frame refers to the video frame received at the next moment after the nth video frame is received. By comparing the video timing of the nth video frame with the n+1th video frame, it can be determined whether the nth video frame is a valid video frame.

[0131] Optionally, the video timing includes at least: a line synchronization signal, a field synchronization signal, and a valid display data selection signal.

[0132] The video detection sub-circuit 102 is further configured to:

[0133] Analyze the line synchronization signal, the field synchronization signal, and the effective display data selection signal to obtain the total number of clocks per line, the number of effective pixels per line, the total number of lines per frame, and the number of effective lines per frame of the nth video frame and the n+1th video frame; when the total number of clocks per line, the number of effective pixels per line, the total number of lines per frame, and the number of effective lines per frame of the nth video frame and the n+1th video frame are all equal, determine that the nth video frame is a valid video frame; when any of the total number of clocks per line, the number of effective pixels per line, the total number of lines per frame, and the number of effective lines per frame of the nth video frame and the n+1th video frame are not equal, determine that the nth video frame is an invalid video frame.

[0134] In the embodiment of the present disclosure, if the nth video frame satisfies the following formula (1), then the nth video frame is determined to be a valid video frame, otherwise it is an invalid video frame:

[0135] FRAMEn(HTT / HAC / VTT / VAC)=FRAMEn+1(HTT / HAC / VTT / VAC) (1)

[0136] Among them, FRAMEn represents the nth video frame, FRAMEn+1 represents the N+1th video frame, HTT represents the total number of clocks per line, HAC represents the number of valid pixels per line, VTT represents the total number of lines per frame, and VAC represents the number of valid lines per frame. Figure 6 , the label information F of the video frame can be expressed as follows:

[0137] F=(HTTn=HTTn+1&HACn=HACn+1&VTTn=VTTn+1&VACn=VACn+1) (2)

[0138] That is, when F is 1, it is a valid video frame, and when F is 0, it is an invalid video frame.

[0139] The disclosed embodiment improves the efficiency of video frame validity detection by detecting whether a video frame is valid based on a line synchronization signal, a field synchronization signal, and a valid display data selection signal in a video timing sequence.

[0140] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0141] Figure 7The following schematically illustrates a flow chart of a video output method provided by the present disclosure, wherein the method comprises:

[0142] Step 201: When the signal format of a video stream received through a target channel changes, the video stream is parsed to obtain video frames and audio data.

[0143] Step 202: If the video frame is a valid video frame, add a valid tag to the audio data and write the audio data into an audio buffer;

[0144] Step 203, generating an output side timing signal corresponding to the valid video frame;

[0145] Step 204: output the valid video frame according to the output side timing signal, read the audio data in the audio buffer according to the output side timing signal, and encode the audio data with the valid tag added thereto and output it.

[0146] Optionally, after step 201, the method further comprises: parsing the video stream to obtain audio auxiliary data;

[0147] The step 204 includes:

[0148] constructing an audio sampling clock according to the audio auxiliary data;

[0149] When receiving the output-side timing signal, reading the audio data from the audio buffer based on the audio sampling clock;

[0150] Encoding the audio data to which the valid tag is added to obtain an audio analog signal;

[0151] The analog audio signal is output.

[0152] Optionally, the audio auxiliary data includes at least: a timing tree complex, a video clock, and audio clock parameters;

[0153] The step 204 further includes: constructing an audio sampling clock through a crystal oscillator based on the timing tree complex, the video clock, and the audio clock parameters.

[0154] Optionally, the step 204 further includes:

[0155] The audio sampling clock is constructed using the following formula:

[0156] Fs = (N*Ftmds) / (CTS*128);

[0157] Wherein, the Fs represents an audio sampling clock, the N represents an audio clock parameter, the Ftmds represents a video frame clock, and the CTS represents a timing tree complex.

[0158] Optionally, before step 202, the method further includes: comparing the video timing of the nth video frame with the video timing of the (n+1)th video frame to determine whether the nth video frame is a valid video frame.

[0159] Optionally, the video timing includes at least: a line synchronization signal, a field synchronization signal, and a valid display data selection signal;

[0160] Before step 202, the method further includes:

[0161] Analyze the line synchronization signal, the field synchronization signal, and the effective display data selection signal to obtain the total number of clocks per line, the number of effective pixels per line, the total number of lines per frame, and the number of effective lines per frame of the nth video frame and the (n+1)th video frame;

[0162] When the total number of clocks per row, the number of valid pixels per row, the total number of rows per frame, and the number of valid rows per frame of the nth video frame and the n+1th video frame are all equal, determining that the nth video frame is a valid video frame;

[0163] When any of the total number of clocks per row, the number of valid pixels per row, the total number of rows per frame, and the number of valid rows per frame of the nth video frame and the n+1th video frame are not equal, the nth video frame is determined to be an invalid video frame.

[0164] Optionally, step 203 includes:

[0165] When the enable signal is received, an output-side timing signal is generated in the local clock domain.

[0166] The present invention labels the audio data according to the validity of the video frame when the format of the video stream on the same channel is switched, thereby calibrating the valid and invalid audio data. Only the audio data of the valid video frame is played, and the invalid audio data is filtered out, thereby ensuring the continuity of the audio data and eliminating the noise of the audio playback.

[0167] The various component embodiments of the present disclosure can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the computing processing equipment according to the embodiments of the present disclosure. The present disclosure can also be implemented as a device or apparatus program (e.g., computer program and computer program product) for executing a part or all of the methods described herein. Such a program implementing the present disclosure can be stored on a non-transient computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0168] For example, Figure 8 A computing processing device is shown that can implement the method according to the present disclosure. The computing processing device conventionally includes a processor 310 and a computer program product or non-transitory computer-readable medium in the form of a memory 320. The memory 320 can be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk or a ROM. The memory 320 has a storage space 330 for program code 331 for executing any method step in the above method. For example, the storage space 330 for program code can include individual program codes 331 for implementing various steps in the above method respectively. These program codes can be read from or written to one or more computer program products. These computer program products include program code carriers such as a hard disk, a compact disk (CD), a memory card or a floppy disk. Such a computer program product is typically as described in reference to Figure 9 The portable or fixed storage unit. The storage unit may have Figure 8 The memory 320 in the computing and processing device may be similarly arranged as a memory segment, storage space, or the like. The program code may be compressed, for example, in a suitable form. Typically, the storage unit includes computer-readable code 331′, i.e., code that can be read by a processor such as 310, and when executed by the computing and processing device, causes the computing and processing device to perform the steps of the method described above.

[0169] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0170] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0171] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0172] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0173] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A video output circuit, characterized in that: The circuit comprises: a video parsing subcircuit configured to send video frames and audio data obtained by parsing the video stream to the video detection subcircuit when a signal format of the video stream received through the target channel changes; The video detection subcircuit is configured to, when the video frame is a valid video frame, add a valid tag to the audio data, write the audio data into the audio buffer, and send an enable signal to the output-side timing generation subcircuit; The video detection subcircuit is further configured to compare the video timing of the nth video frame with the video timing of the n+1th video frame to determine whether the nth video frame is a valid video frame, wherein the video timing includes at least: a horizontal synchronization signal, a vertical synchronization signal, and a valid display data selection signal; The output-side timing generation subcircuit is configured to generate an output-side timing signal corresponding to the valid video frame based on the enable signal, and send the output-side timing signal to the video output subcircuit and the audio output subcircuit respectively; The video output subcircuit is configured to output the valid video frame according to the output side timing signal; The audio output sub-circuit is configured to read the audio data in the audio buffer according to the output-side timing signal, and encode the audio data with the valid tag added thereto and then output it.

2. The circuit according to claim 1, wherein: The video analysis sub-circuit is further configured to: Parsing the video stream to obtain audio auxiliary data; The audio output subcircuit includes: an audio sampling clock creation module, configured to construct an audio sampling clock according to the audio auxiliary data; an audio encoding module, configured to read the audio data from the audio buffer based on the audio sampling clock when receiving the output-side timing signal; Encoding the audio data to which the valid tag is added to obtain an audio analog signal; The audio output module is configured to output the audio analog signal.

3. The circuit according to claim 2, characterized in that The audio auxiliary data includes at least: a timing tree complex, a video clock, and audio clock parameters; The audio sampling clock creation module is further configured to construct an audio sampling clock through a crystal oscillator based on the timing tree complex, the video clock, and the audio clock parameters.

4. The circuit according to claim 3, characterized in that The audio sampling clock creation module is further configured to: The audio sampling clock is constructed using the following formula: Fs = (N*Ftmds) / (CTS*128); Wherein, the Fs represents an audio sampling clock, the N represents an audio clock parameter, the Ftmds represents a video frame clock, and the CTS represents a timing tree complex.

5. The circuit according to claim 1, wherein: The video detection sub-circuit is further configured to: Analyze the line synchronization signal, the field synchronization signal, and the effective display data selection signal to obtain the total number of clocks per line, the number of effective pixels per line, the total number of lines per frame, and the number of effective lines per frame of the nth video frame and the (n+1)th video frame; When the total number of clocks per row, the number of valid pixels per row, the total number of rows per frame, and the number of valid rows per frame of the nth video frame and the n+1th video frame are all equal, determining that the nth video frame is a valid video frame; When any of the total number of clocks per row, the number of valid pixels per row, the total number of rows per frame, and the number of valid rows per frame of the nth video frame and the n+1th video frame are not equal, the nth video frame is determined to be an invalid video frame.

6. The circuit according to claim 1, wherein: The output-side timing generation sub-circuit is further configured as follows: When the enable signal is received, an output-side timing signal is generated in the local clock domain.

7. A video output method, characterized in that: The method comprises: When a signal format of a video stream received through a target channel changes, parsing the video stream to obtain video frames and audio data; Comparing the video timing of the nth video frame with the video timing of the n+1th video frame to determine whether the nth video frame is a valid video frame, wherein the video timing includes at least: a line synchronization signal, a field synchronization signal, and a valid display data selection signal; If the video frame is a valid video frame, adding a valid tag to the audio data and then writing the audio data into an audio buffer; Generating an output side timing signal corresponding to the valid video frame; The valid video frame is output according to the output side timing signal, the audio data in the audio buffer is read according to the output side timing signal, and the audio data with the valid tag added is encoded and then output.

8. The method according to claim 7, characterized in that The method further comprises: Parsing the video stream to obtain audio auxiliary data; The step of reading the audio data in the audio buffer according to the output-side timing signal and encoding the audio data with the valid tag added thereto and outputting the encoded audio data comprises: constructing an audio sampling clock according to the audio auxiliary data; When receiving the output-side timing signal, reading the audio data from the audio buffer based on the audio sampling clock; Encoding the audio data to which the valid tag is added to obtain an audio analog signal; The analog audio signal is output.

9. The method according to claim 8, characterized in that The audio auxiliary data includes at least: a timing tree complex, a video clock, and audio clock parameters; The step of constructing an audio sampling clock according to the audio auxiliary data comprises: An audio sampling clock is constructed through a crystal oscillator based on the timing tree complex, the video clock, and the audio clock parameters.

10. The method according to claim 9, characterized in that The method of constructing an audio sampling clock through a crystal oscillator based on the timing tree complex, the video clock, and the audio clock parameters includes: The audio sampling clock is constructed using the following formula: Fs = (N*Ftmds) / (CTS*128); Wherein, the Fs represents an audio sampling clock, the N represents an audio clock parameter, the Ftmds represents a video frame clock, and the CTS represents a timing tree complex.

11. The method according to claim 7, characterized in that The comparing the video timing of the nth video frame with the (n+1)th video frame to determine whether the nth video frame is a valid video frame includes: Analyze the line synchronization signal, the field synchronization signal, and the effective display data selection signal to obtain the total number of clocks per line, the number of effective pixels per line, the total number of lines per frame, and the number of effective lines per frame of the nth video frame and the (n+1)th video frame; When the total number of clocks per row, the number of valid pixels per row, the total number of rows per frame, and the number of valid rows per frame of the nth video frame and the n+1th video frame are all equal, determining that the nth video frame is a valid video frame; When any of the total number of clocks per row, the number of valid pixels per row, the total number of rows per frame, and the number of valid rows per frame of the nth video frame and the n+1th video frame are not equal, the nth video frame is determined to be an invalid video frame.

12. The method according to claim 7, characterized in that Generating the output side timing signal corresponding to the valid video frame includes: When an enable signal is received, an output-side timing signal is generated in the local clock domain.

13. A computing and processing device, characterized in that: include: a memory having computer readable code stored therein; One or more processors, when the computer-readable code is executed by the one or more processors, the computing processing device performs the video output method according to any one of claims 7 to 12.

14. A non-transitory computer-readable medium, characterized in that A computer program for the video output method according to any one of claims 7 to 12 is stored therein.

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