Motherboard, array substrate, and display device

Abstract

The mother board, array substrate and display device provided by the present disclosure include a plurality of array substrates arranged in an array. The array substrate includes a display area, a first border area located on one side of the display area, and a second border area located on the side of the display area away from the first border area. Among them, a plurality of lighting test terminals are provided in the first border area, and a plurality of connection holes are provided in the second border area. The boundaries of the first border areas of adjacent array substrates in the column direction coincide with the boundaries of the second border areas; a plurality of lighting test lines are coupled to the lighting test terminals and extend to the second border areas of adjacent array substrates in the column direction; a plurality of array detection lines penetrate the row gaps between adjacent two rows of the display area and are coupled to the lighting test lines. The array detection line includes a first branch located in the second border area, and the first branch includes a first conductive structure and a second conductive structure arranged in parallel. At least one of the first conductive structure and the second conductive structure includes a plurality of island structures.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a mother board, an array substrate, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high image quality, no radiation, and convenient carrying. In recent years, it has developed rapidly and has gradually replaced the traditional Cathode Ray Tube display (CRT), occupying a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various products of different sizes, covering almost all the main electronic products in today's information society, such as liquid crystal TVs, high-definition digital TVs, computers (desktop and notebook), mobile phones, tablet computers, navigators, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays, etc. Summary of the Invention

[0003] Embodiments of the present disclosure provide a mother board, an array substrate, and a display device to improve display abnormalities caused by static electricity and improve the product yield.

[0004] A mother board provided by an embodiment of the present disclosure includes:

[0005] A plurality of array substrates arranged in an array, the array substrate including a display area, a first border area on one side of the display area, and a second border area on a side of the display area away from the first border area, wherein, a plurality of lighting test terminals are provided in the first border area, a plurality of connection holes are provided in the second border area, and the boundaries of the first border areas of the adjacent array substrates in the column direction coincide with the boundaries of the second border areas;

[0006] A plurality of lighting test lines, coupled to the lighting test terminals and extending to the second border areas of the adjacent array substrates in the column direction;

[0007] A plurality of array detection lines, penetrating through the row gaps between adjacent two rows of the display area and coupled to the lighting test lines, the array detection line including a first part located in the second border area, the first part including a first conductive structure and a second conductive structure arranged in parallel, and at least one of the first conductive structure and the second conductive structure includes a plurality of island structures.

[0008] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, the layer where the second conductive structure is located is between the layer where the first conductive structure is located and the layer where the lighting test line is located, and the first conductive structure includes a plurality of first island structures.

[0009] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, the connection hole includes a first connection hole for coupling the first conductive structure and the second conductive structure, the second conductive structure includes a hollow structure, and the orthographic projection of the hollow structure on the plane of the array substrate is located within the orthographic projection of the first connection hole on the plane of the array substrate.

[0010] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, the second conductive structure includes a plurality of second island structures.

[0011] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, at least one of the second island structures includes a series part and a parallel part integrally arranged, the parallel part is arranged in parallel with the first island structure, and the series part is coupled between two adjacent first island structures.

[0012] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, at least one of the first island structures includes the second series part and the second parallel part integrally arranged, the second parallel part is arranged in parallel with the second island structure, and the second series part is coupled between two adjacent second island structures.

[0013] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, the array substrate further includes a transfer electrode covering the connection hole, the lighting test line and the transfer electrode are arranged on the same layer, and the minimum distance between the lighting test line and the transfer electrode is greater than or equal to a preset value to prevent static electricity on the lighting test line from being transmitted to the connection hole through the transfer electrode.

[0014] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, the array substrate further includes an inner common electrode line wound around the display area and an outer common electrode line located on the side of the inner common electrode line away from the display area;

[0015] The connection holes include a second connection hole located between the inner common electrode line and the outer common electrode line, and a third connection hole at a corner of the second border area away from the display area and on a side of the outer common electrode line away from the inner common electrode line; the transfer electrodes include a second transfer electrode covering the second connection hole and a third transfer electrode covering the third connection hole, and a minimum distance between the lighting test line and the second transfer electrode or the third transfer electrode is greater than or equal to 1300 μm.

[0016] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, the connection holes include first connection holes for coupling the first conductive structure and the second conductive structure, the transfer electrodes include first transfer electrodes covering the first connection holes, and a minimum distance between the lighting test line and the first transfer electrodes is greater than or equal to 5000 μm. In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, the array detection line further includes a second branch coupled to an end of the first branch, and the second branch is disposed on the same layer as the first conductive structure.

[0017] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, the array substrate includes gate lines and data lines intersecting in the display area, the first conductive structure is disposed on the same layer as the gate lines, and the second conductive structure is disposed on the same layer as the data lines.

[0018] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, the array substrate includes pixel electrodes arranged in an array in the display area, and the lighting test line is disposed on the same layer as the pixel electrodes.

[0019] Based on the same inventive concept, the embodiments of the present disclosure provide an array substrate, which is obtained by cutting the above-mentioned mother board provided by the embodiments of the present disclosure.

[0020] Based on the same inventive concept, the embodiments of the present disclosure provide a display device, including an array substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the counter substrate, wherein the array substrate is the above-mentioned array substrate provided by the embodiments of the present disclosure.

[0021] The beneficial effects of the present disclosure are as follows:

[0022] The mother board, array substrate and display device provided by the embodiments of the present disclosure include a plurality of array substrates arranged in an array. The array substrate includes a display area, a first border area located on one side of the display area, and a second border area located on the side of the display area away from the first border area. Among them, a plurality of lighting test terminals are provided in the first border area, and a plurality of connection holes are provided in the second border area. The boundaries of the first border areas of adjacent array substrates in the column direction coincide with the boundaries of the second border areas; a plurality of lighting test lines are coupled to the lighting test terminals and extend to the second border areas of adjacent array substrates in the column direction; a plurality of array detection lines are coupled to the lighting test lines, and the array detection lines include a first part located in the second border area. The first part includes a first conductive structure and a second conductive structure arranged in parallel. At least one of the first conductive structure and the second conductive structure includes a plurality of island structures. By setting at least one of the first conductive structure and the second conductive structure to include a plurality of island structures, it is equivalent to making the large first conductive structure and / or second conductive structure into small pieces and then connecting them in parallel. In this way, the accumulation of static electricity on the array detection lines can be reduced, and the probability of discharging to the adjacent connection holes due to excessive static electricity can be lowered. Therefore, the abnormal function of the signal lines connected to the connection holes caused by static electricity is improved, and the product yield is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of the mother board provided by the embodiments of the present disclosure;

[0024] Figure 2 Schematic diagram of static electricity defect provided by the embodiments of the present disclosure;

[0025] Figure 3 For Figure 1 An enlarged schematic diagram of area Z1 in

[0026] Figure 4a For Figure 3 An enlarged schematic diagram of area Z2 in

[0027] Figure 4b For Figure 4a Schematic diagram of the layer where the first conductive structure is located in

[0028] Figure 4c For Figure 4a Layer change schematic diagram of

[0029] Figure 5 For the cross-sectional view along line III-IV in Figure 4a

[0030] Figure 6 For the cross-sectional view along line I-II in Figure 4a

[0031] Figure 7 For Figure 1 ​​Another enlarged schematic view of region Z1 in

[0032] Figure 8a is Figure 7 An enlarged schematic view of region Z3 in

[0033] Figure 8b is Figure 8a A schematic view of the layer where the first conductive structure is located in

[0034] Figure 8c is Figure 8a A schematic view of layer change of

[0035] Figure 9 is Figure 8a A cross-sectional view along line V-VI in

[0036] Figure 10 is Figure 8a A cross-sectional view along line VII-VIII in

[0037] Figure 11 is Figure 1 Another enlarged schematic view of region Z1 in

[0038] Figure 12a is Figure 11 An enlarged schematic view of region Z4 in

[0039] Figure 12b is Figure 12a A schematic view of the layer where the first conductive structure is located in

[0040] Figure 12c is Figure 12a A schematic view of layer change of

[0041] Figure 13 is Figure 12a A cross-sectional view along line XI-XII in

[0042] Figure 14 is Figure 12a A cross-sectional view along line IX-X in

[0043] Figure 15 is Figure 1 An enlarged schematic view of region Z5 in

[0044] Figure 16 A schematic view of the display device provided by the embodiment of the present disclosure. Detailed implementation manners

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure. Also, the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted in the present disclosure.

[0046] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the field to which the present disclosure pertains. The terms "first", "second", and similar terms used in the specification and claims of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms "including" or "comprising" and the like mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms "inside", "outside", "above", "below", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0047] When designing the product, considering factors such as cost and equipment, the requirement for glass utilization rate is to be maximized, and there will be a situation where the array substrates on the glass substrate (GLASS) are tightly typeset with a spacing of 0 between the array substrates (zero cut). In the normal case during product design, after the array process is completed, array testing (Array Test, AT) is required to ensure that when there is an abnormality in the process, it can be detected at the array substrate stage 100%, with early warning to avoid waste of materials in the subsequent process and increase the product cost.

[0048] As Figure 1 shown, each signal inside the array substrate is connected to the array test line (ATL) through the pull-down signal line (i.e., the lighting test line ETL) of the lighting test terminal (ET PAD). The array test line (ATL) is connected to the array test terminal (ATPAD), and the detection signal is given by the array test terminal (AT PAD) for array testing. In some special typesetting situations, as Figure 1 shown, when the dual in-line package opposite (DPO) and the dual in-line package side (DP) are designed with zero cut and the array test line (ATL) passes through the dual in-line package opposite (DPO) and the dual in-line package side (DP), the common voltage (Com) test line in the array test line (ATL) will connect all the common electrode lines (CL) of several array substrates together to form a large piece of metal, which is extremely likely to accumulate static electricity during the production and manufacturing process. The static electricity discharges through the lighting test line (ETL) to the closest connection hole (h). As Figure 2As shown, there are two discharge paths for static electricity. When the discharge path is connected to the in-plane functional signal (discharge path 1), it will cause the abnormal function of the signal line connected to the via hole (h). When the discharge path is not connected to the in-plane, the static electricity will cross the common electrode line (CL) and release to other points in the plane (discharge path 2), causing the internal functional via holes (h) and traces of the array substrate to burn out, resulting in display defects and affecting the product yield.

[0049] To solve the above technical problems existing in the related art, an embodiment of the present disclosure provides a mother board, as Figure 1 and Figure 3 shown, including:

[0050] A plurality of array substrates 001 arranged in an array. The array substrate 001 includes a display area AA, a first border area BB1 (i.e., the terminal side DP) located on one side of the display area AA, and a second border area BB2 (i.e., the terminal opposite side DPO) located on the side of the display area AA away from the first border area BB1. Among them, a plurality of lighting test terminals 101 are provided in the first border area BB1, and a plurality of via holes 102 are provided in the second border area BB2. The boundaries of the first border area BB1 and the second border area BB2 of adjacent array substrates 001 in the column direction Y coincide. Specifically, the horizontal cutting line L1 represents the coincident boundary between the adjacent first border area BB1 and the second border area BB2.

[0051] A plurality of lighting test lines 103, which are coupled to the lighting test terminals 101 and extend to the second border area BB2 of the adjacent array substrate 001 in the column direction Y.

[0052] A plurality of array detection lines 104, which penetrate the row gaps between adjacent two rows of the display area AA and are coupled to the lighting test lines 103. The array detection line 104 includes a first branch 41 located in the second border area BB2. The first branch 41 includes a first conductive structure 411 and a second conductive structure 412 arranged in parallel. At least one of the first conductive structure 411 and the second conductive structure 412 includes a plurality of island structures (for example Figure 3 shows that the first island structure 411 includes a plurality of first island structures 4111).

[0053] In the motherboard provided in the embodiment of the present disclosure, by setting at least one of the first conductive structure 411 and the second conductive structure 412 to include a plurality of island structures, it is equivalent to breaking the large first conductive structure 411 and / or the second conductive structure 412 into small pieces and connecting them in parallel, which can reduce the accumulation of static electricity on the array detection line 104 and reduce the probability of discharging to the adjacent connection hole 102 due to excessive static electricity, thereby improving the abnormal function of the signal line connected to the connection hole 102 caused by static electricity and improving the product yield. In addition, the first conductive structure 411 and the second conductive structure 412 are arranged in parallel, which can reduce the impedance of the array detection line 104 and improve the accuracy of detection.

[0054] In some embodiments, in the above motherboard provided in the embodiments of the present disclosure, as Figure 3 , Figure 4a , Figure 4b , Figure 5 and Figure 6 As shown, the layer where the second conductive structure 412 is located is located between the layer where the first conductive structure 411 is located and the layer where the switching electrode 105 is located, and a first passivation layer PVX1 can be arranged between the layer where the first conductive structure 411 is located and the layer where the second conductive structure 412 is located, and a second passivation layer PVX2, a flat layer PLN and a third passivation layer PVX3 are arranged between the layer where the second conductive structure 412 is located and the layer where the switching electrode 105 is located. The first conductive structure 411 can include a plurality of first island structures 4111, which is equivalent to breaking the large first conductive structure 411 into small pieces and connecting them in parallel with the second conductive structure 412, which can reduce the accumulation of static electricity and reduce the probability of poor display caused by static electricity.

[0055] In some embodiments, in the above motherboard provided in the embodiments of the present disclosure, as Figure 3 , Figure 4c and Figure 6 As shown, the connection hole 102 includes a first connection hole 21 for coupling the first conductive structure 411 and the second conductive structure 412, the transfer electrode 105 includes a first transfer electrode 51 covering the first connection hole 21, the second conductive structure 712 is continuous as a whole, and may include a hollow structure K arranged corresponding to the first connection hole 21, the orthographic projection of the hollow structure K on the plane where the array substrate 001 is located is located within the orthographic projection of the first connection hole 21 on the plane where the array substrate 001 is located, and in a specific implementation, the first island structure 4111 can be partially exposed through the hollow structure K, so that the first transfer electrode 51 can be coupled to the first island structure 4111 at the hollow structure K, and coupled to the second conductive structure 412 in the area where the first connection hole 21 and the hollow structure K do not overlap.

[0056] In some embodiments, in the above motherboard provided by the embodiment of the present disclosure, the second conductive structure 712 can not only beFigure 3 , Figure 4a and Figure 4c shown in continuous setting, or as shown in Figure 7 , Figure 8a , Figure 8c , Figure 9 and Figure 10 shown, the second conductive structure 412 is set to include a plurality of second island-like structures 4121, which is equivalent to making the large second conductive structure 412 into small pieces and then connecting it in parallel with the first conductive structure 411 to reduce electrostatic accumulation and lower the probability of electrostatic-induced display defects. And as shown in Figure 7 , Figure 8a , Figure 8b , Figure 9 and Figure 10 shown, the first conductive structure 411 includes a plurality of first island-like structures 4111, and the first island-like structures 4111 are arranged in parallel with the second island-like structures 4121; that is, both the first conductive structure 411 and the second conductive structure 412 are designed in an island-like manner, thus greatly reducing electrostatic accumulation and significantly improving electrostatic-induced display defects.

[0057] It should be understood that the first conductive structure 411 in the present disclosure may contain Figure 7 , Figure 8a , Figure 8b , Figure 9 and Figure 10 shown a smaller number of first island-like structures 4111, or may contain Figure 11 , Figure 12a , Figure 12b , Figure 13 and Figure 14 shown a larger number of first island-like structures 4111 in; correspondingly, the second conductive structure 412 may also contain Figure 7 , Figure 8a , Figure 8c , Figure 9 and Figure 10 shown a smaller number of second island-like structures 4121, or may contain Figure 11 , Figure 12a , Figure 12c , Figure 13 and Figure 14 shown a larger number of second island-like structures 4121 in. The more the number of the first island-like structures 4111 and the second island-like structures 4121, the more conducive to reducing electrostatic accumulation and avoiding electrostatic-induced display defects.

[0058] In some embodiments, such as Figure 8a , Figure 8b , Figure 8c , Figure 10 , Figure 12a , Figure 12b , Figure 12c andFigure 14 As shown, in the present disclosure, at least one second island structure 4121 includes an integrally provided first series part C1 and a first parallel part P1. The first parallel part P1 is arranged in parallel with the first island structure 4111, and the first series part C1 is coupled between two adjacent first island structures 4111. In other words, in the area of the first parallel part P1 of the first sub-part 41, there are two film layers including the first island structure 4111 and the second island structure 4121, and in the area of the first series part C1, there is only one film layer of the second island structure 4121, that is, a layer-changing design is performed in the area of the first series part C1 of the first sub-part 41. It should be noted that in the first parallel part P1 and the first island structure 4111 that are arranged in parallel with each other, the orthographic projection of the first island structure 4111 on the plane where the array substrate 001 is located can be located within the orthographic projection of the first parallel part P1 on the plane where the array substrate 001 is located; in the first series part C1 and the first island structure 4111 that are connected in series with each other, only the end orthographic projections of the two overlap with each other.

[0059] Continue to refer to Figure 8a 、 Figure 8b 、 Figure 8c 、 Figure 10 、 Figure 12a 、 Figure 12b 、 Figure 12c and Figure 14 It can be seen that at least one first island structure 4111 in the present disclosure may include an integrally provided second series part C2 and a second parallel part P2. The second parallel part P2 is arranged in parallel with the second island structure 4121, and the second series part C2 is coupled between two adjacent second island structures 4121. In other words, in the area of the second parallel part P2 of the first sub-part 41, there are two film layers including the first island structure 4111 and the second island structure 4121, and in the area of the second series part C2, there is only one film layer of the second island structure 4121, that is, a layer-changing design is performed in the area of the second series part C2 of the first sub-part 41. It should be noted that in the second parallel part P2 and the second island structure 4121 that are arranged in parallel with each other, the orthographic projection of the second island structure 4121 on the plane where the array substrate 001 is located can be located within the orthographic projection of the second parallel part P2 on the plane where the array substrate 001 is located; in the second series part C2 and the second island structure 4121 that are connected in series with each other, only the end orthographic projections of the two overlap with each other.

[0060] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, such as Figure 3 、 Figure 6 、 Figure 7 、 Figure 10 、 Figure 11 and Figure 14As shown, the array detection line 104 may further include a second branch 42 coupled to the end of the first branch 41, and the second branch 42 is disposed on the same layer as the first conductive structure 411. It should be noted that in the present disclosure, the parallel region is a double-film layer structure, which functions to reduce resistance; the series region is a single-film layer structure, which functions to change layers. Therefore, when a plurality of first island structures 4111 (belonging to the first conductive structure 411) are arranged in parallel with the continuously arranged second conductive structure 412, and the second branch 42 is disposed on the same layer as the first conductive structure 411, it is equivalent to a layer-changing design of the array detection line 104 as a whole from the layer where the first conductive structure 411 is located - the layer where the second conductive structure 412 is located - the layer where the first conductive structure 411 is located, as Figure 4c shown. When the first island structure 4111 closest to the second branch 42 is integrally provided with the second branch 42 and has a second series portion C2, and the remaining first island structures 4111 are arranged in parallel with the first parallel portion P1 of the second island structure 4121, it is equivalent to a layer-changing design of the array detection line 104 as a whole from the layer where the first conductive structure 411 is located - the layer where the second conductive structure 412 is located - the layer where the first conductive structure 411 is located, as Figure 8c shown. When the first island structure 4111 closest to the second branch 42 is integrally provided with the second branch 42 and has a second series portion C2, the second island structure 4121 closest to the second branch 42, and the second island structure 4121 located near the symmetry axis extending in the column direction Y of the first branch 41 are respectively arranged in parallel with the second parallel portion P2, and the remaining second island structures 4121 include a first series portion C1 connected in series with the second island structure 421, it is equivalent to a multiple layer-changing design of the array detection line 104 as a whole from the layer where the first conductive structure 411 is located - the layer where the second conductive structure 412 is located - the layer where the first conductive structure 411 is located - the layer where the second conductive structure 412 is located - the layer where the first conductive structure 411 is located -... - the layer where the first conductive structure 411 is located. The more layer-changing designs there are, it means the more the number of the first island structures 4111 and the second island structures 4121, and the smaller the size, which is more conducive to reducing electrostatic accumulation and greatly reduces the probability of electrostatic-induced display defects.

[0061] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, as Figure 3 、 Figure 7 、 Figure 11 and Figure 15As shown, a transfer electrode 105 may cover the transfer hole 102. Optionally, the lighting test line 103 is disposed on the same layer as the transfer electrode 105, and the minimum distance (such as a, b, c) between the lighting test line 103 and the transfer electrode 105 is greater than or equal to a preset value to avoid being affected by static electricity due to insufficient distance between the lighting test line 103 and the transfer electrode 105, effectively preventing the static electricity on the lighting test line 103 from being transmitted to the connection hole 102 through the transfer electrode 105. Therefore, the functional abnormality of the signal line connected to the connection hole 102 caused by static electricity is improved, and the product yield is increased.

[0062] It should be noted that the connection hole 102 in the present disclosure includes a first connection hole 21 for coupling the first conductive structure 411 and the second conductive structure 412. By setting the minimum distance c between the first connection hole 21 and the lighting test line 103 to be relatively large (for example, greater than 5000 μm), the display defect caused by static electricity can be improved; combined with the islanding design scheme of the above-mentioned first conductive structure 411 and the second conductive structure 412, the static electricity accumulation can be reduced, thereby better preventing the display defect caused by static electricity.

[0063] It should be noted that in the present disclosure, "the same layer" means a layer structure formed by using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask plate through a single patterning process. That is, a single patterning process corresponds to one mask plate (also called a photomask). According to the different specific patterns, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or may be at different heights or have different thicknesses.

[0064] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, such as Figure 1 and Figure 14As shown, the array substrate 001 further includes an inner common electrode line 106 wound around the display area AA, and an outer common electrode line 107 located on a side of the inner common electrode line 106 away from the display area AA; the connection hole 102 includes a second connection hole 22 located between the inner common electrode line 106 and the outer common electrode line 107, and a third connection hole 23 located at a corner of the second frame area BB2 away from the display area AA and on a side of the outer common electrode line 107 away from the inner common electrode line 106; the transfer electrode 105 includes a second connection hole 22 covering the second connection hole 22. The inventors have discovered that when the minimum spacing a between the lighting test line 103 and the second transfer electrode 52, and the minimum spacing b between the lighting test line 103 and the third transfer electrode 53 are respectively greater than or equal to 1300 μm, it is possible to effectively avoid electrostatic discharge caused by insufficient spacing between the lighting test line 103 and the second transfer electrode 52 or the third transfer electrode 53, thereby burning out the second connection hole 22 or the third connection hole 23 and causing poor display.

[0065] In some embodiments, in the above motherboard provided by the embodiment of the present disclosure, the array substrate 001 may include gate lines and data lines intersectingly arranged in the display area AA, the first conductive structure 411 is arranged in the same layer as the gate lines, and the second conductive structure 412 is arranged in the same layer as the data lines. Figure 3 , Figure 6 , Figure 7 , Figure 10 , Figure 11 and Figure 14 It can be seen that the two ends of the array detection line 104 are the second divisions 42 arranged in the same layer as the first conductive structure 411. Therefore, when the first conductive structure 411 is arranged in the same layer as the gate line, the second division 42 is also arranged in the same layer as the gate line. The material of the gate line (such as molybdenum metal) is usually not easily corroded by water and oxygen, while the material of the data line (such as titanium metal layer / aluminum metal layer / titanium metal layer) is easily corroded by water and oxygen. Therefore, when the second division 42 is also arranged in the same layer as the gate line, the two ends of the array detection line 104 are not easily corroded by water and oxygen, and then the water and oxygen can be effectively prevented from corroding the second conductive structure 412 of the first division 41 along the second division 42, thereby improving the yield of the array detection line 104.

[0066] In some embodiments, in the above-mentioned mother board provided by the embodiments of the present disclosure, the array substrate 001 may further include pixel electrodes (pixels) arranged in an array within the display area AA, and the lighting test line 103 may be provided on the same layer as the pixel electrodes. The material of the pixel electrodes is usually a transparent conductive material with good waterproof and oxygen-proof effects, such as indium tin oxide (ITO) and indium zinc oxide (IZO). By setting the lighting test line 103 on the same layer as the pixel electrodes, it is possible to prevent water and oxygen from easily eroding the cutting port of the lighting test line 103 after the array substrate 001 is divided along the horizontal cutting line L1, thereby preventing water and oxygen from invading the lighting test terminal 101 through the lighting test line 103 and avoiding corrosion of the lighting test terminal 101.

[0067] Based on the same inventive concept, the embodiments of the present disclosure provide an array substrate, which can be obtained by cutting the mother board along the Figure 1 shown horizontal cutting line L1 and vertical cutting line L2. Since the principle of solving problems of this array substrate is similar to that of the above-mentioned mother board, the implementation of this array substrate provided by the embodiments of the present disclosure can refer to the implementation of the above-mentioned mother board provided by the embodiments of the present disclosure, and the repeated parts will not be described again.

[0068] Based on the same inventive concept, the embodiments of the present disclosure provide a display device, as Figure 16 shown, including an array substrate 001 and a counter substrate 002 (also called a color filter substrate) arranged opposite to each other, and a liquid crystal layer 003 located between the array substrate 001 and the counter substrate 002. The array substrate 001 is the above-mentioned array substrate 001 provided by the embodiments of the present disclosure. Since the principle of solving problems of this display device is similar to that of the above-mentioned array substrate, the implementation of this display substrate provided by the embodiments of the present disclosure can refer to the implementation of the above-mentioned array substrate provided by the embodiments of the present disclosure, and the repeated parts will not be described again.

[0069] In some embodiments, as Figure 16 shown, the above-mentioned display device provided by the embodiments of the present disclosure may further include a backlight module 004 located on the light incident side of the array substrate 001, and this backlight module may be Figure 16 the direct-lit backlight module shown, or may be a side-lit backlight module. Optionally, the direct-lit backlight module may include a matrix light source, a reflective sheet, a diffusion plate, a brightness enhancement film, etc. stacked on the light output side of the matrix light source. The reflective sheet includes openings arranged opposite to the positions of the lamp beads in the matrix light source; the side-lit backlight module may include a light bar, a reflective sheet, a light guide plate, a diffusion sheet, a prism group, etc. stacked, and the light bar is located on one side in the thickness direction of the light guide plate.

[0070] The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.). Micro light-emitting diodes with a sub-millimeter scale or even a micron scale, like organic light-emitting diodes (OLEDs), belong to self-luminous devices. Similar to organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and a large viewing angle. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting diodes that emit light based on organic substances, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life. Moreover, when micro light-emitting diodes are used as backlights, a more precise dynamic backlight effect can be achieved. While effectively improving the screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlights between the bright and dark areas of the screen, optimizing the visual experience.

[0071] In some embodiments, the display device can be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any product or component with a display function. The display device includes but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip, etc. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory and a power module, etc., and realizes the power supply and signal input / output functions through additional wires, signal lines, etc. For example, the control chip may further include a hardware circuit and computer-executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors such as logic chips, transistors, or other discrete components; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, etc. Additionally, those skilled in the art can understand that the above structure does not constitute a limitation on the above display device provided by the embodiments of the present disclosure. In other words, the above display device provided by the embodiments of the present disclosure may include more or fewer of the above components, or combine some components, or have different component arrangements.

[0072] Although the preferred embodiments of the present disclosure have been described, it should be understood that those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.

Claims

1. A motherboard, characterized in that, Including: A plurality of array substrates arranged in an array. The array substrate includes a display area, a first border area located on one side of the display area, and a second border area located on the side of the display area far from the first border area. Wherein, a plurality of lighting test terminals are provided in the first border area, and a plurality of connection holes are provided in the second border area. The boundaries of the first border areas of the adjacent array substrates in the column direction coincide with the boundaries of the second border areas; A plurality of lighting test lines, which are coupled to the lighting test terminals and extend to the second border areas of the adjacent array substrates in the column direction; A plurality of array detection lines, which penetrate the row gaps between adjacent two rows of the display areas and are coupled to the lighting test lines. The array detection line includes a first branch located in the second border area. The first branch includes a first conductive structure and a second conductive structure arranged in parallel. At least one of the first conductive structure and the second conductive structure includes a plurality of island structures; Wherein, the layer where the second conductive structure is located is between the layer where the first conductive structure is located and the layer where the lighting test line is located. The first conductive structure includes a plurality of first island structures, and the second conductive structure includes a plurality of second island structures.

2. The motherboard according to claim 1, wherein The connection hole includes a first connection hole for coupling the first conductive structure and the second conductive structure. The second conductive structure includes a hollow structure, and the orthographic projection of the hollow structure on the plane where the array substrate is located is located within the orthographic projection of the first connection hole on the plane where the array substrate is located.

3. The motherboard according to claim 1, characterized in that, At least one of the second island structures includes a first series part and a first parallel part integrally arranged. The first parallel part is arranged in parallel with the first island structure, and the first series part is coupled between two adjacent first island structures.

4. The mother board according to claim 1 or 3, characterized in that At least one of the first island structures includes a second series part and a second parallel part integrally arranged. The second parallel part is arranged in parallel with the second island structure, and the second series part is coupled between two adjacent second island structures.

5. The mother board according to any one of claims 1 to 3, characterized in that, The array substrate further includes a transfer electrode covering the connection hole. The lighting test line is arranged on the same layer as the transfer electrode. The minimum distance between the lighting test line and the transfer electrode is greater than or equal to a preset value to prevent static electricity on the lighting test line from being transmitted to the connection hole through the transfer electrode.

6. The motherboard according to claim 5, characterized in that, The array substrate further includes an inner common electrode line wound around the display area and an outer common electrode line located on the side of the inner common electrode line far from the display area; The connection hole includes a second connection hole located between the inner common electrode line and the outer common electrode line, and a third connection hole located at the corner of the second border area far from the display area and on the side of the outer common electrode line far from the inner common electrode line. The transfer electrode includes a second transfer electrode covering the second connection hole and a third transfer electrode covering the third connection hole. The minimum distance between the lighting test line and the second transfer electrode or the third transfer electrode is greater than or equal to 1300μm.

7. The motherboard according to claim 5, characterized in that, The connection hole includes a first connection hole for coupling the first conductive structure and the second conductive structure. The transfer electrode includes a first transfer electrode covering the first connection hole. The minimum distance between the lighting test line and the first transfer electrode is greater than or equal to 5000 μm.

8. The mother board according to any one of claims 1 to 3, 6, and 7, characterized in that, The array detection line further includes a second branch coupled to the end of the first branch, and the second branch is disposed on the same layer as the first conductive structure.

9. The mother board according to any one of claims 1 to 3, 6, and 7, characterized in that, The array substrate includes gate lines and data lines that are cross - arranged in the display area. The first conductive structure is disposed on the same layer as the gate lines, and the second conductive structure is disposed on the same layer as the data lines.

10. The mother board according to any one of claims 1 to 3, 6, and 7, characterized in that, The array substrate includes pixel electrodes arranged in an array in the display area, and the lighting test line is disposed on the same layer as the pixel electrodes.

11. An array substrate, characterized in that, The array substrate is obtained by cutting the mother board according to any one of claims 1 to 10.

12. A display device, characterized in that, It includes an array substrate and a counter substrate that face each other, and a liquid crystal layer located between the array substrate and the counter substrate. The array substrate is the array substrate according to claim 11.

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