Method and apparatus for predicting flash memory llr

Abstract

The application discloses a flash memory LLR prediction method and device, which comprises the following steps: determining the voltage distribution of each voltage region of all storage pages in a specified storage unit of a target flash memory; wherein each voltage region of all storage pages in the specified storage unit of the target flash memory comprises a plurality of voltage intervals; matching the voltage distribution of each voltage region with a plurality of groups of preset voltage distributions of the voltage region in preset sample data; wherein the voltage region in the preset sample data comprises a plurality of voltage intervals; taking the LLR value corresponding to each voltage interval corresponding to a group of preset voltage distributions in the matched preset sample data as the LLR value of each voltage interval of the voltage region; wherein the division mode of the voltage region and the voltage interval of the preset sample data is consistent with the division mode of the voltage region and the voltage interval of the target flash memory.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and more particularly to a method and apparatus for predicting LLRs in flash memory. Background Technology

[0002] Flash memory (NAND Flash) is a new type of storage medium with advantages such as large storage capacity, fast read and write speeds, long lifespan, and low cost. Solid-state drives (SSDs) using flash memory as the storage medium are being widely used in consumer PCs and enterprise data centers. However, due to the storage characteristics and manufacturing processes of flash memory, data stored in flash memory is often affected by factors such as P / E cycles, retention, and disturbances, leading to bit flips and causing uncorrectable errors when the system reads data from the flash memory.

[0003] Since the reading of flash memory information relies on comparing its voltage with the threshold voltage to determine the n bits of information represented by a cell, changes in the voltage distribution curve will cause the initially set read voltage to become inaccurate, so the read voltage needs to be adjusted. However, once two adjacent voltage curves intersect, errors that cannot be resolved by adjusting the read voltage will inevitably occur, because no matter how the read voltage is adjusted, some cells (memory units) whose voltages are located in the overlapping part will be misjudged. Figure 1 The horizontal axis represents the voltage threshold, and the vertical axis represents the number of basic storage units (i.e., the number of cells) in flash memory. Figure 1 The read level line in the image represents the adjusted optimal read voltage.

[0004] To correct these errors, various error-correcting code strategies are applied. Among them, LDPC (Low Density Parity Check Code) decoding, with its strong error-correcting capabilities and low latency, has been widely adopted. In multi-bit decoding (soft decoding) of LDPC, the accurate calculation of the initial LLR (log-likelihood ratio) value plays a crucial role in improving the decoding capability and speed (reducing the number of iterations) of LDPC decoding. Summary of the Invention

[0005] This application provides a method and apparatus for predicting LLR values ​​in flash memory, which can predict LLR values ​​with high accuracy, reduce the number of iterations in LDPC soft decoding, ensure a smaller read latency, and improve the overall decoding capability of soft decoding.

[0006] This application provides a method for predicting the LLR of a flash memory, comprising: determining the voltage distribution of each voltage region of all storage pages in a specified storage unit of a target flash memory; wherein, each voltage region of all storage pages in the specified storage unit of the target flash memory includes multiple voltage intervals;

[0007] The voltage distribution of each voltage region is matched with multiple preset voltage distributions of that voltage region in the preset sample data; wherein, the voltage region in the preset sample data includes multiple voltage intervals;

[0008] The LLR value corresponding to each voltage interval of a set of preset voltage distributions in the matched preset sample data is taken as the LLR value of each voltage interval of the voltage region.

[0009] The voltage region and voltage interval division method of the preset sample data is consistent with the voltage region and voltage interval division method of the target flash memory.

[0010] In one exemplary embodiment, determining the voltage distribution of each voltage region of all memory pages in a specified memory unit of the target flash memory includes:

[0011] Divide all storage pages in a specified storage unit of the target flash memory into multiple voltage regions, and divide the multiple voltage regions into multiple groups according to the storage page division method;

[0012] For each voltage region in each group, perform the following operation:

[0013] Determine the optimal reading voltage for this voltage region;

[0014] Based on the optimal reading voltage and preset bias value of the voltage region, multiple voltage intervals of the voltage region and the number of cells corresponding to each voltage interval are determined; the voltage region and the number of cells corresponding to each voltage interval of the voltage region constitute the voltage distribution of the voltage region.

[0015] In one exemplary embodiment, all storage pages in a designated storage unit of the target flash memory are divided into multiple voltage regions, and the multiple voltage regions are divided into multiple groups according to the storage page division method, including:

[0016] The target flash memory is divided into multiple voltage regions according to the location of the read threshold voltage, and the multiple voltage regions are further divided into multiple groups according to the storage page partitioning method.

[0017] In one exemplary embodiment, determining multiple voltage intervals of the voltage region and the number of cells corresponding to each voltage interval based on the optimal read voltage and a preset bias value of the voltage region includes:

[0018] Based on the optimal reading voltage and preset bias value of the voltage region, multiple voltage ranges of the voltage region are determined;

[0019] Based on the optimal read voltage of the voltage region, the data of the memory page where the voltage region is located is read by offsetting the preset bias value to the left and right by a preset multiple;

[0020] The number of times the data from the memory page containing the voltage region falls into each voltage range is taken as the number of cells corresponding to that voltage range.

[0021] In one exemplary embodiment, matching the voltage distribution of each voltage region with multiple sets of preset voltage distributions for that voltage region in preset sample data includes:

[0022] For each voltage region, perform the following matching operation:

[0023] The first matching difference is obtained by subtracting the absolute value of the number of cells corresponding to the corresponding voltage interval in each group of the voltage region from the number of cells corresponding to each voltage interval in the preset sample data. The second matching difference is obtained by summing the first matching differences of all voltage intervals in the voltage region.

[0024] In one exemplary embodiment, the LLR value corresponding to each voltage interval of a set of preset voltage distributions in the matched preset sample data is used as the LLR value of each voltage interval of the voltage region, including:

[0025] The preset voltage distribution of the voltage region in the preset sample data corresponding to the minimum second matching difference is taken as a set of preset voltage distributions in the preset sample data for matching;

[0026] The LLR value corresponding to each voltage interval of a set of preset voltage distributions in the matched preset sample data is taken as the LLR value of each voltage interval of the voltage region.

[0027] In one exemplary embodiment, the target flash memory is a TLC type flash memory.

[0028] In one exemplary embodiment, the preset sample data includes multiple voltage ranges and corresponding LLR values ​​obtained by converting reference voltage distribution curves of flash memory of the same type as the target flash memory at different stages of its life cycle.

[0029] This application provides a prediction device for flash memory LLR, including: a memory and a processor;

[0030] The memory is used to store the program for flash LLR prediction;

[0031] The processor is configured to read and execute the program for predicting flash LLR, and execute the aforementioned method for predicting flash LLR.

[0032] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0033] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0034] Figure 1 A statistical chart of cell voltage thresholds;

[0035] Figure 2 This is a flowchart of a flash memory LLR prediction method according to an embodiment of this application;

[0036] Figure 3 This is a schematic diagram of a prediction device for a flash LLR according to an embodiment of this application. Detailed Implementation

[0037] Figure 1 This is a flowchart of the flash memory LLR prediction method according to an embodiment of this application, as follows: Figure 1 As shown, the flash memory LLR prediction method of this embodiment includes steps S11-S13:

[0038] S11. Determine the voltage distribution of each voltage region in all memory pages of the target flash memory in a specified memory unit;

[0039] S12. Match the voltage distribution of each voltage region with multiple preset voltage distributions of that voltage region in the preset sample data;

[0040] S13. Take the LLR value corresponding to each voltage interval of a set of preset voltage distributions in the matched preset sample data as the LLR value of each voltage interval of the voltage region.

[0041] Specifically, each voltage region of all storage pages in a designated storage unit of the target flash memory includes multiple voltage intervals. The voltage regions and voltage intervals of the preset sample data are divided in the same way as those of the target flash memory.

[0042] The specified storage unit can be one or more blocks, or one or more word lines, etc.

[0043] In one exemplary embodiment, the target flash memory is a TLC type flash memory.

[0044] In one exemplary embodiment, the preset sample data includes multiple voltage ranges and corresponding LLR values ​​obtained by converting reference voltage distribution curves of flash memory of the same type as the target flash memory at different stages of its life cycle.

[0045] In step S11, in one exemplary embodiment, determining the voltage distribution of each voltage region of all storage pages in a specified storage unit of the target flash memory includes:

[0046] The storage pages in the specified storage unit of the target flash memory are divided into multiple voltage regions, and the multiple voltage regions are divided into multiple groups according to the storage page division method;

[0047] For each voltage region in each group, perform the following operation:

[0048] Determine the optimal reading voltage for this voltage region;

[0049] Based on the optimal reading voltage and preset bias value of the voltage region, multiple voltage intervals of the voltage region and the number of cells corresponding to each voltage interval are determined; the voltage region and the number of cells corresponding to each voltage interval of the voltage region constitute the voltage distribution of the voltage region.

[0050] In one exemplary embodiment, the storage pages in a designated storage unit of the target flash memory are divided into multiple voltage regions, and the multiple voltage regions are divided into multiple groups according to the storage page division method, including:

[0051] The storage pages in the specified storage unit of the target flash memory are divided into multiple voltage regions according to the location of the read threshold voltage, and the multiple voltage regions are divided into multiple groups according to the storage page division method.

[0052] Taking TLC flash memory as an example, the flash voltage is divided into N voltage regions (R1 to RN) according to the location of the read threshold voltage. For TLC flash memory, N = 7. Based on different page division methods, R1 to RN are divided into three groups: P1 group (e.g., Low page) contains n1 regions (including R1 and R5), P2 group (e.g., Middle page) contains n2 regions (R2, R4, and R6), and P3 group (e.g., Upper page) contains n3 regions (R3 and R7). This example only represents one division method, which is related to the specifications defined by the flash memory manufacturer.

[0053] Flash memory types can also include SLC, MLC, etc.

[0054] In one exemplary embodiment, the optimal read voltage for the voltage region can be determined by statistical analysis and rereading. For the aforementioned TLC flash memory, the optimal read voltages corresponding to the N voltage regions R1 to RN are Vt1 to VtN, respectively.

[0055] In one exemplary embodiment, determining multiple voltage intervals of the voltage region and the number of cells corresponding to each voltage interval based on the optimal read voltage and a preset bias value of the voltage region includes:

[0056] Based on the optimal reading voltage and preset bias value of the voltage region, multiple voltage ranges of the voltage region are determined;

[0057] Based on the optimal read voltage of the voltage region, the data of the memory page where the voltage region is located is read by offsetting the preset bias value to the left and right by a preset multiple;

[0058] The number of times the data from the memory page containing the voltage region falls into each voltage range is taken as the number of cells corresponding to that voltage range.

[0059] For example, the aforementioned P1 group includes two voltage regions (R1 and R5), with a preset offset value of delta. Assuming the optimal read voltage for R1 is Vo, the current memory page data can be read using Vo, Vo+delta, Vo+2delta, Vo+3delta, Vo-delta, Vo-2delta, and Vo-3delta as read voltages. Assuming the optimal read voltage for R5 is V1, the current memory page data can be read using V1, V1+delta, V1+2delta, V1+3delta, V1-delta, V1-2delta, and V1-3delta as read voltages. The P1 group is divided into the following 15 voltage ranges based on the reading voltage: [-∝, Vo-3delta], [Vo-3delta, Vo-2delta], [Vo-2delta, Vo-delta], [Vo-delta, Vo], [Vo, Vo+delta], [Vo, Vo+2delta], [Vo+2delta, Vo+3delta], [Vo+3delta, V1-3delta], [V1-3delta, V1-2delta], [V1-2delta, V1-delta], [V1-delta, V1], [V1, V1+delta], [V1, V1+2delta], [V1, V1+3delta], [V1+3delta, +∝]. The number of data points falling within the aforementioned voltage ranges is counted, and the number of cells corresponding to each range can be denoted as Cv1, Cv2, ..., Cvx. The number of cells in each voltage range is distinguished by voltage region. For example, G1 and G2 contain Cv1, Cv2, ..., Cv8, Cv9, Cv10, ..., Cvx, respectively. Therefore, G1 and G2 represent the voltage distribution of the two voltage regions, Low Page.

[0060] It should be noted that, under our statistical method, cells will not fall into the position of boundary voltage. After each round of reading, each cell will be statistically included in a uniquely determined voltage range.

[0061] In step S12, in an exemplary embodiment, the voltage distribution of each voltage region is matched with multiple sets of preset voltage distributions for that voltage region in preset sample data, including:

[0062] For each voltage region, perform the following matching operation:

[0063] The first matching difference is obtained by subtracting the absolute value of the number of cells corresponding to the corresponding voltage interval in each group of the voltage region from the number of cells corresponding to each voltage interval in the preset sample data. The second matching difference is obtained by summing the first matching differences of all voltage intervals in the voltage region.

[0064] For example, the multiple voltage regions Gi (i = 1, 2, 3, etc., depending on the division method of P1, P2, P3) obtained above are processed separately: multiple preset voltage distributions D0 to Dj representing the voltage region in the preset dataset (corresponding to preset sample data) are matched with Gi respectively to obtain the preset voltage distribution Dy with the highest matching degree. For example, if the voltage region has 8 voltage intervals, and the number of cells in each voltage interval is Cv1, Cv2, ..., Cv8, and the voltage intervals in the preset sample data that match the voltage region are Bv1, Bv2, ..., Bv8, then |Cv1-Bv1| is the first matching difference, and |Cv1-Bv1+|Cv2-Bv2|+...+|Cv8-Bv8| is the second matching difference. That is, matching is performed by comparing the number of basic storage units in each voltage interval of each preset sample.

[0065] In step S13, in an exemplary embodiment, the LLR value corresponding to each voltage interval of a set of preset voltage distributions in the matched preset sample data is used as the LLR value of each voltage interval of the voltage region, including:

[0066] The preset voltage distribution of the voltage region in the preset sample data corresponding to the minimum second difference is taken as a set of preset voltage distributions in the matching preset sample data;

[0067] The LLR value corresponding to each voltage interval of a set of preset voltage distributions in the matched preset sample data is taken as the LLR value of each voltage interval of the voltage region.

[0068] For example, by finding the LLR value corresponding to each voltage interval of the voltage region in the preset dataset based on Dy, a high-precision LLR value prediction for all voltage intervals of that voltage region can be completed. Repeating this step will yield the LLR value prediction for all voltage intervals of that page. For other pages of TLC particles, such as the middle page and upper page, repeating the above steps will also yield the LLR values ​​for all voltage intervals in the processed page.

[0069] This application analyzes selected particle types using statistical methods (or through simulation modeling) to obtain reference voltage distribution curves and corresponding LLR (log-likelihood ratio) values ​​for each voltage range at different stages of the particle's lifecycle. The voltage distribution data and LLR values ​​are transformed into preset data according to certain rules. During the flash memory's lifecycle, the voltage distribution status of the current particle can be judged and matched at any time. Finally, prediction is performed based on the preset values ​​to obtain a high-precision prediction of the LLR value for the current voltage range.

[0070] This application embodiment utilizes an online calculation and matching method of voltage distribution to predict LLR values, eliminating the need for online LLR value calculation and thus reducing computational resources and storage space. This application embodiment also avoids a complex and time-consuming multi-attempt decoding process; the number of rereads is fixed and minimal, enabling high-precision LLR value prediction with minimal latency.

[0071] Figure 3 This is a schematic diagram of a prediction device for a flash memory LLR according to an embodiment of this application, as shown. Figure 3 As shown, the flash memory LLR prediction device of this embodiment includes a memory and a processor.

[0072] The memory is used to store the program for predicting flash LLR;

[0073] The processor is configured to read and execute the program for predicting the LLR of flash memory, and execute the aforementioned method for predicting the LLR of flash memory.

[0074] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0075] Any feature shown and / or discussed in this application may be implemented individually or in any suitable combination.

[0076] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. Other sequences of steps are possible, as will be understood by those skilled in the art.

[0077] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A method for predicting LLR in flash memory, characterized in that, Determine the voltage distribution of each voltage region of all storage pages in a specified storage unit of the target flash memory; wherein, each voltage region of all storage pages in the specified storage unit of the target flash memory includes multiple voltage intervals; The voltage distribution of each voltage region is matched with multiple preset voltage distributions of that voltage region in the preset sample data; wherein, the voltage region in the preset sample data includes multiple voltage intervals; The LLR value corresponding to each voltage interval of a set of preset voltage distributions in the matched preset sample data is taken as the LLR value of each voltage interval of the voltage region. The voltage region and voltage interval division method of the preset sample data is consistent with the voltage region and voltage interval division method of the target flash memory; the preset sample data includes multiple voltage intervals and corresponding LLR values ​​obtained by converting the reference voltage distribution curves of flash memory of the same type as the target flash memory at different stages of its life cycle.

2. The prediction method as described in claim 1, characterized in that, Determine the voltage distribution of each voltage region in all memory pages within a specified memory unit of the target flash memory, including: Divide all storage pages in a specified storage unit of the target flash memory into multiple voltage regions, and divide the multiple voltage regions into multiple groups according to the storage page division method; For each voltage region in each group, perform the following operation: Determine the optimal reading voltage for this voltage region; Based on the optimal reading voltage and preset bias value of the voltage region, multiple voltage intervals of the voltage region and the number of cells corresponding to each voltage interval are determined; the voltage region and the number of cells corresponding to each voltage interval of the voltage region constitute the voltage distribution of the voltage region.

3. The prediction method as described in claim 2, characterized in that, The target flash memory is divided into multiple voltage regions within a specified storage unit, and these voltage regions are further divided into multiple groups according to the storage page partitioning method, including: The target flash memory is divided into multiple voltage regions according to the location of the read threshold voltage, and the multiple voltage regions are further divided into multiple groups according to the storage page partitioning method.

4. The prediction method as described in claim 3, characterized in that, Based on the optimal read voltage and preset bias value of the voltage region, determine multiple voltage intervals of the voltage region and the number of cells corresponding to each voltage interval, including: Based on the optimal reading voltage and preset bias value of the voltage region, multiple voltage ranges of the voltage region are determined; Based on the optimal read voltage of the voltage region, the data of the memory page where the voltage region is located is read by offsetting the preset bias value to the left and right by a preset multiple; The number of times the data from the memory page containing the voltage region falls into each voltage range is taken as the number of cells corresponding to that voltage range.

5. The prediction method as described in claim 4, characterized in that, Match the voltage distribution of each voltage region with multiple preset voltage distributions for that voltage region in the preset sample data, including: For each voltage region, perform the following matching operation: The first matching difference is obtained by subtracting the absolute value of the number of cells corresponding to the corresponding voltage interval in each group of the voltage region from the number of cells corresponding to each voltage interval in the preset sample data. The second matching difference is obtained by summing the first matching differences of all voltage intervals in the voltage region.

6. The prediction method as described in claim 5, characterized in that, The LLR value corresponding to each voltage interval of a set of preset voltage distributions in the matched preset sample data is used as the LLR value of each voltage interval in that voltage region, including: The preset voltage distribution of the voltage region in the preset sample data corresponding to the minimum second matching difference is taken as a set of preset voltage distributions in the preset sample data for matching; The LLR value corresponding to each voltage interval of a set of preset voltage distributions in the matched preset sample data is taken as the LLR value of each voltage interval of the voltage region.

7. The prediction method as described in claim 1, characterized in that, The target flash memory is a TLC type flash memory.

8. The prediction method as described in claim 1, characterized in that, The preset sample data includes multiple voltage ranges and corresponding LLR values ​​obtained by converting reference voltage distribution curves of flash memory of the same type as the target flash memory at different stages of its life cycle.

9. A prediction device for a flash memory LLR, comprising: Memory and processor; characterized in that: The memory is used to store the program for flash LLR prediction; The processor is configured to read and execute the program for flash memory LLR prediction, and to execute the method described in claims 1-8.

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