Chip and clock detection method

Abstract

A chip and a clock detection method relate to the field of computer technology. At least one of a reference clock generation circuit, a glitch detection circuit and a duty cycle detection circuit is configured on the chip. This facilitates the subsequent detection of the frequency of the clock signal on the chip based on the reference clock generation circuit, thereby avoiding the need to additionally derive a standard reference clock through an analog circuit when detecting the clock signal on the chip, thereby saving chip resources. In addition, through the chip, the glitch contained in the clock signal on the same chip and the duty cycle of the clock signal can also be detected, thereby improving the flexibility of detecting the clock signal.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a chip and a clock detection method. Background Art

[0002] Since the chip works at a certain frequency under the control of the pulse signal output by the clock, the stability of the clock in the chip affects the system stability of the chip to a certain extent. In order to ensure the system stability of the chip, it is usually necessary to detect the clock in the chip to determine whether the clock in the chip is in a stable working state.

[0003] In the related art, in order to test the clock in the chip, a reference clock is configured on the chip, and the frequency of the reference clock is the same as the theoretical operating frequency of the clock in the chip. A reference clock counter is configured for the reference clock, and a detected clock counter is configured for the clock in the chip. Based on the two counters, the number of pulses in the pulse signals output by the two clocks in the same timing duration is counted respectively, and the counting result of the reference clock counter is compared with the counting result of the detected clock counter. If the difference between the two counting results is large, it indicates that the actual operating frequency of the clock in the chip is unstable, that is, it indicates that the clock is not in a stable working state.

[0004] The above clock detection process requires an additional reference clock to be configured on the chip. The reference clock is usually generated in an analog manner, which results in a large chip overhead during the detection process and wastes chip resources. Summary of the invention

[0005] The embodiments of the present application provide a chip and a clock detection method, which can reduce the overhead required for detecting the clock on the chip, thereby saving chip resources.

[0006] In a first aspect, the present application provides a chip, the chip comprising a processor and a clock, the clock being used to generate a clock signal, the chip further comprising at least one of a reference clock generation circuit, a glitch detection circuit, or a duty cycle detection circuit. The processor is used to detect the clock signal based on at least one of the following: detecting the frequency of the clock signal based on a reference clock signal generated by the reference clock generation circuit; or detecting whether the clock signal contains glitches based on the glitch detection circuit; or detecting the duty cycle of the clock signal based on the duty cycle detection circuit.

[0007] Based on the chip provided by the embodiment of the present application, when it is necessary to detect the clock on the chip, the frequency of the clock signal on the chip can be detected based on the reference clock generation circuit, thereby avoiding the need to additionally derive a standard reference clock through an analog circuit when detecting the clock signal on the chip, thereby saving chip resources. In addition, through the chip provided by the embodiment of the present application, it is also possible to detect the glitches contained in the clock signal on the same chip and the duty cycle of the clock signal, thereby improving the flexibility of detecting the clock signal.

[0008] Based on the chip provided in the first aspect, in a possible implementation, the reference clock generation circuit includes P cascaded delay circuits, each of the P cascaded delay circuits includes a control terminal, the control terminal is used to input a control signal to control the corresponding delay circuit to be turned on or off, and P is a positive integer greater than 1. Among them, the first-stage delay circuit in the P cascaded delay circuits includes a first input terminal and a first output terminal. The first input terminal of the first-stage delay circuit is used to input an initial clock signal, and the initial clock signal is output from the first output terminal of the first-stage delay circuit after passing through at least one stage of the turned-on delay circuit. The first output terminal of the first-stage delay circuit is connected to the output terminal of the reference clock generation circuit, and the output terminal of the reference clock generation circuit is used to output a reference clock signal.

[0009] In the embodiment of the present application, by controlling the control signals of each delay circuit to control the number of delay circuits connected in series, it is possible to achieve different frequencies of the reference clock signal output by the reference clock generation circuit. Therefore, the reference clock generation circuit can be trained in advance based on the ideal operating frequency of the clock on the chip until the reference clock signal output by the reference clock generation circuit meets the aforementioned ideal operating frequency. Thus, the reference clock circuit provided in the embodiment of the present application can adapt to the clocks used on different chips, thereby improving the application flexibility of the chip provided in the embodiment of the present application.

[0010] Based on the chip provided in the first aspect, in a possible implementation, each of the P cascaded delay circuits includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The second output terminal of the first-stage delay circuit is connected to the first input terminal of the second-stage delay circuit, and the second input terminal of the first-stage delay circuit is connected to the first output terminal of the second-stage delay circuit. The first input terminal of the last-stage delay circuit in the P cascaded delay circuits is connected to the second output terminal of the last-stage delay circuit of the last-stage delay circuit; the second output terminal of the last-stage delay circuit is connected to the second input terminal of the last-stage delay circuit; the first output terminal of the last-stage delay circuit is connected to the second input terminal of the last-stage delay circuit of the last-stage delay circuit.

[0011] Based on the chip provided in the first aspect, in a possible implementation, the first input end of the intermediate delay circuit in the P cascaded delay circuits is connected to the second output end of the previous delay circuit of the intermediate delay circuit. The first output end of the intermediate delay circuit is connected to the second input end of the previous delay circuit of the intermediate delay circuit. The second output end of the intermediate delay circuit is connected to the first input end of the next delay circuit of the intermediate delay circuit. The second input end of the intermediate delay circuit is connected to the first output end of the next delay circuit of the intermediate delay circuit. The intermediate delay circuit is any delay circuit in the P cascaded delay circuits except the first delay circuit and the last delay circuit.

[0012] The above are used to illustrate the input and output of the first delay circuit in P cascaded delay circuits, the input and output of the last delay circuit, and the input and output of the intermediate delay circuit in P cascaded delay circuits. Through the above connection relationship, it is possible to control the control signal of each delay circuit to control the number of delay circuits connected in series, and it is possible to achieve different frequencies of the reference clock signal output by the reference clock generation circuit. Thereby, the reference clock circuit provided in the embodiment of the present application can adapt to the clocks used on different chips, thereby improving the application flexibility of the chip provided in the embodiment of the present application.

[0013] Based on the chip provided in the first aspect, in a possible implementation, the chip stores first target circuit configuration information, and the first target circuit configuration information indicates the configuration of the control signals corresponding to the respective delay circuits in the reference clock generation circuit. After the control signals corresponding to the respective delay circuits in the reference clock generation circuit are set according to the first target circuit configuration information, the frequency of the reference clock signal output by the reference clock generation circuit is an ideal operating frequency, and the ideal operating frequency is the ideal operating frequency of the clock signal.

[0014] In an embodiment of the present application, the training process of the reference clock generation circuit can be completed before the chip leaves the factory. In this scenario, the first target circuit configuration information obtained after training is written into the chip. This allows the frequency of the clock signal to be detected to be detected based on the first target circuit configuration information.

[0015] Based on the chip provided in the first aspect, in a possible implementation, the first target circuit configuration information indicates that each delay circuit corresponds to a high level or a low level control signal. When the control signal corresponding to any delay circuit in the P cascaded delay circuits is high level, the path from any delay circuit to the next level delay circuit is turned on, and when the control signal corresponding to any delay circuit is low level, the path from any delay circuit to the next level delay circuit is turned off.

[0016] In the embodiment of the present application, each delay circuit in the reference clock generation circuit can be turned on and off by high and low level control signals, which improves the flexibility of controlling the reference clock generation circuit. At the same time, in the first target circuit configuration information, it is only necessary to indicate that each delay circuit corresponds to a high level or a low level control signal, which reduces the complexity of the first target circuit configuration information, thereby reducing the resources required to write the first target circuit configuration information on the chip.

[0017] Based on the chip provided in the first aspect, in a possible implementation, the reference clock generation circuit further includes a gating circuit, and the gating circuit includes a control terminal. The first output terminal of the first-stage delay circuit is connected to the output terminal of the reference clock generation circuit through the gating circuit. The control terminal of the gating circuit is used to input a gating enable signal, and the gating enable signal is used to deduct one or more pulses in the clock signal output by the first output terminal of the first-stage delay circuit to obtain a reference clock signal.

[0018] In the embodiment of the present application, there may be a situation where the frequency of the clock signal generated by the reference clock generating circuit has a certain error with the ideal operating frequency no matter how the control signals of each delay circuit are adjusted. In this scenario, when the frequency of the pulse signal output by the reference clock generating circuit and the ideal operating frequency are within a certain error, the frequency of the clock signal output by the reference clock generating circuit can be fine-tuned through the above-mentioned gating circuit to make the frequency of the clock signal output by the reference clock generating circuit as consistent as possible with the ideal operating frequency. This improves the accuracy of subsequent detection of the frequency of the clock signal.

[0019] Based on the chip provided in the first aspect, in a possible implementation, the reference clock generation circuit further includes a NAND gate, and the NAND gate includes a first input terminal, a second input terminal, and an output terminal. Among them, the first input terminal of the NAND gate is used to input an enable signal, and the enable signal indicates whether to turn on or off the reference clock generation circuit. The second input terminal of the NAND gate is connected to the first output terminal of the first-stage delay circuit. The output terminal of the NAND gate is connected to the first input terminal of the first-stage delay circuit.

[0020] In the embodiment of the present application, the reference clock generating circuit can also be turned on and off by controlling the enable signal input to the NAND gate, thereby improving the application flexibility of the reference clock generating circuit.

[0021] Based on the chip provided in the first aspect, in a possible implementation, any of the P delay circuits includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and any of the first NAND gate, the second NAND gate and the third NAND gate includes a first input terminal, a second input terminal and an output terminal. Among them, the first input terminal of the delay circuit is connected to the first input terminal of the first NAND gate and the second NAND gate. The second input terminal of the delay circuit is connected to the second input terminal of the third NAND gate. The first output terminal of the delay circuit is connected to the output terminal of the third NAND gate. The second output terminal of the delay circuit is connected to the output terminal of the first NAND gate. The control terminal of the delay circuit is connected to the second input terminal of the first NAND gate and the input terminal of the inverter. The output terminal of the inverter is connected to the second input terminal of the second NAND gate. The output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate.

[0022] The above is a specific structure of a delay circuit in a reference clock generation circuit provided in an embodiment of the present application. By combining the above several simple logic gates, the function of the delay circuit in the reference clock generation circuit provided in an embodiment of the present application can be realized. The complexity of the reference clock circuit provided in an embodiment of the present application is reduced, thereby improving the production efficiency of the chip provided in an embodiment of the present application.

[0023] Based on the chip provided in the first aspect, in a possible implementation, the burr detection circuit includes N cascaded delay circuits, N AND gates, and N+1 triggers. Each of the N AND gates includes a first input terminal, a second input terminal, and an output terminal. Each of the N+1 triggers includes an input terminal, an output terminal, and a control terminal. N is a positive integer greater than 1. Among them, the input terminal of the first-stage delay circuit in the N cascaded delay circuits and the second input terminal of each AND gate in the N AND gates are used to input a clock signal. The output terminal of each delay circuit except the last-stage delay circuit in the N cascaded delay circuits is connected to the input terminal of the next-stage delay circuit. The output terminal of each delay circuit in the N delay circuits is respectively connected to the first input terminal of an AND gate. The control terminal of the first trigger in the N+1 triggers is used to input a clock signal, and the control terminals of the N triggers except the first trigger in the N+1 triggers are connected to the output terminals of the N AND gates, wherein one AND gate corresponds to one trigger. The output terminal of each trigger in the N+1 triggers is connected to the input terminal of the same trigger through an inverter. The output signals at the output terminals of the N+1 flip-flops are used to detect whether the clock signal contains glitches.

[0024] The all-digital glitch detection circuit can detect whether the clock signal contains glitches, so that the chip provided by the embodiment of the present application can be applied in different test scenarios, thereby improving the application flexibility of the chip provided by the embodiment of the present application.

[0025] Based on the chip provided in the first aspect, in a possible implementation manner, second target circuit configuration information is stored on the chip. The second target circuit configuration information indicates which of the N triggers the target trigger is. The output signal of the target trigger and the output signal of the first trigger are used to detect whether the clock signal contains glitches.

[0026] In the embodiment of the present application, the second target circuit configuration information can be written into the chip before the chip leaves the factory, so as to facilitate the subsequent rapid detection of whether the clock signal contains glitches based on the second target circuit configuration information.

[0027] Based on the chip provided in the first aspect, in one possible implementation, the N delay circuits are delay circuits with the same structure, the target trigger is determined based on a glitch detection range and a delay duration of a single delay circuit among the N delay circuits, and the glitch detection range indicates the pulse width of the glitch contained in the clock signal.

[0028] In the embodiment of the present application, the glitch detection range can be used to know which trigger is used to detect the glitch. Since the glitch detection circuit includes multiple triggers, the glitch detection circuit provided by the embodiment of the present application can be applied in different glitch detection ranges, thereby improving the application flexibility of the chip provided by the implementation of the present application.

[0029] Based on the chip provided in the first aspect, in a possible implementation, any delay circuit among the N delay circuits includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and any one of the first NAND gate, the second NAND gate and the third NAND gate includes a first input terminal, a second input terminal and an output terminal. Among them, the input terminal of the delay circuit is connected to the first input terminal of the first NAND gate and the second NAND gate. The output terminal of the delay circuit is connected to the input terminal of the next level delay circuit. The control terminal of the delay circuit is connected to the second input terminal of the first NAND gate and the input terminal of the inverter. The output terminal of the inverter is connected to the second input terminal of the second NAND gate. The output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate. The output terminal of the first NAND gate is connected to the second input terminal of the third NAND gate.

[0030] The above is a specific structure of a delay circuit in a glitch detection circuit provided in an embodiment of the present application. By combining the above several simple logic gates, the function of the delay circuit in the glitch detection circuit provided in the embodiment of the present application can be realized. The complexity of the glitch detection circuit provided in the embodiment of the present application is reduced, thereby improving the production efficiency of the chip provided in the embodiment of the present application.

[0031] Based on the chip provided in the first aspect, in a possible implementation, the duty cycle detection circuit includes a first delay adjustment circuit, a second delay adjustment circuit, and M cascaded third delay adjustment circuits, a frequency divider, a first inverter, a second inverter, a first two-stage register, and M+1 second two-stage registers, M+1 XOR gates, and M+1 triggers, where M is a positive integer greater than 1. Among them, any one of the first two-stage register and the M+1 second two-stage register includes a first input terminal, a second input terminal, and an output terminal, each of the M+1 XOR gates includes a first input terminal, a second input terminal, and an output terminal, each of the M+1 triggers includes an input terminal, an output terminal, and a control terminal, and the frequency divider includes an input terminal, an output terminal, and a control terminal. The control end of the frequency divider is used to input a clock signal, the input end of the frequency divider is connected to the output end of the frequency divider through a second inverter, the output end of the frequency divider is connected to the input end of the first delay adjustment circuit, the output end of the first delay adjustment circuit is connected to the input end of the second delay adjustment circuit, the output end of the second delay adjustment circuit is connected to the input end of the first-stage third delay adjustment circuit in the cascaded M third delay adjustment circuits, and the output end of each third delay adjustment circuit in the cascaded M third delay adjustment circuits except the last-stage third delay adjustment circuit is connected to the input end of the next-stage third delay adjustment circuit. The output end of the second delay adjustment circuit and the output end of each third delay adjustment circuit of the cascaded M third delay adjustment circuits are connected to the first input end of the M+1 second two-stage registers in a one-to-one correspondence. The second input ends of the M+1 second two-stage registers are all connected to the output end of the first inverter, the input end of the first inverter is used to input a clock signal, and the output ends of the M+1 second two-stage registers are connected to the first input ends of the M+1 XOR gates in a one-to-one correspondence. The output ends of the M+1 XOR gates are connected to the input ends of the M+1 flip-flops in a one-to-one correspondence. The output end of the first inverter is also connected to the first input end of the first two-stage register, the output end of the frequency divider is connected to the second input end of the first two-stage register, and the output end of the first two-stage register is connected to the second input end of the M+1 XOR gates. The output signal of the output end of the M+1 flip-flops is used to detect the duty cycle of the clock signal.

[0032] The duty cycle of the clock signal can be detected by the all-digital duty cycle detection circuit, so that the chip provided by the embodiment of the present application can be applied in different test scenarios, thereby improving the application flexibility of the chip provided by the embodiment of the present application.

[0033] Based on the chip provided in the first aspect, in a possible implementation, any third delay adjustment circuit among the M third delay adjustment circuits includes k cascaded delay circuits, each of the k cascaded delay circuits includes a control terminal, the control terminal is used to input a control signal to control the corresponding delay circuit to be turned on or off, and k is a positive integer greater than 1. Among them, the first-stage delay circuit among the k cascaded delay circuits includes a first input terminal and a first output terminal. The first input terminal of the first-stage delay circuit is connected to the input terminal of the third delay adjustment circuit. The first output terminal of the first-stage delay circuit is connected to the output terminal of the third delay adjustment circuit.

[0034] The third delay adjustment module in the duty cycle detection circuit can be realized by k cascaded delay circuits, and the delay length of the third delay adjustment module can be flexibly adjusted according to different requirements based on the control signals corresponding to each delay circuit. This not only reduces the complexity of the duty cycle detection circuit on the chip, but also improves the application flexibility of the chip.

[0035] Based on the chip provided in the first aspect, in a possible implementation, each of the k cascaded delay circuits includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The second output terminal of the first-stage delay circuit is connected to the first input terminal of the second-stage delay circuit, and the second input terminal of the first-stage delay circuit is connected to the first output terminal of the second-stage delay circuit. The first input terminal of the last-stage delay circuit in the k cascaded delay circuits is connected to the second output terminal of the last-stage delay circuit of the last-stage delay circuit; the second output terminal of the last-stage delay circuit is connected to the second input terminal of the last-stage delay circuit; the first output terminal of the last-stage delay circuit is connected to the second input terminal of the last-stage delay circuit of the last-stage delay circuit.

[0036] Based on the chip provided in the first aspect, in a possible implementation, the first input end of the intermediate delay circuit in the k cascaded delay circuits is connected to the second output end of the previous delay circuit of the intermediate delay circuit. The first output end of the intermediate delay circuit is connected to the second input end of the previous delay circuit of the intermediate delay circuit. The second output end of the intermediate delay circuit is connected to the first input end of the next delay circuit of the intermediate delay circuit. The second input end of the intermediate delay circuit is connected to the first output end of the next delay circuit of the intermediate delay circuit. The intermediate delay circuit is any delay circuit except the first delay circuit and the last delay circuit in the k cascaded delay circuits.

[0037] Based on the chip provided in the first aspect, in a possible implementation, any delay circuit among the k delay circuits includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and any one of the first NAND gate, the second NAND gate and the third NAND gate includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the delay circuit is connected to the first input terminal of the first NAND gate and the second NAND gate. The second input terminal of the delay circuit is connected to the second input terminal of the third NAND gate. The first output terminal of the delay circuit is connected to the output terminal of the third NAND gate. The second output terminal of the delay circuit is connected to the output terminal of the first NAND gate. The control terminal of the delay circuit is connected to the second input terminal of the first NAND gate and the input terminal of the inverter. The output terminal of the inverter is connected to the second input terminal of the second NAND gate. The output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate.

[0038] The connection method between the above-mentioned k delay circuits and the internal structure of the delay circuit are consistent with the relevant contents in the aforementioned reference clock generating circuit, and the corresponding technical effects are not repeated here.

[0039] Based on the chip provided in the first aspect, in a possible implementation, the chip stores third target circuit configuration information, wherein the third target circuit configuration information indicates the number of delay circuits connected in series among the k delay circuits, and the delay durations of the first delay adjustment circuit and the second delay adjustment circuit. After the first delay adjustment circuit, the second delay adjustment circuit, and the third delay adjustment circuit are set according to the third target circuit configuration information, if a clock signal with a duty cycle of 50% is input to the duty cycle detection circuit, half of the output signals at the output ends of the M+1 triggers are high level signals and half are low level signals.

[0040] In the embodiment of the present application, the third target circuit configuration information can be written into the chip before the chip leaves the factory, so as to facilitate the subsequent rapid detection of the duty cycle of the clock signal based on the third target circuit configuration information.

[0041] Based on the chip provided in the first aspect, in one possible implementation, the k delay circuits are delay circuits with the same structure, the number of delay circuits connected in series among the k delay circuits is determined based on an allowable range of duty cycles and a delay duration of a single delay circuit among the k delay circuits, and the allowable range of duty cycles indicates an allowable floating range of the duty cycle of the clock signal.

[0042] In the embodiment of the present application, the delay circuits connected in series in the k delay circuits can be set according to the duty cycle allowable range. In this way, the duty cycle detection circuit provided in the embodiment of the present application can be applied in different duty cycle allowable ranges, thereby improving the application flexibility of the chip provided in the implementation of the present application.

[0043] In the second aspect, a clock detection method is provided. The method is used to explain the working process of each circuit on the chip provided in the first aspect, so as to realize the detection function of each circuit. The technical effects of each implementation method in the clock detection method provided in the second aspect can refer to the relevant technical effects of the chip provided in the first aspect, and will not be repeated here.

[0044] Specifically, the method is applied to a processor on a chip, the chip also includes a clock, the clock is used to generate a clock signal, and the chip also includes at least one of a reference clock generation circuit, a glitch detection circuit, or a duty cycle detection circuit. In the method, the processor detects the clock signal based on at least one of the following: detecting the frequency of the clock signal based on a reference clock signal generated by a reference clock generation circuit; or detecting whether the clock signal contains glitches based on a glitch detection circuit; or detecting the duty cycle of the clock signal based on a duty cycle detection circuit.

[0045] Based on the clock detection method provided in the second aspect, in a possible implementation manner, the implementation process of detecting the frequency of the clock signal based on the reference clock signal generated by the reference clock generating circuit can be: controlling the reference clock generating circuit to output a reference clock signal with an ideal operating frequency, where the ideal operating frequency is the ideal operating frequency of the clock signal; if the actual operating frequency of the clock signal is different from the frequency of the reference clock signal, it is determined that the frequency of the clock signal is unstable.

[0046] Based on the clock detection method provided in the second aspect, in a possible implementation manner, if the actual operating frequency of the clock signal is the same as the frequency of the reference clock signal, it is determined that the frequency of the clock signal to be detected is stable.

[0047] Based on the clock detection method provided in the second aspect, in a possible implementation, the reference clock generation circuit includes P cascaded delay circuits, and the chip stores first target circuit configuration information, and the first target circuit configuration information indicates the configuration of the control signals corresponding to each delay circuit in the reference clock generation circuit. In this scenario, the implementation process of controlling the reference clock generation circuit to output a reference clock signal with an ideal operating frequency can be: based on the first target circuit configuration information, control the control signals corresponding to each delay circuit in the reference clock generation circuit, so that the reference clock generation circuit outputs a reference clock signal with an ideal operating frequency.

[0048] Based on the clock detection method provided in the second aspect, in a possible implementation, the glitch detection circuit includes N cascaded delay circuits and N+1 triggers. In this scenario, the implementation process of detecting whether the clock signal contains glitches based on the glitch detection circuit can be: input the clock signal into the first trigger to obtain the first output signal; the first trigger is any one of the N+1 triggers; the clock signal is input into the X+1th trigger after passing through X cascaded delay circuits to obtain the X+1th output signal; wherein X is each positive integer from 1 to N in turn; the output signal of the target trigger in the glitch detection circuit and the first output signal are obtained, and the target trigger is a trigger other than the first trigger among the N+1 triggers; if the output signal of the target trigger and the first output signal are different in the same clock cycle, it is determined that the clock signal contains glitches.

[0049] Based on the clock detection method provided in the second aspect, in a possible implementation, if the output signal of the target trigger and the output signal of the first trigger output the same signal in the same clock cycle, it is determined that the clock signal does not contain glitches.

[0050] Based on the clock detection method provided in the second aspect, in a possible implementation manner, second target circuit configuration information is stored on the chip, wherein the second target circuit configuration information indicates which of the N+1 triggers the target trigger is. In this scenario, the implementation process of obtaining the output signal of the target trigger in the glitch detection circuit may be: based on the second target circuit configuration information, obtaining the output signal of the target trigger in the glitch detection circuit.

[0051] Based on the clock detection method provided in the second aspect, in a possible implementation, the duty cycle detection circuit includes a frequency divider, a first inverter, and M+1 triggers. In this scenario, the implementation process of detecting the duty cycle of the clock signal based on the duty cycle detection circuit can be: inputting the clock signal to the input end of the frequency divider and the first inverter; obtaining the output signal of the output end of the M+1 triggers in the duty cycle detection circuit; if the output signal of the output end of the M+1 triggers includes a high-level signal and a low-level signal, then outputting a first duty cycle prompt signal, the first duty cycle prompt signal is used to indicate that the duty cycle of the clock signal is within the allowable duty cycle range.

[0052] Based on the clock detection method provided in the second aspect, in a possible implementation, if the output signals of the output terminals of the M+1 triggers are all high-level signals, a second duty cycle prompt signal is output, and the second duty cycle prompt signal indicates that the duty cycle of the clock signal is not within the allowable duty cycle range, and the proportion of low-level signals in the clock signal exceeds the allowable duty cycle range. If the output signals of the output terminals of the M+1 triggers are all low-level signals, a third duty cycle prompt signal is output, and the third duty cycle prompt signal indicates that the duty cycle of the clock signal is not within the allowable duty cycle range, and the proportion of high-level signals in the clock signal exceeds the allowable duty cycle range.

[0053] Based on the clock detection method provided in the second aspect, in a possible implementation, the method is applied to the aforementioned chip, on which the third target circuit configuration information is stored, wherein the third target circuit configuration information indicates the number of delay circuits connected in series among the k delay circuits included in any third delay adjustment circuit, and the delay duration of the first delay adjustment circuit and the second delay adjustment circuit. In this scenario, before the clock signal is input to the input end of the frequency divider and the first inverter, the duty cycle detection circuit can also be configured based on the third target circuit configuration information.

[0054] In a third aspect, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium. When the instructions are executed on a computer, the computer executes the clock detection method described in the second aspect.

[0055] In a fourth aspect, a computer program product comprising instructions is provided. When the instructions are executed on a computer, the computer executes the clock detection method described in the first aspect.

[0056] The technical effects obtained by the above-mentioned third and fourth aspects are similar to the technical effects obtained by the corresponding technical means in the second aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0058] Figure 2 A schematic diagram of the structure of a reference clock generation circuit provided in an embodiment of the present application;

[0059] Figure 3 A schematic diagram of the structure of another reference clock generating circuit provided in an embodiment of the present application;

[0060] Figure 4 A schematic diagram of the structure of another reference clock generating circuit provided in an embodiment of the present application;

[0061] Figure 5 It is a flow chart of a training reference clock generating circuit provided in an embodiment of the present application;

[0062] Figure 6 is a structural schematic diagram of a burr detection circuit provided in an embodiment of the present application;

[0063] Figure 7 It is a pulse timing diagram in a glitch detection circuit provided in an embodiment of the present application;

[0064] Figure 8 It is a schematic diagram of the connection relationship of various delay circuits in a burr detection circuit provided in an embodiment of the present application;

[0065] Fig. 9 is a structural schematic diagram of a duty cycle detection circuit provided in an embodiment of the present application;

[0066] Fig.10 It is a pulse timing diagram of output signals of various circuits in a duty cycle detection circuit provided in an embodiment of the present application;

[0067] Fig.11 is a flow chart of a clock detection method provided in an embodiment of the present application;

[0068] Fig.12 is a flow chart of another clock detection method provided in an embodiment of the present application;

[0069] Fig.13 This is a complete flow chart of training and detecting clock frequency provided by an embodiment of the present application;

[0070] Fig.14 is a flow chart of another clock detection method provided in an embodiment of the present application;

[0071] Fig.15 is a flow chart of another clock detection method provided in an embodiment of the present application;

[0072] Fig.16 This is a detection result of a duty cycle detection circuit when a low level accounts for too large a proportion and a detection result of a duty cycle detection circuit when a high level accounts for too large a proportion provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0074] It should be understood that the "multiple" mentioned herein refers to two or more. In the description of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish between the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.

[0075] Before explaining the embodiments of the present application in detail, the application scenarios of the embodiments of the present application are briefly described.

[0076] For the convenience of subsequent explanation, in the embodiments of the present application, the output signal of the clock on the chip is referred to as the clock signal of the chip.

[0077] With the development of chip technology, the stability requirements for chip systems are getting higher and higher. The clock signal in the chip is an indispensable signal in the chip system. When the clock in the chip is attacked, the frequency and duty cycle of the clock signal may change. At the same time, the clock signal may introduce glitch signals, which may cause the chip to fail to work properly. In actual chip applications, in order to improve the security level of the chip, it is usually necessary to detect the clock signal of the chip.

[0078] The clock detection method provided in the embodiment of the present application is applied to the above scenario of detecting the clock signal of the chip. The clock signal on the chip can be detected without introducing an external standard reference clock, thereby avoiding waste of resources on the chip.

[0079] The structure of the chip is first explained below. Figure 1 Schematic diagram of the structure of a chip provided in an embodiment of the present application. Figure 1 As shown, the chip 100 includes a processor 101 , an interface circuit 102 , a clock 103 , a reference clock generating circuit 104 , a glitch detection circuit 105 and a duty cycle detection circuit 106 .

[0080] The interface circuit 102 is used to receive instructions and transmit them to the processor 101, and the processor 101 is used to execute the instructions. The clock 103 is a circuit that can output a pulse signal of a certain frequency. The clock 103 is used to input a clock signal to the processor 101 and control the operating frequency of the processor 101 through the clock signal.

[0081] In the embodiment of the present application, the processor 101 is also used to execute the clock detection method provided in the embodiment of the present application to complete the detection of the clock 103 on the same chip.

[0082] It should be noted that Figure 1 This is only an optional structure of the chip involved in the embodiment of the present application. The embodiment of the present application does not limit the specific structure of the chip. Any chip configured with a clock is within the protection scope of the chip involved in the embodiment of the present application.

[0083] In order to detect the clock on the chip without introducing an external standard reference clock, in the embodiment of the present application, the digital circuit on the chip is improved in advance, so that the clock signal on the chip can be detected based on the improved digital circuit later. The specific improvements include the following aspects.

[0084] (1) A reference clock generation circuit 104 is configured on a chip.

[0085] The reference clock generating circuit 104 is used to output the reference clock signal required for the clock signal of the detection chip. In the embodiment of the present application, a standard reference clock is simulated by the reference clock generating circuit 104. Since the reference clock generating circuit is a fully digital circuit, and the digital circuit is based on binary, the small fluctuation of the power supply voltage has basically no effect on the stability, and the temperature and process deviation have much less effect on the reliability of the operation of the digital circuit than the analog circuit. Therefore, the digital circuit has the advantages of high reliability and good stability relative to the analog circuit. Furthermore, the digital circuit design is easier to transplant the process than the analog circuit, and when changing different processes, the digital circuit can quickly complete the design. Based on the advantages of the above-mentioned digital circuit, the reference clock generating circuit provided in the embodiment of the present application has the characteristics of high reliability and good stability.

[0086] A fully digital circuit means that the circuit is composed of multiple logic gates, and the function of the reference clock generating circuit is realized by connecting multiple logic gates.

[0087] In a possible implementation, the reference clock generating circuit includes P cascaded delay circuits, each delay circuit is used to perform a certain delay processing on the input signal, and P is a positive integer greater than 1.

[0088] Each of the P cascaded delay circuits includes a control terminal, which is used to input a control signal to control the corresponding delay circuit to be turned on or off. Each of the P cascaded delay circuits includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal.

[0089] Among them, the relationship between the reference clock signal output by the reference clock generation circuit and the first-stage delay circuit is as follows:

[0090] The first input end of the first-stage delay circuit is used to input an initial clock signal, and the initial clock signal is output from the first output end of the first-stage delay circuit after passing through at least one stage of the conducting delay circuit. The first output end of the first-stage delay circuit is connected to the output end of the reference clock generating circuit, and the output end of the reference clock generating circuit is used to output a reference clock signal.

[0091] The input and output of the first delay circuit and the input and output of the last delay circuit in P cascaded delay circuits are as follows:

[0092] The second output end of the first delay circuit is connected to the first input end of the second delay circuit, and the second input end of the first delay circuit is connected to the first output end of the second delay circuit. The first input end of the last delay circuit in the P cascaded delay circuits is connected to the second output end of the last delay circuit of the last delay circuit. The second output end of the last delay circuit is connected to the second input end of the last delay circuit. The first output end of the last delay circuit is connected to the second input end of the last delay circuit of the last delay circuit.

[0093] The input and output of the intermediate delay circuit in the P cascaded delay circuits are as follows (the intermediate delay circuit is any delay circuit in the P cascaded delay circuits except the first delay circuit and the last delay circuit):

[0094] The first input end of the intermediate delay circuit in the P cascaded delay circuits is connected to the second output end of the delay circuit of the previous stage of the intermediate delay circuit. The first output end of the intermediate delay circuit is connected to the second input end of the delay circuit of the previous stage of the intermediate delay circuit. The second output end of the intermediate delay circuit is connected to the first input end of the delay circuit of the next stage of the intermediate delay circuit. The second input end of the intermediate delay circuit is connected to the first output end of the delay circuit of the next stage of the intermediate delay circuit.

[0095] Figure 2 2 is a schematic diagram of a reference clock generating circuit 200 provided in an embodiment of the present application. Figure 2 As shown, the reference clock generating circuit 200 includes P cascaded delay circuits. The P cascaded delay circuits are connected in sequence from left to right. Each delay circuit includes a control terminal, which is used to input a control signal.

[0096] like Figure 2 As shown, from left to right, the first input terminal of the first delay circuit is used to input the initial clock signal. The initial clock signal is transmitted through Figure 2After being processed by at least one delay circuit among the P delay circuits shown, the reference clock signal is output from the first input terminal of the first delay circuit, and then output from the output terminal of the reference clock generating circuit.

[0097] exist Figure 2 In the reference clock generating circuit shown in FIG. 1 , the connection relationship between each input terminal and input terminal in the first-stage delay circuit to the last-stage delay circuit is as follows: Figure 2 The specific connection relationship has been described in detail in the above embodiments and will not be repeated here.

[0098] Based on the above content, it can be known that each of the P cascaded delay circuits includes a control terminal, which is used to input a control signal to control the corresponding delay circuit to be turned on or off. It can be seen that the control terminal of each delay circuit in the P delay circuits is used to input a control signal, and the path from each delay circuit connected in series to the next delay circuit is opened or closed by the corresponding control signal.

[0099] That is, each delay circuit corresponds to a control signal, and the path from each delay circuit to the next delay circuit can be opened or closed by the control signal. For example, when the control signal corresponding to a delay circuit is high, the path from the delay circuit to the next delay circuit is turned on. When the control signal corresponding to a delay circuit is low, the path from the delay circuit to the next delay circuit is turned off.

[0100] Therefore, the number of delay circuits connected in series can be controlled by controlling the control signals of each delay circuit. The number of delay circuits connected in series can be called the series series number, wherein different series series numbers result in different frequencies of reference clock signals output by the reference clock generation circuit. Therefore, the reference clock generation circuit can be trained in advance based on the ideal operating parameters of the clock on the chip, and the training process includes: continuously adjusting the control signals corresponding to each delay circuit until the reference clock signal output by the reference clock generation circuit meets the aforementioned ideal operating parameters. For example, starting from the first delay circuit, the control signals corresponding to the delay circuits can be set to a high level in sequence until the clock signal output by the reference clock generation circuit meets the ideal operating parameters.

[0101] When the clock signal output by the reference clock generation circuit satisfies the aforementioned ideal operating parameters, the configuration information of the control signal corresponding to each delay circuit can be referred to as the target circuit configuration information of the reference clock generation circuit. The target circuit configuration information can also be referred to as a configuration level or a configuration codeword, etc. Among them, the configuration information of the control signal can specifically indicate whether the control signal is a high level or a low level or indicate the number of delay circuits connected in series in the reference clock generation circuit. In addition, the target circuit configuration information obtained by training the reference clock generation circuit can also be referred to as the first target circuit configuration information.

[0102] In one possible implementation, any delay circuit in the above-mentioned reference clock generating circuit may include a first NAND gate, a second NAND gate, a third NAND gate and an inverter, any one of the first NAND gate, the second NAND gate, and the third NAND gate includes a first input terminal, a second input terminal and an output terminal, and the inverter includes an input terminal and an output terminal.

[0103] At this time, for any delay circuit, the first input end of the delay circuit is connected to the first input end of the first NAND gate and the second NAND gate. The second input end of the delay circuit is connected to the second input end of the third NAND gate. The first output end of the delay circuit is connected to the output end of the third NAND gate. The second output end of the delay circuit is connected to the output end of the first NAND gate. The control end of the delay circuit is connected to the second input end of the first NAND gate and the input end of the inverter. The output end of the inverter is connected to the second input end of the second NAND gate. The output end of the second NAND gate is connected to the first input end of the third NAND gate.

[0104] In other words, the serial connection mode of each delay circuit in the reference clock generating circuit can be specifically expressed as follows.

[0105] Among them, the first input end of the first NAND gate in the first delay circuit after the series connection is used to input the signal to be modulated, and the signal to be modulated is the above-mentioned initial clock signal. After the series connection, the first input end of the first NAND gate in the other delay circuits except the first delay circuit is connected to the output end of the first NAND gate in the previous delay circuit connected in series. The second input end of the first NAND gate in any delay circuit and the input end of the inverter are used to input the control signal corresponding to any delay circuit. The output end of the inverter in any delay circuit is connected to the second input end of the second NAND gate in the same delay circuit, the first input end of the second NAND gate in any delay circuit is the same as the input signal of the first input end of the first NAND gate in the same delay circuit, and the output end of the second NAND gate in any delay circuit is connected to the first input end of the third NAND gate in the same delay circuit. The second input terminal of the third NAND gate in the last delay circuit after the series connection is connected to the output terminal of the first NAND gate in the same delay circuit, and the second input terminal of the third NAND gate in the other delay circuits except the last delay circuit after the series connection is connected to the output terminal of the third NAND gate in the next delay circuit. The output terminal of the third NAND gate in the first delay circuit after the series connection is used to output a clock signal after the frequency of the signal to be modulated is adjusted, so as to obtain a reference clock signal.

[0106] Figure 3 A schematic diagram of the structure of a reference clock generation circuit provided in an embodiment of the present application. Figure 3 As shown, the reference clock generating circuit 200 includes P delay circuits 201, each of which includes three NAND gates 2011-2013 and an inverter 2014. Each delay circuit corresponds to a control signal. Figure 3 The control signal is marked as SEL.

[0107] It should be understood that the NAND gate has two input terminals and one output terminal. When the input signals of the NAND gate's input terminals are all high level, the output signal of the output terminal is low level. When at least one of the input signals of the NAND gate's input terminals is low level, the output signal of the output terminal is high level. The inverter can reverse the phase of the input signal of the input terminal by 180 degrees.

[0108] by Figure 3 The first delay circuit on the left is used as an example to illustrate. Figure 2 As shown, any NAND gate in NAND gates 2011-2013 includes a first input terminal, a second input terminal and an output terminal. Figure 3 The first input terminal of the NAND gate is marked with a number 1, and the second input terminal of the NAND gate is marked with a number 2. The inverter 2014 includes an input terminal and an output terminal.

[0109] Among them, Figure 3In the first delay circuit on the left, the first input terminals of the NAND gate 2011 and the NAND gate 2012 are both used to input the signal a, which is the initial clock signal. The second input terminal of the NAND gate 2011 is used to input the control signal SEL, and the output terminal of the NAND gate 2011 is connected to the first input terminal of the NAND gate 2011 in the next delay circuit. The input terminal of the inverter 2014 is used to input the control signal SEL. The output terminal of the inverter 2014 is connected to the second input terminal of the NAND gate 2012. The first input terminal of the NAND gate 2012 has the same input signal as the first input terminal of the NAND gate 2011 in the same delay circuit. The output terminal of the NAND gate 2012 is connected to the first input terminal of the NAND gate 2013, and the second input terminal of the NAND gate 2013 is connected to the output terminal of the NAND gate 2013 in the next delay circuit.

[0110] Signal a is a pulse signal of a certain frequency, and the process of each delay circuit processing the signal is described by taking the first delay circuit as an example. When signal a is input to the first delay circuit, signal a is input to the first input terminal of NAND gate 2011 and the first input terminal of NAND gate 2012. When the SEL signal is at a high level, the output of NAND gate 2011 is a pulse signal with a certain delay, indicating that the path leading to the next level delay circuit is opened. However, since the output signal of inverter 2014 is a low level signal, the output of NAND gate 2012 is a high level signal, and the output signal of NAND gate 2012 is input to the first input terminal of NAND gate 2013, and the output signal of NAND gate 2013 in the next level delay circuit is input to the second input terminal of NAND gate 2013. Since the output of NAND gate 2012 is a high level signal, the output of NAND gate 2013 is an output signal with a certain delay relative to the output signal of NAND gate 2013 in the next level delay circuit.

[0111] Correspondingly, when the SEL signal is at a low level, the NAND gate 2011 outputs a high level signal, indicating that the path to the next level delay circuit is closed, and the NAND gate 2013 of the next level delay circuit also outputs a high level signal. In addition, when the NAND gate 2012 inputs the signal a, the NAND gate 2012 outputs a pulse signal with a certain delay relative to the signal a, and the output signal of the NAND gate 2012 and the output signal of the NAND gate 2013 in the next level delay circuit are input to the NAND gate 2013 of the current level delay circuit. Since the output signal of the NAND gate 2013 in the next level delay circuit is a high level signal, the NAND gate 2013 outputs a pulse signal with a certain delay relative to the output signal of the NAND gate 2012.

[0112] It should be understood that the delay circuit provided in the embodiment of the present application includes two paths, one path leading to the next level delay circuit, and the other path leading to the output end of the current level delay circuit. When the control signal of the delay circuit is at a high level, the path leading to the next level delay circuit is turned on, and the signal a is input to the next level delay circuit to achieve further delay; when the control signal of the delay circuit is at a low level, the path through the next level delay circuit is disconnected, and the signal a passes through the NAND gate 2012 and the NAND gate 2013 of the current level delay circuit and then returns from the output end of the current level delay circuit to the previous level delay circuit. The output end of the NAND gate 2011 of the last level delay circuit is connected to the second input end of the NAND gate 2013 of the last level delay circuit.

[0113] Figure 4 is a schematic diagram of the structure of another reference clock generating circuit provided in an embodiment of the present application. Figure 4 As shown, in Figure 3 On the basis of the reference clock generating circuit shown in FIG. 1 , the reference clock generating circuit further includes a NAND gate 2000, which is used to process the enable signal and the output signal of the first output end of the first-stage delay circuit in the reference clock generating circuit through the NAND gate 2000 to obtain a signal a, and input the signal a to the first delay circuit, so as to adjust the frequency of the signal a through each delay circuit later. In other words, the first input end of the NAND gate 2000 is used to input the enable signal, and the enable signal indicates whether to turn on or off the reference clock generating circuit. The second input end of the NAND gate 2000 is connected to the first output end of the first-stage delay circuit. The output end of the NAND gate 2000 is connected to the first input end of the first-stage delay circuit.

[0114] Specifically, when the enable signal is at a high level, it indicates that the reference clock generating circuit is turned on. At this time, the reference clock generating circuit is driven by the enable signal, and the first output end of the first-stage delay circuit first outputs a clock signal of a certain frequency at the initial moment of the enable signal input. The clock signal and the enable signal pass through the NAND gate 2000 and then output a signal a. Then, after the signal a passes through the cascaded P delay circuits, the first output end of the first-stage delay circuit finally outputs a clock signal with a stable frequency. When the enable signal is at a low level, it indicates that the reference clock generating circuit is turned off. At this time, the first output end of the first-stage delay circuit will not output a clock signal of a certain frequency.

[0115] pass Figures 2 to 4 For any of the reference clock generating circuits shown, for any of the delay circuits, if the corresponding SEL signal is at a high level, it indicates that the path from the delay circuit to the next delay circuit is opened, so that the pulse signal can continue to be delayed through the next delay circuit. If the corresponding SEL signal is at a low level, it indicates that the path from the delay circuit to the next delay circuit is closed.

[0116] It should be noted that for Figures 2 to 4 In any of the reference clock generating circuits shown, when the control signal SEL corresponding to a delay circuit is at a low level, since the path from the delay circuit to the next delay circuit is closed, the subsequent delay circuits of the delay circuit do not need to delay the pulse signal. Therefore, the control signals corresponding to the subsequent delay circuits of the delay circuit also need to be set to a low level.

[0117] It can be seen from this that adjusting the SEL signal of each delay circuit specifically refers to: how many consecutive delay circuits starting from the first-stage delay circuit have their control signals at high level.

[0118] For example, for Figures 2 to 4 Any of the reference clock generation circuits shown, Figures 2 to 4 The configuration information of the control signals of any of the delay circuits shown from left to right can be [1, 1, 1, 0, 0, 0, 0…, 0], where “1” represents a high level and “0” represents a low level. This indicates that the paths leading to the next level from the first three delay circuits are opened, and the paths leading to the next level of delay circuits from subsequent delay circuits are closed.

[0119] based on Figures 2 to 4 In any of the circuits shown, if the control signal SEL corresponding to each delay circuit is adjusted, the frequency of the input pulse signal a can be adjusted. Therefore, the reference clock generation circuit can be trained in advance based on the ideal operating parameters of the clock on the chip so that the reference clock generation circuit outputs a reference clock signal that meets the ideal operating frequency. Then, the configuration information of each control signal SEL in the reference clock generation circuit at this time is written onto the chip as the target circuit configuration information for use in subsequent clock detection. The target circuit configuration information at this time specifically refers to: the control signal corresponding to P delay circuits is high or low. For example, the high level is 1 and the low level is 0.

[0120] In addition, the above-mentioned process of training the reference clock generation circuit can be: adjusting the control signals of each delay circuit in the reference clock generation circuit, after adjusting the control signals of each delay circuit in the reference clock generation circuit, counting the number of pulses in the output signal of the reference clock generation circuit within the first timing duration, if the difference between the number of pulses counted within the first timing duration and the first theoretical value is within the first reference difference, then determining the target circuit configuration information based on the control signals of each delay circuit after this adjustment. If the difference between the number of pulses counted within the first timing duration and the first theoretical value exceeds the first reference difference, then continue to adjust the control signals of each delay circuit in the reference clock generation circuit. Wherein, the first theoretical value indicates the number of pulses in the pulse signal whose frequency is the ideal operating frequency within the first timing duration.

[0121] For example, assuming the ideal operating frequency of the chip clock is 24 MHz, Figures 2 to 4 For any of the reference clock generation circuits shown, assuming that the target circuit configuration information is [1, 1, 1, 1, 0, 0, 0…, 0], it means that Figure 2 In the figure, the first four delay circuits from left to right are opened in sequence through the series paths between the delay circuits of the next level, and when the paths between the other delay circuits are closed through the delay circuits of the next level, the frequency of the reference clock signal output by the reference clock generating circuit is 24 MHz.

[0122] In addition, after each adjustment of the control signal of each delay circuit in the reference clock generation circuit, in order to make the reference clock generation circuit generate a stable clock signal, several cycles can be waited after the control signal of each delay circuit is adjusted, so that the reference clock generation circuit outputs a stable clock signal. Among them, the loop formed by the NAND gate 2000 and the subsequent delay circuits in the reference clock generation circuit is also called an oscillation loop. At this time, after waiting for several cycles, the reference clock generation circuit outputs a stable clock signal, that is, the oscillation loop outputs a stable clock signal.

[0123] In addition, the above adjustment of the control signals of each delay circuit in the reference clock generating circuit can be achieved by binary division, thereby accelerating the above training process. That is, if the frequency of the clock signal output by the reference clock generating circuit after this adjustment does not meet the ideal operating frequency, the control signals of each delay circuit that needs to be adjusted next time are obtained based on the control signals of each delay circuit adjusted last time and binary division.

[0124] for example, Figures 2 to 4 Any of the reference clock generation circuits shown includes 60 delay circuits. First, assume that the control signals corresponding to the first 30 delay circuits are high level, and the control signals corresponding to the last 30 delay circuits are low level, and then determine the frequency of the clock signal output by the reference clock generation circuit at this time. Based on the frequency and the ideal operating frequency, determine whether the target number is within 30 or more than 30, where the target number specifically refers to: the number of delay circuits connected in the reference clock generation circuit when the frequency of the clock signal output by the reference clock generation circuit meets the ideal operating frequency. If the target number is within 30, continue to assume that the control signals corresponding to the first 15 delay circuits are high level, and the control signals corresponding to the last 45 delay circuits are low level, and then determine the frequency of the clock signal output by the reference clock generation circuit at this time. Repeat the above process until the frequency of the clock signal output by the reference clock generation circuit is determined to be substantially consistent with the ideal operating frequency.

[0125] The above uses the reference clock generating circuit including 60 delay circuits as an example to illustrate how to adjust the control signals of each delay circuit. The detailed process of the dichotomy of delay circuits with other numbers is not explained in detail in the embodiments of the present application.

[0126] In addition, it should be noted that no matter how the control signals of each delay circuit are adjusted, there may be a situation where the frequency of the clock signal generated by the reference clock generating circuit has a certain error with the ideal operating frequency. In this scenario, when the frequency of the pulse signal output by the reference clock generating circuit is within a certain error with the ideal operating frequency, the frequency of the clock signal output by the reference clock generating circuit can be fine-tuned by deducting pulses, so that the frequency of the clock signal output by the reference clock generating circuit is as consistent as possible with the ideal operating frequency.

[0127] The pulse-decreasing method can be implemented by gated enable signal. In a possible implementation, Figure 4 As shown, the reference clock generation circuit may further include a gating circuit, wherein the gating circuit is connected to the first output terminal of the first delay circuit connected in series. When a gating enable signal is input to the gating circuit, the gating enable signal is used to deduct one or P pulses of the clock signal output from the second output terminal of the first delay circuit connected in series, thereby achieving pulse deduction. The above-mentioned gating circuit can be specifically implemented by a trigger, and the embodiment of the present application does not limit the internal structure of the gating circuit.

[0128] In other words, the gating circuit includes an input terminal, an output terminal and a control terminal. The input terminal of the gating circuit is connected to the first output terminal of the first-stage delay circuit, and the output terminal of the gating circuit is connected to the output terminal of the reference clock generating circuit, that is, the first output terminal of the first-stage delay circuit is connected to the output terminal of the reference clock generating circuit through the gating circuit. The control terminal of the gating circuit is used to input a gating enable signal. Figure 4 In order to facilitate distinction, the control end of the gate control circuit is marked as the number "1", the input end of the gate control circuit is marked as the number "2", and the output end of the gate control circuit is marked as the number "3".

[0129] Specifically, when the gated enable signal is pulled low (for example, the gated enable signal is at a low level 0), the clock signal output by the reference clock generation circuit is gated. When the gated enable signal is pulled high (for example, the gated enable signal is at a high level 1), the clock signal output by the reference clock generation circuit passes normally, thereby fine-tuning the frequency of the clock signal output by the reference clock generation circuit. In this scenario, after training the reference clock generation circuit, the target circuit configuration information includes not only the control signal corresponding to each delay circuit being at a high level or a low level, but also the configuration information of the gated enable signal.

[0130] It should be noted that Figure 4 There is no correlation between the gate enable signal of the input gate circuit and the enable signal of the input NAND gate 2000, and the two are independent signals.

[0131] Figure 5 1 is a flow chart of a training reference clock generation circuit provided by an embodiment of the present application. Figure 5 As shown, after the training starts, the configuration level of the reference clock generation circuit and the number of pulses are set first. The configuration level is used to indicate whether the control signal corresponding to each delay circuit is high or low as mentioned above. Figure 2 After the clock signal output by the reference clock generating circuit shown in the figure circulates for several cycles, the number of pulses of the reference clock generating circuit within the first timing duration is counted to obtain a counting result. Then, it is determined whether the counting result meets the first theoretical value, and the first theoretical value indicates the number of pulses of the pulse signal with a frequency of the ideal working frequency within the first timing duration. If the counting result meets the first theoretical value, the configuration level of this time is used as the final configuration level, thereby obtaining the target circuit configuration information. If the counting result does not meet the first theoretical value, the configuration level is changed by binary division, and the number of deducted pulses is changed accordingly, and the re-counting process is returned until the final configuration level is obtained.

[0132] It should be noted that Figure 3 and Figure 4 The specific structure of the delay circuit in is only an optional circuit structure of the delay circuit provided in the embodiment of the present application. Any other circuit structure with the same function is also within the protection scope of the delay circuit involved in the embodiment of the present application, and will not be illustrated one by one here.

[0133] (2) The glitch detection circuit 105 is configured on the chip.

[0134] In the embodiment of the present application, in order to facilitate the subsequent detection of the glitch signal in the clock signal of the chip. A glitch detection circuit can also be pre-configured on the chip. The glitch detection circuit is the same as the aforementioned reference clock generation circuit, which is a fully digital circuit. The advantages of the fully digital circuit are not repeated here. In addition, the glitch signal in the detection clock signal in the embodiment of the present application can also be called the glitch in the detection clock signal, that is, "glitch signal" and "glitch" are used to indicate the same concept in the embodiment of the present application.

[0135] In a possible implementation, the glitch detection circuit includes N delay circuits, N AND gates, and N+1 triggers. Each delay circuit includes an input terminal and an output terminal, each AND gate includes a first input terminal, a second input terminal, and an output terminal, and each trigger includes an input terminal, an output terminal, and a control terminal. N is a positive integer greater than 1.

[0136] Among them, N delay circuits are connected in series. After the series connection, the output end of each delay circuit except the last delay circuit is connected to the input end of the next delay circuit, and the output end of each delay circuit in the N delay circuits is also connected to the first input end of an AND gate. The input end of the first delay circuit connected in series and the second input end of each AND gate are used to input the clock signal of the chip to be detected. The clock signal of the chip to be detected is subsequently referred to as the clock signal to be detected. The output end of each trigger in the N+1 triggers is connected in reverse phase to the input end of the same trigger, and the control ends of N triggers in the N+1 triggers are respectively connected to the output end of an AND gate, and the control ends of the remaining triggers in the N+1 triggers except the aforementioned N triggers are used to input the clock signal to be detected. Among them, the remaining triggers in the N+1 triggers except the aforementioned N triggers can also be called the first trigger.

[0137] Since the working principle of the AND gate is: when all inputs are at high level at the same time, the output is high level, otherwise the output is low level. Therefore, based on the above-mentioned glitch detection circuit, each AND gate will output a signal of the AND between the clock signal to be detected and the clock signal to be detected after a certain delay, and the delay time of the clock signal to be detected after the delay input to each AND gate is gradually increased. Since the pulse width of the glitch signal in the clock signal to be detected is usually lower than the pulse width of the clock signal under normal circumstances, therefore, as the delay time of the clock signal to be detected gradually increases, if the delay time of a certain delay circuit for the clock signal to be detected exceeds the pulse width of the glitch signal, the output signal of the AND gate connected to the delay circuit will not have a pulse corresponding to the glitch signal. Therefore, a target trigger can be selected from the N triggers connected to each AND gate based on the glitch detection range, and then the output signal of the target trigger can be compared with the output signal of the trigger inputting the clock signal to be detected, so as to determine whether there is a glitch signal in the clock signal to be detected. That is, the glitch signal in the clock signal to be detected can be detected based on the output signals of the output terminals of N+1 flip-flops.

[0138] That is, in an embodiment of the present application, the glitch detection circuit includes N cascaded delay circuits, N AND gates, and N+1 triggers, each of the N AND gates includes a first input terminal, a second input terminal, and an output terminal, each of the N+1 triggers includes an input terminal, an output terminal, and a control terminal, and N is a positive integer greater than 1.

[0139] Among them, the input end of the first delay circuit in the N cascaded delay circuits and the second input end of each AND gate in the N AND gates are used to input the clock signal. The output end of each delay circuit except the last delay circuit in the N cascaded delay circuits is connected to the input end of the next delay circuit. The output end of each delay circuit in the N delay circuits is respectively connected to the first input end of an AND gate. The control end of the first trigger in the N+1 triggers is used to input the clock signal, and the control ends of the N triggers in the N+1 triggers except the first trigger are connected to the output ends of the N AND gates, wherein one AND gate corresponds to one trigger. The output end of each trigger in the N+1 triggers is connected to the input end of the same trigger through an inverter. The output signal of the output end of the N+1 trigger is used to detect whether the clock signal contains glitches.

[0140] Figure 6 is a schematic diagram of the structure of a burr detection circuit provided in an embodiment of the present application. Figure 6 As shown, N delay circuits are connected in series, and the output end of each delay circuit in the first N-1 delay circuits after the series connection is connected to the input end of the next delay circuit. The output end of each delay circuit is also connected to the first input end of an AND gate. Figure 6 In FIG. 1 , the first input terminal of the AND gate is marked as 1, and the second input terminal of the AND gate is marked as 2. The second input terminal of each AND gate is used to input a clock signal to be detected.

[0141] Below Figure 6 The basic working principle of the burr detection circuit provided in the embodiment of the present application is described as an example.

[0142] like Figure 6 As shown, the detected clock signal is input to the input end of the first delay circuit connected in series and the second input end of each AND gate. Figure 7 Schematic diagram of pulse timing in a burr detection circuit provided in an embodiment of the present application. Figure 7 As shown, the detected clock signal is marked as clk, and the pulse distribution of clk is as follows Figure 7 As shown. The output signal of the first delay circuit is marked as clk-dly1, the output signal of the second delay circuit is marked as clk-dly2, ..., and the output signal of the Nth delay circuit is marked as clk-dlyN. Among them, the pulse distribution of clk-dly1, clk-dly2, ..., clk-dlyN is as follows Figure 7 As shown. Figure 7 As shown, relative to the clock signal clk to be detected, the delay time lengths of the output signals clk-dly1, clk-dly2, ..., clk-dlyN of the delay circuits relative to the clock signal clk to be detected gradually increase.

[0143] When the output signal of each delay circuit and the clock signal to be detected are input into the corresponding AND gate, the AND gate outputs the signal of the AND of the clock signal to be detected and the clock signal to be detected after the delay. Figure 7 As shown, clk-det1 is the output signal of clk-dly1 and clk after passing through the AND gate, clk-det2 is the output signal of clk-dly2 and clk after passing through the AND gate, ..., clk-detN is the output signal of clk-dlyN and clk after passing through the AND gate.

[0144] Based on the above Figure 7 It can be seen from the pulse distribution shown that when there is a glitch signal in the clock signal clk to be detected, if the delay time of the delay circuit for the clock signal to be detected is less than the pulse width of the glitch signal, then the pulse corresponding to the glitch signal will exist in the output signal of the AND gate connected to the delay circuit; if the delay time of the delay circuit for the clock signal to be detected is greater than the pulse width of the glitch signal, then the pulse corresponding to the glitch signal will not exist in the output signal of the AND gate connected to the delay circuit. Since the pulse width of the glitch signal is usually lower than the pulse width of the clock signal under normal circumstances, as the number of delay circuits connected in series increases, the pulses corresponding to the glitch signal may be detected in the output signals of the first few AND gates, but the pulses corresponding to the glitch signal will not be detected in the output signals of subsequent AND gates. For example, Figure 7 In the pulse distribution corresponding to clk-det1, Figure 7 There is one more pulse at the position of the oval frame than at the corresponding position of clk-detN. This pulse is the pulse corresponding to the glitch signal in the output signal of the detected clock.

[0145] also, Figure 7 The pulse distribution in the output signal of each AND gate can be determined by sampling the trigger. Figure 6 As shown, each AND gate output is connected to a flip-flop. Figure 6 The trigger in may include a control terminal ( Figure 6 The control terminal is marked as CP), the input terminal ( Figure 6 The input terminal is marked as D) and the output terminal ( Figure 6 The output terminal is marked as Q in the figure. Figure 6 As shown, Figure 6 The output of each AND gate is connected to the control end of a trigger. In this way, the trigger can collect data on the rising edge of the output signal of the AND gate. In addition, Figure 6 The input of the trigger is the inverted signal of the output of the trigger. Figure 6 The flip-flop shown can change the output state at every rising edge of the output signal of the AND gate.

[0146] For example, at the first rising edge of the output signal of the AND gate, the stored 1 is converted to 0 and 0 is stored, and at the second rising edge of the output signal of the AND gate, the stored 0 is converted to 1 and 1 is stored. Therefore, the pulse distribution in each clock cycle of the output signal of the AND gate can be determined by the 1 and 0 recorded by the trigger.

[0147] At this time, a target trigger is selected from the N triggers connected to each AND gate, and then the output signal of the target trigger is compared with the output signal of the trigger that inputs the clock signal to be detected. Specifically, the distribution of 1 and 0 collected in each clock cycle is compared to determine whether there is a glitch signal in the clock signal to be detected. Figure 6 As shown in the figure, from top to bottom, the data collected by the fourth trigger is selected based on the glitch detection range to determine whether the clock signal to be detected has a glitch signal, and the distribution of 1 and 0 collected by the fourth trigger within a certain clock cycle is 1000, but the distribution of 1 and 0 collected by the last trigger (which collects the clock signal to be detected) within the clock cycle is 1010, which indicates that there is a glitch signal in the clock signal to be detected within the clock cycle.

[0148] In addition, the above-mentioned selecting a target trigger from N triggers connected to each AND gate based on the glitch detection range specifically refers to: determining the delay duration of the output signal of each delay circuit relative to the clock signal to be detected, selecting the delay circuit corresponding to the minimum delay duration from the delay durations whose delay durations exceed the glitch detection range, and using the trigger connected to the selected delay circuit as the target trigger.

[0149] In one possible implementation, Figure 6 The inherent delay time lengths of the delay circuits shown are the same, and the inherent delay time length of the delay circuit refers to the delay time length of the output signal of the delay circuit relative to the input signal of the delay circuit itself. At this time, the above-mentioned selection of a target trigger from the N triggers connected to each AND gate based on the glitch detection range specifically refers to: dividing the glitch detection range and the inherent delay time length of a single delay circuit, taking the integer after the division, assuming that the integer is i, then taking the trigger connected to the i-th delay circuit in the N delay circuits connected in series as the target trigger.

[0150] In addition, the internal structure of the delay circuit included in the glitch detection circuit configured on the chip can be a delay circuit with the same structure as the internal structure of the delay circuit included in the aforementioned reference clock generation circuit, but the connection relationship between each delay circuit is different, so that the inherent delay length of each delay circuit in the glitch detection circuit is the same as the inherent delay length of the delay circuit in the reference clock generation circuit. So that after training the reference clock generation circuit, the above-mentioned target trigger can be determined based on the inherent delay length and glitch detection range of the delay circuit in the trained reference clock generation circuit. That is, in the embodiment of the present application, the glitch detection circuit does not need to be pre-trained, and only based on the inherent delay length and glitch detection range of a single delay circuit in the trained reference clock generation circuit, it can be determined which trigger in the glitch detection circuit needs to be used as the target trigger.

[0151] Specifically, after training the reference clock generation circuit, determine the inherent delay length of a single delay circuit in the trained reference clock generation circuit, and then determine the upper limit of the glitch detection range. Based on the upper limit of the glitch detection range and the aforementioned inherent delay length, the above-mentioned target trigger can be configured. For example, the inherent delay length of a single delay circuit in the trained reference clock generation circuit is 1ns, and the pulse signal with a pulse width within 3ns is called a glitch signal, then i in the glitch detection circuit is configured as 3 / 1=3. At this time, for Figure 6 The glitch detection circuit shown in the figure connects the output signal of the trigger connected to the third delay circuit in series and Figure 6 By comparing the output signal of the last trigger in the detection, it can be determined whether there is a glitch signal in the clock signal to be detected.

[0152] It should be noted that in the glitch detection circuit, the internal structure of a single delay circuit can be Figure 2 The internal structures of the delay circuits included in the reference clock generation circuit are the same, but the connection relationships between the delay circuits are different. Figure 8 It is a schematic diagram of the connection relationship of various delay circuits in a burr detection circuit provided in an embodiment of the present application.

[0153] like Figure 8 As shown, any delay circuit among the N delay circuits 601 includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and any one of the first NAND gate, the second NAND gate, and the third NAND gate includes a first input terminal, a second input terminal and an output terminal, and the inverter includes an input terminal and an output terminal. Figure 8 In the figure, the first NAND gate is marked as 6011, the second NAND gate is marked as 6012, the third NAND gate is marked as 6013, and the inverter is marked as 6014. The first input terminal of each NAND gate is marked as a number "1", and the second input terminal of each NAND gate is marked as a number "2".

[0154] like Figure 8 As shown, the first input end of the first NAND gate 6011 is the input end of the delay circuit 601, and the output end of the third NAND gate 6013 is the output end of the delay circuit 601, wherein the N delay circuits are connected in series specifically means that the output end of the first delay circuit 601 is connected to the input end of the second delay circuit 601, the output end of the second delay circuit 601 is connected to the input end of the third delay circuit 601, and so on, until the output end of the N-1th delay circuit 601 is connected to the input end of the Nth delay circuit 601. That is, the input end of each stage of delay circuit is connected to the output end of the previous stage of delay circuit, and the output end of each stage of delay circuit is connected to the input end of the next stage of delay circuit.

[0155] for Figure 6 In the glitch detection circuit shown in FIG. 1 , the output terminal of the third NAND gate 6013 in any delay circuit is also connected to Figure 6 One of them is connected to the first input terminal of the AND gate.

[0156] That is, in the embodiment of the present application, any one of the N delay circuits in the glitch detection circuit includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and any one of the first NAND gate, the second NAND gate, and the third NAND gate includes a first input terminal, a second input terminal and an output terminal.

[0157] The input end of the delay circuit is connected to the first input end of the first NAND gate and the first input end of the second NAND gate. The output end of the delay circuit is connected to the input end of the next delay circuit. The control end of the delay circuit is connected to the second input end of the first NAND gate and the input end of the inverter. The output end of the inverter is connected to the second input end of the second NAND gate. The output end of the second NAND gate is connected to the first input end of the third NAND gate. The output end of the first NAND gate is connected to the second input end of the third NAND gate.

[0158] In addition, Figure 8 In the connection relationship shown, the control signals corresponding to each delay circuit are configured as high-level signals so that Figure 6 Each trigger in the glitch detection circuit shown can collect signals, thereby realizing the detection of glitch signals.

[0159] It should be noted that, since the range of the glitch signal may be changing, the glitch detection circuit pre-configured on the chip may include a large number of delay circuits and AND gates and triggers subsequently connected to the delay circuits. In subsequent actual measurements, the trigger connected to which delay circuit is connected in series can be determined based on the glitch detection range. For example, 20 delay circuits connected in series are pre-configured in the glitch detection circuit. When it is determined that N is 3, the glitch signal can be detected only through the output signal of the trigger connected to the third delay circuit.

[0160] In addition, if the glitch detection range of the clock signal can be determined before the chip leaves the factory, it is possible to determine which trigger the upper target trigger is before the chip leaves the factory, generate second target circuit indication information, and then write the information about which trigger the second target trigger is into the chip. The second target circuit configuration information can also be called target circuit configuration information for the glitch detection circuit.

[0161] (3) The duty cycle detection circuit 106 is configured on the chip.

[0162] In the embodiment of the present application, in order to facilitate the subsequent detection of the duty cycle of the clock signal on the chip, a duty cycle detection circuit can also be configured on the chip in advance. The duty cycle detection circuit is the same as the aforementioned reference clock generation circuit, which is a fully digital circuit. The advantages of the fully digital circuit will not be repeated here.

[0163] In one possible implementation, Fig. 9 is a schematic diagram of a duty cycle detection circuit provided in an embodiment of the present application. Fig. 9 As shown, the duty cycle detection circuit includes a first delay adjustment circuit ( Fig. 9 The first delay adjustment circuit is marked as DLY-FIX, the second delay adjustment circuit ( Fig. 9 The second delay adjustment circuit is marked as DLE-TRIM-DUTY) and the M third delay adjustment circuits ( Fig. 9 The third delay adjustment circuit is marked as DLY-CLK-DUTY), a frequency divider, an inverter, M+2 two-stage registers, M+1 XOR gates ( Fig. 9 The logic gate marked with XOR in the figure indicates an exclusive OR gate), M+1 flip-flops. M is a positive integer greater than 1.

[0164] Each XOR gate includes a first input terminal, a second input terminal and an output terminal. Each two-stage register includes a first input terminal, a second input terminal and an output terminal. Fig. 9The first input terminal of each two-stage register is marked as a number "1", and the second input terminal of each two-stage register is marked as a number "2". Each trigger includes an input terminal, an output terminal, and a control terminal. Each XOR gate includes a first input terminal, a second input terminal, and an output terminal. Fig. 9 The first input terminal of each XOR gate is marked as a number "1", and the second input terminal of each XOR gate is marked as a number "2". The frequency divider, the inverter, the first delay adjustment circuit, the second delay adjustment circuit, and the M third delay adjustment circuits all include an input terminal and an output terminal.

[0165] Among them, M third delay adjustment circuits are connected in series, the output end of the frequency divider is connected to the input end of the first delay adjustment circuit, the output end of the first delay adjustment circuit is connected to the input end of the second delay adjustment circuit, and the output end of the second delay adjustment circuit is connected to the input end of the first third delay adjustment circuit after the series connection. The output end of the second delay adjustment circuit and the output end of each third delay adjustment circuit after the series connection are connected to the first input end of a two-stage register, and the output end of each two-stage register is connected to the first input end of an XOR gate. Fig. 9 In the M+1 two-stage registers, the M two-stage registers connected to each XOR gate are called two-stage register A.

[0166] In addition, the output terminal of the inverter is connected to the first input terminal of a two-stage register remaining in the M+1 two-stage registers except the aforementioned M two-stage registers, Fig. 9 The two-stage register is marked as two-stage register B. The output end of the frequency divider is also connected to the second input end of the two-stage register B, and the output end of the two-stage register B is connected to the second input end of each XOR gate. In addition, the output end of the inverter is also connected to the second input end of each two-stage register A. The input ends of the aforementioned frequency divider and inverter are both used to input the clock signal to be detected.

[0167] The above-mentioned two-stage register A can also be called the second two-stage register, and the two-stage register B can also be called the first two-stage register. The frequency divider can be specifically obtained by combining a trigger and an inverter, that is, the frequency divider includes an input end, an output end and a control end, and the input end and the output end are connected through an inverter. In addition, the inverter in the frequency divider can be called the second inverter, and the inverter for inputting the clock signal to be detected can be called the first inverter. In this scenario, the connection relationship of the above-mentioned duty cycle detection circuit can also be described as follows.

[0168] The duty cycle detection circuit includes a first delay adjustment circuit, a second delay adjustment circuit and M cascaded third delay adjustment circuits, a frequency divider, a first inverter, a second inverter, a first two-stage register and M+1 second two-stage registers, M+1 XOR gates and M+1 triggers, where M is a positive integer greater than 1.

[0169] Among them, any one of the first two-stage register and the M+1 second two-stage register includes a first input terminal, a second input terminal and an output terminal, each of the M+1 XOR gates includes a first input terminal, a second input terminal and an output terminal, each of the M+1 triggers includes an input terminal, an output terminal and a control terminal, and the frequency divider includes an input terminal, an output terminal and a control terminal. The control terminal of the frequency divider is used to input a clock signal, the input terminal of the frequency divider and the output terminal of the frequency divider are connected through a second inverter, the output terminal of the frequency divider is connected to the input terminal of the first delay adjustment circuit, the output terminal of the first delay adjustment circuit is connected to the input terminal of the second delay adjustment circuit, and the output terminal of the second delay adjustment circuit is connected to the input terminal of the first stage third delay adjustment circuit in the cascaded M third delay adjustment circuits.

[0170] The output end of the second delay adjustment circuit and the output end of each of the cascaded M third delay adjustment circuits are connected to the first input ends of the M+1 second two-stage registers in a one-to-one correspondence. The second input ends of the M+1 second two-stage registers are all connected to the output end of the first inverter, the input end of the first inverter is used to input the clock signal, and the output ends of the M+1 second two-stage registers are connected to the first input ends of the M+1 XOR gates in a one-to-one correspondence. The output ends of the M+1 XOR gates are connected to the input ends of the M+1 triggers in a one-to-one correspondence.

[0171] The output end of the first inverter is also connected to the first input end of the first two-stage register, the output end of the frequency divider is connected to the second input end of the first two-stage register, and the output end of the first two-stage register is connected to the second input end of M+1 XOR gates. The output signal of the output end of the M+1 trigger is used to detect the duty cycle of the clock signal.

[0172] Below Fig. 9 Take the example to explain the working principle of the duty cycle detection circuit provided in the embodiment of the present application.

[0173] like Fig. 9 As shown, after the clock signal to be detected is input into the frequency divider, the frequency divider converts the clock signal to be detected into a pulse signal with 1 / 2 of the original frequency. Fig.10 1 is a pulse timing diagram of output signals of various circuits in a duty cycle detection circuit provided in an embodiment of the present application. Fig.10As shown, the clock signal to be detected is marked as clk, and the output signal of the frequency divider is marked as clk-div2, and the frequency of clk-div2 is 1 / 2 of the frequency of clk.

[0174] For the convenience of subsequent explanation, the pulse signal with 1 / 2 of the original frequency is called a frequency-divided signal, and the frequency-divided signal is delayed in sequence after passing through the first delay adjustment circuit and the second delay adjustment circuit. Fig.10 In the example, the output signal of the first delay adjustment circuit is marked as clk-dly-fix, and the output signal of the second delay adjustment circuit is marked as clk-dly0. Fig.10 As shown, the output signal of the first delay adjustment circuit is delayed for a period of time relative to the output signal clk-div2 of the frequency divider, and the output signal clk-dly0 of the second delay adjustment circuit is delayed for another period of time relative to the output signal clk-dly-fix of the first delay adjustment circuit. Fig.10 In the figure, the delay duration between the output signal clk-dly-fix of the first delay adjustment circuit and the output signal clk-div2 of the frequency divider is marked as DLY-FIX, and the delay duration between the output signal clk-dly0 of the second delay adjustment circuit and the output signal clk-dly-fix of the first delay adjustment circuit is marked as DLY-TRIM.

[0175] The output signal of the second delay adjustment circuit is input to the first third delay adjustment circuit connected in series, and each third delay adjustment circuit delays its input signal for a certain period of time. Fig.10 As shown, the output signals of the third delay adjustment circuits are marked as clk-dly1, clk-dly2, clk-dly3, ..., clk-dlyM in sequence. Fig.10 As shown in FIG. 1 , if the inherent delay duration of a single third delay adjustment circuit is marked as DLY-DUTY, then Fig.10 As shown, the delay length of clk-dly1 relative to clk-dly0 is DLY-DUTY, the delay length of clk-dly2 relative to clk-dly2 is DLY-DUTY, ..., the delay length of clk-dlyM relative to clk-dlyM-1 is DLY-DUTY.

[0176] Fig. 9 and Fig.10 In the embodiment, after the clock signal clk to be detected is input to the inverter, the output signal of the inverter is marked as clk-INV. Fig. 9 As shown, Fig.10In which clk-dly0, clk-dly1, clk-dly2, clk-dly3, ..., clk-dlyM are respectively input to the two-stage register A with the output signal clk-INV of the inverter for synchronization processing. The function of the synchronization processing process is to adjust the rising edge or falling edge of each signal in clk-dly0, clk-dly1, clk-dly2, clk-dly3..., clk-dlyM to align with the rising edge or falling edge of clk-INV. Specifically, at each rising edge of the output signal clk-INV of the inverter, the corresponding clk-dly signal is determined to be high or low. If it is high, a high level is output until the next rising edge. The corresponding clk-dly signal is continued to be judged to be high or low. If it is low, a low level is output. In this way, the signals processed by the two-stage registers are respectively as follows Fig.10 As shown in clk-dff2-dly0, clk-dff2-dly1, clk-dff2-dly2, clk-dff2-dly3, …, clk-dff2-dlyM.

[0177] In addition, if Fig. 9 As shown, the output signal clk-INV of the inverter and the output signal clk-div2 of the divider are also input into the two-stage register B for synchronization processing, and the obtained signal is marked as clk-no-dly0. The signal clk-no-dly0 can also be called "the output signal of the anti-clock acquisition two-frequency clock", and then clk-no-dly0 and clk-dff2-dly0, clk-dff2-dly1, clk-dff2-dly2, clk-dff2-dly3, ..., clk-dff2-dlyM are respectively input into the corresponding XOR gate. Among them, the function of the XOR gate is: if the input levels of the two input terminals are different, the output is a high level; if the input levels of the two input terminals are the same, the output is a low level. As shown Fig. 9 As shown, the output signals of each XOR gate are marked as clk-data-dly0, clk-data-dly1, clk-data-dly2, clk-data-dly3, …, clk-data–dlyM in sequence.

[0178] Specifically, Fig.10 As shown, the two input signals of any XOR gate are either the same signal or inverted signals, so each XOR gate outputs a high level signal or a low level signal.

[0179] In addition, the output signals of each XOR gate can be collected through triggers. Fig. 9 As shown, the trigger includes a control terminal ( Fig. 9The control terminal is marked as CP), the input terminal ( Fig. 9 The input terminal is marked as D) and the output terminal ( Fig. 9 The output terminal is marked as Q), and the output terminal of each XOR gate is connected to the input terminal of a trigger. Fig. 9 The control terminal of the trigger in is used to input the output signal clk-INV of the inverter. The output signal of the output terminal of the trigger is consistent with the input signal of the input terminal of the trigger. That is, Fig. 9 The trigger in is used to collect the output signal of the XOR gate at each rising edge of the output signal clk-INV of the inverter. Based on the above, it can be seen that each XOR gate outputs a high level signal or a low level signal, so the data collected by the trigger is either 0 or 1.

[0180] based on Fig.10 From the pulse distribution shown, it can be seen that the output signal of each XOR gate can represent the distribution of high and low levels on the left and right sides of the falling edge of the clock signal to be detected in a clock cycle. Since the high level is usually represented by 1 and the low level is usually represented by 0, the distribution of high and low levels on the left and right sides of the falling edge can also be called "output code words on the left and right sides of the falling edge".

[0181] Based on the information represented by the output signals of the above-mentioned XOR gates, a time interval can be set in advance based on the allowable range of the duty cycle to collect the distribution of high and low levels on both sides of the falling edge of the clock signal to be detected in a clock cycle within the time interval. If there are both high and low levels in the output signals of each XOR gate within the time interval, it is determined that the duty cycle of the clock signal to be detected is within the allowable range of the duty cycle. If the output signals of each XOR gate within the time interval are all high or all low (for example, all 0 or all 1), it is determined that the duty cycle of the clock signal to be detected is not within the allowable range of the duty cycle.

[0182] It should be noted that in Fig. 9 In the duty cycle detection circuit shown, the total delay duration of each third delay adjustment circuit can indicate the above time interval, so the delay duration of each third delay adjustment circuit can be set in advance based on the allowable range of the duty cycle.

[0183] In a possible implementation, each third delay adjustment circuit may include k delay circuits, k is a positive integer greater than 1, and the structure and connection relationship of the delay circuits included in the third delay adjustment circuit may be the same as Figure 2 The structures and connection relationships of the delay circuits in the reference clock generating circuits shown are the same.

[0184] That is, in a possible implementation, any third delay adjustment circuit among the M third delay adjustment circuits includes k cascaded delay circuits, and each of the k cascaded delay circuits includes a control terminal, and the control terminal is used to input a control signal to control the corresponding delay circuit to be turned on or off. Among them, the first-stage delay circuit among the k cascaded delay circuits includes a first input terminal and a first output terminal. The first input terminal of the first-stage delay circuit is connected to the input terminal of the third delay adjustment circuit. The first output terminal of the first-stage delay circuit is connected to the output terminal of the third delay adjustment circuit.

[0185] Regarding the connection relationship between the delay circuits from the first delay circuit to the last delay circuit in the third delay adjustment circuit, reference can be made to the aforementioned Figure 2 The embodiments of the present invention will not be described in detail here.

[0186] In addition, and Figure 2 As in, any delay circuit among the k delay circuits includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and any of the first NAND gate, the second NAND gate and the third NAND gate includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the delay circuit is connected to the first input terminal of the first NAND gate and the second NAND gate. The second input terminal of the delay circuit is connected to the second input terminal of the third NAND gate. The first output terminal of the delay circuit is connected to the output terminal of the third NAND gate. The second output terminal of the delay circuit is connected to the output terminal of the first NAND gate. The control terminal of the delay circuit is connected to the second input terminal of the first NAND gate and the input terminal of the inverter. The output terminal of the inverter is connected to the second input terminal of the second NAND gate. The output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate.

[0187] That is, any delay circuit among the k delay circuits in the third delay adjustment circuit includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, any one of the first NAND gate, the second NAND gate and the third NAND gate includes a first input terminal, a second input terminal and an output terminal, and the inverter includes an input terminal and an output terminal.

[0188] Among them, the first input end of the first NAND gate in the first delay circuit after the series connection is the input end of the corresponding third delay adjustment circuit, and the first input end of the first NAND gate in the other delay circuits except the first delay circuit after the series connection is connected to the output end of the first NAND gate in the previous delay circuit connected in series. The second input end of the first NAND gate in any delay circuit and the input end of the inverter are used to input the control signal corresponding to any delay circuit. The output end of the inverter in any delay circuit is connected to the second input end of the second NAND gate in the same delay circuit, the first input end of the second NAND gate in any delay circuit is the same as the input signal of the first input end of the first NAND gate in the same delay circuit, and the output end of the second NAND gate in any delay circuit is connected to the first input end of the third NAND gate in the same delay circuit. The second input end of the third NAND gate in the last delay circuit after the series connection is connected to the output end of the first NAND gate in the same delay circuit, and the second input end of the third NAND gate in the other delay circuits except the last delay circuit after the series connection is connected to the output end of the third NAND gate in the next delay circuit. The output end of the third NAND gate in the first delay circuit connected in series is the output end of the corresponding third delay adjustment circuit.

[0189] The specific connection relationship between the delay circuits in the third delay adjustment circuit can be referred to Figure 2 , which will not be described in detail here.

[0190] At this point, after training Figure 2 After the reference clock generating circuit shown in the figure is trained, the number of delay circuits connected in series in the third delay adjustment circuit can be set based on the inherent delay time length and the allowable range of the duty cycle of a single delay circuit in the trained reference clock generating circuit, thereby setting the delay time length of each third delay adjustment circuit. That is, a plurality of delay circuits are pre-set in any third delay adjustment circuit, and when used, the number of delay circuits connected in series in the third delay adjustment circuit is set based on the allowable range of the duty cycle.

[0191] For example, the duty cycle range is 40% to 60%, and one clock cycle is 1 nanosecond (ns). The high level duration in one clock cycle is 0.4 to 0.6 ns (the low level duration is 0.6 to 0.4 ns). At this time, the time interval corresponding to the duty cycle range is 0.1 ns. Assume that the third delay adjustment circuit has 10 levels (that is, Fig. 9In the duty cycle detection circuit shown, N=10), the delay time length of each level of the third delay adjustment circuit is 0.1ns / 10=0.01ns. If the inherent delay time length of a single delay circuit in the trained reference clock generation circuit is 0.005ns, 0.01 / 0.005=2 delay circuits need to be set in each third delay adjustment circuit. At this time, the number of delay circuits determined can also be referred to as the number of configuration levels for the third delay adjustment circuit.

[0192] Before the chip leaves the factory, if the allowable range of the duty cycle of the clock signal can be determined, the number of delay units connected in series among the k delay units included in any third delay adjustment circuit can be determined based on the allowable range of the duty cycle. At this time, the target circuit configuration information for the duty cycle detection circuit can be generated based on the number of delay units connected in series among the k delay units included in any third delay adjustment circuit, and the target circuit configuration information for the duty cycle detection circuit can be written into the chip.

[0193] In addition, the delay durations in the first delay adjustment circuit and the second delay adjustment circuit are obtained by training in advance. During the training process, a clock signal with an ideal duty cycle is input to the duty cycle detection circuit, and then the delay durations of the first delay adjustment circuit and the second delay adjustment circuit are continuously adjusted until the ratio between the number of triggers that output 0 and the number of triggers that output 1 in each trigger is consistent with the ideal duty cycle, at which time the training purpose is achieved. After the training purpose is achieved, the delay durations of the first delay circuit and the second delay adjustment circuit after the last adjustment are carried in the target circuit configuration information of the duty cycle detection circuit, so that the target circuit configuration information is written into the chip.

[0194] The target circuit configuration information for the duty cycle detection circuit may also be referred to as third target circuit configuration information.

[0195] The consistency between the ratio of the number of triggers that output 0 and the number of triggers that output 1 in each of the above-mentioned triggers and the ideal duty cycle means that the ratio between the number of triggers that output 0 and the number of triggers that output 1 in each trigger is the same as the ratio between the high level width and the low level width in the ideal duty cycle.

[0196] Specifically, after the delay time length of the third delay adjustment circuit is configured based on the duty cycle allowable range, a clock signal whose duty cycle satisfies the ideal duty cycle is input to Fig. 9The duty cycle detection circuit shown in the figure then adjusts the delay time lengths of the first delay adjustment circuit and the second delay adjustment circuit. After each adjustment, it is determined whether the ratio between the number of triggers that output 0 and the number of triggers that output 1 in each trigger is consistent with the ideal duty cycle. If they are consistent, the delay time lengths of the first delay adjustment circuit and the second delay adjustment circuit after this adjustment are determined as the target circuit configuration information of the duty cycle detection circuit. If they are inconsistent, the delay time lengths of the first delay adjustment circuit and the second delay adjustment circuit are continuously adjusted.

[0197] For example, the ideal duty cycle of the clock signal on the current chip is usually 50%. Therefore, when training the duty cycle detection circuit, a standard clock signal with a duty cycle of 50% can be input to the duty cycle detection circuit, and then the delay lengths of the first delay adjustment circuit and the second delay adjustment circuit are adjusted until the number of triggers that output 0 and the number of triggers that output 1 in each trigger are basically the same, that is, nearly half of the triggers in each trigger output data of 0, and nearly half of the triggers output data of 1.

[0198] It should be noted that Fig. 9 The first delay adjustment circuit (DLY-FIX) in the duty cycle detection circuit shown is used to implement a coarse adjustment of the delay of the input signal, and the second delay adjustment circuit (DLE-TRIM-DUTY) is used to implement a fine adjustment of the delay of the input signal. Fig. 9 The duty cycle detection circuit shown may also be provided with only one delay adjustment circuit, which is not limited in the embodiment of the present application.

[0199] also, Fig. 9 The configuration signal in is used to configure the delay size of each delay adjustment circuit. That is, after the delay length of each delay adjustment circuit is determined, the delay length of each delay adjustment circuit is set through the configuration signal.

[0200] The above content describes in detail the digital circuit expanded on the chip. In the embodiment of the present application, the reference clock generation circuit, glitch detection circuit and duty cycle detection circuit can be configured on the chip at the same time before the chip leaves the factory, so as to facilitate the detection of the frequency, glitch signal and duty cycle of the clock signal on the same chip based on these three circuits after leaving the factory.

[0201] Optionally, before the chip leaves the factory, after configuring the above-mentioned reference clock generation circuit, glitch detection circuit and duty cycle detection circuit, an enable switch may be configured for each circuit, so that after leaving the factory, a certain circuit can be enabled according to measurement requirements and the enable switch, and the clock signal on the same chip can be detected based on the circuit.

[0202] Optionally, before the chip leaves the factory, only one or more of the above three circuits can be configured based on actual measurement requirements. For example, if only the frequency of the chip's clock signal needs to be detected in the actual application scenario, the above reference clock generation circuit can be configured on the chip before the chip leaves the factory. Alternatively, if only the frequency of the chip's clock signal and the glitch signal need to be detected in the actual application scenario, the above reference clock generation circuit and the glitch detection circuit can be configured on the chip before the chip leaves the factory. Examples are not given one by one here.

[0203] It should be noted that, when the delay circuit included in the glitch detection circuit and the delay circuit included in the reference clock generating circuit have the same structure, since the delay circuit used in the glitch detection circuit to detect the glitch signal needs to be determined based on the inherent delay length and glitch detection range of the delay circuit in the reference clock generating circuit after training, in this scenario, even if only the glitch signal in the chip's clock signal needs to be detected, the reference clock generating circuit and the glitch detection circuit are configured on the chip at the same time.

[0204] Similarly, in the case where the delay circuit included in the third delay adjustment circuit in the duty cycle detection circuit and the delay circuit included in the reference clock generating circuit have the same structure, since the number of delay circuits connected in series in the third delay adjustment circuit needs to be determined based on the inherent delay duration and the allowable range of the duty cycle of the delay circuit in the reference clock generating circuit after training, in this scenario, even if only the duty cycle of the chip's clock signal needs to be detected, the reference clock generating circuit and the duty cycle detection circuit are configured on the chip at the same time.

[0205] In addition, the training process of the reference clock generation circuit and the training process of the duty cycle detection circuit can be completed before the chip leaves the factory. In this scenario, the target circuit configuration information of the trained reference clock generation circuit and the target circuit configuration information of the trained duty cycle detection circuit are written into the chip. This facilitates the subsequent detection of the clock signal to be detected based on the trained target circuit configuration information.

[0206] Optionally, the training process of the reference clock generation circuit and the training process of the duty cycle detection circuit can also be completed based on specific requirements after the chip leaves the factory. In this scenario, after the chip leaves the factory, the reference clock generation circuit and the duty cycle detection circuit can be trained based on ideal operating parameters such as ideal operating frequency and ideal duty cycle according to specific requirements. The training process can also refer to the above content and will not be described in detail here.

[0207] It should be noted that, in the embodiments of the present application, the ideal operating parameters refer to the operating parameters of the clock expected when configuring the clock for the chip. The ideal operating parameters may include an ideal operating frequency and / or an ideal duty cycle. Among them, the ideal operating frequency refers to the frequency of the expected clock signal, and the ideal duty cycle refers to the duty cycle of the expected clock signal. When applying the embodiments of the present application, the ideal operating frequency and the ideal duty cycle can be obtained through the configuration data of the chip when it leaves the factory. For example, the rated operating frequency of the clock configured when the chip leaves the factory can be used as the ideal operating frequency, and the rated signal duty cycle of the clock configured when the chip leaves the factory can be used as the ideal duty cycle.

[0208] For example, currently, the chips commonly used in the market have a clock with a rated operating frequency of 24 MHz and a rated signal duty cycle of 50% configured when the chips are shipped out of the factory. In this case, the aforementioned ideal operating parameters may include an ideal operating frequency of 24 MHz and / or an ideal duty cycle of 50%.

[0209] The training process of the reference clock generation circuit, the glitch detection circuit and the duty cycle detection circuit has been explained in detail in the aforementioned embodiments. The following is a detailed description of the process of detecting the clock signal on the chip based on the configured circuits.

[0210] Fig.11 is a flow chart of a clock detection method provided by an embodiment of the present application. Figure 1 The chip further comprises a clock for generating a clock signal, and the chip further comprises at least one of a reference clock generating circuit, a glitch detection circuit or a duty cycle detection circuit. Fig.11 As shown, the method includes the following steps.

[0211] Step 1101: The processor detects a clock signal based on at least one of the following.

[0212] like Fig.11 As shown, at least one item in step 1101 includes: detecting the frequency of the clock signal based on a reference clock signal generated by a reference clock generating circuit; or, detecting whether the clock signal contains glitches based on a glitch detection circuit; or, detecting the duty cycle of the clock signal based on a duty cycle detection circuit.

[0213] based on Fig.11 In the embodiment shown, the frequency of the clock signal on the chip can be detected based on the reference clock generating circuit, thereby avoiding the need to derive a standard reference clock through an analog circuit when detecting the clock signal on the chip, thereby saving chip resources. Fig.11 The illustrated embodiment can also detect glitches contained in the clock signal and the duty cycle of the clock signal on the same chip, thereby improving the flexibility of detecting the clock signal.

[0214] about Fig.11 The specific implementation methods of detecting the frequency of the clock signal, detecting the burrs in the clock signal, and detecting the duty cycle of the clock signal will be described in detail through the following three embodiments, which will not be elaborated here.

[0215] Fig.12 1 is a flow chart of a clock detection method provided in an embodiment of the present application. The method is used to detect the frequency of the clock signal of the chip. For the convenience of subsequent description, the clock signal of the chip to be detected is referred to as the clock signal to be detected.

[0216] based on Figure 1 As can be seen from the chip shown, the method provided in the embodiment of the present application is applied to the processor of the chip. Fig.12 As shown, the method includes the following steps.

[0217] Step 1201: The processor determines a second timing duration based on an ideal operating frequency, and controls control signals corresponding to each delay circuit included in a reference clock generating circuit according to first target circuit configuration information, so that the reference clock generating circuit outputs a reference clock signal, wherein the first target circuit configuration information indicates that the control signals corresponding to each delay circuit in the reference clock are high or low levels.

[0218] Since the first target circuit configuration information is the circuit configuration information after the reference clock generating circuit is trained according to the ideal operating frequency, when the processor controls the control signals corresponding to each delay circuit according to the first target circuit configuration information, the reference clock generating circuit can output a reference clock signal, and the frequency of the reference clock signal is the above-mentioned ideal operating frequency.

[0219] The second timing duration is a timing duration designed to count the clock signal to be detected. The second timing duration can be configured based on specific needs after the chip leaves the factory, or it can be configured before the chip leaves the factory. It should be noted that the "first" and "second" in the second timing duration and the aforementioned first timing duration have no specific meanings. The "first" and "second" here are only used to distinguish two different timing durations.

[0220] Step 1202: The processor counts the number of pulses in the reference clock signal within the second timing duration, and the number of pulses in the clock signal to be detected within the second timing duration, to obtain a first counting result and a second counting result, respectively.

[0221] Since the frequency of the standard reference clock is the ideal operating frequency mentioned above, the frequency of the clock signal to be detected can be detected with the standard reference clock as a theoretical reference object.

[0222] When counting specifically, a pulse signal with a pulse width equal to the second timing duration can be designed based on the second timing duration, and then the counter is controlled by the pulse signal. During the counting process, if the pulse signal is at a high level, no operation needs to be performed on the counter, and the counter continues to count. If the pulse signal is at a low level, the counter is controlled to stop counting. Thus, the counter counts within the second timing duration.

[0223] Step 1203: If the difference between the first counting result and the second counting result exceeds the second reference difference, a first frequency prompt signal is output, where the first frequency prompt signal indicates that the frequency of the clock signal to be detected is unstable.

[0224] Correspondingly, if the difference between the first counting result and the second counting result is within the second reference difference, a second frequency prompt signal is output, and the second frequency prompt signal indicates that the frequency of the clock signal to be detected is stable.

[0225] The second reference difference is a preset threshold value, which can be 5, 10, etc. The preset threshold value can be determined based on the floating range of the ideal operating frequency and the second timing duration. For example, the ideal operating frequency is 24MHz, the second timing duration is 1 second (s), and the floating range of the ideal operating frequency is: floating around 24MHz by 100Hz, then the second reference difference is 100Hz*1s=100.

[0226] It should also be noted that the “first” and “second” in the second reference difference and the aforementioned first reference difference have no specific meanings, and the “first” and “second” here are only used to distinguish two different reference differences.

[0227] It can be seen that in the embodiment of the present application, the frequency of the clock signal to be detected based on the reference clock signal generated by the reference clock generating circuit can be specifically: the reference clock generating circuit is controlled to output a reference clock signal with an ideal operating frequency, the ideal operating frequency is the ideal operating frequency of the clock signal, and if the actual operating frequency of the clock signal to be detected is different from the frequency of the reference clock signal, it is determined that the frequency of the clock signal to be detected is unstable. Correspondingly, if the actual operating frequency of the clock signal to be detected is the same as the frequency of the reference clock signal, it is determined that the frequency of the clock signal to be detected is stable.

[0228] Whether the actual operating frequency of the clock signal to be detected is the same as the frequency of the reference clock signal can be determined by the two counting results in step 1203. If the difference between the two counting results exceeds the second reference difference, it indicates that the actual operating frequency of the clock signal to be detected is different from the frequency of the reference clock signal. If the difference between the two counting results does not exceed the second reference difference, it indicates that the actual operating frequency of the clock signal to be detected is the same as the frequency of the reference clock signal.

[0229] In addition, when the processor outputs the first frequency prompt signal, the chip system may also send out an alarm signal to prompt that the frequency of the current clock signal to be detected is unstable.

[0230] In a possible implementation, the first frequency prompt signal can be 1, and the second frequency prompt signal can be 0. In this scenario, when the two counting results are not much different, indicating that the second counting result is within the theoretical value range, the processor outputs the second frequency prompt signal "0", indicating that the frequency of the clock signal to be detected is within a reasonable range at this time, and the chip system does not alarm. When the two counting results differ greatly, indicating that the second counting result exceeds the theoretical value range, the processor outputs the first frequency prompt signal "1", and the chip system sends an alarm signal.

[0231] Fig.13 1 is a complete flow chart of training and detecting clock frequency provided by an embodiment of the present application. Fig.13 As shown, the processor on the chip first trains the reference clock generation circuit. During the training, the processor uses the pulse signal that meets the ideal operating frequency as a reference object to train the reference clock generation circuit. During each training, a counter is used to count the difference between the number of pulses in the output signal of the reference clock generation circuit and the number of pulses in the aforementioned pulse signal to determine whether the training purpose has been achieved. The training purpose is to allow the reference clock generation circuit to also generate a reference clock signal that meets the ideal operating frequency, and the configuration information of the control signal corresponding to each delay circuit in the reference clock generation circuit at this time is written into the chip as the first target circuit configuration information.

[0232] The subsequent processor can detect the frequency of the clock signal to be detected based on the first target circuit configuration information. Specifically, during the detection, the processor configures the control signals of each delay circuit in the reference clock generation circuit according to the first target circuit configuration information, and then uses the output signal of the reference clock generation circuit as a reference object to count the clock signal to be detected. By comparing the two counting results, it can be determined whether the frequency of the clock signal to be detected is stable, and then a frequency prompt signal is output based on the determination result. Fig.13 The specific implementation of the process shown can refer to the above-mentioned embodiment, which will not be repeated here.

[0233] also, Fig.13 The processor in the embodiment may be configured with a state machine control circuit. In specific applications, the state machine control circuit is used to complete the Fig.13 The training and testing process.

[0234] In summary, in the embodiment of the present application, a reference clock generation circuit can be expanded on the chip in advance, and then the reference clock generation circuit can be trained (trim) based on the ideal operating frequency to obtain the first target circuit configuration information of the reference clock generation circuit. In this way, the clock signal on the same chip can be detected based on the first target circuit configuration information, thereby avoiding the need to derive a standard reference clock through an analog circuit when detecting the clock signal on the chip, thereby saving chip resources.

[0235] Fig.14 1 is another flow chart of a clock detection method provided in an embodiment of the present application. The method is used to detect a glitch signal in a clock signal on a chip. Similarly, for the convenience of subsequent description, the clock signal of the chip to be detected is referred to as a clock signal to be detected. Figure 1 As can be seen from the chip shown, the method provided in the embodiment of the present application is applied to the processor of the chip. Fig.14 As shown, the method includes the following steps.

[0236] Step 1401: The processor controls the clock signal to be detected to be input into the glitch detection circuit.

[0237] The burr detection circuit can be specifically Figure 6 At this time, inputting the clock signal to be detected into the glitch detection circuit in step 1401 specifically refers to: inputting the clock signal to be detected into the input end of the first delay circuit of the N delay circuits connected in series and the second input end of each AND gate.

[0238] In other words, the clock signal is input into the first flip-flop to obtain the first output signal, and the first flip-flop is one of the N+1 flip-flops. Figure 6 In the glitch detection circuit shown in the figure, the first trigger is a trigger that is not connected to an AND gate. The clock signal is input into the X+1th trigger after passing through X cascaded delay circuits to obtain the X+1th output signal. Wherein, X is each positive integer from 1 to N in turn, and the X+1th trigger is a trigger among the N+1 triggers except the first trigger. Specifically, for Figure 6 In the glitch detection circuit shown, the X+1th trigger is a trigger connected to N AND gates respectively.

[0239] Step 1402: The processor obtains the output signal of a target trigger among N triggers connected to an AND gate among N+1 triggers in the glitch detection circuit, and the output signal of a first trigger among N+1 triggers.

[0240] The method for determining the target trigger has been explained in the aforementioned glitch detection circuit and will not be repeated here.

[0241] Step 1403: If the output signal of the target trigger and the output signal of the first trigger have different output signals in the same clock cycle, it is determined that a glitch signal exists in the clock signal to be detected.

[0242] Accordingly, if the output signal of the target trigger and the output signal of the first trigger output the same signal in the same clock cycle, it is determined that there is no glitch signal in the clock signal to be detected.

[0243] The above judgment determines whether the output signal of the target trigger and the output signals of the triggers other than the N triggers are the same in the same clock cycle. The specific implementation method can refer to Figure 6 The working principle of the glitch detection circuit shown will not be described in detail here.

[0244] Fig.15 1 is a flow chart of a clock detection method provided in an embodiment of the present application. The method is used to detect the duty cycle of the clock signal on the chip. Similarly, for the convenience of subsequent description, the clock signal of the chip to be detected is referred to as the clock signal to be detected. Figure 1 As can be seen from the chip shown, the method provided in the embodiment of the present application is applied to the processor of the chip. Fig.15 As shown, the method includes the following steps.

[0245] Step 1501: The processor controls the clock signal to be detected to be input into the duty cycle detection circuit.

[0246] against Fig. 9 The duty cycle detection circuit shown in FIG. 1 specifically refers to: inputting the clock signal to be detected into the duty cycle detection circuit. Fig. 9 The divider and the input of the inverter are shown.

[0247] Step 1502: The processor obtains output signals from the output terminals of M+1 triggers in the duty cycle detection circuit.

[0248] As mentioned above Fig. 9 From the working principle of the duty cycle detection circuit shown, it can be seen that each trigger captures either 0 or 1. In other words, the output signal of each XOR gate is either low level or high level.

[0249] Step 1503: If the output signals at the output terminals of the M+1 triggers contain both low levels and high levels, a first duty cycle prompt signal is output, where the first duty cycle prompt signal is used to indicate that the duty cycle of the clock signal to be detected is within the allowable duty cycle range.

[0250] Step 1504: If the output signals of the output terminals of the M+1 triggers are all low levels, a second duty cycle prompt signal is output, and the second duty cycle prompt signal indicates that the duty cycle of the output signal of the clock to be detected is not within the duty cycle range, and the proportion of the signal at a high level in the clock signal to be detected exceeds the allowable range of the duty cycle.

[0251] Step 1505: If the output signals of the output terminals of the M+1 triggers are all high level, a third duty cycle prompt signal is output, and the third duty cycle prompt signal indicates that the duty cycle of the clock signal to be detected is not within the duty cycle range, and the proportion of the signal at the low level in the clock output signal to be detected exceeds the allowable range of the duty cycle.

[0252] In addition, in step 1504 and step 1505, the processor may only output the same duty cycle prompt signal. In this case, the duty cycle prompt signal is only used to indicate that the duty cycle of the clock signal to be detected is not within the allowable duty cycle range and has no other indication meaning.

[0253] For example, for Fig. 9 The duty cycle detection circuit shown, after training based on a 50% clock signal, if the duty cycle of the clock signal to be detected is 50%, half of the output signals of each trigger are high level and half are low level. At this time, the processor can output the first duty cycle prompt signal.

[0254] Fig.16 The present invention provides a detection result of a duty cycle detection circuit when the low level ratio is too large and a detection result of a duty cycle detection circuit when the high level ratio is too large. If the low level ratio in the detected clock signal is too large, it indicates that the duration of the low level in a cycle is too long. Fig.16 As shown, the output signals of the third delay adjustment circuits collected at the first rising edge of the output signal clk-INV of the inverter may all be low level ( Fig.16 The level marked as collected is 0), so the output signal after synchronous processing by each two-stage register A may be a completely opposite signal to the output signal after processing by the two-stage register B, so that the outputs of each XOR gate are all high levels. Fig. 9After the trigger shown collects the output signals of each XOR gate, the collected signals may all be 1. In this scenario, the processor will output a second duty cycle prompt signal, which indicates that the output signal of the clock to be detected has a large proportion of low levels.

[0255] Accordingly, if Fig.16 As shown, if the high level ratio in the detected clock signal is too large, it indicates that the duration of the low level in one cycle is too long. At this time, the output signals of each third delay adjustment circuit collected at the first rising edge of the output signal clk-INV of the inverter may all be high level ( Fig.16 The level marked as collected is 1), so the output signal after synchronous processing by each two-stage register A may be exactly the same as the output signal after synchronous processing by the two-stage register B, so that the outputs of each XOR gate are all low levels. Fig. 9 After the trigger shown collects the output signals of each XOR gate, the collected signals may all be 0. In this scenario, the processor will output a third duty cycle prompt signal, which indicates that the proportion of high level in the clock signal to be detected is relatively large.

[0256] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0257] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A chip, characterized in that: The chip includes a processor and a clock, the clock is used to generate a clock signal, and the chip also includes at least one of a reference clock generation circuit, a burr detection circuit, or a duty cycle detection circuit; The processor is configured to detect the clock signal based on at least one of the following: Detecting the frequency of the clock signal based on a reference clock signal generated by the reference clock generating circuit; or, Detecting whether the clock signal contains glitches based on the glitches detection circuit; or, detecting a duty cycle of the clock signal based on the duty cycle detection circuit; Wherein, the reference clock generating circuit comprises P cascaded delay circuits, each of the P cascaded delay circuits comprises a control terminal, the control terminal is used to input a control signal to control the corresponding delay circuit to be turned on or off, and P is a positive integer greater than 1; The first stage delay circuit of the P cascaded delay circuits comprises a first input terminal and a first output terminal; The first input end of the first-stage delay circuit is used to input an initial clock signal, and the initial clock signal is output from the first output end of the first-stage delay circuit after passing through at least one stage of the conducting delay circuit; The first output end of the first-stage delay circuit is connected to the output end of the reference clock generating circuit, and the output end of the reference clock generating circuit is used to output the reference clock signal.

2. The chip according to claim 1, characterized in that: Each of the P cascaded delay circuits includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; The second output end of the first-stage delay circuit is connected to the first input end of the second-stage delay circuit, and the second input end of the first-stage delay circuit is connected to the first output end of the second-stage delay circuit; The first input end of the last delay circuit in the P cascaded delay circuits is connected to the second output end of the previous delay circuit of the last delay circuit; the second output end of the last delay circuit is connected to the second input end of the last delay circuit; the first output end of the last delay circuit is connected to the second input end of the previous delay circuit of the last delay circuit.

3. The chip according to claim 2, characterized in that: A first input end of an intermediate delay circuit in the P cascaded delay circuits is connected to a second output end of an upper-stage delay circuit of the intermediate delay circuit; The first output end of the intermediate delay circuit is connected to the second input end of the previous delay circuit of the intermediate delay circuit; The second output end of the intermediate delay circuit is connected to the first input end of the next stage delay circuit of the intermediate delay circuit; The second input end of the intermediate delay circuit is connected to the first output end of the next stage delay circuit of the intermediate delay circuit; The intermediate delay circuit is any delay circuit among the P cascaded delay circuits except the first-stage delay circuit and the last-stage delay circuit.

4. The chip according to any one of claims 1 to 3, characterized in that: The chip stores first target circuit configuration information, wherein the first target circuit configuration information indicates configuration conditions of control signals corresponding to each delay circuit in the reference clock generation circuit; After the control signals corresponding to the delay circuits in the reference clock generating circuit are set according to the first target circuit configuration information, the frequency of the reference clock signal output by the reference clock generating circuit is the ideal operating frequency, and the ideal operating frequency is the ideal operating frequency of the clock signal.

5. The chip according to claim 4, characterized in that: The first target circuit configuration information indicates that each delay circuit corresponds to a control signal of a high level or a low level respectively; Among them, when the control signal corresponding to any delay circuit in the P cascaded delay circuits is at a high level, the path from any delay circuit to the next level delay circuit is connected, and when the control signal corresponding to any delay circuit is at a low level, the path from any delay circuit to the next level delay circuit is disconnected.

6. The chip according to claim 1, characterized in that: The reference clock generating circuit also includes a gating circuit; The first output end of the first-stage delay circuit is connected to the output end of the reference clock generating circuit through the gating circuit; The gating circuit includes a control end, the control end of the gating circuit is used to input a gating enable signal, and the gating enable signal is used to deduct one or more pulses in the clock signal output by the first output end of the first-stage delay circuit to obtain the reference clock signal.

7. The chip according to claim 1, characterized in that: The reference clock generating circuit further comprises a NAND gate, wherein the NAND gate comprises a first input terminal, a second input terminal and an output terminal; The first input terminal of the NAND gate is used to input an enable signal, and the enable signal indicates whether to turn on or off the reference clock generating circuit; The second input terminal of the NAND gate is connected to the first output terminal of the first-stage delay circuit; The output end of the NAND gate is connected to the first input end of the first-stage delay circuit.

8. The chip according to any one of claims 1 to 3 and 5 to 7, characterized in that: Any one of the P delay circuits comprises a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and any one of the first NAND gate, the second NAND gate and the third NAND gate comprises a first input terminal, a second input terminal and an output terminal; The first input terminal of the delay circuit is connected to the first input terminals of the first NAND gate and the second NAND gate; The second input terminal of the delay circuit is connected to the second input terminal of the third NAND gate; The first output terminal of the delay circuit is connected to the output terminal of the third NAND gate; The second output terminal of the delay circuit is connected to the output terminal of the first NAND gate; The control end of the delay circuit is connected to the second input end of the first NAND gate and the input end of the inverter; The output terminal of the inverter is connected to the second input terminal of the second NAND gate; The output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate.

9. The chip according to claim 1, characterized in that: The burr detection circuit includes N cascaded delay circuits, N AND gates, and N+1 triggers, each of the N AND gates includes a first input terminal, a second input terminal, and an output terminal, each of the N+1 triggers includes an input terminal, an output terminal, and a control terminal, and N is a positive integer greater than 1; The input end of the first stage delay circuit in the N cascaded delay circuits and the second input end of each AND gate in the N AND gates are used to input the clock signal; The output end of each delay circuit except the last delay circuit in the N cascaded delay circuits is connected to the input end of the next delay circuit; The output end of each of the N delay circuits is respectively connected to the first input end of an AND gate; The control end of the first flip-flop among the N+1 flip-flops is used to input the clock signal, and the control ends of the N flip-flops except the first flip-flop among the N+1 flip-flops are connected to the output ends of the N AND gates, wherein one AND gate corresponds to one flip-flop; The output terminal of each of the N+1 flip-flops is connected to the input terminal of the same flip-flop through an inverter; The output signals of the output terminals of the N+1 flip-flops are used to detect whether the clock signal contains glitches.

10. The chip according to claim 9, characterized in that: The chip stores second target circuit configuration information; The second target circuit configuration information indicates which one of the N flip-flops the target flip-flop is; The output signal of the target trigger and the output signal of the first trigger are used to detect whether the clock signal contains glitches.

11. The chip according to claim 10, characterized in that: The N delay circuits are delay circuits with the same structure, and the target trigger is determined based on a glitch detection range and a delay duration of a single delay circuit among the N delay circuits, wherein the glitch detection range indicates a pulse width of a glitch contained in the clock signal.

12. The chip according to any one of claims 9 to 11, characterized in that: Any delay circuit among the N delay circuits comprises a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and any one of the first NAND gate, the second NAND gate and the third NAND gate comprises a first input terminal, a second input terminal and an output terminal; The input end of the delay circuit is connected to the first input end of the first NAND gate and the first input end of the second NAND gate; The output end of the delay circuit is connected to the input end of the next stage delay circuit; The control end of the delay circuit is connected to the second input end of the first NAND gate and the input end of the inverter; The output terminal of the inverter is connected to the second input terminal of the second NAND gate; The output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate; The output terminal of the first NAND gate is connected to the second input terminal of the third NAND gate.

13. The chip according to claim 1, characterized in that: The duty cycle detection circuit includes a first delay adjustment circuit, a second delay adjustment circuit, and M cascaded third delay adjustment circuits, a frequency divider, a first inverter, a second inverter, a first two-stage register, and M+1 second two-stage registers, M+1 XOR gates, and M+1 flip-flops, where M is a positive integer greater than 1; Any one of the first two-stage register and the M+1 second two-stage registers includes a first input terminal, a second input terminal and an output terminal, each of the M+1 XOR gates includes a first input terminal, a second input terminal and an output terminal, each of the M+1 flip-flops includes an input terminal, an output terminal and a control terminal, and the frequency divider includes an input terminal, an output terminal and a control terminal; The control end of the frequency divider is used to input the clock signal, the input end of the frequency divider and the output end of the frequency divider are connected through the second inverter, the output end of the frequency divider is connected to the input end of the first delay adjustment circuit, the output end of the first delay adjustment circuit is connected to the input end of the second delay adjustment circuit, the output end of the second delay adjustment circuit is connected to the input end of the first stage of the M cascaded third delay adjustment circuits, and the output end of each of the other third delay adjustment circuits except the last stage of the third delay adjustment circuit in the M cascaded third delay adjustment circuits is connected to the input end of the third delay adjustment circuit of the next stage; The output end of the second delay adjustment circuit and the output end of each of the M cascaded third delay adjustment circuits are connected to the first input ends of the M+1 second two-stage registers in a one-to-one correspondence; The second input ends of the M+1 second two-stage registers are all connected to the output end of the first inverter, the input end of the first inverter is used to input the clock signal, and the output ends of the M+1 second two-stage registers are connected to the first input ends of the M+1 XOR gates in a one-to-one correspondence; The output ends of the M+1 XOR gates are connected to the input ends of the M+1 flip-flops in a one-to-one correspondence; The output end of the first inverter is also connected to the first input end of the first two-stage register, the output end of the frequency divider is connected to the second input end of the first two-stage register, and the output end of the first two-stage register is connected to the second input end of the M+1 XOR gates; The output signals at the output terminals of the M+1 flip-flops are used to detect the duty cycle of the clock signal.

14. The chip according to claim 13, characterized in that: Any third delay adjustment circuit among the M third delay adjustment circuits includes k cascaded delay circuits, each of the k cascaded delay circuits includes a control terminal, the control terminal is used to input a control signal to control the corresponding delay circuit to be turned on or off, and k is a positive integer greater than 1; The first stage delay circuit of the k cascaded delay circuits comprises a first input terminal and a first output terminal; The first input end of the first-stage delay circuit is connected to the input end of the third delay adjustment circuit; The first output end of the first-stage delay circuit is connected to the output end of the third delay adjustment circuit.

15. The chip according to claim 14, characterized in that: The chip stores third target circuit configuration information, wherein the third target circuit configuration information indicates the number of delay circuits connected in series among the k delay circuits, and the delay durations of the first delay adjustment circuit and the second delay adjustment circuit; After the first delay adjustment circuit, the second delay adjustment circuit and the third delay adjustment circuit are set according to the third target circuit configuration information, if a clock signal with a duty cycle of 50% is input to the duty cycle detection circuit, half of the output signals at the output ends of the M+1 triggers are high-level signals and half are low-level signals.

16. The chip according to claim 14, characterized in that: The k delay circuits are delay circuits with the same structure. The number of delay circuits connected in series among the k delay circuits is determined based on an allowable range of duty cycles and a delay duration of a single delay circuit among the k delay circuits. The allowable range of duty cycles indicates an allowable floating range of the duty cycle of the clock signal.

17. A clock detection method, characterized in that: The method is applied to a processor on a chip, the chip further comprising a clock, the clock being used to generate a clock signal, the chip further comprising at least one of a reference clock generation circuit, a glitch detection circuit, or a duty cycle detection circuit; The method comprises: The processor detects the clock signal based on at least one of the following: Detecting the frequency of the clock signal based on a reference clock signal generated by the reference clock generating circuit; or, Detecting whether the clock signal contains glitches based on the glitches detection circuit; or, detecting a duty cycle of the clock signal based on the duty cycle detection circuit; Wherein, detecting the frequency of the clock signal based on the reference clock signal generated by the reference clock generating circuit includes: Controlling the reference clock generating circuit to output a reference clock signal having an ideal operating frequency, wherein the ideal operating frequency is an ideal operating frequency of the clock signal; If the actual operating frequency of the clock signal is different from the frequency of the reference clock signal, determining that the frequency of the clock signal is unstable; The reference clock generating circuit includes P cascaded delay circuits, and the chip stores first target circuit configuration information, which indicates the configuration of each delay circuit in the reference clock generating circuit corresponding to the control signal; The step of controlling the reference clock generating circuit to output a reference clock signal having an ideal operating frequency includes: Based on the first target circuit configuration information, control signals corresponding to each delay circuit in the reference clock generation circuit are controlled so that the reference clock generation circuit outputs a reference clock signal having an ideal operating frequency.

18. The method according to claim 17, characterized in that The burr detection circuit includes N cascaded delay circuits and N+1 triggers; The detecting whether the clock signal contains a glitch based on the glitch detection circuit comprises: Input the clock signal into a first trigger to obtain a first output signal; the first trigger is any one of the N+1 triggers; The clock signal is input into the X+1th trigger after passing through X cascaded delay circuits to obtain the X+1th output signal; wherein X is each positive integer from 1 to N in sequence, and the X+1th trigger is a trigger among the N+1 triggers except the first trigger; Acquire an output signal of a target trigger in the burr detection circuit and the first output signal, wherein the target trigger is a trigger among the N+1 triggers except the first trigger; If the output signal of the target trigger and the first output signal have different output signals in the same clock cycle, it is determined that the clock signal contains a glitch.

19. The method according to claim 18, characterized in that The chip stores second target circuit configuration information, wherein the second target circuit configuration information indicates which of the N+1 triggers the target trigger is; The obtaining of the output signal of the target trigger in the burr detection circuit comprises: Based on the second target circuit configuration information, an output signal of the target trigger in the glitch detection circuit is obtained.

20. The method of claim 17, wherein: The duty cycle detection circuit includes a frequency divider, a first inverter and M+1 triggers; The step of detecting the duty cycle of the clock signal based on the duty cycle detection circuit comprises: Inputting the clock signal to the input terminals of the frequency divider and the first inverter; Obtaining output signals of output terminals of the M+1 triggers in the duty cycle detection circuit; If the output signals of the output terminals of the M+1 triggers include high-level signals and low-level signals, a first duty cycle prompt signal is output, wherein the first duty cycle prompt signal is used to indicate that the duty cycle of the clock signal is within an allowable duty cycle range.

21. The method of claim 20, wherein: If the output signals of the output terminals of the M+1 triggers are all high-level signals, a second duty cycle prompt signal is output, wherein the second duty cycle prompt signal indicates that the duty cycle of the clock signal is not within the allowable duty cycle range, and the proportion of low-level signals in the clock signal exceeds the allowable duty cycle range; If the output signals of the output terminals of the M+1 triggers are all low-level signals, a third duty cycle prompt signal is output, and the third duty cycle prompt signal indicates that the duty cycle of the clock signal is not within the allowable duty cycle range, and the proportion of high-level signals in the clock signal exceeds the allowable duty cycle range.

22. The method of claim 20, wherein: The method is applied to the chip according to claim 15, wherein the chip stores third target circuit configuration information, wherein the third target circuit configuration information indicates the number of delay circuits connected in series among k delay circuits included in any third delay adjustment circuit, and the delay durations of the first delay adjustment circuit and the second delay adjustment circuit; Before inputting the clock signal to the input terminals of the frequency divider and the first inverter, the method further includes: Based on the third target circuit configuration information, the duty cycle detection circuit is configured.

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