Multi-core heterogeneous communication method and vehicle

Abstract

The application discloses a multi-core heterogeneous communication method and a vehicle. The multi-core heterogeneous communication method comprises the following steps: based on target data of a target core, obtaining a partition memory area corresponding to the size of the target data from a shared memory area; obtaining a target cache area of the target data according to a next cache area indicator in the partition memory area; storing the target data into the target cache area in the partition memory area, wherein the partition memory area comprises a plurality of cache areas; notifying a subscribed thread of the target data of a storage message of the target data, wherein the subscribed thread is from the multi-core; based on the notification, the subscribed thread obtains the target data. The cross-core shared memory area is used to replace an on-chip communication network as a data interaction medium between heterogeneous cores, and the shared memory area is a first-level memory. The first-level memory is used to replace a multi-level memory, zero-copy between the multi-cores is realized, and the data communication efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of automotive control technology, and more specifically, to a multi-core heterogeneous communication method and a vehicle. Background Technology

[0002] Existing multi-core heterogeneous communication technologies employ three types of storage units: independent cache, shared memory, and shared bus. Independent cache is used for storing and accessing data within each core; shared memory is used for access between homogeneous cores; and the shared bus is used for communication between heterogeneous cores. When data is communicated between multiple cores, it needs to be swapped between these three storage units. This swapping inevitably involves a copying process, which prolongs communication time and reduces the efficiency of data communication between heterogeneous multi-core systems. Summary of the Invention

[0003] In view of the above problems, this application proposes a multi-core heterogeneous communication method and a vehicle.

[0004] In a first aspect, embodiments of this application provide a multi-core heterogeneous communication method, the method comprising: obtaining a partitioned memory region corresponding to the size of the target data from a shared memory region based on target data of a target core, the shared memory region including multiple partitioned memory regions; obtaining a target cache region of the target data according to a next cache region indicator in the partitioned memory region; storing the target data into the target cache region of the partitioned memory region, the partitioned memory region including multiple cache regions; notifying subscribed threads that have subscribed to the target data of a storage message for the target data, the subscribed threads being from the multi-core; and obtaining the target data based on the notification.

[0005] Secondly, embodiments of this application provide a vehicle, the vehicle including: a vehicle body and electronic devices, the electronic devices including a multi-core heterogeneous controller and a memory, the multi-core heterogeneous controller being used to execute the multi-core heterogeneous communication method provided in the first aspect above.

[0006] The solution provided in this application obtains a partitioned memory region corresponding to the size of the target data in the shared memory region, caches the target data through the cache area in the partitioned memory region, and sends a notification to the subscribed threads of the target data. It uses a cross-core shared memory region to replace the on-chip communication network as the data interaction medium between heterogeneous cores. Moreover, the shared memory region is a level-one memory. By using level-one memory to replace multi-level memory, zero copy between multiple cores is achieved, which improves the data communication efficiency. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 A flowchart illustrating a multi-core heterogeneous communication method provided in an embodiment of this application is shown.

[0009] Figure 2 A flowchart illustrating a multi-core heterogeneous communication method provided in another embodiment of this application is shown.

[0010] Figure 3 A detailed flowchart of step S260 in another embodiment of this application is shown.

[0011] Figure 4 A detailed flowchart of step S280 in another embodiment of this application is shown.

[0012] Figure 5 A flowchart illustrating a multi-core heterogeneous communication method provided in another embodiment of this application is shown.

[0013] Figure 6 A detailed flowchart of step S330 in another embodiment of this application is shown.

[0014] Figure 7 A schematic diagram of the inter-core shared memory space provided in an embodiment of this application is shown.

[0015] Figure 8 A schematic diagram of the structure of a vehicle including a multi-core heterogeneous controller, provided in an embodiment of this application, is shown. Detailed Implementation

[0016] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0017] To address the problems raised in the background art, the inventors have proposed a multi-core heterogeneous communication method and vehicle provided in the embodiments of this application. This method involves obtaining a partitioned memory region corresponding to the target data size within a shared memory area, caching the target data through a cache area within the partitioned memory region, and sending notifications to the subscribed threads of the target data. It uses a cross-core shared memory region to replace the on-chip communication network as the data interaction medium between heterogeneous cores. Furthermore, the shared memory region is a single-level memory, and by using single-level memory to replace multi-level memory, zero-copy between multiple cores is achieved, improving data communication efficiency.

[0018] Please see Figure 1 , Figure 1 A flowchart illustrating a multi-core heterogeneous communication method according to an embodiment of this application is shown. In a specific embodiment, the multi-core heterogeneous communication method is applied to, for example... Figure 8 The vehicle shown.

[0019] The following will address Figure 1 The process shown is described in detail. The multi-core heterogeneous communication method may specifically include the following steps:

[0020] Step S110: Based on the target data of the target core, obtain the partition memory region corresponding to the size of the target data from the shared memory region, wherein the shared memory region includes multiple partition memory regions.

[0021] The target data is the data that the publisher needs to publish; it can be sensor data or status data recorded by the program.

[0022] The shared memory area includes an index area and a data area, with the data area comprising multiple partitioned memory regions.

[0023] The index area can be an index table built from multiple partition identifiers and their corresponding offset indexes. The partition corresponding to the partition identifier can be located by using the partition identifier and the offset index.

[0024] The partitioned memory areas in the data area are mainly used for storing data, retrieving data, and counting the stored data.

[0025] For the target data size, retrieve the partition memory area corresponding to the target data size from the data area.

[0026] In some implementations, the data type corresponding to the target data is obtained. If there is no data area in the shared memory area corresponding to the target data type, a new shared memory area is requested for the storage and publication of the target data.

[0027] In other implementations, the partitioned memory region may also include multiple sub-partitioned memory regions. Data with the same publisher, the same flow direction, or the same type can be stored in the sub-partitioned memory regions of the partitioned memory region. Subscribed threads can retrieve multiple data at once, which is beneficial for efficient data interaction.

[0028] The publisher needs to perform an offset index on the sub-partition memory region, obtain the base address of the sub-partition memory region and the base address of the partition memory region, and offset the sub-partition memory region relative to the partition memory region to obtain the offset index of the sub-partition memory region relative to the partition memory region. Users can read data from the same publisher, with the same flow direction, or of the same type based on the offset index.

[0029] Optionally, the offset indexes of multiple sub-partition memory regions relative to the partition memory region can be used to generate a sub-partition memory region offset index table and stored in the partition memory region to improve indexing efficiency.

[0030] Step S120: Obtain the target cache area of ​​the target data according to the next cache area indicator in the partitioned memory area.

[0031] The next cache indicator is used to indicate the available cache. The publisher uses the next cache indicator to obtain the target cache corresponding to the target data.

[0032] Step S130: Store the target data into the target cache area in the partitioned memory area, wherein the partitioned memory area includes multiple cache areas.

[0033] The partitioned memory region includes multiple cache areas for storing data. Target data is stored in the target cache area, enabling the target cache area to save and publish the target data.

[0034] Step S140: Notify the subscribed threads that have subscribed to the target data of the storage message of the target data, wherein the subscribed threads are from the multi-core.

[0035] Multi-core processors include, but are not limited to, ARM (Advanced RISC Machine) cores, DSP (Digital Signal Processing) cores, microcontroller cores, and GPU (Graphics Processing Unit) cores. A predefined core (such as an ARM core) creates a shared memory space from main memory and divides this shared memory into an index area and a data area according to a specific format. The size of the shared memory space is less than or equal to the size of the main memory. The index area is primarily used for indexing and locating data in the data area. The data area is primarily used for storing data, facilitating data sharing.

[0036] The notification of target data storage can be sent via inter-core multicast messages or via hardware interrupts. When using hardware interrupts, a poll operation within the interrupt can be used. The poll operation identifies whether there is a new publication and requires atomic operations. The poll operation can handle multiple identical interrupts simultaneously, completing the most publication checks with the fewest interrupts, thus reducing system overhead.

[0037] Based on the target cache where the target data is stored, the current cache pointer is set to the target cache. After the target data is published, the publication information of the target data is notified to the subscribed threads through a preset notification method.

[0038] Step S150: Based on the notification, the subscribed thread obtains the target data.

[0039] When an inter-core multicast message or a hard interrupt message is received, the subscribed thread obtains the target buffer corresponding to the target data through the inter-core multicast message or hard interrupt message, and then obtains the target data through the target buffer.

[0040] In this application, the partitioned memory region can be a circular linked list data structure, which includes a shared memory lock, a data header indicator, a depth indicator, a current cache indicator, a next cache indicator, a cache descriptor, and multiple caches for storing data.

[0041] Shared memory locks are primarily used to temporarily lock a cache area to prevent multiple users from simultaneously accessing the same cache area, which could lead to data inaccuracies. Header indicators are primarily used to indicate the head node in a circular linked list. Depth indicators are primarily used to indicate the subscription depth of the cache area. Current cache area indicators are primarily used to indicate the location of the latest data cached. Next cache area indicators are primarily used to indicate the next available cache area. Cache descriptors are primarily used to store the offset index of the cache area and the timestamp corresponding to the data stored within the cache area. Cache areas are primarily used to store data that needs to be published and data already published by the publisher. The number of depth indicators is the same as the number of cache areas.

[0042] The solution provided in this application obtains a partitioned memory region corresponding to the size of the target data in the shared memory region, caches the target data through the cache area in the partitioned memory region, and sends a notification to the subscribed threads of the target data. It uses a cross-core shared memory region to replace the on-chip communication network as the data interaction medium between heterogeneous cores. Moreover, the shared memory region is a level-one memory. By using level-one memory to replace multi-level memory, zero copy between multiple cores is achieved, which improves the data communication efficiency.

[0043] Please see Figure 2 , Figure 2 This paper illustrates a flowchart of a multi-core heterogeneous communication method according to another embodiment of the present application, which specifically includes the following steps:

[0044] Step S210: Obtain the thread's preset data type.

[0045] Each thread can be configured with multiple preset data types.

[0046] Step S220: Compare the data types with the preset data types.

[0047] Step S230: If the data type is consistent with the preset data type, subscribe to the data and obtain the notification message of the data.

[0048] When the data type matches the thread's default data type, the thread subscribes to the data. When the data is generated and stored in the corresponding cache, and a storage notification message is sent, the thread receives the notification message.

[0049] Step S240: Based on the target data of the target core, obtain the partition memory region corresponding to the size of the target data from the shared memory region, wherein the shared memory region includes multiple partition memory regions.

[0050] Step S250: Obtain the target cache area of ​​the target data according to the next cache area indicator in the partitioned memory area.

[0051] For a detailed explanation of steps S240 to S250, please refer to steps S110 to S120, which will not be repeated here.

[0052] Step S260: Store the target data into the target cache area in the partitioned memory area, wherein the partitioned memory area includes multiple cache areas.

[0053] In some implementations, please refer to Figure 3 Step S260 includes steps S262 to S266, which are described in detail below:

[0054] Step S262: Start the recycling process corresponding to the cache area.

[0055] Upon receiving a notification message that no cache space is available, the publisher or multi-core heterogeneous controller initiates a reclamation process to reclaim the cache space.

[0056] Step S264: Obtain the current number of queries corresponding to the cache area.

[0057] Each cache area consists of a prefix area and a real data area. The prefix area stores the data size, the current number of reads, and the read shared memory lock. The real data area stores the actual data. The data size is the same as the data size stored in the real data area. The current number of reads refers to the number of other users who have read the data when the cache area's eviction process is initiated. The read shared memory lock is used by publishers when publishing data.

[0058] Step S266: If the current number of queries is 0, release the data in the cache area.

[0059] When the current number of views is 0, it means that no user is currently viewing the data in the cache. At this time, the data in the cache is released to obtain an empty cache, which makes it easier for the publisher to publish new data to the cache.

[0060] In some implementations, a recycling process is automatically initiated at a preset frequency. The current lookup count of the cache indicated by the header indicator is obtained, and caches containing historical data exceeding a preset value for the depth indicator and with a current lookup count of 0 are released sequentially. The preset frequency and the preset value for the depth indicator are determined by the core that created the inter-core shared memory space.

[0061] In the specific implementation process, when storing the target data into the target cache area in the partition memory area, the shared memory lock in the partition memory is also invoked to set the shared memory lock; the offset index corresponding to the target cache area is obtained and stored in the target cache area descriptor corresponding to the target cache area; and the shared memory lock is reset.

[0062] After acquiring the target cache corresponding to the target data, the shared memory lock in the partition memory area is invoked and set to prevent other publishers from using the same target cache at the same time, thus avoiding data corruption. The offset index corresponding to the target cache is obtained and stored in the target cache descriptor. Once the offset index is obtained, the next cache indicator is incremented to point to the next available cache, facilitating the indication of the cache corresponding to the next target data. At this point, the shared memory lock is reset, releasing it so that other publishers can promptly invoke the shared memory lock when publishing other data.

[0063] Step S270: Notify the subscribed threads that have subscribed to the target data of the storage message of the target data, wherein the subscribed threads are from the multi-core.

[0064] Step S280: Based on the notification, the subscribed thread obtains the target data.

[0065] For a detailed explanation of steps S270 to S280, please refer to steps S140 to S150, which will not be repeated here.

[0066] In some implementations, subscribed threads can also subscribe to historical data in the cache; see [link to relevant documentation]. Figure 4 The detailed steps, including steps S282 to S286, are described below:

[0067] Step S282: Obtain the depth indicators corresponding to all cache areas in the partitioned memory region.

[0068] The depth indicator is used to represent the historical data stored in the cache.

[0069] Step S284: Obtain the historical data of the cache corresponding to the maximum depth indicator.

[0070] After subscribing to the target data, the subscribed thread can also obtain the historical data of the cache corresponding to the maximum depth indicator.

[0071] Step S286: Increment the current lookup count corresponding to the historical data in the cache.

[0072] Once a subscribed thread subscribes to the historical data in the cache corresponding to the maximum depth indicator, the current lookup count for the historical data is incremented. The subscribed thread then completes its subscription, decrements the current lookup count, and exits the subscription process.

[0073] In the embodiments of this application, the subscribed thread can not only subscribe to the target data, but also to the historical data of the cache corresponding to the maximum depth indicator, thereby improving the utilization rate of historical data.

[0074] The current cache indicator points to the cache corresponding to the target data. Based on the current cache indicator, the target data can be found, and the latest messages for that data can be subscribed to. The current view count in the prefix section of the cache increments according to the number of current subscribers. When the subscription ends, the current view count decreases accordingly, and the subscription process exits.

[0075] In some implementations, the publisher can also set the number of readers for the target cache. This is done by locking the target cache using a shared memory lock, and then resetting the shared memory lock after the set number of readers is reached. Once the number of readers is set, other subscribed threads cannot subscribe to the target cache until they have completed their subscription and exited.

[0076] The solution provided in this application allows the publisher to cache the target data in a cache area after it is generated and then publish it for other users to view, thus achieving data sharing among multi-core heterogeneous systems. Furthermore, during the publication process, the publisher temporarily locks the cache area using shared memory, preventing data corruption caused by multiple publishers using the same cache area. Moreover, when there is no available cache area within a partitioned memory region, a cache area reclamation process is initiated, releasing and reclaiming cache areas with zero current views. This allows for cache area reuse, saving memory between inter-core shared memory spaces and improving the utilization rate of inter-core shared memory space.

[0077] Please see Figure 5 , Figure 5 A flowchart illustrating a multi-core heterogeneous communication method according to another embodiment of this application is shown:

[0078] Step S310: Create a shared memory area in memory using one of the cores in the multi-core system. The shared memory area includes an index area and a data area. The index area includes multiple partition identifiers and an offset index corresponding to each partition identifier.

[0079] Step S320: Initialize the shared memory area.

[0080] Initialization refers to setting variables to their default values. In this application, initializing the inter-core shared memory space means allocating corresponding memory space for the inter-core shared memory space.

[0081] In the specific implementation process, initializing the shared memory area includes defining the number of partitioned memory regions in the data area; defining the number of cache regions in each partitioned memory region and the size of each cache region, wherein the sum of the sizes of all cache regions in the partitioned memory regions is less than or equal to the size of the data area.

[0082] The number of partitioned memory regions can be set when creating a shared memory space, or partitioned memory regions can be created according to the user's needs.

[0083] The number and size of the cache areas are set when the partitioned memory regions are created, and can be flexibly configured according to the contents of different partitioned memory regions. The sum of the cache sizes in all partitioned memory regions is less than or equal to the size of the data region.

[0084] By setting the number and size of partitioned memory regions and caches, these regions can be used directly without needing to determine their size, thus further improving cache utilization efficiency.

[0085] Step S330: Each core maps its core memory to the shared memory area using a preset mapping method.

[0086] Shared memory can reside within one of the cores in a multi-core system, or it can be a newly allocated memory region. Each core maps its core memory to the shared memory region using its default mapping method.

[0087] In some implementations, please refer to Figure 6 Step S330 includes steps S331 to S335, which are described in detail below:

[0088] Step S331: Obtain the base address of the partitioned memory region and the base address of the data region.

[0089] Partitioned memory regions can be inter-core memory from different cores. Because the memory mapping of each core is inconsistent, the base address corresponding to each partitioned memory region is different.

[0090] Step S332: Offset the base address of the partition memory region relative to the base address of the data region to obtain the relative address of the partition memory region.

[0091] Step S333: Use the relative address as the offset index.

[0092] Offset the base address of the partition memory region relative to the base address of the data region, obtain the relative address of the partition memory region relative to the data region, and use the relative address as the offset index.

[0093] Step S334: Obtain the virtual address of each core in the shared memory area using the offset index and the base address.

[0094] Step S335: Each core maps its core memory to the shared memory region using the virtual address.

[0095] Each core can map the shared memory space between cores to its own virtual memory space through the offset index, thereby enabling memory data sharing among multiple cores.

[0096] In this application, the base address within the kernel can be obtained by adding the offset index to the virtual address.

[0097] Step S340: Based on the target data of the target core, obtain the partition memory region corresponding to the size of the target data from the shared memory region, wherein the shared memory region includes multiple partition memory regions.

[0098] Step S350: Obtain the target cache area of ​​the target data according to the next cache area indicator in the partitioned memory area.

[0099] Step S360: Store the target data into the target cache area in the partitioned memory area, wherein the partitioned memory area includes multiple cache areas.

[0100] Step S370: Notify the subscribed threads that have subscribed to the target data of the storage message of the target data, wherein the subscribed threads are from the multi-core.

[0101] Step S380: Based on the notification, the subscribed thread obtains the target data.

[0102] Steps S340 to S380 are described in the same way as steps S110 to S150, and will not be repeated here.

[0103] In the embodiments of this application, the publisher creates and initializes the inter-core shared memory space; and each core maps the inter-core shared memory space to the shared memory space so that the publisher can store data in the inter-core shared memory space, thereby realizing zero copy of data between multi-core heterogeneous systems, avoiding data switching between multiple storage units, and improving the efficiency of data interaction between multi-core heterogeneous systems.

[0104] Please see Figure 7 , Figure 7 A schematic diagram of the inter-core shared memory space applicable to the above embodiments is shown. The inter-core shared memory space includes an index area and a data area. The index area includes an index table built from the ID (Toptic ID) and offset of the partition memory area. The data area includes multiple partition memory area Topics. When there is data with the same publisher, the same flow direction, or the same type, the partition memory area Topic also includes multiple sub-partition memory areas. The sub-partition memory area is a circular linked list data structure, including a shared memory lock, a header indicator, a depth indicator, a current buffer indicator, a next buffer indicator, a buffer descriptor Ring, and multiple buffers Buffer. The buffer descriptor Ring includes a storage area desc for storing the offset index of the buffer and the timestamp corresponding to the data stored in the buffer. The storage area desc of the buffer descriptor Ring corresponds to a buffer Buffer. Each buffer Buffer includes a prefix area and a data area Data. The prefix area includes the shared memory lock, the current number of subscriptions, and the data size DataSize.

[0105] When data is received from the sensor or when the program records certain status information, the relevant processing program publisher obtains the memory space of the corresponding Topic in the inter-core shared memory. If the Topic is published for the first time, the publisher needs to apply for inter-core shared memory space for it.

[0106] The publisher retrieves an unused Toptic block from the data area, the size of which meets the publisher's defined topic size. The publisher records the offset of the Toptic's base address relative to the base address of the data area in the corresponding Topic ID entry of the Topic record table in the index area. Subsequent publishers of the same Topic will then index the Topic based on the Topic record table.

[0107] After obtaining the base address of the Topic data structure located in the data area, the publisher uses the Next_buffer instruction in the Topic data structure to acquire the next available buffer in the Ring, which serves as the storage area for the data to be published. Note that for heterogeneous core mutual exclusion, the step of acquiring Next_buffer requires acquiring a shared memory lock. After acquisition, Next_buffer is incremented and the lock is released. If the area indicated by Next_buffer coincides with the header instruction, it indicates that there is currently no available buffer, and the publisher needs to delay the publication and apply pressure to subsequent publication actions.

[0108] In a multi-publisher scenario, since the process from acquiring the Next_buffer to generating the Ring's desc requires a shared memory lock, it provides order preservation in a multi-publisher environment. However, it guarantees lock-free data publishing and supports parallel publishing by heterogeneous cores with different speeds.

[0109] After the publisher completes the data publication, it checks and updates the Current_buffer and notifies the subscribed threads of the publication via inter-core multicast messages or hard interrupt notifications.

[0110] After receiving a notification from the publisher, a subscribed thread triggers a view event. The subscribed thread increments the current view count of the prefix region; changing the view count requires acquiring a shared memory lock. The subscribed thread obtains the latest message from the Current_buffer and can additionally retrieve historical data up to a certain depth as needed. Retrieving historical data also requires setting the current view count for that historical data. After completing the subscription, the subscribed thread decrements the current view count and exits the subscription process.

[0111] When the publisher finds that there are no free desc in the current Ring, it starts the recycling process, checks the current lookup count of the buffer indicated by the header, and if the lookup count is 0, it releases the buffer and uses the buffer to publish new data.

[0112] This application employs a large shared memory area as the venue for data interaction between heterogeneous cores. Data exchange between cores occurs entirely within this memory from generation to destruction, achieving zero-copy data exchange and significantly reducing latency. The use of a circular buffer enables asynchronous sharing of publish and subscribe, ensuring no contention for shared memory usage by heterogeneous cores at different read / write speeds. This lock-free publishing and subscribing process further reduces latency. A distributed publish / subscribe system is adopted, where each publisher publishes only one copy of the data, and all subscribed threads share the data source. Compared to end-to-end data interaction systems, this one-to-many system is more efficient. It also supports parallel data publishing by multiple publishers and lock-free publishing of the main process, further improving system data publishing efficiency. Furthermore, the decentralized publish / subscribe system avoids data interaction system failures and resets caused by master core anomalies or resets in master-slave models.

[0113] Please refer to Figure 8 The diagram illustrates a structural block diagram of a vehicle according to an embodiment of this application. The vehicle includes a vehicle body and electronic equipment.

[0114] The electronic device may be an in-vehicle terminal or other electronic device capable of running applications. The electronic device in this application may include one or more of the following components: a controller, a processor, a memory, and one or more applications, wherein the one or more applications may be stored in the memory and configured to be executed by one or more processors, and the one or more applications are configured to perform the methods described in the foregoing method embodiments.

[0115] The controller can be a CPU controller, a microprogram controller, or a multi-core heterogeneous controller. In this application, the controller is a multi-core heterogeneous controller, which is used to control multi-core heterogeneous communication.

[0116] A processor may include one or more processing cores. The processor connects various parts of the electronic device through various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in memory, and by calling data stored in memory. Optionally, the processor may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and Modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the displayed content; and the modem handles wireless communication. It is understood that the modem may also be implemented separately as a communication chip, without being integrated into the processor.

[0117] The memory may include random access memory (RAM) or read-only memory (ROM). The memory can be used to store instructions, programs, code, code sets, or instruction sets. The memory may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as touch functionality, sound playback functionality, image playback functionality, etc.), and instructions for implementing the various method embodiments described below. The data storage area may also store data created during the use of the electronic device (such as phonebook data, audio and video data, chat log data, etc.).

[0118] The publisher uses a multi-core heterogeneous controller to create and initialize an inter-core shared memory space in memory on one of the cores. Each core maps the inter-core shared memory space to its own virtual memory space, allowing the publisher to store data in the inter-core shared memory space. This achieves zero-copy data between multi-core heterogeneous systems, avoids data swapping between multiple storage units, and improves the efficiency of data interaction between multi-core heterogeneous systems.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A multi-core heterogeneous communication method, characterized by, The method comprises: creating a shared memory area in memory by one core in a plurality of cores; initializing the shared memory area; obtaining a base address of a partition memory area in the shared memory area and a base address of a data area in the shared memory area; offsetting the base address of the partition memory area relative to the base address of the data area to obtain a relative address of the partition memory area; taking the relative address as an offset index; obtaining a virtual address of each core in the shared memory area by the offset index and the base address; mapping the in-core memory to the shared memory area by the virtual address; the shared memory area comprises an index area and a data area, the index area comprises a plurality of partition identifiers and an offset index corresponding to each partition identifier; the data area comprises a plurality of partition memory areas, when there are data of the same publisher or the same flow direction or the same type, the partition memory area further comprises a plurality of sub-partition memory areas, the sub-partition memory area is a circular linked list data structure, and the sub-partition memory area comprises a shared memory lock, a data head indicator, a depth indicator, a current cache area indicator, a next cache area indicator, a cache descriptor, and a plurality of cache areas; wherein the cache descriptor comprises a storage area for storing the offset index of the cache area and a timestamp corresponding to the data stored in the cache area, the storage area of the cache descriptor corresponds to a cache area, each cache area comprises a prefix area and a data area, and the prefix area comprises a shared memory lock, a current number of inquiries, and data; based on target data of a target core, obtaining a partition memory area corresponding to the size of the target data from the shared memory area; obtaining a target cache area of the target data according to the next cache area indicator in the partition memory area; storing the target data into the target cache area in the partition memory area; starting a recycling process corresponding to the cache area; obtaining a current number of inquiries corresponding to the cache area; if the current number of inquiries is 0, releasing the data in the cache area; storing the target data into the target cache area in the partition memory area; starting a recycling process corresponding to the cache area; obtaining a current number of inquiries corresponding to the cache area; if the current number of inquiries is 0, releasing the data in the cache area; based on the notification, the subscribed thread obtains the target data; obtains the corresponding depth indicator of all cache areas in the partition memory area; obtains the historical data of the cache area corresponding to the maximum depth indicator; and increments the current number of inquiries corresponding to the historical data in the cache area.

2. The method of claim 1, wherein, Before the step of obtaining a partition memory area corresponding to the size of the target data from the shared memory area based on the target data of the target core, the method further comprises: obtaining a preset data type of a thread; comparing the data type of the data with the preset data type; if the data type is consistent with the preset data type, subscribing to the data and obtaining a notification message of the data.

3. The method of claim 1, wherein, The shared memory lock is set. ​ Obtaining an offset index corresponding to the target cache area, and storing the offset index in a target cache area descriptor corresponding to the target cache area; Resetting the shared memory lock; Storing the target data into the target cache area.

4. The method of claim 1, wherein, The initialization of the shared memory area comprises: Defining a quantity of partition memory areas in the data area; Defining a quantity of cache areas corresponding to each of the partition memory areas and a size of each of the cache areas, and a sum of sizes of all the cache areas in the partition memory areas is less than or equal to a size of the data area.

5. A vehicle characterized by comprising: Comprise: A vehicle body and an electronic device, the electronic device comprising a multi-core heterogeneous controller and a memory, the multi-core heterogeneous controller being configured to perform the method according to any one of claims 1-4.

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