Thin film transistor and display device including the same

Abstract

A thin film transistor and a display device including the same are provided. The thin film transistor includes first and second gates overlapping each other and being spaced apart from each other in a thickness direction of the thin film transistor, and an active layer disposed between the first and second gates, the active layer including a first active layer and a second active layer, wherein the active layer includes a channel portion, a first connection portion contacting one side of the channel portion, and a second connection portion contacting the other side of the channel portion, the channel portion includes first and second channel portions disposed side by side in a plan view, each of the first and second channel portions extends from the first connection portion to the second connection portion, the first channel portion overlaps the first and second gates, the second channel portion overlaps the second gate, the second active layer is disposed in the first and second channel portions, the first active layer is made of a material having a mobility lower than that of the second active layer, and is not disposed in at least a portion of the second channel portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0152695, filed on November 9, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] One embodiment of the present invention relates to a thin-film transistor and a display device including the thin-film transistor, and more specifically, to a thin-film transistor having a stacked structure and a selective dual-gate structure of some active layers and a display device including the thin-film transistor. Background Technology

[0004] Because thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching devices in display devices such as liquid crystal displays or organic light-emitting devices.

[0005] Based on the material constituting the active layer, thin-film transistors can be classified into amorphous silicon thin-film transistors that use amorphous silicon as the active layer, polycrystalline silicon thin-film transistors that use polycrystalline silicon as the active layer, and oxide semiconductor thin-film transistors that use oxide semiconductors as the active layer.

[0006] Among thin-film transistors (TFTs), oxide semiconductor TFTs offer the advantage of readily obtainable desired characteristics due to their high carrier mobility and large resistance variation depending on oxygen content. Furthermore, the manufacturing cost of oxide semiconductor TFTs is reduced because the oxide constituting the active layer is grown at relatively low temperatures during the fabrication process. Given the properties of oxides, their transparency facilitates the realization of transparent display devices.

[0007] Display devices may include switching thin-film transistors (TFTs) and driving TFTs. Generally, it is advantageous for switching TFTs to have a smaller subthreshold swing (S-factor) to improve current on-off characteristics when used as switches; and it is advantageous for driving TFTs to have a larger S-factor to present a gradual transition between low and high currents (sometimes referred to as "grayscale"). However, because TFTs typically have a smaller S-factor to improve on-off characteristics, it is difficult to represent grayscale when these TFTs are used as driving TFTs in display devices.

[0008] The S-factor is determined by the gate voltage V. GS Drain-source current I is greater than 0V and less than the threshold voltage Vth.DS Relative to gate voltage V GS The inverse of the slope of the curve. The S-factor represents the value when V GS I when changing DS Rate of change. The increase in the S factor indicates that when V GS I when changing DS The rate of decrease in change (rate of gradual change). Similarly, the decreasing S-factor represents the rate of decrease in change when V... GS I when changing DS The rate of increase of change.

[0009] Therefore, thin-film transistors with large S-factors are needed as driving thin-film transistors for display devices to easily reproduce grayscale levels. In addition to having a large S-factor, increasing the drain-source current in the on-state is also important. Summary of the Invention

[0010] The present invention was made in view of the above-mentioned problems. One object of the present invention is to provide a thin-film transistor having a large S-factor and excellent current characteristics in the on-state. More specifically, one embodiment of the present invention is to provide a thin-film transistor having a large S-factor during the threshold voltage period and a large current value in the on-state.

[0011] In particular, by providing thin-film transistors with dual-gate and dual-active-layer structures as required, a large S-factor is achieved, and a high current is also achieved in the on-state. Therefore, thin-film transistors exhibit excellent grayscale performance and are also very suitable as driving transistors.

[0012] In addition to the objectives of the invention as described above, those skilled in the art will clearly understand additional objectives and features of the invention from the following description.

[0013] According to one aspect of the invention, the above and other objectives can be achieved by providing a thin-film transistor comprising: a first gate and a second gate that overlap and are spaced apart from each other in the thickness direction of the thin-film transistor; and an active layer disposed between the first gate and the second gate, the active layer comprising a first active layer and a second active layer, wherein the active layer comprises: a channel portion; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side of the channel portion, wherein the channel portion comprises a first channel portion and a second channel portion disposed side-by-side in a plan view, each of the first channel portion and the second channel portion extending from the first connection portion to the second connection portion, the first channel portion overlapping the first gate and the second gate, the second channel portion overlapping the second gate, a second active layer disposed in the first channel portion and the second channel portion, the first active layer being made of a material having a carrier mobility lower than that of the second active layer, and not disposed in at least a portion of the second channel portion. In an N-type thin-film transistor, the carrier mobility can be electron mobility. However, those skilled in the art will recognize that the invention is not limited to N-type thin-film transistors. Here, the channel portion can be defined as the portion of the active layer that overlaps with the second gate.

[0014] The first active layer may be disposed between the first gate and the second active layer.

[0015] The mobility of the second active layer can be higher than that of the first active layer. For example, the mobility of the second active layer can be twice that of the first active layer, or more than twice that of the first active layer.

[0016] The first active layer may include a gallium (Ga)-based oxide semiconductor material.

[0017] The first active layer may include at least one of IGZO (InGaZnO) based oxide semiconductor material (Ga concentration optionally greater than or equal to In concentration) (Ga concentration ≥ In concentration), GZO (GaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, and GZTO (GaZnSnO) based oxide semiconductor material.

[0018] The second active layer may include at least one of an IGZO (InGaZnO)-based oxide semiconductor material (where the Ga concentration is optionally less than the In concentration) (Ga concentration < In concentration), an IZO (InZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO (SiInZnO)-based oxide semiconductor material, and a ZnON (Zn oxynitride)-based oxide semiconductor material.

[0019] The first active layer may cover the entire first gate in a region overlapping with the channel portion.

[0020] The first active layer may not be provided in the second channel portion.

[0021] The surface of the second active layer facing the first gate may be completely covered by the first active layer in the channel portion.

[0022] The ratio of the width of the first channel portion to the width of the second channel portion may range from 3:7 to 7:3.

[0023] The second active layer may include: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0024] According to another aspect of the present invention, the above and other objects can be achieved by providing a display device including: a pixel driving circuit; and a display element connected to the pixel driving circuit, wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor, and the first thin film transistor is the above-mentioned thin film transistor.

[0025] The second thin film transistor may include at least one of an active layer made of the same material as that of the first active layer and an active layer made of the same material as that of the second active layer.

[0026] The second thin film transistor may include a gate provided on the same layer as the second gate and may not include a gate provided on the same layer as the first gate.

[0027] The first thin film transistor may be a driving transistor, and the second thin film transistor may be a switching transistor. Description of the Drawings

[0028] The above and other objects, features, and other advantages of the present invention will be more clearly understood from the following detailed description given with reference to the accompanying drawings. In the drawings:

[0029] Figure 1A This is a plan view illustrating a thin-film transistor according to one embodiment of the present invention;

[0030] Figure 1B It is along Figure 1A A sectional view taken by line I-I';

[0031] Figure 1C It is along Figure 1A A sectional view taken from line II-II';

[0032] Figure 1D This is a detailed view of the channel portion of a thin-film transistor according to an embodiment of the present invention;

[0033] Figure 1E This is a cross-sectional view of the channel portion of a thin-film transistor based on a comparative example;

[0034] Figure 2 This is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present invention;

[0035] Figure 3 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0036] Figure 4 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0037] Figure 5A and 5B It is a graph illustrating the threshold voltage of a thin-film transistor;

[0038] Figure 6 This is a schematic diagram illustrating a display device according to another embodiment of the present invention;

[0039] Figure 7 It is a diagram Figure 6 The circuit diagram of any pixel;

[0040] Figure 8 It is a diagram Figure 7 A planar image of pixels;

[0041] Figure 9 It is along Figure 8 A sectional view taken from line III-III';

[0042] Figure 10 This is a circuit diagram illustrating any pixel of a display device according to yet another embodiment of the present invention;

[0043] Figure 11 This is a circuit diagram illustrating any pixel of a display device according to another embodiment of the present invention. Detailed Implementation

[0044] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is defined only by the scope of the claims.

[0045] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings to describe various embodiments of the invention are merely examples, and therefore the invention is not limited to the details illustrated. Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0046] Where the terms “including,” “having,” and “contains” are used in the description in this application, other parts may be added unless “only” is used.

[0047] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0048] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "after," one or more additional parts may be placed between the two parts, unless "exactly" or "directly" is used.

[0049] This document may use spatially relative terms such as “below,” “lower,” “below,” “above,” and “upper” to readily describe the relationship of one or more elements shown in the figures to other elements. It will be understood that these terms are intended to cover different orientations of the device beyond those depicted in the figures. For example, if the device shown in the figures is reversed, a device described as being “below” or “lower” to other devices may be arranged to be “above” to other devices. Thus, the exemplary term “below or lower” may include both “below or lower” and “upper” orientations. Similarly, the exemplary term “upper” or “above” may include both “above” and “below or lower” orientations.

[0050] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless “exactly” or “directly” is used.

[0051] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0052] The term "at least one" should be understood to include any one and all combinations of one or more of the relevant listed items. For example, "at least one of the first, second and third items" means a combination of all items selected from the first, second and third items, as well as the first, second or third item.

[0053] When the thickness direction is mentioned herein, it is understood to be the direction perpendicular to the plane of the substrate on which transistors are grown / placed (e.g., base substrate 110). When a plan view is mentioned herein, it is understood to be a view taken along the thickness direction (i.e., a direction parallel to the thickness direction). When the first component is described herein as covering the second component, it is understood to mean that the first component is positioned in the plan view to cover the second component. When the first component is described herein as completely covering the second component, it is understood to mean that the first component is positioned in the plan view to completely cover the second component, such that the second component is completely obscured by the first component and cannot be seen in the plan view. When the first component is described herein as overlapping the second component, it is understood to mean that the overlap is seen in the plan view. When the first component is described herein as being on or disposed on the second component, it is understood to mean that the first and second components are stacked in the thickness direction, optionally without an intermediate layer. When the first axis is mentioned herein, it is understood to be parallel to the second component. Figure 1A The left and right directions, that is, parallel to Figure 1A The straight line drawn from the first contact hole CH1 to the second contact hole CH2. When referring to the second axis in this document, it will be understood as being parallel to... Figure 1A The vertical direction is perpendicular to the first axis. When defining length in this document, it will be understood as a distance measured parallel to the first axis. When defining width in this document, it will be understood as a distance measured parallel to the second axis.

[0054] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The various embodiments of the present invention can be implemented independently of each other, or implemented jointly in a mutually dependent relationship.

[0055] In the accompanying drawings, even when depicted in different figures, the same or similar elements are referred to by the same reference numerals.

[0056] In embodiments of the present invention, for ease of description, the source and drain are distinguished from each other. However, the source and drain can be used interchangeably. The source can be the drain, and the drain can be the source. Furthermore, the source in any embodiment of the present invention can be the drain in another embodiment of the present invention, and the drain in any embodiment of the present invention can be the source in another embodiment of the present invention.

[0057] For ease of description, in some embodiments of the present invention, the source region is separated from the source, and the drain region is separated from the drain. However, the embodiments of the present invention are not limited to this structure. For example, the source region can be the source, and the drain region can be the drain. Furthermore, the source region can be the drain, and the drain region can be the source.

[0058] Figure 1A This is a plan view illustrating a thin-film transistor according to one embodiment of the present invention; Figure 1B It is along Figure 1A A sectional view taken by line I-I'; Figure 1C It is along Figure 1A The sectional view taken from line II-II'.

[0059] Reference Figure 1A , 1B According to 1C, a thin-film transistor 100 according to one embodiment of the present invention includes: a first gate 151 and a second gate 152 that are spaced apart from and overlap each other; and an active layer 130 disposed between the first gate 151 and the second gate 152. The active layer 130 includes the first active layer 131 and the second active layer 132 (in vertical view).

[0060] Reference Figure 1B The thin-film transistor 100 is disposed on the base substrate.

[0061] Glass or plastic can be used as the base substrate 110. Transparent plastics with flexible properties, such as polyimide, can be used as the plastic. When polyimide is used as the base substrate 110, heat-resistant polyimide that can withstand high temperatures can be used, taking into account the high-temperature deposition process performed on the base substrate 110.

[0062] although Figure 1B and 1C Not shown, but a buffer layer may be disposed on the base substrate 110 (see Figure 110). Figure 3 The buffer layer protects the active layer 130. The upper surface of the base substrate 110 can be made uniform through the buffer layer.

[0063] The first gate 151 is disposed on the base substrate 110.

[0064] The first gate 151 may comprise at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first gate 151 may have a multilayer structure comprising at least two conductive layers having different physical properties from each other.

[0065] A first gate insulating layer 141 is disposed on the first gate 151. The first gate insulating layer 141 protects the active layer 130.

[0066] The first gate insulating layer 141 may comprise at least one of silicon oxide, silicon nitride, and metal-based oxide. The first gate insulating layer 141 may have a single-layer structure or a multi-layer structure. According to one embodiment of the invention, the first gate insulating layer 141 may serve as a buffer layer to block oxygen (O2) or moisture (H2O) from permeating from the base substrate. For this purpose, the first gate insulating layer 141 may be made of an oxide such as silicon oxide.

[0067] Reference Figure 1B and 1C The first gate insulating layer 141 can be disposed on the entire surface of the base substrate 110 without being patterned.

[0068] The active layer 130 is disposed on the first gate insulating layer 141.

[0069] The active layer 130 may comprise a semiconductor material. According to one embodiment of the present invention, the active layer 130 may comprise an oxide semiconductor material.

[0070] According to one embodiment of the present invention, the active layer 130 includes a channel portion 130n, a first connecting portion 130a, and a second connecting portion 130b (in plan view). The first connecting portion 130a contacts one side of the channel portion 130n and extends along a first axis from one side of the channel portion 130n; the second connecting portion 130b contacts the other side of the channel portion 130n and extends along the first axis from the other side of the channel portion 130n.

[0071] The first connection portion 130a and the second connection portion 130b can be formed by selectively conductiveizing the active layer 130. Here, conductiveizing means making a portion (i.e., a selected portion) of the active layer conductive. In practice, this can be achieved by reducing the selected portion of the active layer 130, thereby introducing oxygen vacancies into the selected portion of the active layer 130, thereby improving the conductivity of the selected portion of the active layer. Therefore, at least a portion of the first connection portion 130a and / or at least a portion of the second connection portion 130b can be conductive. Therefore, the first connection portion 130a and the second connection portion 130b can also be referred to as conductive portions. According to one embodiment of the present invention, the first connection portion 130a of the active layer 130 can be a source region and the second connection portion 130b can be a drain region, but one embodiment of the present invention is not limited thereto; the first connection portion 130a can be a drain region and the second connection portion 130b can be a source region.

[0072] According to one embodiment of the present invention, the active layer 130 includes a first active layer 131 and a second active layer 132. The second active layer 132 may be disposed on the first active layer 131, thereby at least partially overlapping the first active layer 131.

[0073] According to one embodiment of the invention, the first active layer 131 may be made of a material having a lower mobility than the second active layer 132. For example, the mobility of the second active layer 132 may be two or more times the mobility of the first active layer 131. More specifically, the mobility of the second active layer 132 may be 2 to 5 times the mobility of the first active layer 131.

[0074] The threshold voltage Vth of the thin-film transistor 100 can be shifted in the positive (+) direction through a first active layer 131 having a relatively low mobility. Furthermore, the threshold voltage Vth of the thin-film transistor 100 can be shifted in the negative (-) direction through a second active layer 132 having a relatively high mobility. The first active layer 131 is designed to be influenced by the first gate 151 (facing the first gate 151), and the second active layer 132 is designed to be influenced by the second gate 152 (facing the second gate 152). Because the first active layer 131 and the second active layer 132 overlap each other, the S-factor of the thin-film transistor 100 can be increased (see...). Figure 5A and 5B The S factor will be described later.

[0075] The first active layer 131 may be made of an oxide semiconductor material with low mobility. For example, the first active layer 131 may include a gallium (Ga)-based oxide semiconductor material. The first active layer 131 including a gallium (Ga)-based oxide semiconductor material may have a relatively low mobility and may have a stable film structure.

[0076] According to one embodiment of the present invention, the first active layer 131 may include at least one of an IGZO (InGaZnO)-based oxide semiconductor material (Ga concentration ≥ In concentration), a GZO (GaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, and a GZTO (GaZnSnO)-based oxide semiconductor material. However, one embodiment of the present invention is not limited thereto, and the first active layer 131 may be formed of other oxide semiconductor materials with lower mobility known in the art.

[0077] Among the elements constituting the oxide semiconductor, indium (In) is known as an element for improving the mobility of the semiconductor layer or the active layer. Therefore, when the first active layer 131 contains indium, based on the molar amount, the content of indium (In) may be set to be less than or equal to gallium (Ga).

[0078] The second active layer 132 may be made of an oxide semiconductor material with higher mobility. For example, the second active layer 132 may include an indium (In)-based or zinc (Zn)-based oxide semiconductor material.

[0079] According to one embodiment of the present invention, the second active layer 132 may include at least one of an IGZO (InGaZnO)-based oxide semiconductor material (Ga concentration < In concentration), an IZO (InZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, an FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO (SiInZnO)-based oxide semiconductor material, and a ZnON (Zn oxynitride)-based oxide semiconductor material.

[0080] Gallium (Ga) may reduce the mobility of the oxide semiconductor. Therefore, when the indium (In)-based oxide semiconductor constituting the second active layer 132 contains gallium (Ga), based on the number of moles, the content of indium (In) may be set to be greater than the content of gallium (Ga).

[0081] Referring to Figure 1A 、 1B and 1C, the second active layer 132 is disposed on the first active layer 131. The second active layer 132 may cover the first active layer 131. According to one embodiment of the present invention, the first active layer 131 is disposed between the first gate 151 and the second active layer 132.

[0082] According to one embodiment of the present invention, the width w21 of the second active layer 132 is greater than the width w11 of the first active layer 131. For example, the width w11 of the first active layer 131 can be 30% to 70% of the width w21 of the second active layer 132 (0.3 ≤ w11 / w21 ≤ 0.7).

[0083] Figure 1D This is a detailed view illustrating the channel portion 130n of a thin-film transistor 100 according to an embodiment of the present invention (the area of ​​the channel portion 130n is illustrated as...). Figure 1D The cross-hatched lines in the diagram. According to one embodiment of the invention, the first active layer 131 may have a width w11 and may at least cover the first gate 151 in the channel portion 130n. Specifically, see... Figure 1D The channel portion 130n is a region defined by its length Lt and width Wt. In the plan view, the width of the first active layer 131 can be defined as "w11". The width of the portion of the first gate 151 overlapping with the channel portion 130n is equal to w1, and w1 is defined here as the width w1 of the first channel portion 130n1. (Refer to...) Figure 1D The width w11 of the first active layer 131 is greater than the width w1 of the region of the first gate 151 overlapping with the channel portion 130n (w11>w1). See reference... Figure 1A and 1D The length of the first active layer 131 is greater than the length L1 of the first gate 151. Therefore, on the plane, the first active layer 131 can at least cover the first gate 151 in the region of the channel portion 130n. Therefore, the electric field generated through the first gate 151 can be blocked by the first active layer 131, so that the electric field will not affect the second active layer 132 or its effect can be minimized.

[0084] The second gate insulating layer 142 is disposed on the active layer 130. The second gate insulating layer 142 protects the channel portion 130n.

[0085] The second gate insulating layer 142 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The second gate insulating layer 142 may have a single-layer structure or a multi-layer structure.

[0086] Reference Figure 1B and 1C The second gate insulating layer 142 may have a patterned structure. In the process of patterning the second gate insulating layer 142, the active layer 130 may be selectively conductive, thereby forming the first connection portion 130a and the second connection portion 130b. However, one embodiment of the present invention is not limited to this; the second gate insulating layer 142 may be disposed on the entire surface of the base substrate 110 without being patterned (see...). Figure 2 ).

[0087] The second gate 152 is disposed on the second gate insulating layer 142. The second gate 152 overlaps with the channel portion 130n of the active layer 130.

[0088] The second gate 152 may comprise at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The second gate 152 may have a multilayer structure comprising at least two conductive layers having different physical properties from each other. The second gate 152 may be made of the same material as the first gate 151, or may be made of the same material as the first gate 151.

[0089] According to one embodiment of the present invention, the second gate insulating layer 142 can be patterned by performing an etching process using the second gate 152 as a mask. In this process, the active layer 130 can be selectively conductive to form a first connection portion 130a and a second connection portion 130b. More specifically, according to one embodiment of the present invention, the region of the active layer 130 overlapping with the second gate 152 is not conductive, thereby becoming a channel portion 130n with semiconductor characteristics; and the region of the active layer 130 not overlapping with the second gate 152 can be conductive, thereby becoming the first connection portion 130a and the second connection portion 130b.

[0090] Reference Figure 1A and 1C The first gate 151 and the second gate 152 are separated from each other in the thickness direction, and the active layer 130 is inserted therebetween and can be connected to each other through the contact hole CH3 located in the outer area of ​​the active layer 130.

[0091] According to one embodiment of the present invention, the same voltage can be applied to the first gate 151 and the second gate 152. The voltage applied to the first gate 151 and the second gate 152 is referred to as the gate voltage.

[0092] According to one embodiment of the present invention, an active layer 130 is disposed in a first gate 151 and a second gate 152, and a channel portion 130n can be defined as the portion of the active layer 130 covered by the second gate 152 in a plan view. Thus, the channel portion 130n overlaps with the second gate 152, and the region of the channel portion 130n that overlaps with the first gate 151 in addition to the second gate 152 is defined as the first channel portion 130n1. The region of the channel portion 130n that overlaps with the second gate 152 but not with the first gate 151 is defined as the second channel portion 130n2.

[0093] Reference Figure 1A The channel portion 130n may include a first channel portion 130n1 and a second channel portion 130n2 arranged side-by-side (e.g., parallel to each other). Each of the first channel portion 130n1 and the second channel portion 130n2 extends from the first connection portion 130a to the second connection portion 130b. The first channel portion 130n1 overlaps with the first gate 151 and the second gate 152. The second channel portion 130n2 overlaps with the second gate 152 but not with the first gate 151.

[0094] According to one embodiment of the present invention, a second active layer 132 is disposed above the first channel portion 130n1 and the second channel portion 130n2. The second active layer may be disposed in the first channel portion 130n1 and the second channel portion 130n2. The first active layer 131 is not disposed in at least a portion of the second channel portion 130n2.

[0095] Reference Figure 1A and 1C The first active layer 131 may cover the entire first gate 151 in the region overlapping with the channel portion 130n. More specifically, the first gate 151 may be designed to face only the first active layer 131 in the channel portion 130n. Therefore, when a voltage is applied to the first gate 151 and the second gate 152, the electric field effect generated through the first gate 151 can be applied to the first active layer 131, and the electric field effect generated through the second gate 152 can be applied to the second active layer 132.

[0096] According to one embodiment of the present invention, a first gate 151 faces a first channel portion 130n1, and a portion of the first channel portion 130n1 facing the first gate 151 may be formed by a first active layer 131. Specifically, the lower portion of the first channel portion 130n1 affected by the electric field effect generated by the first gate 151 may be formed by the first active layer 131 having lower mobility characteristics. As a result, the threshold voltage of the thin-film transistor 100 can be shifted in the positive (+) direction through the lower portion of the first channel portion 130n affected by the first gate 151.

[0097] Specifically, the channel portion 130n may include a channel portion 131n formed in the first active layer 131 and a channel portion 132n formed in the second active layer 132. According to one embodiment of the present invention, the electric field effect caused by the first gate 151 is applied only to the channel portion 131n formed in the first active layer 131, thereby the threshold voltage of the thin-film transistor 100 may be shifted in the positive (+) direction.

[0098] The second active layer 132, which has high carrier mobility, has poor interface characteristics with an insulating layer, such as the first gate insulating layer 141, especially an oxide-based insulating layer. According to one embodiment of the invention, the first gate insulating layer 141 can serve as a buffer layer to block oxygen (O2) or moisture (H2O) from permeating from the base substrate 110, and therefore can be made of an oxide such as silicon oxide. In this case, when the second active layer 132 contacts the first gate insulating layer 141, a charge trap can be generated at the interface between the second active layer 132 and the first gate insulating layer 141, thereby making the threshold voltage of the thin-film transistor 100 unstable. When an electric field effect is applied to the second active layer 132, which has high mobility characteristics, especially the lower surface of the second active layer 132 in contact with the first gate insulating layer 141, the threshold voltage of the thin-film transistor 100 may not be uniform, and its driving may be unstable.

[0099] Therefore, according to one embodiment of the present invention, in order to prevent the electric field effect generated by the first gate 151 from being applied to the lower surface of the second active layer 132, the first active layer 131 may be designed to completely cover the first gate 151 in the channel portion 130n. For this purpose, as... Figure 1A , 1C As shown in Figure 1D, the first active layer 131 may extend from the first channel portion 130n1 (defined as a portion of the channel portion 130n covering the first gate 151) to a portion of the second channel portion 130n2.

[0100] Figure 1E This is a cross-sectional view illustrating the channel portion 130n of a thin-film transistor according to a comparative example. (e.g.) Figure 1E As shown, when the first active layer 131 does not cover the entire first gate 151 in the channel portion 130n, a portion NC of the second active layer 132 faces the first gate 151. As a result, the electric field effect generated through the first gate 151 can be directly applied to the lower portion of the second active layer 132, thereby causing problems such as charge traps at the interface between the second active layer 132 and the first gate insulating layer 141. In this case, the driving stability of the thin-film transistor can be degraded.

[0101] Figure 1A , 1C The arrangement of the first active layer 131 shown in Figure 1D takes into account process tolerances, but one embodiment of the present invention is not limited thereto. When a precise process can be performed without error, the first active layer 131 may completely cover the first gate 151 in the channel portion 130n, and may be designed not to be disposed on or in the second channel portion 130n2.

[0102] Reference Figure 1A , 1B In the first gate 151, the second active layer 132 faces the first gate 152. The second active layer 132 can be designed such that its surface facing the first gate 151 can be completely covered by the first active layer 131 in the channel portion 130n. Specifically, the second active layer 132 can be designed to directly face the second gate 152 with a second gate insulating layer 142 inserted therebetween, but not to directly face the first gate 151 with a first gate insulating layer 141 inserted therebetween.

[0103] When the portion of the second active layer 132 facing the first gate 151 is completely covered by the first active layer 131 in the channel portion 130n (i.e., when the first active layer 131 is inserted between the second active layer 132 and the first gate 151), the second active layer 132 is not affected by the electric field generated by the first gate 151. As a result, threshold voltage instability of the thin-film transistor 100 can be prevented.

[0104] In the second channel portion 130n2, the second active layer 132 is affected by the electric field generated by the second gate 152 and has high mobility. In particular, the portion of the second channel portion 130n2 formed by the second active layer 132 has only high mobility characteristics, thereby shifting the threshold voltage of the thin-film transistor 100 in the negative (-) direction (see...). Figure 5A ).

[0105] As a result, according to one embodiment of the present invention, the first channel portion 130n1, which allows the threshold voltage to be offset in the positive (+) direction, and the second channel portion 130n2, which allows the threshold voltage to be offset in the negative (-) direction, are arranged parallel to each other, thereby increasing the S-factor of the thin film transistor 100.

[0106] Furthermore, when the thin-film transistor 100 is turned on, charge can be primarily deflected through the second active layer 132, which directly faces the second gate 152 and has high mobility characteristics. As a result, the current characteristics of the thin-film transistor 100 in the on-state can be improved.

[0107] According to one embodiment of the present invention, the ratio of the width w1 of the first channel portion 130n1 to the width w2 of the second channel portion 130n2 can range from 3:7 to 7:3. When the width w1 of the first channel portion 130n1 is less than 30% of the total width (w1+w2) of the channel portion 130n, the effect of shifting the threshold voltage in the positive (+) direction deteriorates, thereby having little effect on improving the S-factor of the thin-film transistor 100. On the other hand, when the width w1 of the first channel portion 130n1 exceeds 70% of the total width (w1+w2) of the channel portion 130n, the width w2 of the second channel portion 130n2 narrows, thereby deteriorating the effect of shifting the threshold voltage in the negative (-) direction. As a result, the effect on improving the S-factor of the thin-film transistor 100 is not significant.

[0108] More specifically, the ratio of the width w1 of the first channel portion 130n1 to the width w2 of the second channel portion 130n2 can range from 4:6 to 6:4, or from 4.5:5.5 to 5.5:4.5.

[0109] Reference Figure 1B and 1C An interlayer insulating layer 160 may be disposed on the second gate 152. The interlayer insulating layer 160 may be made of organic or inorganic insulating materials. The interlayer insulating layer 160 may be formed of a composite layer of organic and inorganic layers.

[0110] A thin-film transistor 100 according to one embodiment of the present invention may include a first electrode 171 and a second electrode 172 disposed on an interlayer insulating layer 160. The first electrode 171 may serve as a source, and the second electrode 172 may serve as a drain, but one embodiment of the present invention is not limited thereto. The first electrode 171 may serve as a drain, and the second source 172 may serve as a source. Furthermore, the first connection portion 130a and the second connection portion 130b may serve as a source and a drain, respectively, and the first electrode 171 and the second electrode 172 may serve as connection electrodes between components.

[0111] Reference Figure 1A and 1B Each of the first electrode 171 and the second electrode 172 can be connected to the active layer 130 via contact holes CH1 and CH2. Specifically, the first electrode 171 can contact the first connection portion 130a via contact hole CH1. The second electrode 172 can be separated from the first electrode 171, thereby contacting the second connection portion 130b via contact hole CH2.

[0112] Figure 2 This is a cross-sectional view illustrating a thin-film transistor 200 according to another embodiment of the present invention. Descriptions of already described elements will be omitted below to avoid repetition.

[0113] and Figures 1A to 1C Compared to the thin-film transistor 100, Figure 2 The thin-film transistor 200 includes an unpatterned second gate insulating layer 142. For example... Figure 2 As shown, the second gate insulating layer 142 may not be patterned.

[0114] When the second gate insulating layer 142 is not patterned, the active layer 130 can be selectively conductive by selective ion doping, selective hydrogen implantation or selective ultraviolet irradiation, thereby forming the first connection portion 130a and the second connection portion 130b.

[0115] Figure 3 This is a cross-sectional view illustrating a thin-film transistor 300 according to another embodiment of the present invention.

[0116] Reference Figure 3 A light-shielding layer 111 may be disposed on the base substrate 110. The light-shielding layer 111 may be made of a material with light-shielding properties. The light-shielding layer 111 blocks light incident from the outside to protect the active layer 130.

[0117] although Figure 3 It is not shown in the figure, but the lower buffer layer may be disposed between the base substrate 110 and the light-shielding layer.

[0118] Reference Figure 3 A buffer layer 120 may be disposed on the light-shielding layer 111. The buffer layer 120 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The buffer layer 120 includes an active layer 130. Furthermore, the upper surface of the base substrate 110 on which the light-shielding layer 111 is disposed may be made more uniform by the buffer layer 120.

[0119] Reference Figure 3 Other components of the thin-film transistor 300, including the first gate 151, may be disposed on the buffer layer 120.

[0120] Figure 4 This is a cross-sectional view illustrating a thin-film transistor 400 according to another embodiment of the present invention.

[0121] exist Figure 4 The thin-film transistor 400, compared to Figure 1B The thin-film transistor 100, the second active layer 132 may have a multilayer structure.

[0122] Reference Figure 4 The second active layer 132 may include a first oxide semiconductor layer 132a and a second oxide semiconductor layer 132b on the first oxide semiconductor layer 132a. The first oxide semiconductor layer 132a and the second oxide semiconductor layer 132b may have high mobility characteristics.

[0123] However, another embodiment of the present invention is not limited to the above examples.

[0124] The first oxide semiconductor layer 132a and the second oxide semiconductor layer 132b may comprise the same semiconductor material or different semiconductor materials. The first active layer 131 may also have a multilayer structure. For example, the first active layer 131 may have a structure in which multiple semiconductor layers made of different oxide semiconductor materials with low mobility characteristics are stacked on top of each other.

[0125] Figure 5A and 5B This is a threshold voltage curve of a thin-film transistor. Specifically, Figure 5A This is a threshold voltage curve of a thin-film transistor, which is commonly used as a switching element. Figure 5B This is a threshold voltage curve of a thin-film transistor 100 according to an embodiment of the present invention. Figure 5A and 5B In this context, au represents any unit.

[0126] The threshold voltage curve of a thin-film transistor is obtained through the gate voltage V. GS The corresponding drain-source current I DS It is represented by a curve. Figure 5A and 5B The gate voltage V is shown. GS The corresponding drain-source current I DS .exist Figure 5A and 5B The threshold voltage Vth shown represents the time period during which the gate voltage V GS The corresponding drain-source current I DS The reciprocal of the slope of the curve is the S-factor. A steep slope results in a smaller S-factor; a gentle slope results in a larger S-factor. A larger S-factor corresponds to a larger drain-source current I at the gate voltage during the threshold voltage Vth period. DS The rate of change is low.

[0127] When the S-factor increases, the drain-source current I corresponding to the gate voltage during the threshold voltage Vth period increases. DS The rate of change is lower, so it is easier to adjust the gate voltage V. GS To adjust the drain-source current I DS The amplitude. In current-driven display devices, such as organic light-emitting display devices, the drain-source current I of the driving thin-film transistor can be adjusted. DS The grayscale level of a pixel is controlled by the amplitude of the gate voltage. The drain-source current I of the driving thin-film transistor is determined by the gate voltage. DS The amplitude of the light-emitting diode (LED) is thus increased. Therefore, in an organic light-emitting display device driven by current, the gray level of the pixel becomes easier to adjust as the S-factor of the driving thin-film transistor increases.

[0128] like Figure 5A As shown in the threshold voltage curve of a thin-film transistor, which is typically used as a switching element, when the threshold voltage shifts in the positive (+) direction in the region where the voltage is greater than 0V and in the negative (-) direction in the region where the voltage is less than 0V, the gate voltage V GS The corresponding drain-source current I DS The slope of the curve can decrease during the period of the threshold voltage Vth.

[0129] In a thin-film transistor 100 according to one embodiment of the present invention, the threshold voltage can be shifted in the positive (+) direction through the first channel portion 130n1, and the threshold voltage can be shifted in the negative (-) direction through the second channel portion 130n2. As a result, the thin-film transistor 100 according to one embodiment of the present invention can have a large S-factor, such as... Figure 5B As shown.

[0130] The following describes a display device according to another embodiment of the present invention. The display device according to another embodiment of the present invention may include the thin-film transistors 100, 200, 300, and 400 described above.

[0131] Figure 6 This is a schematic diagram illustrating a display device 500 according to another embodiment of the present invention.

[0132] like Figure 6 As shown, a display device 500 according to another embodiment of the present invention includes a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0133] Gate lines GL and data lines DL are disposed in the display panel 310, and multiple pixels P are disposed in the intersection area of ​​gate lines GL and data lines DL. Images are displayed by driving the pixels P.

[0134] The controller 340 controls the gate driver 320 and the data driver 330.

[0135] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using signals provided from an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, rearranges the sampled data, and provides the rearranged digital image data (RGB) to the data driver 330.

[0136] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Additionally, control signals for controlling the shift register may be included in the gate control signal GCS.

[0137] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0138] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage and provides the data voltage to the data line DL.

[0139] Gate driver 320 may include shift register 350.

[0140] The shift register 350 sequentially provides gate pulses to the gate line GL within a frame using a start signal and a gate clock transmitted from the controller 340. In this case, a frame refers to the time period during which an image is output through the display panel 310. The gate pulses have an on-state voltage capable of turning on the switching elements (thin-film transistors) disposed in the pixel P.

[0141] In addition, shift register 350 provides a gate cutoff signal to gate line GL during other periods of a frame when no gate pulse is provided, which enables the switching element to turn off. Hereinafter, the gate pulse and gate cutoff signal will be collectively referred to as the scan signal SS or Scan.

[0142] According to one embodiment of the present invention, the gate driver 320 may be packaged on the base substrate 110. In this way, the structure in which the gate driver 320 is directly packaged on the base substrate 110 is referred to as a gate-in-panel (GIP) structure.

[0143] Figure 7 It is a diagram Figure 6 The circuit diagram of any pixel P. Figure 8 It is a diagram Figure 7 A planar image of pixel P. Figure 9 It is along Figure 8 The sectional view taken from line III-III'.

[0144] Figure 7 The circuit diagram is an equivalent circuit diagram of pixel P of a display device 500 that includes an organic light-emitting diode (OLED) as a display element 710. Pixel P includes the display element 710 and a pixel driving circuit PDC for driving the display element 710.

[0145] According to another embodiment of the present invention, the display device 500 includes a pixel driving circuit PDC and a display element 710. The pixel driving circuit PDC includes a first thin-film transistor TR1 and a second thin-film transistor TR2. Any of the aforementioned thin-film transistors 100, 200, 300, and 400 can be used as the first thin-film transistor TR1. In this case, the second thin-film transistor TR2 may include a gate disposed on the same layer as the second gate 152, but does not include a gate disposed on the same layer as the first gate 151.

[0146] According to another embodiment of the present invention, the first thin-film transistor TR1 is a driving transistor, and the second thin-film transistor TR2 is a switching transistor.

[0147] The second thin-film transistor TR2 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS provided via the gate line GL.

[0148] The data line DL provides the data voltage Vdata to the pixel drive circuit PDC, and the second thin-film transistor TR2 controls the application of the data voltage Vdata.

[0149] The driving power line PL provides a driving voltage Vdd to the display element 710, and the first thin-film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0150] When the second thin-film transistor TR2 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata provided via the data line DL is supplied to the gates G11 and G12 of the first thin-film transistor TR1, which is connected to the display element 710. The data voltage Vdata is charged into the first capacitor C1 formed between the gates G11 and G12 of the first thin-film transistor TR1 and the source S1.

[0151] The amount of current supplied to the organic light-emitting diode (OLED) 710 via the first thin-film transistor TR1 is controlled according to the data voltage Vdata, thereby controlling the gray level of the light emitted from the display element 710.

[0152] Reference Figure 8 and 9 The first thin-film transistor TR1 and the second thin-film transistor TR2 are disposed on the base substrate 110.

[0153] The base substrate 110 can be made of glass or plastic. Plastics with flexible properties, such as polyimide (PI), can be used as the base substrate 110.

[0154] Light-shielding layers 111 and 211 are disposed on substrate 110. Light-shielding layers 111 and 211 can block light incident from the outside to protect active layers A1 and A2.

[0155] A buffer layer 120 is disposed on light-shielding layers 111 and 211. The buffer layer 120 is made of insulating material and protects the active layers A1 and A2 from external moisture or oxygen.

[0156] The first gate G11 of the first thin-film transistor TR1 is disposed on the buffer layer 120. The second thin-film transistor TR2 may not include a gate disposed on the same layer as the first gate G11 of the first thin-film transistor TR1.

[0157] A gate insulating layer 141 is disposed on the first gate G11.

[0158] The active layer A1 of the first thin-film transistor TR1 and the active layer A2 of the second thin-film transistor TR2 are disposed on the first gate insulating layer 141. For example, the active layers A1 and A2 may comprise an oxide semiconductor material. The active layers A1 and A2 may be composed of an oxide semiconductor layer made of an oxide semiconductor material.

[0159] The active layer A1 of the first thin-film transistor TR1 includes a first active layer A11 and a second active layer A12. The first active layer A11 and the second active layer A12 are configured to overlap each other. The first active layer A11 may be made of a material having a lower mobility than the second active layer A12. For example, the mobility of the second active layer A12 may be two times or more than the mobility of the first active layer A11.

[0160] The first active layer A11 is made of an oxide semiconductor material with low mobility. The second active layer A12 can be made of an oxide semiconductor material with higher mobility.

[0161] The width of the second active layer A12 is greater than the width W11 of the first active layer. The first active layer A11 may have a width sufficient to cover at least the first gate G11 in the region overlapping with the second gate G12.

[0162] The active layer A2 of the second thin-film transistor TR2 may include at least one of an active layer made of the same material as the first active layer A11 of the first thin-film transistor TR1 and an active layer made of the same material as the second active layer A12 of the first thin-film transistor TR1. Figure 9 In the second thin-film transistor TR2, the active layer A2 includes both an active layer made of the same material as the first active layer A11 of the first thin-film transistor TR1 and an active layer made of the same material as the second active layer A12 of the first thin-film transistor TR1.

[0163] The second gate insulating layer 142 is disposed on the active layers A1 and A2.

[0164] The second gate G12 of the first thin-film transistor TR1 and the gate G2 of the second thin-film transistor TR2 are disposed on the second gate insulating layer 142.

[0165] Furthermore, the gate line GL may be disposed on the second gate insulating layer 142. The gate G2 of the second thin-film transistor TR2 may extend from the gate line GL, but one embodiment of the present invention is not limited thereto, and a portion of the gate line GL may be the gate G2 of the second thin-film transistor TR2.

[0166] Reference Figure 8 and 9 The first capacitor electrode C11 of the storage capacitor C1 is disposed on the second gate insulating layer 142. The first capacitor electrode C11 can be connected to the second gate G12 of the first thin-film transistor TR1. The first capacitor electrode C11 can be integrally formed with the second gate G12 of the first thin-film transistor TR1. (Refer to...) Figure 8 The first gate G11 and the second gate G12 of the first thin-film transistor TR1 can be connected via contact hole H3.

[0167] An interlayer insulating layer 160 is disposed on the second gate G12 of the first thin-film transistor TR1, the gate G2 of the second thin-film transistor TR2, the gate line GL, and the first capacitor electrode C11. The interlayer insulating layer 160 may be made of organic or inorganic insulating materials.

[0168] The source S1 and drain D1 of the first thin-film transistor TR1 are disposed on the interlayer insulating layer 160. The source S1 of the first thin-film transistor TR1 may be referred to as the first electrode 171, and the drain D1 of the first thin-film transistor TR1 may be referred to as the second electrode 172.

[0169] Furthermore, the source S2 and drain D2 of the second thin-film transistor TR2 are disposed on the interlayer insulating layer 160. The data line DL, the drive power line PL, and the second capacitor electrode C12 of the storage capacitor C1 can be disposed on the interlayer insulating layer 160.

[0170] A portion of the drive power line PL can extend to become the drain D1 of the first thin-film transistor TR1. The drain D1 of the first thin-film transistor TR1 is connected to the active layer A1 via a contact hole H1.

[0171] The source S1 of the first thin-film transistor TR1 can be connected to the active layer A1 via contact hole H2, and can be connected to the light-shielding layer 111 via another contact hole H4.

[0172] The source S1 of the first thin-film transistor TR1 and the second capacitor electrode C12 are connected to each other. The source S1 of the first thin-film transistor TR1 and the second capacitor electrode C12 can be formed as one unit.

[0173] A portion of the data line DL can be extended to become the source S2 of the second thin-film transistor TR2. The source S2 of the second thin-film transistor TR2 can be connected to the active layer A2 via the contact hole H6.

[0174] The drain D2 of the second thin-film transistor TR2 can be connected to the drain electrode D2 via contact hole H7, can be connected to the first capacitor electrode C11 via another contact hole H5, and can be connected to the light-shielding layer 211 via another contact hole H8.

[0175] A planarization layer 180 is disposed on the source S1 and drain D1 of the first thin film transistor TR1, the source S2 and drain D2 of the second thin film transistor TR2, the data line DL, the drive power line PL, and the second capacitor electrode C12.

[0176] The planarization layer 180 is made of an insulating material and planarizes the upper portions of the first thin-film transistor TR1 and the second thin-film transistor TR2, and protects the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0177] The first pixel electrode 711 of the display element 710 is disposed on the planarization layer 180. The first pixel electrode 711 is in contact with the second capacitor electrode C12 via a contact hole H9 formed in the planarization layer 180. As a result, the first pixel electrode 711 can be connected to the source S1 of the first thin-film transistor TR1.

[0178] The embankment 750 is disposed at the edge of the first pixel electrode 711. The embankment 750 defines the light-emitting area of ​​the display element 710.

[0179] An organic light-emitting layer 712 is disposed on the first electrode 711, and a second pixel electrode 713 is disposed on the organic light-emitting layer 712. Thus, the display element 710 is completed. Figure 8 and Figure 9 The display element 710 shown is an organic light-emitting diode (OLED). Therefore, the display device 500 according to another embodiment of the present invention is an organic light-emitting display device.

[0180] Figure 10 This is a circuit diagram illustrating any pixel P of a display device 600 according to another embodiment of the present invention.

[0181] Figure 10 This is an equivalent circuit diagram illustrating the pixel P of an organic light-emitting display device.

[0182] Figure 10The pixel P of the display device 600 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0183] In pixel P, signal lines DL, GL, PL, RL, and SCL are set to provide signals to the pixel driving circuit PDC.

[0184] The data voltage Vdata is provided to the data line DL, the scan signal SS is provided to the gate line GL, the driving voltage Vdd for driving the pixel is provided to the driving power line PL, the reference voltage Vref is provided to the reference line RL, and the sensing control signal SCS is provided to the sensing control line SCL.

[0185] The pixel driving circuit PDC includes, for example, a second thin-film transistor TR2 (switching transistor) connected to the gate line GL and the data line DL; a first thin-film transistor TR1 (driving transistor) for controlling the amplitude of the current output to the display element 710 according to the data voltage Vdata transmitted via the second thin-film transistor TR2; and a third thin-film transistor TR3 (reference transistor) for sensing the characteristics of the first thin-film transistor TR1.

[0186] The storage capacitor C1 is disposed between the gate of the first thin-film transistor TR1 and the display element 710.

[0187] The second thin-film transistor TR2 is turned on by the scan signal SS provided to the gate line GL to transmit the data voltage Vdata provided to the data line DL to the gate of the first thin-film transistor TR1.

[0188] The third thin-film transistor TR3 is connected to the first node n1 and the reference line RL located between the first thin-film transistor TR1 and the display element 710, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the first thin-film transistor TR1 as a driving transistor during the sensing period.

[0189] A second node n2, connected to the gate of the first thin-film transistor TR1, is connected to the second thin-film transistor TR2. A storage capacitor C1 is formed between the second node n2 and the first node n1.

[0190] When the second thin-film transistor TR2 is turned on, the data voltage Vdata supplied via the data line DL is provided to the gate of the first thin-film transistor TR1. The data voltage Vdata is then charged into the storage capacitor C1 formed between the gate and source of the first thin-film transistor TR1.

[0191] When the first thin-film transistor TR1 is turned on, current is supplied to the display element 710 via the first thin-film transistor TR1 according to the driving voltage Vdd used to drive the pixel, thereby outputting light from the display element 710.

[0192] Figure 11 This is a circuit diagram illustrating the pixels of a display device 700 according to another embodiment of the present invention.

[0193] Figure 11 The pixel P of the display device 700 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0194] The pixel drive circuit PDC includes thin-film transistors TR1, TR2, TR3, and TR4.

[0195] In pixel P, signal lines DL, EL, GL, PL, SCL, and RL are set to provide drive signals to the pixel drive circuit PDC.

[0196] and Figure 10 Compared to the pixel P, Figure 11 The pixel P further includes an emission control line EL. An emission control signal EM is provided to the emission control line EL.

[0197] In addition, with Figure 10 Compared to the pixel drive circuit PDC, Figure 11 The pixel driving circuit PDC further includes a fourth thin-film transistor TR4, which serves as a light-emitting control transistor for controlling the light-emitting timing of the first thin-film transistor TR1.

[0198] The storage capacitor C1 is disposed between the gate of the first thin-film transistor TR1 and the display element 710.

[0199] The second thin-film transistor TR2 is turned on by the scan signal SS provided to the gate line GL to transmit the data voltage Vdata provided to the data line DL to the gate of the first thin-film transistor TR1.

[0200] The third thin-film transistor TR3 is connected to the reference line RL, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the first thin-film transistor TR1, which is the driving transistor, during the sensing period.

[0201] The fourth thin-film transistor TR4 transmits a driving voltage Vdd to the first thin-film transistor TR1 according to the light emission control signal EM, or shields the driving voltage Vdd. When the fourth thin-film transistor TR4 is turned on, current is supplied to the first thin-film transistor TR1, thereby outputting light from the display element 710.

[0202] In addition to the structure described above, the pixel driving circuit PDC according to another embodiment of the present invention can be formed in various structures. For example, the pixel driving circuit PDC may include five or more thin-film transistors.

[0203] According to the present invention, the following beneficial effects can be obtained.

[0204] In a thin-film transistor according to one embodiment of the present invention, the channel portion has a selective dual active layer structure and also has a selective dual gate structure, thereby improving the S-factor of the thin-film transistor.

[0205] According to one embodiment of the present invention, since the channel portion has a high-mobility semiconductor portion and a portion in which high-mobility semiconductor and low-mobility semiconductor overlap, a negative (-) shift and a positive (+) shift of the threshold voltage can occur simultaneously in a channel portion, thereby improving the S-factor of the thin-film transistor.

[0206] In a display device according to one embodiment of the present invention, a thin-film transistor with a large S-factor and excellent on-current characteristics is used as the driving transistor, thereby achieving excellent grayscale representation capability and excellent current characteristics.

[0207] It will be apparent to those skilled in the art that the disclosure described above is not limited to the embodiments and drawings described herein; various substitutions, modifications, and variations may be made in this invention without departing from the spirit or scope thereof. Therefore, the scope of this invention is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this invention.

Claims

1. A thin-film transistor, comprising: The first gate and the second gate overlap and are separated from each other in the thickness direction of the thin-film transistor; as well as An active layer is disposed between the first gate and the second gate, the active layer comprising a first active layer and a second active layer. The active layer includes: Channel section; The first connecting portion that contacts one side of the channel portion; and The second connecting portion that contacts the other side of the channel portion, The channel portion includes a first channel portion and a second channel portion arranged side by side in the plan view. Each of the first channel portion and the second channel portion extends from the first connecting portion to the second connecting portion. The first channel overlaps with the first gate and the second gate. The second channel overlaps with the second gate. The second active layer is disposed in the first channel portion and the second channel portion. The first active layer is made of a material having a lower mobility than the second active layer, and is not disposed in at least a portion of the second channel portion.

2. The thin-film transistor of claim 1, wherein the second channel portion does not overlap with the first gate.

3. The thin-film transistor of claim 1, wherein the first active layer covers the first gate in the channel portion and extends into a portion of the second channel portion.

4. The thin-film transistor of claim 1, wherein the first active layer and the second active layer overlap and are in contact with each other.

5. The thin-film transistor of claim 1, wherein the channel portion is defined as the portion of the active layer that overlaps with the second gate.

6. The thin-film transistor of claim 1, wherein the first active layer is disposed between the first gate and the second active layer.

7. The thin-film transistor of claim 1, wherein the mobility of the second active layer is higher than that of the first active layer.

8. The thin-film transistor of claim 1, wherein the mobility of the second active layer is twice that of the first active layer.

9. The thin-film transistor of claim 1, wherein the mobility of the second active layer is more than twice the mobility of the first active layer.

10. The thin-film transistor of claim 1, wherein the first active layer comprises a gallium (Ga)-based oxide semiconductor material.

11. The thin-film transistor of claim 1, wherein the first active layer comprises at least one of IGZO (InGaZnO) based oxide semiconductor material (Ga concentration ≥ In concentration), GZO (GaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, and GZTO (GaZnSnO) based oxide semiconductor material.

12. The thin film transistor according to claim 1, wherein the second active layer includes at least one of an IGZO (InGaZnO)-based oxide semiconductor material (Ga concentration < In concentration), an IZO (InZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO (SiInZnO)-based oxide semiconductor material, and a ZnON (Zn oxynitride)-based oxide semiconductor material.

13. The thin film transistor according to claim 1, wherein the first active layer covers the entire first gate in a region overlapping with the channel portion.

14. The thin film transistor according to claim 1, wherein the first active layer is not provided in the second channel portion.

15. The thin film transistor according to claim 1, wherein a surface of the second active layer facing the first gate is completely covered by the first active layer in the channel portion.

16. The thin film transistor according to claim 1, wherein a ratio of a width of the first channel portion to a width of the second channel portion ranges from 3:7 to 7:

3.

17. The thin film transistor according to claim 1, wherein the second active layer includes: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.

18. The thin film transistor according to claim 1, wherein at least a part of the first connection portion is conductive.

19. The thin film transistor according to claim 1, wherein at least a part of the second connection portion is conductive.

20. The thin film transistor according to claim 1, wherein the thin film transistor is provided on a base substrate.

21. The thin film transistor according to claim 20, wherein the base substrate includes glass or polyimide.

22. A display device, comprising: a pixel driving circuit; and a display element connected to the pixel driving circuit, wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor, and the first thin film transistor is the thin film transistor according to any one of claims 1 to 21.

23. The display device according to claim 22, wherein the second thin film transistor includes at least one of an active layer made of the same material as that of the first active layer and an active layer made of the same material as that of the second active layer.

24. The display device according to claim 22, wherein the second thin film transistor includes a gate provided on the same layer as the second gate and does not include a gate provided on the same layer as the first gate.

25. The display device according to claim 22, wherein the first thin film transistor is a driving transistor and the second thin film transistor is a switching transistor.

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