A method and system implemented by a dual-time-plane synchronization enhancement architecture

Abstract

The present invention relates to the field of time synchronization, and particularly to a method and system implemented by a dual-time-plane synchronization enhancement architecture. It mainly includes: the time master synchronization plane in the 1588 domain tracks the upstream reference master time as the master plane time information and transmits the master plane time information to the time auxiliary synchronization plane; the time auxiliary synchronization plane in the system clock domain observes at least one reference time source to obtain the auxiliary plane time information, compares the auxiliary plane time information with the master plane time information to form clock adjustment information, transmits the clock adjustment information to the time master synchronization plane in a non-delay mode, and sends the auxiliary plane time information to the applications of this node and downstream nodes; the time master synchronization plane corrects the master plane time information according to the clock adjustment information. The present invention can provide multiple independent clock sources and improve the accuracy and stability of clock signals.

Description

Technical Field

[0001] The present invention relates to the field of time synchronization, and in particular to a method and system for implementing a dual-time-plane synchronization enhancement architecture.

Background Art

[0002] High-precision time synchronization is one of the key requirements for 5G bearers. Different synchronization accuracies need to be provided according to different technical implementations or service scenarios. The 5G synchronization requirements are mainly reflected in three aspects: basic service time synchronization requirements, collaborative service time synchronization requirements, and new service synchronization requirements. The mainstream time synchronization technology adopted in the industry is based on the IEEE 1588 protocol, and the boundary clock (abbreviated as BC) and ordinary clocks (abbreviated as OC) models are generally used to construct the system. For the synchronization network constructed by BC and OC, the clock information is transmitted downstream in a hop-by-hop tracking manner. The synchronization architecture of nodes is generally a single-time-plane synchronization architecture scheme based on physical layer frequency synchronization.

[0003] The 1588 protocol adopts a master-slave synchronization system. The synchronization architecture of nodes usually adopts a single-time-plane synchronization architecture scheme based on physical layer frequency synchronization, which has the following technical problems. 1. It is only applicable to single-time-source tracking, and the stability and reliability of time synchronization are poor; 2. It cannot perceive its own synchronization output result, and there are invalid output situations in applications, which affect downstream synchronization and synchronization applications; 3. There is a long hold time for time source or synchronization path switching, and the time performance is difficult to guarantee.

[0004] In view of this, how to overcome the defects of the existing technology and solve the defects in the existing clock synchronization system is a problem to be solved in this technical field.

Summary of the Invention

[0005] Aiming at the above defects or improvement requirements of the existing technology, the present invention solves the problem of poor stability and reliability of time synchronization with a single time tracking source.

[0006] The embodiments of the present invention adopt the following technical solutions:

[0007] In a first aspect, the present invention provides a method for implementing a dual-time-plane synchronization enhancement architecture, specifically as follows: The time master synchronization plane in the 1588 domain tracks the upstream reference master time as the master plane time information, and transmits the master plane time information to the time auxiliary synchronization plane; the time auxiliary synchronization plane in the system clock domain observes at least one reference time source to obtain the auxiliary plane time information, compares the auxiliary plane time information with the master plane time information to form clock adjustment information, transmits the clock adjustment information to the time master synchronization plane through a zero-delay mode, and sends the auxiliary plane time information to the applications of this node and downstream nodes, where the clock adjustment information includes status analysis information and / or phase adjustment information; the time master synchronization plane corrects the master plane time information according to the clock adjustment information, and transmits the corrected master plane time information to the applications of this node and downstream nodes.

[0008] Preferably, the observing the reference time source to obtain the auxiliary plane time information specifically includes: Each node in the time auxiliary synchronization plane periodically sends a synchronization time packet message to adjacent nodes, and at the same time triggers the local system domain time to generate synchronization timestamp information. When each node receives the synchronization time packet message from an adjacent node, it uses the synchronization timestamp information in the synchronization time packet as the first timestamp information, and triggers the local system domain time to generate the second timestamp information; each node sends a delay request information to the adjacent node, and at the same time triggers the local system domain clock to generate the third timestamp information. When the adjacent node receives the delay request message, it triggers the local system domain clock to generate the fourth timestamp, and returns the fourth timestamp to the sender of the delay request information through a delay response packet; obtain the difference between each group of corresponding first timestamp information and second timestamp information, and the difference between each group of corresponding third timestamp information and fourth timestamp information, and use the average value of the two groups of timestamp differences as the deviation value between the local system clock domain time and the adjacent node system clock domain time, and calibrate the auxiliary plane time information according to the deviation value.

[0009] Preferably, the time auxiliary synchronization plane in the system clock domain observing at least one reference time source to obtain the auxiliary plane time information further includes: When the hop count between the node in the time auxiliary synchronization plane and the reference time source is 0, use the deviation value between the local system clock domain time and the adjacent node system clock domain time as the auxiliary plane time information; when the hop count between the node in the time auxiliary synchronization plane and the reference time source is not 0, use the sum of the deviation value between the upstream node system clock domain time and the adjacent node system clock domain time and the deviation value between the local system clock domain time and the adjacent node system clock domain time as the auxiliary plane time information.

[0010] Preferably, the comparison of the auxiliary plane time information with the primary plane time information to form clock adjustment information specifically includes: the time source ID is carried in the time announcement information sent by each node in the time auxiliary synchronization plane to adjacent nodes; when a node has received a time announcement message carrying the same time source ID on other ports, the time announcement information carrying the same time source ID is compared in terms of hop count, and the time information in the time announcement information with the smallest hop count is selected and associated with the receiving port for use; if time announcement information with the same hop count is received on different ports, the time announcement information received on the port with a higher priority is selected and associated with the receiving port for use.

[0011] Preferably, the comparison of the auxiliary plane time information with the primary plane time information to form clock adjustment information further includes: the time auxiliary synchronization plane compares the received primary plane time information with its own time information, and obtains the deviation value between the primary plane time information and its own time information as the clock adjustment information, where the clock adjustment information includes any one or more of status analysis information, phase adjustment information, and frequency information.

[0012] Preferably, there is also a transparent clock domain. The comparison of the auxiliary plane time information with the primary plane time information to form clock adjustment information specifically includes: the transparent clock domain maintains its own transparent clock information, and the transparent time domain is associated with the physical port; the synchronization messages in the sending direction of the time primary synchronization plane and the time auxiliary synchronization plane are sent to the corresponding physical ports through the transparent time domain; the transparent time domain corrects the time information in the synchronization message according to the time stamp when the synchronization message passes through the domain entrance and the time stamp when it passes through the domain exit.

[0013] On the other hand, the present invention provides a system implemented by a dual-time-plane synchronization enhancement architecture, specifically: a time primary synchronization plane is established in the 1588 domain. The time primary synchronization plane tracks the reference primary time information through the PTP (Slave) port, transmits the time information to downstream nodes through the PTP (Master) port, and sends the primary plane time information to the time auxiliary synchronization plane through the time information channel; a time auxiliary synchronization plane is established in the system clock domain. The time auxiliary plane tracks the time information of the upstream node through the PTP port, transmits the time information to downstream nodes through the PTP port, and sends the clock adjustment information to the time primary synchronization plane through the inter-layer data channel.

[0014] Preferably, it further includes: a physical layer clock is established in the system clock domain, and the upstream reference clock frequency information is tracked through the line interface and sent to downstream nodes, the time primary synchronization plane, and the time auxiliary synchronization plane.

[0015] Preferably, it further includes a transparent clock domain. Specifically, the transparent clock domain is associated with the physical port. The domain entry and domain exit of the transparent clock domain include transparent timestamp units, so as to obtain the timestamp when the synchronization message passes through the domain entry and the timestamp when it passes through the domain exit. The synchronization messages received by the primary time synchronization plane are forwarded to the time synchronization module in the 1588 domain through the transparent clock domain. The synchronization messages received by the secondary time synchronization plane are forwarded to the time deviation calculation module in the system clock domain through the transparent clock domain. The synchronization messages in the sending direction of the primary time synchronization plane and the secondary time synchronization plane are sent to the corresponding physical ports through the transparent time domain.

[0016] Compared with the prior art, the beneficial effects of the embodiments of the present invention are as follows: By setting up a dual-time plane, a second stable and accurate independent clock source can be provided, and the primary time synchronization plane can not only be calibrated according to the upstream reference master time and the physical layer clock frequency in accordance with the 1588 protocol, but also be calibrated according to the clock adjustment information provided by the secondary time synchronization plane. It can effectively monitor the synchronization output performance of the primary time synchronization plane and serve as a backup clock source when the clock signal of the primary time synchronization plane is missing, improving the reliability of time synchronization. Using the dual-plane method can also enhance the stability of system time synchronization. During the loss or switching of the time source of the upstream reference master time used by the primary time synchronization plane, the performance correction of its time output can be maintained, improving the switching and holding performance. Using the architecture of the dual-time plane can observe multiple reference time sources simultaneously and provide multiple independent clock sources, improving the accuracy and stability of the clock signal.

Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a flowchart of a method implemented by a dual-time plane synchronization enhancement architecture provided by an embodiment of the present invention;

[0019] Figure 2 It is a flowchart of another method implemented by a dual-time plane synchronization enhancement architecture provided by an embodiment of the present invention;

[0020] Figure 3 It is a schematic diagram of a system architecture implemented by a dual-time plane synchronization enhancement architecture provided by an embodiment of the present invention;

[0021] Figure 4 It is a schematic diagram of another system architecture implemented by a dual-time plane synchronization enhancement architecture provided by an embodiment of the present invention;

[0022] Figure 5 Schematic diagram of the system architecture implemented by another dual-time-plane synchronization enhancement architecture provided by an embodiment of the present invention;

[0023] Figure 6 Schematic diagram of the data flow of the auxiliary plane synchronization calibration process implemented by a dual-time-plane synchronization enhancement architecture provided by an embodiment of the present invention;

[0024] Figure 7 Schematic diagram of the network topology used in the auxiliary plane synchronization calibration process example provided by an embodiment of the present invention.

Specific implementation manners

[0025] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0026] The present invention is an architecture of a specific functional system. Therefore, in specific embodiments, the functional logic relationships of each structural module are mainly described, and the specific software and hardware implementation manners are not limited.

[0027] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The present invention will be described in detail below with reference to the drawings and embodiments.

[0028] Embodiment 1:

[0029] When implementing BC / OC nodes in a synchronization system, the commonly used single-time synchronization plane architecture includes a time synchronization plane and a physical layer clock. The physical layer clock belonging to the system clock domain tracks the frequency information of the upstream reference primary clock (PRC for short) through the line interface and sends it downstream through the line interface, and also provides a frequency reference for the time synchronization plane. The time synchronization plane tracks the upstream reference primary time clock (PRTC for short) information through the slave port of the Precision Time Protocol (PTP) port, provides it to specific applications, and transmits time information to downstream nodes through the master port of the PTP port. In the method provided in this embodiment, the existing time synchronization plane is used as the primary time synchronization plane, the existing time synchronization calibration method is retained, and an additional time auxiliary synchronization plane is added as the second calibration time source to increase the accuracy and stability of time synchronization.

[0030] AsFigure 1 As shown in Figure 1 , the specific steps of the method implemented by the dual-time-plane synchronization enhancement architecture provided by the embodiments of the present invention are as follows.

[0031] Step 101: The time primary synchronization plane in the 1588 domain tracks the upstream reference master time as the master plane time information, and transmits the master plane time information to the time secondary synchronization plane.

[0032] In the solution provided in this embodiment, in order to retain the existing time synchronization method, the time primary synchronization plane is set in the 1588 domain. The time primary synchronization plane tracks the upstream reference master time information through the PTP port (Slave). The master clock periodically publishes PTP time synchronization and time information. The time primary synchronization plane receives the timestamp information sent by the reference master clock from the PTP (Slave) port, calculates the master-slave line time delay and the master-slave time difference based on this information, and adjusts the local time using this time difference, so that the device time maintains the same frequency and phase as the master device time. After the time primary synchronization plane is synchronized according to the reference master clock, it provides its own clock to the specific application, and transmits the time information to the downstream node through the PTP port (Master) for use as the clock of the application and the downstream node.

[0033] Compared with the prior art in which the time plane is only calibrated by the reference master clock, the time primary synchronization plane in this embodiment also accepts the synchronization calibration information of the time secondary synchronization plane. Therefore, the time information synchronized with the reference master clock needs to be transmitted to the time secondary synchronization plane through the time information channel for performance comparison and analysis.

[0034] Step 102: The time secondary synchronization plane in the system clock domain observes at least one reference time source to obtain the secondary plane time information, compares the secondary plane time information with the master plane time information to form the clock adjustment information, transmits the clock adjustment information to the time primary synchronization plane through the zero-delay mode, and sends the secondary plane time information to the application and the downstream node of this node.

[0035] In this embodiment, the time-assisted synchronization plane serves as the second clock source and needs to have high stability and synchronization accuracy. Therefore, the system domain clock can be introduced as the time-assisted synchronization plane to provide the frequency basis for time synchronization. The time-assisted synchronization plane maintains a free oscillation time using the system clock and observes the reference clock source within its domain to obtain an accurate clock signal. This time is not correlated with the time outside the system and can be used as an independent clock source. It exchanges synchronization information with upstream and downstream nodes through the PTP port, enabling the clocks of each node to remain synchronized and avoiding calibration information errors caused by clock asynchronization between different nodes. In this embodiment, to improve the accuracy of the clock and avoid the unavailability of the reference time source, multiple reference time sources are observed, and each reference time source is distinguished by a time source ID (clockID).

[0036] The time-assisted synchronization plane provides a synchronization enhancement function for the time master synchronization plane and provides clock adjustment information for the time master synchronization plane. The time-assisted synchronization plane compares the received master plane time information with its own time information to obtain the deviation value between the master plane time information and its own time information as the clock adjustment information. Among them, the clock adjustment information includes any one or more of status analysis information, phase adjustment information, and frequency information. The clock adjustment information is transmitted to the time master synchronization plane through the inter-layer data channel to correct its synchronization status and results.

[0037] In the specific implementation process, the auxiliary plane time information of the time-assisted synchronization plane can also be used as one of the clock data sources of the synchronization control system to provide independent time information for the applications of this node or downstream nodes. The time information transmission of the time-assisted synchronization plane is in a non-delay mode and is not affected by delays such as the tracking establishment and synchronization adjustment of the traditional best master clock (BMC) algorithm. Downstream nodes can quickly obtain time information, avoiding the impact of time delay on synchronization accuracy.

[0038] Step 103: The time master synchronization plane corrects the master plane time information according to the clock adjustment information and sends the corrected master plane time information to the applications of this node and downstream nodes.

[0039] After the time master synchronization plane receives the clock adjustment information sent by the nodes in the time auxiliary synchronization plane, it calculates the deviation value between the time master synchronization plane and the reference master clock according to the adjustment information, as well as the phase adjustment information, and synchronously calibrates and corrects its own clock. The corrected master plane time information is fully synchronized with the reference master clock, and can be sent to specific applications for use as a clock signal, and sent to downstream nodes as a clock reference value for the downstream nodes. On the other hand, in order to simplify calculations and control and save system resources, when the deviation value between the master synchronization plane and the reference master clock is less than the acceptable error range, it indicates that the time information of the time master synchronization plane is accurate and available. At this time, the time auxiliary synchronization plane does not need to send clock adjustment information to the time master synchronization plane, and the time master synchronization plane does not need to correct the time information either, and can directly send the original master plane time information to the applications of this node and downstream nodes.

[0040] After steps 101 - 103 provided in this embodiment, that is, the time master synchronization plane is double - calibrated by the upstream reference master clock and the time auxiliary synchronization plane, avoiding the deficiencies of a single time tracking source in the prior art. In actual use, the time auxiliary synchronization plane can exist as an independent clock source, and can also provide monitoring, calibration, and backup for the time signal of the time master synchronization plane. When the clock signal of the time master synchronization plane is stable and accurate, the dual - time - plane architecture can provide two independent and accurate clock source signals through the two time planes; when the clock signal of the time master synchronization plane has a deviation or error, it can be calibrated and corrected through the clock adjustment information sent by the time auxiliary plane; when the clock signal of the time master synchronization plane is missing, the time information of the time auxiliary synchronization plane can still be used to replace the time information of the time master synchronization plane to continuously provide a stable and accurate clock source without additional adjustment.

[0041] To further improve the stability and accuracy of time synchronization, in a specific implementation, the physical - layer clock of the system clock domain can also be used to provide a clock frequency reference for the time master synchronization plane and the time auxiliary synchronization plane. The physical - layer clock tracks the upstream reference master clock frequency information through the line interface and sends it downstream through the line interface. While providing a frequency reference for the time master synchronization plane and the time auxiliary synchronization plane to use, the physical - layer clock uses the upstream PRC as a reference, and the downstream master synchronization plane and auxiliary synchronization plane use the physical - layer clock as the reference frequency.

[0042] In a specific implementation scenario, since a dual time source of a primary time synchronization plane and an auxiliary time synchronization plane is used to provide clock signals, when one of the time sources can be used normally, the other time source is used for auxiliary calibration. When the primary time synchronization plane can provide clock signals normally, the data of the auxiliary time synchronization plane is mainly used for monitoring and calibration, and has a relatively small weight assigned during the synchronization process of the primary time synchronization plane, which is used to smooth small fluctuations, enhance stability, and optimize performance during the process. In some scenarios, when abnormal situations such as the loss of the clock signal of the primary time synchronization plane occur, or during the switching process, the signal of the auxiliary time synchronization plane is provided to specific applications and downstream nodes for use to ensure the clock performance during abnormalities or switching. In a specific implementation, when the signal of the auxiliary time synchronization plane is abnormal, the data will not be transmitted to the primary time synchronization plane for synchronization calibration to avoid synchronization errors caused by abnormal signals.

[0043] Furthermore, in a scenario where abnormal situations occur in the two time synchronization planes, situations such as the loss of the time source or the interruption of the synchronization path are relatively easy to identify, while the judgment of performance degradation is more difficult. During deployment, all time sources will adopt the same time reference, such as Coordinated Universal Time (UTC), and the auxiliary time synchronization plane performs abnormal analysis by simultaneously observing multiple time source references. In a multi-source deployment environment, abnormalities will cause the deviation results during multi-source observations to be discrete, so abnormal situations can be accurately discriminated, thus avoiding the impact of abnormal data on the synchronization of the primary plane. When an abnormality is identified, a synchronization failure alarm can be triggered while outputting the clock signal and sent to downstream nodes, and correct clock signals are re-established at downstream nodes to avoid tracking incorrect clock signals.

[0044] In the specific implementation process of this solution, both of the two time synchronization planes need to interact with external PTP messages through PTP ports. However, in most specific implementation scenarios, the physical ports serving as PTP ports for the two time synchronization planes are shared. Since the primary time synchronization plane and the auxiliary time synchronization plane belong to the 1588 domain and the system clock domain respectively, the timestamps triggered by packets of different planes need to correspond. If differentiated at the physical layer port, it is very difficult to implement in hardware, so a new technical solution needs to be adopted for the processing of timestamps. Two available implementation solutions are provided below.

[0045] (1) Dual time domain + Transparent Clock (TC) domain solution.

[0046] Outside the 1588 domain and the system clock domain constructed in the dual-time plane, a transparent clock domain is also constructed. The auxiliary plane time information is compared with the master plane time information to form clock adjustment information. The transparent clock domain maintains its own transparent clock information, and the time can be independent of the 1588 domain and the system clock domain, or it can come from the system clock domain.

[0047] The transparent time domain is associated with the physical port. The synchronization messages in the sending directions of the time master synchronization plane and the time auxiliary synchronization plane are sent to the corresponding physical ports through the transparent time domain. The synchronization messages of the dual-time plane need to be received and sent through the TC domain, and the synchronization messages of different time planes are distinguished by the domain number (Domain). The synchronization message (DomainN) received by the time master synchronization plane will only be forwarded to the PTP synchronization module in the 1588 domain after passing through the TC domain, while the synchronization message (DomainM) received by the time auxiliary synchronization plane will only be forwarded to the deviation processing time deviation measurement module in the system clock domain after passing through the TC domain. Through the unidirectional forwarding of the TC domain, the synchronization messages of different time planes are distinguished.

[0048] Furthermore, both the 1588 domain and the system clock domain are BC clocks, and their timestamp units are set inside the system and associated with the clocks of their respective domains. Therefore, accurate timestamp processing can be performed when receiving or sending synchronization messages. However, since the BC timestamp is generated based on the system domain time, there is a deviation between this time and the 1588 domain time of the time master synchronization plane, which also means that the timestamp used for synchronization calculation in the 1588 domain is inaccurate and needs to be corrected by a difference. In the solution provided in this embodiment, this difference can be obtained by the auxiliary synchronization plane by comparing the time messages sent by the master synchronization plane. On the other hand, both the dual-time planes only interact with the TC domain. When the synchronization event packets of the master and auxiliary planes pass through the TC domain, the delay of the synchronization event packets forwarded through the TC domain needs to be corrected. For the delay of the synchronization messages forwarded within the system in the TC domain, the transparent time domain corrects the time information in the synchronization messages according to the timestamp at the domain entrance and the timestamp at the domain exit of the synchronization messages, and then sends the corrected time packets passing through the TC domain to the outside to send a clock synchronization signal, so that the internal forwarding process will not affect the synchronization.

[0049] (2) Dual-time plane timestamp difference correction scheme.

[0050] When constructing the dual-time plane, the timestamp unit of the PTP port is bound to one of the 1588 domain and the system clock domain. In actual implementation, since the system clock domain is relatively stable and has no adjustment, the system clock domain clock is generally bound to reduce the design difficulty.

[0051] Taking the binding system clock domain as an example, the synchronization messages of the dual-time plane need to be sent and received through the system clock domain. The synchronization messages of different time planes are distinguished by the domain number (Domain). The synchronization messages received by the primary time synchronization plane (DomainN) are forwarded to the PTP synchronization module in the 1588 domain for processing, while the synchronization messages received by the secondary time synchronization plane (DomainM) are forwarded to the deviation processing time deviation measurement module in the system clock domain for processing. The synchronization messages in the sending direction of both planes are forwarded to the physical port for sending and processed by the same BC timestamp unit.

[0052] Furthermore, since the timestamps of the 1588 domain synchronization messages are inaccurate, the deviation depends on the time deviation between the 1588 domain and the system clock domain. The difference calculation method provided in the transparent transmission scheme can be referred to calculate the difference for correction. The PTP synchronization module in the 1588 domain corrects the received timestamp by adding the correction value. On the other hand, for the sending direction, the correction value is written into the correction domain of the message when the event message is sent for pre-correction, so that the time packets sent by the physical interface can carry accurate timestamp information.

[0053] The above two schemes are both feasible timestamp correction schemes. In actual implementation, either one can be selected for implementation, or it can be adjusted or extended according to specific scenario requirements. Since the timestamp processing level of Scheme (1) is more, the achieved accuracy is lower than that of Scheme (2), but the requirement for the tracking speed of the interface chip is lower. The timestamp processing level of Scheme (2) is relatively less, and the achieved accuracy is higher than that of Scheme (1), but the interface chip needs to have a faster tracking and synchronization ability.

[0054] In the dual-time plane architecture provided in this embodiment, the secondary time synchronization plane, as an independent time signal source, needs to obtain its own time signal through a system clock domain that is different from and more stable than the primary time synchronization plane, that is, obtain its own time information by observing the reference time source signal in the system clock domain. In the specific implementation process, as Figure 2 shown, the specific process of the secondary time synchronization plane observing the reference time source is as follows.

[0055] Step 201: Each node in the secondary time synchronization plane periodically sends a synchronization time packet message to adjacent nodes, and at the same time triggers the local system domain time to generate synchronization timestamp information. When each node receives the synchronization time packet message from an adjacent node, it takes the synchronization timestamp information in the synchronization time packet as the first timestamp information, and triggers the local system domain time to generate the second timestamp information.

[0056] After the time-assisted synchronization planes of adjacent nodes are connected through PTP ports, each node regularly sends synchronization message (Sync) messages. In this embodiment, the synchronization messages are exchanged bidirectionally between adjacent nodes. Each node receives the synchronization messages from adjacent nodes and sends synchronization messages to adjacent nodes. When each node sends a synchronization message, it triggers the local system domain time to generate a synchronization timestamp information t1 L , t1 L The timestamp information can be sent to adjacent nodes through synchronization messages or follow-up messages. For adjacent nodes, the synchronization timestamp information t1 L in the synchronization message is the first timestamp information t1 N . At the same time, each node also receives the synchronization message sent by the adjacent node, which triggers the generation of the second timestamp information t2 generated by the local system clock domain time L , and pairs and stores it with the first timestamp information t1 N sent by the adjacent node (t1 N , t2 L ).

[0057] Step 202: Each node sends delay request information to adjacent nodes in a directed manner, and at the same time triggers the local system domain clock to generate the third timestamp information. When the adjacent node receives the delay request message, it triggers the local system domain clock to generate the fourth timestamp, and returns the fourth timestamp to the sender of the delay request message through the delay response message

[0058] Each node regularly sends delay request (Delay-Req) messages through the PTP port, triggering the generation of the third timestamp information t3 generated by the local system domain time L . t3 L The timestamp information is retained locally. At the same time, the local node also receives the delay request message sent by the adjacent node, and generates the timestamp information t4 generated by the local system clock domain time when receiving it L , and sends t4 L to the adjacent node through the delay response message. For the adjacent node, the timestamp information t4 L in the delay response message is the fourth timestamp information t4 N . The corresponding adjacent node will also complete the same response action, sending the fourth timestamp information t4 N through the delay response message, and pairs and stores it with the locally retained timestamp information t3 L (t3 L , t4 N ).

[0059] Step 203: Obtain the difference between the first timestamp information and the second timestamp information corresponding to each group, as well as the difference between the third timestamp information and the fourth timestamp information corresponding to each group. Take the average of the two groups of timestamp differences as the deviation value between the local system clock domain time and the adjacent node system clock domain time, and calibrate the auxiliary plane time information according to the deviation value.

[0060] Using the measurement principle of PTP, a node can calculate the deviation value between the local system clock domain time and the adjacent node system clock domain time by using Formula 1.

[0061]

[0062] Through Steps 201 - 203, the time auxiliary synchronization plane can adjust its own clock according to the calculated deviation value, obtain a clock signal synchronized with the reference time source, and provide a more accurate and stable clock signal for external applications, downstream nodes, and the time master synchronization plane.

[0063] Furthermore, in the synchronization network, the reference time source device will be connected to the nodes of the auxiliary time synchronization plane through the PTP port, and the hop count information (StepsRemoved) in the announcement message sent by the reference time source is a zero value. When an adjacent node receives an announcement message with a hop count of zero, it means that the device connected to the PTP port receiving the message is the reference time source device, and this node will work in the master clock state. When the hop count between the nodes of the time auxiliary synchronization plane and the reference time source is 0, the deviation value between the local system clock domain time and the adjacent node system clock domain time is used as the auxiliary plane time information. At the same time, the node connected to the reference time source device will also send an announcement message (Announce) to the upstream and downstream nodes, and the reference time source information is carried in the announcement message. The carrying method of the reference time source information can utilize the idle field in the standard announcement message or adopt the Type - Length - Value (TLV) format.

[0064] The time deviation value of the node not connected to the reference time source device needs to be associated with the PTP port, which can be denoted as T LNoffset-nodeNum-protNum , where nodeNum is the node number and portNum is the port number. And the TLNoffset value measured by this port is also equal to the deviation value between the local system clock domain time of this node and the reference time of the reference time source device, that is, T LSoffset-clockID-nodeNum =

[0065] T LNoffset-nodeNum-protNum , where clockID is the time source ID of the clock of each node itself, nodeNum is the node number, and T LSoffset-clockID-nodeNum information will be carried through the announcement message and sent to the downstream nodes.

[0066] Due to reasons such as delay and errors in transceiver processing, the error of the reference time source information received by nodes farther from the reference time source device is greater. In steps 201 - 203, the deviation data stored by each node corresponds one by one to adjacent nodes. For nodes far from the reference time source device, the deviation value may have a greater error. When the hop count between a node in the time - assisted synchronization plane and the reference time source is not 0, the sum of the deviation value between the upstream node's system clock domain time and the adjacent node's system clock domain time, and the deviation value between the local system clock domain time and the adjacent node's system clock domain time is used as the auxiliary plane time information. For nodes not directly connected to the reference time source device, when receiving the advertisement message sent by an adjacent node, the T LSoffset-clockID-nodeNum of the upstream node can be obtained from it and is represented as T RX-LSoffset-clockID-nodeNum in this node. Adding T RX-LSoffset-clockID-nodeNum to the T LNoffset-nodeNum-protNum measured by the corresponding port can obtain the deviation value T LSoffset-clockID-nodeNum between the local system clock domain time of this node and the reference time source corresponding to the node with clockID. Specifically, formula 2 can be used for calculation.

[0067] T LSoffset-clockID-nodeNum = T RX-LSoffset-clockID-nodeNum + T LNoffset-nodeNum-protNum (Formula 2)

[0068] T LSoffset-clockID-nodeNum will also be carried by the advertisement message and sent to the downstream node. The downstream node corrects the local clock information according to the deviation value.

[0069] In the above process, due to the network topology, each node may have multiple upstream nodes or multiple downstream nodes, so it may receive multiple advertisement messages. Each node processes and forwards the received advertisement messages of the reference time source according to certain rules. The advertisement messages sent by adjacent devices received by the node through the PTP port all carry the clockID of the time source. Since the transmission of advertisement messages with different clockIDs is independent of each other, when this node does not receive an advertisement message with the same clockID on other ports, after recording the information, the hop count information of the advertisement message is incremented by 1, and the deviation value T LSoffset-clockID-nodeNum between the local system clock domain time of the node and the reference time of the reference time source device is carried and sent from the PTP port. In order to generate a synchronization loop, the received advertisement information is sent from other PTP ports except the receiving port.

[0070] Further, when a node has received a time advertisement message carrying the same time source ID on other ports, since the smaller the number of hops the synchronization link passes through, the smaller the error theoretically brought by the link, the advertisement message with the least number of hops is preferentially selected for use. Compare the number of hops of the time advertisement messages carrying the same time source ID, and associate the time information in the time advertisement message with the smallest number of hops with the receiving port for use. If time advertisement messages with the same number of hops are received on different ports, select the time advertisement message received on the port with a higher priority and associate the receiving port for use. After storing the advertisement message associated with the receiving port, increment the hop count information of the advertisement message by 1, and carry the T information of this node LSoffset-clockID-nodeNum and send it from other PTP ports except this receiving port. To avoid conflicts with the time information of the reference time source device, do not send advertisement messages to adjacent ports connected to the reference time source device. In actual implementation, the port priority is sorted according to actual scenarios such as port numbers or services associated with the ports.

[0071] In the method provided in this embodiment, since the transmission of advertisement messages with different clock IDs in the time auxiliary synchronization plane is independent of each other, no matter how many reference time source devices are deployed in the synchronization network, each node can observe the time information of all reference time source devices, and calculate the deviation between the local system clock domain time and the reference time of each reference time source device. Therefore, the deviation values between the system domain time of this node and the time of multiple time sources existing in the network can be observed simultaneously. To further improve the accuracy of synchronization calibration and avoid errors in the reference time source or transmission link, the deviation values stored in each node can be weighted averaged to obtain a reference deviation for subsequent measurements. The deviation values stored in nodes with fewer hops from the reference time source are more accurate, so the weights are greater.

[0072] The method implemented by the dual-time-plane synchronization enhancement architecture provided in this embodiment adopts a dual-time-plane synchronization framework of a time primary synchronization plane and a time auxiliary synchronization plane. The time auxiliary synchronization plane synchronizes with its own reference time source through advertisement information, provides a stable and accurate second clock signal source, and provides deviation adjustment data for the time synchronization of the time primary synchronization plane to enhance the stability of synchronization. During the loss or switching of the time source in the time primary synchronization plane, it provides time output performance correction or a backup clock signal source, without hardware tracking adjustment, removes the BMC algorithm, and can observe multiple reference time sources simultaneously. At the same time, by comparing the clocks of the time auxiliary synchronization plane and the time primary synchronization plane, the output performance monitoring and exception handling mechanism of the primary time synchronization plane can be realized.

[0073] Embodiment 2:

[0074] Based on the method implemented by the dual-time-plane synchronous enhancement architecture provided in the above-mentioned Embodiment 1, the present invention further provides a system implemented by the dual-time-plane synchronous enhancement architecture that can be used to implement the above method, as Figure 3 shown, which is a schematic diagram of the system architecture of an embodiment of the present invention.

[0075] A time master synchronization plane is established in the 1588 domain. The time master synchronization plane tracks the upstream reference master time information through the PTP (Slave) port, transmits time information to downstream nodes through the PTP (Master) port, and sends the master plane time information to the time auxiliary synchronization plane through the time information channel;

[0076] The time master synchronization plane belongs to the 1588 domain, tracks the upstream reference master time information through the PTP port (Slave), provides it to specific applications, and transmits time information to downstream nodes through the PTP port (Master). The time master synchronization plane tracks upstream nodes through the PTP port (Master), that is, tracks the time information of the PRTC, and restores the time information consistent with the PRTC locally. In specific implementation, the time information channel can be a physical signal (for example: 1PPS), or a data channel (PTP port), depending on the complexity of system implementation.

[0077] A time auxiliary synchronization plane is established in the system clock domain. The time auxiliary plane tracks the upstream node time information through the PTP port, transmits time information to downstream nodes through the PTP port, and sends clock adjustment information to the time master synchronization plane through the inter-layer data channel.

[0078] The time auxiliary synchronization plane belongs to the system clock domain, maintains a free-oscillation time using the system clock, and performs synchronous information interaction with upstream and downstream nodes through the PTP port. The time auxiliary synchronization plane provides a synchronization enhancement function for the time master synchronization plane and does not directly provide time services to external applications. The data and synchronous calculation schemes for its interaction are implemented according to the method provided in Embodiment 1. The time auxiliary plane can perform a comparison measurement on the time information transmitted by the time master plane through the time message channel to obtain the time deviation value from the time master plane, and then transmit it to the PTP synchronization module of the time master synchronization plane through the inter-layer data channel.

[0079] In the specific implementation process, the time synchronization plane can achieve time tracking solely relying on PTP. To obtain the frequency reference for the clock domain of the time acquisition system and bring higher stability and synchronization accuracy to time synchronization, the physical layer clock in the system domain clock can also be introduced as the frequency basis for time synchronization. Establish the physical layer clock in the system clock domain, track the upstream reference clock frequency information through the line interface, and send the reference clock frequency information to downstream nodes, the time master synchronization plane, and the time auxiliary synchronization plane. The physical layer clock belongs to the physical layer clock of the system clock domain and maintains tracking of the upstream reference master clock (PRC) frequency information through the line interface. In addition to sending downstream through the line interface, it also provides the frequency reference for the time master synchronization plane and the time auxiliary synchronization plane to use.

[0080] Both time synchronization planes need to interact with external PTP messages through PTP ports. To solve the problem of the physical ports of the two time synchronization planes being shared as PTP ports in some scenarios, based on the implementation solution provided in Embodiment 1, the corresponding system structure is provided in this embodiment.

[0081] (1) As Figure 4 shown, use the dual time domain + transparent clock domain scheme.

[0082] The transparent clock domain is associated with the physical port. The domain entrance and domain exit of the transparent clock domain include transparent timestamp units to facilitate obtaining the timestamp of the synchronization message passing through the domain entrance and the timestamp passing through the domain exit. The synchronization message received by the time master synchronization plane is forwarded to the time synchronization module in the 1588 domain through the transparent clock domain. The synchronization message received by the time auxiliary synchronization plane is forwarded to the time deviation calculation module in the system clock domain through the transparent clock domain. The synchronization messages in the sending direction of the time master synchronization plane and the time auxiliary synchronization plane are sent to the corresponding physical ports through the transparent time domain. The time deviation calculation module is used on the one hand to assist the synchronization plane in calculating the time deviation between the local node clock and the reference time source through timestamp information; on the other hand, it can compare and measure the deviation between the time in the 1588 domain and the time in the system clock domain.

[0083] (2) As Figure 5 shown, use the dual time plane timestamp difference correction scheme.

[0084] Establish a BC timestamp processing unit in the system clock domain. When the synchronization messages received by the time master synchronization plane and the time auxiliary synchronization plane reach the physical port, they are respectively processed by the same BC timestamp processing unit to facilitate the correction of the time deviation between the 1588 domain and the system clock domain.

[0085] The above two schemes are both feasible timestamp correction schemes. In actual implementation, either one can be selected for implementation, or it can be adjusted or extended according to the specific scenario requirements with reference to the above schemes.

[0086] The system implemented by the dual-time-plane synchronous enhancement architecture provided in this embodiment, combined with the method provided in Embodiment 1, can effectively monitor the synchronous output performance of the primary time synchronization layer and improve the reliability of time synchronization. When an output anomaly occurs, it can trigger a synchronous failure alarm and send it to downstream nodes to avoid incorrect tracking. On the other hand, during the loss or switching of the time source in the primary time synchronization layer, performance correction can be performed on its time output to improve switching and hold performance. Thirdly, it can observe multiple reference time sources simultaneously, which can improve the accuracy of synchronization and decision-making. Its observed data is also an important data source for the synchronous control system.

[0087] Embodiment 3:

[0088] Based on the method implemented by the dual-time-plane synchronous enhancement architecture provided in Embodiment 1 and the system implemented by the dual-time-plane synchronous enhancement architecture provided in Embodiment 2, in different specific application scenarios, it can also be supplemented and adjusted according to different usage requirements or actual scenarios.

[0089] As Figure 2 shown, the following briefly lists some available technical solutions. For the following technical solutions, in the absence of conflicts, one or more technical solutions can be selected and combined with the technical solutions in Embodiment 1 or Embodiment 2, or reasonably adjusted and extended.

[0090] (1) Multi-source observation. Since the time auxiliary synchronization plane can observe the time of all access reference time sources in the synchronization network, and the time of the reference time sources is all UTC time, when there are large deviations between the observed reference times, it indicates that there is an anomaly in the output of the reference time source device or there is an anomaly in the synchronization link. Combining the analysis of network-level node observation information, it is easy to determine the cause of the fault. The more reference time source devices are accessed in the synchronization network, the more accurate the analysis of the anomaly will be. If the weighted average of the observed values of multiple reference times is taken as the deviation between the auxiliary plane and UTC time, the accuracy and stability of the observation results will be further improved.

[0091] (2) Monitoring the output time performance of the primary time synchronization plane. The time auxiliary synchronization plane can use the observation results of the reference time source time to monitor the time synchronization information transmitted by the primary time synchronization plane through the time information channel. For the primary time synchronization plane, it cannot detect whether the time information sent to downstream nodes after synchronizing with upstream nodes is normal by itself. When abnormal upstream time signals are transmitted to downstream, it will greatly affect the synchronization of downstream areas. Through the monitoring of the time auxiliary synchronization plane, when a deviation greater than the threshold occurs, the primary time synchronization plane can be notified through the inter-layer data channel to stop transmitting time information to downstream and issue an alarm message.

[0092] (3) Enhanced time synchronization performance. The time auxiliary synchronization plane feeds back the deviation value between the time master synchronization plane and the observed reference time in real time through the inter-layer information channel. When the tracking is normal, the deviation value is incorporated into the deviation adjustment of the time master plane according to a certain weight, which can enhance the stability of the time output and the robustness of the synchronization system. In case of an abnormal situation, the time master synchronization plane switches the reference time source or the synchronization path. Since the BMC algorithm is a slow protocol, the 1588 domain will maintain for a long time, and the time output during the hold period is prone to drift or jump. However, due to its observation mechanism, the time auxiliary plane only needs to remove the unobservable reference time from the weighted average calculation, and the switching time is very short. When the time auxiliary plane can observe the reference time, the deviation information it transmits to the time master plane can be assigned more weight to adjust the time output to enhance the time performance during the hold period.

[0093] In a specific implementation scenario, such as Figure 6 shown, the synchronization calibration method of the time auxiliary synchronization plane is as follows.

[0094] In Figure 7 the example network topology, a total of n reference time sources, PRTC-1 to PRTC-n, and n synchronization nodes, node 1, node 2... node n, are set. Each synchronization node adopts the system architecture in Embodiment 2 and executes the synchronization method provided in Embodiment 1.

[0095] After the power-on is completed, the physical layer clock is locked. Node 1 and node 2, and node 2 and the downstream nodes mutually start the adjacent node system clock domain deviation measurement mechanism, and measure the deviation of the system clock domain time between this node and the adjacent node according to the method in steps 201 - 203. Assume that node 1 measures the system clock domain time deviation T LSoffset-2-1 from node 2 to be 2000 ns, and correspondingly node 2 measures the system clock domain time deviation T LSoffset-1-2 from node 1 should be -2000 ns.

[0096] Node 1 also tests the deviation between the system clock domain time and the reference time of the connected PRTC-1. Assume the deviation value T LNoffset-1-1 is 3000 ns. Through the advertisement message sent by PRTC-1, node 1 can determine that the adjacent device is a reference time source device.

[0097] Node 1 increments the hop count of the received advertisement message of PRTC-1 by 1 and carries the deviation value T LNoffset-1-1 of 3000 ns between the system clock domain time of this node and the reference time of PRTC-1 through TLV, and sends it to the downstream node 2.

[0098] Node 2 receives the upstream advertisement message and obtains the deviation value T LNoffset-1-13000 ns, combined with the system domain time deviation value T between this node and the adjacent node 1 LSoffset-2-1 -2000 ns, the deviation value T between the system domain time of this node and the reference time of PRTC-1 can be calculated LNoffset-2-1 to be 3000 ns - 2000 ns = 1000 ns.

[0099] Node 2 adds 1 to the hop count of the advertisement message with the source of PRTC-1 it receives, and carries the deviation value T between the system clock domain time of this node and the reference time of PRTC-1 through TLV LNoffset-2-1 1000 ns, and sends it to the downstream node 3.

[0100] Node 3 uses the same calculation method to obtain the deviation value between its own system domain time and the reference time of PRTC-1. It also forwards the advertisement message with the source of PRTC-1 to the downstream in the same way. The deviation value is transmitted between adjacent nodes in turn until it is sent to all nodes. At this time, all synchronized nodes in the network have calculated the deviation value between their own system domain time and the reference time of PRTC-1.

[0101] The information of other reference master time device sources (PRTC-2 to PRTC-n) in the network is also independently transmitted in the network in the same way until all synchronized nodes have calculated the time deviation between their own system domain time and all reference master time devices. Since the time sources are all traceable to UTC time, normally for the auxiliary synchronization plane of a node, the difference between the observed deviation values from the time sources PRTC-1 to PRTC-n should be very small, and the standard deviation can be used for analysis. In the actual scenario, according to the actual test values, in the case of no abnormality, the deviation values of each node are about 1000 ns.

[0102] Through the above process, it can be seen that for each node in the time auxiliary synchronization plane, all time sources in the synchronization network can be used for synchronization calibration, so an accurate and stable time signal can be obtained.

[0103] Further, in a specific implementation scenario, the process of judging the synchronous network anomaly is described with Node 2 as the observation node. When PRTC-1 outputs degraded information abnormally, after being forwarded by Node 1, it is received by Node 2. After Node 2 identifies the degraded information based on the standard deviation, it excludes the observation data of PRTC-1 from the mean calculation and notifies the subsequent nodes of this anomaly information. If PRTC-1 stops sending information abnormally, or the synchronous link between Node 1 and Node 2 is abnormally interrupted, resulting in Node 2 not receiving the time information of PRTC-1. When the reception timeout judgment threshold is exceeded, Node 2 will clear the information related to PRTC-1. If the time information deviates too much from the UTC time due to the abnormal output performance of PRTC-1, for example, the deviation value T LNoffset-2-1 of PRTC-1 in the observation result of Node 2 is 20,000 ns, while the deviation results of other time sources are still about 1,000 ns. According to the synchronous network limit value specified by the standard to set the judgment threshold, it can be determined that the performance of PRTC-1 is abnormal and the time source with the anomaly can be located.

[0104] According to the above examples, the solutions provided in Embodiment 1 and Embodiment 2 can provide deviation adjustment data for the time synchronization of the time primary synchronization plane, enhancing the stability of synchronization. During the loss or switching of the time source in the time primary synchronization plane, it provides time output performance correction, without hardware tracking adjustment, removes the BMC algorithm, and can observe multiple reference time sources simultaneously. At the same time, by comparing the clocks of the time auxiliary synchronization plane and the time primary synchronization plane, the output performance monitoring and anomaly handling mechanism of the primary time synchronization plane can be realized.

[0105] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for implementing a dual-time-plane synchronous enhancement architecture, characterized in that: The time master synchronization plane in the 1588 domain tracks the upstream reference master time as the master plane time information and transmits the master plane time information to the time auxiliary synchronization plane; The time auxiliary synchronization plane in the system clock domain observes at least one reference time source to obtain the auxiliary plane time information, compares the auxiliary plane time information with the master plane time information to form clock adjustment information, transmits the clock adjustment information to the time master synchronization plane through a delay-free mode, and sends the auxiliary plane time information to the applications of this node and downstream nodes, where the clock adjustment information includes status analysis information and / or phase adjustment information; The time master synchronization plane corrects the master plane time information according to the clock adjustment information and sends the corrected master plane time information to the applications of this node and downstream nodes.

2. The method for implementing the dual-time-plane synchronization enhancement architecture according to claim 1, wherein The observing the reference time source to obtain the auxiliary plane time information specifically includes: Each node in the time auxiliary synchronization plane periodically sends a synchronization time message to adjacent nodes, and at the same time triggers the local system domain time to generate synchronization timestamp information. When each node receives the synchronization time message from an adjacent node, it uses the synchronization timestamp information in the synchronization time message as the first timestamp information and triggers the local system domain time to generate the second timestamp information; Each node sends a delay request message to adjacent nodes, and at the same time triggers the local system domain clock to generate the third timestamp information. When an adjacent node receives the delay request message, it triggers the local system domain clock to generate the fourth timestamp and returns the fourth timestamp to the sender of the delay request message through a delay response message; Obtain the difference between the first timestamp information and the second timestamp information in each group, and the difference between the third timestamp information and the fourth timestamp information in each group, and use the average value of the two timestamp differences as the deviation value between the local system clock domain time and the adjacent node system clock domain time, and calibrate the auxiliary plane time information according to the deviation value.

3. The method for implementing the dual-time-plane synchronous enhancement architecture according to claim 2, wherein The time auxiliary synchronization plane in the system clock domain observing at least one reference time source to obtain the auxiliary plane time information further includes: When the hop count between the node in the time auxiliary synchronization plane and the reference time source is 0, use the deviation value between the local system clock domain time and the adjacent node system clock domain time as the auxiliary plane time information; When the hop count between the node in the time auxiliary synchronization plane and the reference time source is not 0, use the sum of the deviation value between the upstream node system clock domain time and the adjacent node system clock domain time and the deviation value between the local system clock domain time and the adjacent node system clock domain time as the auxiliary plane time information.

4. The method for implementing the dual-time-plane synchronization enhancement architecture according to claim 2, wherein The comparing the auxiliary plane time information with the master plane time information to form clock adjustment information specifically includes: The time source ID is carried in the time announcement information sent by each node in the time auxiliary synchronization plane to adjacent nodes; When the node has received a time advertisement message carrying the same time source ID on other ports, compare the time advertisement messages carrying the same time source ID in terms of hop count, and select the time information in the time advertisement message with the smallest hop count to associate with the receiving port for use; If time advertisement messages with the same hop count are received on different ports, select the time advertisement message received on the port with a higher priority to associate with the receiving port for use.

5. The method implemented by the dual-time-plane synchronization enhancement architecture according to claim 1, characterized in that The comparison of the auxiliary plane time information and the master plane time information to form clock adjustment information further includes: The time auxiliary synchronization plane compares the received master plane time information with its own time information, and obtains the deviation value between the master plane time information and its own time information as the clock adjustment information, where the clock adjustment information includes any one or more of status analysis information, phase adjustment information, and frequency information.

6. The method for implementing the dual-time-plane synchronous enhancement architecture according to claim 1, wherein It further includes a transparent clock domain. The comparison of the auxiliary plane time information and the master plane time information to form clock adjustment information specifically includes: The transparent clock domain maintains its own transparent clock information, and the transparent time domain is associated with the physical port; The synchronization messages in the sending direction of the time master synchronization plane and the time auxiliary synchronization plane are sent to the corresponding physical ports through the transparent time domain; The transparent time domain corrects the time information in the synchronization message according to the time stamp when the synchronization message passes through the domain entrance and the time stamp when it passes through the domain exit.

7. A system implemented by a dual-time-plane synchronous enhancement architecture, characterized in that, Specifically, it includes: Establish a time master synchronization plane in the 1588 domain. The time master synchronization plane tracks the reference master time information through the PTP (Slave) port, transmits the time information to the downstream nodes through the PTP (Master) port, and sends the master plane time information to the time auxiliary synchronization plane through the time information channel; Establish a time auxiliary synchronization plane in the system clock domain. The time auxiliary plane tracks the time information of the upstream node through the PTP port, transmits the time information to the downstream nodes through the PTP port, and sends the clock adjustment information to the time master synchronization plane through the inter-layer data channel; The time auxiliary synchronization plane observes at least one reference time source to obtain the auxiliary plane time information, compares the auxiliary plane time information with the master plane time information to form the clock adjustment information, and transmits the clock adjustment information to the time master synchronization plane through the non-delay mode; The time master synchronization plane corrects the master plane time information according to the clock adjustment information, and sends the corrected master plane time information to the applications of this node and the downstream nodes.

8. The system implemented by the dual-time-plane synchronization enhancement architecture according to claim 7, characterized in that, It further includes: Establish a physical layer clock in the system clock domain, track the upstream reference clock frequency information through the line interface, and send the reference clock frequency information to the downstream nodes, the time master synchronization plane, and the time auxiliary synchronization plane.

9. The system implemented by the dual-time-plane synchronization enhancement architecture according to claim 7, wherein It further includes a transparent clock domain. Specifically: The transparent clock domain is associated with the physical port. The domain entrance and domain exit of the transparent clock domain include transparent timestamp units to facilitate obtaining the time stamp when the synchronization message passes through the domain entrance and the time stamp when it passes through the domain exit; The synchronization message received by the time master synchronization plane is forwarded to the time synchronization module of the 1588 domain through the transparent clock domain; The synchronization messages received by the time-assisted synchronization plane are forwarded to the time deviation measurement module in the system clock domain through the transparent clock domain; The synchronization messages in the sending direction of the time master synchronization plane and the time-assisted synchronization plane are sent to the corresponding physical ports through the transparent time domain.

10. The system implemented by the dual-time-plane synchronous enhancement architecture according to claim 7, characterized in that, The system clock domain contains a BC timestamp processing unit. Specifically: When the synchronization messages received by the time master synchronization plane and the time-assisted synchronization plane reach the physical ports, they are respectively processed by the same BC timestamp processing unit to facilitate the correction of the time deviation between the 1588 domain and the system clock domain.

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