Calibration system and radar for delay calibration of TDC timing channels

Abstract

This invention provides a calibration system and radar for delay calibration of TDC timing channels. The calibration system sends periodic signals to each carry-chain timing channel via a clock generator, enabling each carry-chain timing channel to monitor the transition edge of the same periodic signal. The calibration module subtracts the trigger times of the transition edges of the same periodic signal obtained by each pair of carry-chain timing channels to obtain the delay time between each pair of carry-chain timing channels. Thus, when calculating the time difference between the output times of any two carry-chain timing channels, the system calibrates the time difference based on the delay time, improving the accuracy of the time difference output by the carry-chain timing channels and thereby improving the radar monitoring accuracy.

Description

Technical Field

[0001] This invention relates to the field of radar technology, and in particular to a calibration system and radar for delay calibration of TDC timing channels. Background Technology

[0002] LiDAR is an indispensable sensor for achieving autonomous driving in vehicles. Currently, most LiDAR systems in vehicles utilize Time-of-Flight (TOF) technology, where d = c * t, and d is the measured distance, and c is the speed of light (3 * 10⁸ m / s). Therefore, the accuracy of the measured distance t directly affects the accuracy of the distance measurement. Common methods for measuring distance include high-speed ADCs (Analog-to-Digital Converters), which use carry-chain timing within FPGAs (Field-Programmable Gate Arrays). Carry-chain timing offers advantages such as high accuracy, low cost, and minimal space requirements, making it the preferred method for all LiDAR manufacturers.

[0003] Since a lidar requires multiple carry chains to work simultaneously to complete a measurement, and the signal routing inside the FPGA is different, even if the same signal is transmitted in different carry chains, the final measurement time may be different, which directly affects the ranging accuracy of the lidar. Summary of the Invention

[0004] In view of this, the present invention provides a calibration system and radar for delay calibration of TDC timing channels, which can solve the problem of low radar accuracy caused by different signal routing inside the FPGA chip.

[0005] In a first aspect, embodiments of the present invention provide a calibration system for delay calibration of TDC timing channels, comprising: a clock generator, a TDC timing module and a calibration module, wherein the TDC timing module includes multiple carry chain timing channels;

[0006] The clock generator is connected to multiple carry-chain timing channels;

[0007] The clock generator is used to generate periodic signals and send the periodic signals to each carry chain timing channel;

[0008] Each carry chain timing channel is used to monitor the transition edge of the periodic signal and send the detected transition edge trigger time to the calibration module.

[0009] The calibration module is used to subtract the trigger times of the transition edges of the same periodic signal obtained by each pair of carry chain timing channels to obtain the delay time between each pair of carry chain timing channels; the delay time is used to calibrate the time difference between the output times of any two carry chain timing channels when calculating the time difference between the output times of any two carry chain timing channels.

[0010] In one possible implementation, the calibration system includes a test pad, a first input pin, and a second input pin;

[0011] The test pad is connected to the clock generator and is connected to the first input pin via a first connection line and to the second input pin via a second connection line; the first input pin is connected to at least one carry chain timing channel, and the second input pin is connected to at least one carry chain timing channel; and the carry chain timing channel connected to the first input pin and the carry chain timing channel connected to the second input pin do not overlap;

[0012] The lengths of the first connecting line and the second connecting line are equal.

[0013] In one possible implementation, the calibration system further includes a first resistor and a second resistor;

[0014] The first resistor is connected in series on the first connecting line, and the second resistor is connected in series on the second connecting line.

[0015] In one possible implementation, the clock generator is connected to the test pad via a coaxial cable.

[0016] In one possible implementation, the calibration system further includes a first input pin and a LUT lookup table;

[0017] The first pin of the LUT lookup table input terminal is connected to the output terminal of the clock generator, and the second pin of the LUT lookup table input terminal is connected to the first input pin; the output terminal of the LUT lookup table is connected to each carry chain timing channel respectively; the first pin is any pin of the LUT lookup table input terminal, and the second pin is any pin of the LUT lookup table input terminal other than the first pin;

[0018] The calibration module is used to determine the two carry chain timing channels corresponding to the input signal based on the LUT lookup table when calculating the time difference between the two edge triggering times of the input signal input from the first input pin, and to calibrate the time difference between the two edge triggering times of the input signal using the delay time between the two carry chain timing channels corresponding to the input signal.

[0019] In one possible implementation, the clock generator is a hybrid mode clock manager.

[0020] In one possible implementation, the clock generator is a phase-locked loop.

[0021] In one possible implementation, the calibration module is specifically used for:

[0022] For any two carry chain timing channels, calculate the difference between the trigger times of the transition edges of the same periodic signal obtained by the two carry chain timing channels, and obtain the time difference between the two carry chain timing channels at multiple transition edge trigger times;

[0023] The delay time between the two carry chain timing channels is obtained based on the time difference between the trigger times of multiple transition edges of the two carry chain timing channels.

[0024] In one possible implementation, the calibration module is specifically used for:

[0025] For any two carry chain timing channels, remove the maximum and minimum values ​​from the time differences of the multiple transition edge trigger times of the two carry chain timing channels, and obtain the delay time between the two carry chain timing channels based on the time differences of the transition edge trigger times of the two carry chain timing channels after removing the maximum and minimum values.

[0026] Secondly, embodiments of the present invention provide a radar comprising a calibration system for delay calibration of a TDC timing channel as described in any possible implementation of the first aspect above.

[0027] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows:

[0028] The calibration system provided in this embodiment of the invention sends periodic signals to each carry chain timing channel via a clock generator, enabling each carry chain timing channel to monitor the transition edge of the same periodic signal. The calibration module subtracts the trigger times of the transition edges of the same periodic signal obtained by each pair of carry chain timing channels to obtain the delay time between each pair of carry chain timing channels. Thus, when calculating the time difference between the output times of any two carry chain timing channels, the system calibrates the time difference based on the delay time, improving the accuracy of the time difference output by the carry chain timing channels and thereby improving the radar monitoring accuracy. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a calibration system for delay calibration of TDC timing channels provided in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the laser beam propagation of the lidar provided in an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram showing the laser beam emission time and the time when echo signals of different intensities are received by the radar in the embodiment of the present invention.

[0033] Figure 4 This is a schematic diagram of the laser beam emission time and the signal width of echo signals of different intensities of the lidar provided in the embodiments of the present invention;

[0034] Figure 5 This is a schematic diagram showing the laser beam emission time and the time when echo signals of different intensities are received by the radar in the embodiment of the present invention.

[0035] Figure 6 This is a schematic diagram of the structure of the FPGA chip inside a conventional lidar provided in an embodiment of the present invention;

[0036] Figure 7 This is another structural schematic diagram of a calibration system for delay calibration of TDC timing channels provided in an embodiment of the present invention;

[0037] Figure 8 This is a schematic diagram of the LUT lookup table provided in an embodiment of the present invention. Detailed Implementation

[0038] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0039] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0040] Figure 1 This is a schematic diagram of the structure of a calibration system for delay calibration of a TDC timing channel provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the calibration system includes: a clock generator 118, a TDC timing module 103, and a calibration module. The TDC timing module 103 includes multiple carry chain timing channels.

[0041] The clock generator 118 is connected to multiple carry-chain timing channels;

[0042] The clock generator 118 is used to generate periodic signals and send the periodic signals to each carry chain timing channel;

[0043] Each carry chain timing channel is used to monitor the transition edge of the periodic signal and send the detected transition edge trigger time to the calibration module.

[0044] The calibration module is used to subtract the trigger times of the transition edges of the same periodic signal obtained by each pair of carry chain timing channels to obtain the delay time between each pair of carry chain timing channels; the delay time is used to calibrate the time difference between the output times of any two carry chain timing channels when calculating the time difference between the output times of any two carry chain timing channels.

[0045] In this embodiment, the principle of lidar ranging is as follows:

[0046] like Figure 2 As shown, Q100 is the lidar, and Q101 is the target object. The lidar emits a laser beam, which is reflected upon encountering the target, and the lidar receives the reflected beam. Therefore, the distance between the lidar and the target can be expressed by the formula: D = C * T, where C = 3 * 10⁸ m / s. Therefore, the accuracy of the measurement of T directly affects the ranging accuracy of the lidar.

[0047] like Figure 3 As shown: T100 is taken as the transmission time of the laser radar signal. T101 and T102 are taken as the rising and falling edge trigger times of the received signals after the laser signal is reflected from the target and received by the laser radar. We can interpret the time difference between T101 and T102 as the strength of the laser radar signal received; the larger the ΔTx, the stronger the signal received by the radar, and vice versa. The time difference between T101 and T100 is ΔT, which is the flight time of the radar to the target. Therefore, the distance to the target can be calculated based on this time.

[0048] Specifically, such as Figure 4As shown, S100 is the laser radar transmitted signal, corresponding to time T100, and S101, S102, ..., S10N are received signals of different intensities. We use a threshold to compare them, such as... Figure 4 As shown by line P1, the widths of a series of signals S101, S102...S10N will be obtained. Taking one of the widths as an example, as shown... Figure 4 `width1` represents the width of one of the signals. Figure 3 and Figure 4 We know that width1 = ΔTx = T102 - T101, where width1 is a time quantity. Different widths (ΔTx) correspond to different ΔT values ​​(e.g., ...). Figure 4 (△T1, △T2 in the equation). Therefore, the accuracy of △Tx is crucial, and how to ensure the accuracy of △Tx measurement is an urgent problem to be solved.

[0049] like Figure 1 As shown, the TDC timing module 103 can be the TDC timing module 103 in the FPGA chip 105. The TDC timing module 103 includes multiple carry chain timing channels. The clock generator 118 is used to generate periodic signals, and the carry chain timing channels are used to monitor the trigger time of the transition edge of the input periodic signal.

[0050] like Figure 1 As shown, in some embodiments, the TDC timing module 103 includes carry chain timing channel 1 (the first chain), carry chain timing channel 2 (the second chain), carry chain timing channel 3 (the third chain)...carry chain timing channel n (the nth chain). It should be noted that the number of carry chain timing channels can be set based on the number of radar receiving channels.

[0051] Specifically, when using TDC timing module 103... Figure 3 or Figure 4 When timing the theoretical transmission time T100 of the transmitted signal S100 and the theoretical rising edge trigger time T101 and falling edge trigger time T102 of the received signal S101, the TDC timing module uses different carry chain timing channels to monitor the transmission and received signals. Due to the delay time between different carry chain timing channels, there will be deviations in the pairwise differences between T100, T101 and T102, which will affect the ranging accuracy of the target.

[0052] To address the aforementioned issues, this embodiment employs a clock generator to produce periodic signals and send them to each carry-chain timing channel of the FPGA chip. This allows each carry-chain timing channel to monitor the trigger moment of the transition edge of the same periodic signal and output the timing time of each carry-chain timing channel. The clock generator 118 can be a built-in clock module of the FPGA chip capable of generating fixed-frequency signals, or it can be a newly added external instrument that generates fixed-frequency signals.

[0053] The periodic signal generated by the clock generator, such as Figure 6 As shown, the periodic signal can be a 10kHz frequency signal, therefore the signal period T = 100µs. In the FPGA chip, through program control, each carry-chain timing channel simultaneously detects the edge of the periodic signal emitted by the clock generator, obtaining the edge trigger time. Based on the difference in edge trigger times between different carry-chain timing channels, the delay time between different carry-chain timing channels is determined. Subsequently, when using each carry-chain timing channel to monitor the input signal and calculate the time difference between two signals, the time difference between the corresponding carry-chain timing channels can be used to compensate for the time difference between the two signals, solving the problem of inaccurate target ranging caused by timing errors between carry-chain timing channels.

[0054] In one possible implementation, the calibration system includes a test pad, a first input pin, and a second input pin;

[0055] The test pad is connected to the clock generator, and is connected to the first input pin via a first connection line, and to the second input pin via a second connection line;

[0056] The first input pin is connected to at least one carry chain timing channel, and the second input pin is connected to at least one carry chain timing channel; and the carry chain timing channel connected to the first input pin and the carry chain timing channel connected to the second input pin do not overlap;

[0057] The lengths of the first connecting line and the second connecting line are equal.

[0058] In the prior art, the first input pin 106 and the second input pin 109 are pins on the FPGA chip used to connect to different input ports, so that one signal input to the FPGA chip enters at least one carry chain timing channel through the first input pin, and another signal enters at least one carry chain timing channel through the second input pin.

[0059] This embodiment also includes a PCB board. During PCB layout, a test pad 113 is reserved. The clock generator 118 is connected to the test pad 113 via a coaxial cable. The first input pin 106 is connected to the test pad 113 via a first connecting line 112, and to carry chain timing channel 1 via a trace 108, and to carry chain timing channel 2 via a trace 107. The second input pin 109 is connected to the test pad 113 via a second connecting line 111, and to carry chain timing channel 3 via a trace 110.

[0060] In addition, in this embodiment, when routing on the PCB, the lengths of the first connecting line 112 and the second connecting line 111 are set to be equal.

[0061] During testing, the clock generator 118 transmits the generated periodic signal to carry chain timing channel 1 via test pad 113, first connection line 112, first input pin 106, and trace 108; transmits the generated periodic signal to carry chain timing channel 2 via test pad 113, first connection line 112, first input pin 106, and trace 107; and transmits the generated periodic signal to carry chain timing channel 3 via test pad 113, second connection line 111, and second input pin 109. In practical applications, the signal input to the FPGA chip is transmitted to carry chain timing channel 1 via first input pin 106 and trace 108; the signal input to the FPGA chip is transmitted to carry chain timing channel 2 via first input pin 106 and trace 107; and the signal input to the FPGA chip is transmitted to carry chain timing channel 3 via second input pin 109 and trace 110.

[0062] Since the lengths of the first connection line 112 and the second connection line 111 are equal, the difference between the paths taken by the input signal to the FPGA chip before being output through the three carry chain timing channels and the difference between the paths taken by the periodic signal output from the clock generator before being output through the three carry chain timing channels is the same: trace 108 + carry chain timing channel 1, trace 107 + carry chain timing channel 2, and trace 110 + carry chain timing channel 3. Therefore, when the three carry chain timing channels monitor the trigger time of the transition edge of the same periodic signal, the delay time between trace 108 + carry chain timing channel 1, trace 107 + carry chain timing channel 2, and trace 110 + carry chain timing channel 3 can be calculated. Thus, the delay time between each carry chain timing channel can be calculated more accurately using the above structure.

[0063] Specifically, the edge transition trigger times include rising edge trigger times and falling edge trigger times. Figure 3 and Figure 4Taking the transmit signal S100 and receive signal S101 as an example, the theoretical transmit time T100 of S100 is monitored and obtained through the following path: after S100 enters the input port of the FPGA chip, it enters the carry chain timing channel 3 through the second connection line, the second input pin 109, and the trace 110. The carry chain timing channel 3 monitors the rising edge trigger time of the signal S100 to obtain the actual transmit time T3 of S100.

[0064] The theoretical rising edge trigger time T101 of S101 is monitored through the following path: after the signal S101 enters the input port of the FPGA chip, it enters the carry chain timing channel 1 through the first connection line 112, the first input pin, and the trace 108. The carry chain timing channel 1 monitors the rising edge trigger time of the signal S101 and obtains the actual rising edge trigger time T1 of S101.

[0065] The theoretical falling edge trigger time T102 of S101 is monitored through the following path: after the signal S101 enters the input port of the FPGA chip, it enters the carry chain timing channel 2 through the first connection line 112, the first input pin, and the trace 107. The carry chain timing channel 2 monitors the falling edge trigger time of the input signal S101 and obtains the actual falling edge trigger time T2 of S101.

[0066] Theoretically, T2-T1=T102-T101=△Tx. T1-T3=T101-T100=△T.

[0067] As can be seen from the above path, before S100 and S101 output T100, T101, and T102 through the three carry chain timing channels, the difference in their paths is: 108 + carry chain timing channel 1, 107 + carry chain timing channel 2, and 110 + carry chain timing channel 3. Therefore, the accurate ΔTx and ΔT can be calculated by compensating for the delay time T2-T1 and T1-T3 between the three carry chain timing channels.

[0068] In one possible implementation, the calibration system further includes a first resistor and a second resistor;

[0069] The first resistor is connected in series on the first connecting line, and the second resistor is connected in series on the second connecting line.

[0070] Specifically, when routing on the PCB, a first resistor is connected in series on the first connection line, and a second resistor is connected in series on the second connection line. This prevents signal interference caused by other signals input to the first input pin 106 and the second input pin 109. After completing the delay time test, the first and second resistors are removed.

[0071] In one possible implementation, the clock generator is connected to the test pad via a coaxial cable.

[0072] In this embodiment, using a coaxial cable bundle can achieve better shielding performance.

[0073] In one possible implementation, the calibration system further includes a first input pin and a LUT lookup table;

[0074] The first pin of the LUT lookup table input terminal is connected to the output terminal of the clock generator, and the second pin of the LUT lookup table input terminal is connected to the first input pin; the output terminal of the LUT lookup table is connected to each carry chain timing channel respectively; the first pin is any pin of the LUT lookup table input terminal, and the second pin is any pin of the LUT lookup table input terminal other than the first pin;

[0075] The calibration module is used to determine the two carry chain timing channels corresponding to the input signal based on the LUT lookup table when calculating the time difference between the two edge triggering times of the input signal input from the first input pin, and to calibrate the time difference between the two edge triggering times of the input signal using the delay time between the two carry chain timing channels corresponding to the input signal.

[0076] In this embodiment, if the LiDAR requires a program upgrade during use, i.e., the FPGA chip is recompiled, the paths 107, 108, and 110 will change. To solve this problem, this embodiment incorporates a LUT lookup table.

[0077] like Figure 7 As shown, the clock generator 115, the first input pin 106, and the second input pin 109 are connected one-to-one with the input pins of the LUT lookup table 114. The LUT lookup table 114 is a low-level lookup table within the FPGA chip. Figure 8 The structure of a LUT lookup table is shown. It can include 6 input pins and 1 output pin. When multiple input signals are input, the LUT lookup table will only select one input signal for output, that is, the LUT lookup table is used as a selection switch.

[0078] In this embodiment, the clock generator 115 is an internal clock generator of the FPGA chip, which generates clocks such as... Figure 6 The periodic signal shown is routed to one of the inputs of LUT lookup table 114. Figure 6 The rising edge trigger time passes through 115 to LUT lookup table 114, and then splits into 3 paths from the output of LUT lookup table 114, which respectively enter 3 carry chain timing channels. Therefore, the 3 carry chain timing channels measure... Figure 6 By calculating the time of the rising edge, the time difference between each pair of timing channels 108+carry chain timing channel 1, 107+carry chain timing channel 2, and 116+carry chain timing channel 3 can be determined.

[0079] Specifically, when writing the FPGA program, the LUT lookup table is instantiated in the program, and the first input pin 109, the second input pin 106, and the clock generator are connected to the inputs A1, A2, and A3 of the LUT lookup table 114. The output O5 of the LUT lookup table 114 is connected to carry chain timing channels 1, 2, 3, ..., n, respectively. In this way, even if the program is upgraded, the calibration module can determine the carry chain timing channel corresponding to each input signal based on the stored correspondence between the input pins, input signals, and carry chain timing channels of the LUT lookup table.

[0080] For example, such as Figure 7 As shown, signal S101 enters the first input pin 106 through trace 112, and after being selected by LUT lookup table 114, it enters carry chain timing channel 1 and carry chain timing channel 2 through 107 and 108 respectively.

[0081] from Figure 7 As can be seen, when monitoring the rising edge trigger time T101 and the falling edge trigger time T102 of signal S101, signal S101 travels through the common paths 112, 106 to 114, so there is no delay at these three points. A branch occurs at the output position 114. Signal S101 travels through trace 108 to carry chain timing channel 1, where the actual rising edge trigger time T1 of S101 is detected. Signal S101 travels through trace 107 to carry chain timing channel 2, where the actual falling edge trigger time T2 of S101 is detected. Therefore, the difference in the paths taken by signal S101 at the actual rising edge trigger time T1 and the actual falling edge trigger time T2 in the FPGA chip lies in 107 + carry chain timing channel 2 and 108 + carry chain timing channel 1. Therefore, the error between T1 and T2 can be calibrated by adjusting the delay time of different carry chain timing channels.

[0082] However, since signals S100 and S101 are two separate signals, the LUT lookup table cannot output both signals synchronously. Therefore, a different approach is adopted. Figure 7 The structure shown cannot calculate the delay time between carry chain timing channel 3 and carry chain timing channel 1; it can only calculate the delay time between carry chain timing channel 1 and carry chain timing channel 2.

[0083] In one possible implementation, such as Figure 7 As shown, in the calibration system provided in this embodiment, the second input pin is connected to the input terminal of the carry chain timing channel 3. The calibration module can... Figure 7 The structure in the middle obtains the delay time between any two carry chain timing channels. After obtaining the delay time of any two carry chain timing channels, the S100 signal can be timed for its theoretical transmission time T100 through the following path: S100 enters the carry chain timing channel 3 through the second input pin 109 and the trace 117. The carry chain timing channel 3 monitors the trigger time of the jumping edge of S100 and obtains the actual transmission time T3 of S100.

[0084] Since the timing error caused by different trace lengths is small, while the timing error caused by different carry chain timing channels is large, this embodiment can compensate for T1-T3 based solely on the delay time between carry chain timing channel 1 and carry chain timing channel 3, thereby improving the accuracy of △T to a certain extent.

[0085] In one possible implementation, the clock generator is a Mixed-Mode Clock Manager (MMCM).

[0086] In one possible implementation, the clock generator is a phase-locked loop (PLL).

[0087] In one possible implementation, the calibration module is specifically used for:

[0088] For any two carry chain timing channels, calculate the difference between the trigger times of the transition edges of the same periodic signal obtained by the two carry chain timing channels, and obtain the time difference between the two carry chain timing channels at multiple transition edge trigger times;

[0089] The delay time between the two carry chain timing channels is obtained based on the time difference between the trigger times of multiple transition edges of the two carry chain timing channels.

[0090] In this embodiment, for any two carry chain timing channels, the calibration module can calculate the average of the time differences between the trigger times of multiple transition edges of the two carry chain timing channels, and use the average as the delay time between the two carry chain timing channels.

[0091] In one possible implementation, the calibration module is specifically used for:

[0092] For any two carry chain timing channels, remove the maximum and minimum values ​​from the time differences of the multiple transition edge trigger times of the two carry chain timing channels, and obtain the delay time between the two carry chain timing channels based on the time differences of the transition edge trigger times of the two carry chain timing channels after removing the maximum and minimum values.

[0093] In this embodiment, when calculating the delay time, the calibration module can sort the time differences of the remaining transition edge trigger times after removing the maximum and minimum values, and take the median value of the sorted sequence as the delay time of the two carry chain timing channels. Alternatively, after removing the maximum and minimum values, the average value of the remaining transition edge trigger times can be calculated to obtain the delay time of the two carry chain timing channels.

[0094] Specifically, assuming the rising edge trigger time of the carry chain timing channel 1 signal S101 is T1 = 46824 ps, the falling edge trigger time of the carry chain timing channel 2 signal S101 is T2 = 45139 ps, and the rising edge trigger time of the carry chain timing channel 3 signal S100 is T3 = 47214 ps. If the data is sampled at 100 µs per iteration, and this is repeated 1 million times, 1 million T2-T1 and T3-T1 values ​​will be obtained, i.e., ΔT(2-1)n = T2n-T1n, ΔT(3-1)n = T3n-T1n. After removing the maximum and minimum values ​​from these 1 million ΔT(2-1)n values, the data is sorted for numerical uniqueness, and the median value of the sequence is selected. For example, the median value obtained after removing the maximum and minimum values ​​from ΔT(2-1)n is -1653. This value is stored, indicating that carry chain timing channel 2 is 1653 ps faster than carry chain timing channel 1. When calculating ΔTx, the initial ΔTx is added by 1653ps to obtain the calibrated ΔTx.

[0095] Similarly, in 1 million ΔT(3-1)n, after removing the maximum and minimum values, the resulting data is sorted for numerical uniqueness, and the median value of the sequence is selected. For example, after removing the maximum and minimum values ​​in ΔT(3-1)n, the median value is 561. This value is stored, indicating that carry chain timing channel 3 is 561ps slower than carry chain timing channel 1. When calculating ΔT, the initial ΔT is subtracted by 561ps to obtain the calibrated ΔT, thus eliminating the delay between channels.

[0096] This invention provides a radar comprising a calibration system for delay calibration of a TDC timing channel as described in any of the above possible embodiments.

[0097] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A calibration system for delay calibration of a TDC timing channel, characterized by, include: A clock generator, a TDC timing module, and a calibration module, wherein the TDC timing module includes multiple carry chain timing channels; The clock generator is connected to multiple carry-chain timing channels; The clock generator is used to generate periodic signals and send the periodic signals to each carry chain timing channel; Each carry chain timing channel is used to monitor the transition edge of the periodic signal and send the detected transition edge trigger time to the calibration module. The calibration module is used to subtract the trigger times of the transition edges of the same periodic signals obtained by each pair of carry chain timing channels to obtain the delay time between each pair of carry chain timing channels. The delay time is used to calibrate the time difference between the output times of any two carry chain timing channels when calculating the time difference between their output times. The calibration system also includes a first input pin and a LUT lookup table. The first pin of the LUT lookup table input is connected to the output of the clock generator, and the second pin of the LUT lookup table input is connected to the first input pin. The output of the LUT lookup table is connected to each carry chain timing channel. During program upgrades, the calibration module is used to determine the carry chain timing channel corresponding to each input signal based on the correspondence between the input pins of the stored LUT lookup table, the input signals, and the carry chain timing channels.

2. The calibration system for delay calibration of a TDC timing channel of claim 1, wherein, The first pin is any pin of the LUT lookup table input terminal, and the second pin is any pin of the LUT lookup table input terminal other than the first pin; The calibration module is used to determine the two carry chain timing channels corresponding to the input signal based on the LUT lookup table when calculating the time difference between the two edge triggering times of the input signal input from the first input pin, and to calibrate the time difference between the two edge triggering times of the input signal using the delay time between the two carry chain timing channels corresponding to the input signal.

3. The calibration system for delay calibration of a TDC timing channel of claim 2, wherein, The clock generator is a hybrid mode clock manager.

4. The calibration system for delay calibration of TDC timing channels of claim 2, wherein, The clock generator is a phase-locked loop.

5. The calibration system for delay calibration of a TDC timing channel according to any one of claims 1 to 4, characterized in that, The calibration module is specifically used for: For any two carry chain timing channels, calculate the difference between the trigger times of the transition edges of the same periodic signal obtained by the two carry chain timing channels, and obtain the time difference between the two carry chain timing channels at multiple transition edge trigger times; The delay time between the two carry chain timing channels is obtained based on the time difference between the trigger times of multiple transition edges of the two carry chain timing channels.

6. The calibration system for delay calibration of TDC timing channels according to claim 5, characterized in that, The calibration module is specifically used for: For any two carry chain timing channels, remove the maximum and minimum values ​​from the time differences of the multiple transition edge trigger times of the two carry chain timing channels, and obtain the delay time between the two carry chain timing channels based on the time differences of the transition edge trigger times of the two carry chain timing channels after removing the maximum and minimum values.

7. A radar, characterized in that, Includes the calibration system for delay calibration of TDC timing channels as described in any one of claims 1 to 6.

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