Multi-channel nanosecond time synchronization device for FPGA and use method thereof

Abstract

The present invention discloses a multi-channel nanosecond-level time synchronization device for FPGAs and its use method. The synchronization device comprises: a GPS / BD receiver module, a high-precision clock crystal oscillator module, a time parsing module, a timekeeping module, a clock multiplication module, and a nanosecond-level timestamp generation module. The GPS / BD receiver module receives GPS / BD data and transmits it to the time parsing module via a serial port for parsing. The parsed time is then transmitted to the timekeeping module as a time reference. The high-precision crystal oscillator module is connected to the clock multiplication module, generating a 125MHz clock that, after passing through the clock multiplication module, produces a 1GHz high-speed clock. The timekeeping module synchronizes the calibrated time information with a pulse-second signal (PPS). The nanosecond-level timestamp generation module generates a timestamp by taking the 1GHz clock signal transmitted by the timekeeping module and the synchronized calibrated time information and the pulse-second signal (PPS) signal. The time resolution of the synchronization device of the present invention can reach the nanosecond level.

Description

Technical Field

[0001] The present invention relates to the field of automation technology, and in particular to a multi-channel nanosecond time synchronization device for FPGA and a use method thereof. Background Art

[0002] Time management synchronization is a very important function in the field of automation technology. As the use scenarios of automated test equipment become more and more complex, the requirements for time accuracy are getting higher and higher.

[0003] The existing solution is to integrate a GPS / BD (Global Positioning System / Beidou System) receiver and a high-precision crystal oscillator on each device's hardware board. Software is used to parse GPS / BD data and obtain timestamps, which increases costs. However, this approach suffers from insufficient application synchronization clock management, low accuracy, and high costs. Summary of the Invention

[0004] In view of this, the present invention provides a multi-channel nanosecond time synchronization device for FPGA and a method for using the same, which can solve the problems of insufficient synchronous clock management, low precision and high cost in the prior art.

[0005] In order to solve the above technical problems, the present invention is implemented as follows.

[0006] A multi-channel nanosecond time synchronization device for FPGA, comprising a GPS / BD receiving module, a high-precision clock crystal oscillator module, a time analysis module, a timekeeping module, a clock multiplication module, and a nanosecond timestamp generation module;

[0007] The time analysis module, timekeeping module, clock multiplication module, and nanosecond timestamp generation module are internally connected to the FPGA; wherein the GPS / BD receiving module receives GPS / BD data, transmits it to the time analysis module through the serial port for analysis, and the analyzed time is transmitted to the timekeeping module as the time reference; the high-precision crystal oscillator module is connected to the clock multiplication module, and the high-precision crystal oscillator module generates a 125Mhz clock, which is converted into a 1GHz high-speed clock after passing through the clock multiplication module; the timekeeping module uses the 1GHz high-speed clock to collect the second pulse PPS signal from the GPS / BD receiving module to achieve synchronization of the calibrated time information and the PPS second pulse; the nanosecond timestamp generation module obtains the 1GHz clock signal transmitted by the timekeeping module, the synchronized calibrated time information, and the second pulse PPS signal, generates the integer seconds and fractional seconds required for the timestamp, and generates the timestamp based on the integer seconds and fractional seconds.

[0008] Preferably, the time parsing module is used to parse the GPS / BD data sent by the GPS / BD receiving module outside the FPGA and obtain the time information in the GPS / BD data; when the time information is valid time information, the time information is calibrated and the calibrated time information is sent to the timekeeping module as the time reference.

[0009] Preferably, the timing module is used to obtain the rising edge of the second pulse PPS signal, read the calibrated time information generated by the time analysis module on the rising edge of the second pulse PPS signal, and simultaneously obtain the second pulse PPS signal, so that the calibrated time information is synchronized with the second pulse PPS signal.

[0010] Preferably, when the timing module receives the correct second pulse PPS signal, the calibrated time information is synchronized with the second pulse PPS signal at the rising edge of the second pulse PPS signal; when the timing module fails to receive the correct second pulse PPS signal, the 1GHz clock signal generated by the clock multiplication module is used for timekeeping, and a corresponding second second pulse PPS signal is generated, until the correct second pulse PPS signal can be received, and then the calibrated time information is synchronized with the second pulse PPS signal.

[0011] Preferably, the nanosecond timestamp generation module uses the 1GHz clock signal transmitted by the timekeeping module, the synchronized calibrated time information and the pulse-seconds PPS signal to generate integer seconds and fractional seconds; the integer seconds are counted by one each time the pulse-seconds PPS signal is received based on the calibrated time information; the fractional seconds are cleared each time the pulse-seconds PPS signal is received, and are counted by one when the rising edge of the 1GHz clock signal arrives.

[0012] Preferably, if the time information is valid time information, the time validity flag in the status flag register in the time resolution module is set to valid, the time resolution module determines the time quality, leap seconds and time validity of the time information, calibrates the time information, sends the calibrated time information and the value of the status flag register to the timekeeping module, and triggers the timekeeping module; otherwise, the time information is erroneous time information or invalid time information, the time resolution module sets the time validity flag in the status flag register to invalid, and when the timekeeping module receives the value of the time validity flag as invalid, it uses the 1GHz clock signal generated by the clock multiplication module to keep time;

[0013] The calibrating of the time information includes:

[0014] Obtain the time information t0, obtain the delay time t1 of the time information on the transmission path according to the baud rate of the serial port, obtain the leap second information t2 of the time information, and obtain the time t3 taken to resolve the time information;

[0015] The calibrated time information T=t0+t1+t2+t3.

[0016] A method for using a multi-channel nanosecond time synchronization device for FPGA, the method being based on the multi-channel nanosecond time synchronization device for FPGA as described above, and comprising the following steps:

[0017] Step S31: Acquire GPS / BD signals, parse time information in the GPS / BD signals, set a time validity flag register based on whether the parsed time is valid; and calibrate the parsed valid time information.

[0018] Step S32: triggering the timekeeping module to synchronize the calibrated time information with the pulse per second (PPS) signal from the GPS / BD receiving module;

[0019] Step S33: The nanosecond timestamp generation module uses the 1 GHz clock signal transmitted by the timekeeping module, the synchronized calibrated time information and the pulse per second (PPS) signal to generate integer seconds and fractional seconds to form a nanosecond timestamp.

[0020] Beneficial effects:

[0021] (1) The software module of the time synchronization device of the present invention runs in FPGA, and analyzes and detects anomalies of the pulse-per-second (PPS) signal based on GPS / BD time synchronization management. Once the time synchronization is completed, the time synchronization device itself has a timekeeping function with a time resolution of nanoseconds. The generated nanosecond timestamp is transmitted to other boards through the LVDS interface via the backplane, which can greatly reduce production costs.

[0022] (2) The present invention can provide functions such as time resolution, self-synchronized high-precision timekeeping, and self-synchronized sampling pulse calibration, providing a high-precision clock management solution that can simultaneously meet the clock management needs of multiple channels and multiple boards. The time synchronization device does not require the use of an additional time management chip, and only needs to provide an LVDS interface to connect to other devices that use time management.

[0023] (3) The time synchronization device described in the present invention includes a GPS / BD time resolution module, a timekeeping module, and a nanosecond timestamp generation module, which can be integrated into one. The three modules can be enabled separately, and can simultaneously meet all application requirements of multi-channel and multi-device synchronous clock management; the time synchronization software module is integrated on an FPGA chip, eliminating the need for a dedicated high-precision clock management chip, saving costs, and is not limited to a specific FPGA chip.

[0024] (4) The GPS / BD time parsing module, timekeeping module, and nanosecond timestamp generation module of the present invention are developed based on the hardware description language Verilog and are easy to transplant. The time synchronization device can be easily connected to the application device using a simple LVDS interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a structural diagram of the multi-channel nanosecond time synchronization device for FPGA provided by the present invention.

[0026] Figure 2 This is a schematic diagram of the timekeeping module provided by the present invention.

[0027] Figure 3 This is a schematic diagram of applying the time synchronization device to the multi-channel board provided by the present invention. DETAILED DESCRIPTION

[0028] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0029] like Figure 1 As shown, the present invention proposes a multi-channel nanosecond time synchronization device for FPGA, which includes a GPS / BD receiving module, a high-precision clock crystal oscillator module, a time analysis module, a timekeeping module, a clock multiplication module, and a nanosecond timestamp generation module.

[0030] The time analysis module, timekeeping module, clock multiplication module, and nanosecond timestamp generation module are internally connected to the FPGA; wherein the GPS / BD receiving module receives GPS / BD data, transmits it to the time analysis module through the serial port for analysis, and the analyzed time is transmitted to the timekeeping module as the time reference; the high-precision crystal oscillator module is connected to the clock multiplication module, and the high-precision crystal oscillator module generates a 125Mhz clock, which is converted into a 1GHz high-speed clock after passing through the clock multiplication module; the timekeeping module uses the 1GHz high-speed clock to collect the pulse per second (PPS) signal from the GPS / BD receiving module to synchronize the calibrated time information with the pulse per second (PPS) signal; the nanosecond timestamp generation module obtains the 1GHz clock signal transmitted by the timekeeping module, the synchronized calibrated time information, and the pulse per second (PPS) signal, generates the integer seconds and fractional seconds required for the timestamp, and generates the timestamp based on the integer seconds and fractional seconds.

[0031] Furthermore, the time parsing module is used to parse the GPS / BD data sent by the GPS / BD receiving module outside the FPGA to obtain the time information in the GPS / BD data; when the time information is valid time information, the time information is calibrated and the calibrated time information is sent to the timekeeping module as a time reference.

[0032] Furthermore, the clock multiplication module is used to receive a 125MHz clock generated by a high-precision clock crystal oscillator module outside the FPGA, generate a 1GHz high-speed clock, and send the generated 1GHz high-speed clock to the timekeeping module.

[0033] Furthermore, the timekeeping module is configured to obtain the rising edge of the PPS signal, read the calibrated time information generated by the time resolution module at the rising edge of the PPS signal, and simultaneously obtain the PPS signal to synchronize the calibrated time information with the PPS signal. Furthermore, when the timekeeping module receives a correct PPS signal, it synchronizes the calibrated time information with the PPS signal at the rising edge of the PPS signal. When the timekeeping module fails to receive a correct PPS signal, it uses the 1 GHz clock signal generated by the clock multiplication module for timekeeping and generates a corresponding second PPS signal. Synchronization of the calibrated time information with the PPS signal is then performed until the correct PPS signal is received.

[0034] Furthermore, the nanosecond timestamp generation module uses the 1GHz clock signal transmitted by the timing module, the synchronized calibrated time information, and the pulse-seconds (PPS) signal to generate integer and fractional seconds. The integer seconds are incremented by one each time the PPS signal is received, based on the calibrated time information. The fractional seconds are reset to zero each time the PPS signal is received and incremented by one upon the rising edge of the 1GHz clock signal. Both integer and fractional seconds are stored in 32-bit registers, forming a 64-bit timestamp register.

[0035] Furthermore, if the time information is valid time information, the time validity flag in the status flag register in the time resolution module is set to valid, the time resolution module determines the time quality, leap seconds and time legitimacy of the time information, calibrates the time information, sends the calibrated time information and the value of the status flag register to the timekeeping module, and triggers the timekeeping module; otherwise, the time information is erroneous time information or invalid time information, the time resolution module sets the time validity flag in the status flag register to invalid, and when the timekeeping module receives the value of the time validity flag as invalid, the 1GHz clock signal generated by the clock multiplication module is used for timekeeping.

[0036] Furthermore, the calibrating the time information includes:

[0037] Obtain the time information t0, obtain the delay time t1 of the time information on the transmission path according to the baud rate of the serial port, obtain the leap second information t2 of the time information, and obtain the time t3 taken to resolve the time information;

[0038] The calibrated time information T=t0+t1+t2+t3.

[0039] In this embodiment, the time information and the pulse-second (PPS) signal are sent to the timekeeping module as the basis for synchronization. For example, the output real time is Tr, and the time Tb parsed by the time parsing module is always transmitted to the timekeeping module on the rising edge of the next pulse-second (PPS) signal. Therefore, Tr and the time Tb parsed by the time parsing module have the following corresponding relationship: Tr = Tb + 1s. This means that the parsed time is 1 second later than the actual time, so 1 second needs to be added to the output time. In addition, the GPS / BD signal contains leap seconds. When the parsed time contains leap seconds, 1 second is added or subtracted from the end of Tr to calibrate the time information. The time parsing module receives the GPS / BD signal via the serial port and sets a corresponding status flag based on the validity of the parsed time. If valid, the corresponding time is parsed and the validity is determined. The calibrated time is then provided to other modules for use.

[0040] In the present invention, when the parsed GPS / BD time information is invalid, the timekeeping module uses the 1GHz high-speed clock signal generated by the frequency multiplication module to generate a PPS signal, maintaining timekeeping until the parsed GPS / BD time information becomes valid. If the parsed GPS / BD time information is valid, the time information parsed from the GPS / BD message is calibrated to generate time information synchronized with the GPS / BD. In other words, when the time information corresponding to the time information in the GPS / BD signal becomes invalid, the time synchronization device automatically switches to using the PPS signal generated by the 1GHz high-precision clock generated by the frequency multiplication module.

[0041] like Figure 2 As shown, in this embodiment, when the timekeeping module is able to normally receive valid information from GPS / BD, the nanosecond timestamp generation module updates the integer second module on the rising edge of the second pulse PPS signal and clears the time and calendar information in the fractional second module. If no valid information from GPS / BD is received, the timekeeping module relies on the local clock for timekeeping, generates a second second pulse PPS signal, and corrects the second pulse PPS signal when the GPS / BD information is valid. The correction method is: 1) Calculate the number of second pulses n at 10 minutes based on the second pulse PPS signal; 2) The timekeeping clock is 1GHz, so theoretically the clock count within one second pulse PPS signal clock cycle is 1000M; 3) Calculate the theoretical timekeeping time T at the 10th minute 理论 =1000M×n; 4) Set the threshold to 25ns; when |t 实际 -t 理论 When |≤25, no treatment is performed;

[0042] When |T 实际 -T 理论 |>25, against T 实际 Compensation is performed. If t 实际 -t 理论 If t is a positive number, 实际 Subtract |t 实际 -T 理论 |; If T 实际 -T 理论 If T is negative, 实际 Add |T 实际 -t 理论 |.

[0043] Furthermore, the nanosecond time stamp module is connected to a device requiring time management via a backplane through an LVDS interface, so that the device can obtain the time stamp of the time synchronization device in real time.

[0044] In this embodiment, the time parsing module, the timekeeping module, the clock multiplication module, and the nanosecond timestamp generation module are all integrated into the same FPGA, and each module can be used independently.

[0045] In this embodiment, the FPGA is a minimal FPGA system, comprising a power supply circuit, a configuration circuit, an external high-precision crystal oscillator (125M, 10PPM), and peripheral hardware interface circuits such as LVDS. FPGA technology is widely used due to its logic reconfigurability without changing the hardware circuitry, particularly in the aerospace and aviation fields.

[0046] In a system, boards with different speeds are introduced simultaneously, requiring synchronized clock management for each board. Each application board is connected to the multi-channel nanosecond time synchronization device for FPGAs of this invention via an LVDS interface through the backplane. This allows each board to simultaneously access nanosecond timestamp information, similar to accessing a register. This eliminates the need for expensive high-precision crystal oscillators and clock management chips on each board, significantly reducing costs.

[0047] like Figure 3 As shown, the present invention proposes a method for using a multi-channel nanosecond time synchronization device for FPGA. The method is based on the multi-channel nanosecond time synchronization device for FPGA as described above, and the method includes the following steps:

[0048] Step S31: Acquire GPS / BD signals, parse time information in the GPS / BD signals, set a time validity flag register based on whether the parsed time is valid; and calibrate the parsed valid time information.

[0049] Step S32: triggering the timekeeping module to synchronize the calibrated time information with the pulse per second (PPS) signal from the GPS / BD receiving module;

[0050] Step S33: The nanosecond timestamp generation module uses the 1 GHz clock signal transmitted by the timekeeping module, the synchronized calibrated time information and the pulse per second (PPS) signal to generate integer seconds and fractional seconds to form a nanosecond timestamp.

[0051] The above specific embodiments merely illustrate the design principles of the present invention. The shapes and names of the components described herein may vary and are not limiting. Therefore, those skilled in the art may modify or substitute equivalents for the technical solutions described in the above embodiments. Such modifications and substitutions, without departing from the inventive spirit and technical solutions of the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A multi-channel nanosecond time synchronization device for FPGA, characterized in that: The time synchronization device includes a GPS / BD receiving module, a high-precision clock crystal oscillator module, a time analysis module, a timekeeping module, a clock multiplication module, and a nanosecond timestamp generation module; The time resolution module, timekeeping module, clock multiplication module, and nanosecond timestamp generation module are internally connected to the FPGA; the GPS / BD receiving module receives GPS / BD data, transmits it to the time resolution module through the serial port for resolution, and the resolved time is transmitted to the timekeeping module as the time reference; the high-precision crystal oscillator module is connected to the clock multiplication module, and the high-precision crystal oscillator module generates a 125Mhz clock, which is converted into a 1GHz high-speed clock after passing through the clock multiplication module; the timekeeping module uses the 1GHz high-speed clock to collect the pulse-second PPS signal from the GPS / BD receiving module to synchronize the calibrated time information with the pulse-second PPS signal; the nanosecond timestamp generation module obtains the 1GHz clock signal transmitted by the timekeeping module, the synchronized calibrated time information, and the pulse-second PPS signal, generates the integer seconds and fractional seconds required for the timestamp, and generates the timestamp based on the integer seconds and fractional seconds; The time parsing module is used to parse the GPS / BD data sent by the GPS / BD receiving module outside the FPGA and obtain the time information in the GPS / BD data; when the time information is valid, it calibrates the time information and sends the calibrated time information as the time reference to the timekeeping module; The timing module is used to obtain the rising edge of the second pulse PPS signal and read the calibrated time information generated by the time analysis module on the rising edge of the second pulse PPS signal; If the time information is valid, the time validity flag in the status flag register in the time resolution module is set to valid. The time resolution module determines the time quality, leap seconds, and time validity of the time information, calibrates the time information, sends the calibrated time information and the value of the status flag register to the timekeeping module, and triggers the timekeeping module. Otherwise, the time information is erroneous or invalid, and the time resolution module sets the time validity flag in the status flag register to invalid. When the timekeeping module receives the value of the time validity flag as invalid, it uses the 1GHz clock signal generated by the clock multiplication module to keep time. The nanosecond timestamp generation module uses the 1GHz clock signal transmitted by the timekeeping module, the synchronized calibrated time information and the second pulse PPS signal to generate integer seconds and fractional seconds; the integer seconds are counted by one each time the second pulse PPS signal is received based on the calibrated time information; the fractional seconds are cleared each time the second pulse PPS signal is received, and are counted by one when the rising edge of the 1GHz clock signal arrives.

2. The device according to claim 1, wherein in, The calibrating of the time information includes: Obtain the time information t0, obtain the delay time t1 of the time information on the transmission path according to the baud rate of the serial port, obtain the leap second information t2 of the time information, and obtain the time t3 taken to resolve the time information; The calibrated time information T=t0+t1+t2+t3.

3. The device according to claim 2, wherein When the timing module receives the correct second pulse PPS signal, the calibrated time information is synchronized with the second pulse PPS signal at the rising edge of the second pulse PPS signal; when the timing module fails to receive the correct second pulse PPS signal, the 1GHz clock signal generated by the clock multiplication module is used for timekeeping, and a corresponding second second pulse PPS signal is generated, until the correct second pulse PPS signal is received, the calibrated time information is synchronized with the second pulse PPS signal.

4. A method for using a multi-channel nanosecond time synchronization device for FPGA, characterized in that: The method of use is based on the multi-channel nanosecond time synchronization device for FPGA according to any one of claims 1 to 3, and the method of use comprises the following steps: Step S31: Acquire GPS / BD signals, parse time information in the GPS / BD signals, set a time validity flag register based on whether the parsed time is valid; and calibrate the parsed valid time information. Step S32: triggering the timekeeping module to synchronize the calibrated time information with the pulse per second (PPS) signal from the GPS / BD receiving module; Step S33: The nanosecond timestamp generation module uses the 1 GHz clock signal transmitted by the timekeeping module, the synchronized calibrated time information and the pulse per second (PPS) signal to generate integer seconds and fractional seconds to form a nanosecond timestamp.

5. A computer-readable storage medium, wherein a plurality of instructions are stored in the storage medium; the plurality of instructions are used for a processor to load and execute the method according to claim 4.

6. An electronic device, characterized in that: The electronic device comprises: A processor, which is used to execute multiple instructions; A memory for storing a plurality of instructions; The plurality of instructions are used to be stored in the memory and loaded and executed by the processor to execute the method according to claim 4.

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