SPI master interface with adaptive width

Abstract

The disclosed embodiments provide a width-adaptive SPI master interface, belonging to the field of circuit electronics, capable of implementing an SPI master function with an 8-bit bit width adaptive integer multiple. The width-adaptive SPI master interface is implemented based on an FPGA, and completes the handover with the CPU by setting and resetting the SPI busy flag, ensuring the integrity of the SPI data packet. A single pulse signal generated by a pulse generation unit is used as an enable condition to initiate SPI transmission and reception of 8-bit data basic units, achieving logical separation between the data protocol layer and the transport layer. The interface can adaptively implement 1-byte, 2-byte, 3-byte, and other SPI master functions, adapting to SPI slave peripherals with a variety of data protocols. The interface is highly flexible and versatile, and can be widely used in industrial fields.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit electronics, and in particular relates to a width-adaptive SPI master device interface. Background Art

[0002] The SPI bus is a commonly used standard serial bus interface with simple structure, minimal resource consumption, and high flexibility. It is often used for communication and control between processors and integrated circuits and is widely used in the electronic circuit field. However, typical CPUs have a limited number of SPI interfaces, and the timing of using the CPU's general-purpose I / O to expand the SPI interface is difficult to control, resulting in poor flexibility and applicability.

[0003] Currently, more and more people are leveraging the programmable features of FPGAs to expand SPI bus interfaces, greatly improving product integration. However, as application scenarios expand, IC SPI protocols are becoming increasingly complex to improve access efficiency. A typical feature is the gradual transition from fixed-bit-width SPI access to variable-bit-width SPI access. For example, the JFM25512 SPI serial EEPROM memory designed and produced by Fudan Microelectronics has an SPI bus bit width that varies from a single byte to 131 bytes depending on the instruction. This variable bit width and data protocol are not fixed. Summary of the Invention

[0004] In view of this, the present invention provides a width-adaptive SPI master device interface, which at least partially solves the problem in the prior art that data interaction between SPI master and slave devices cannot be variable and adaptive.

[0005] A width-adaptive SPI master interface is provided. It is based on an FPGA and enables interaction between a central processing unit (CPU) and an external SPI slave device. The SPI master interface is connected to the CPU via a local bus and to an SPI slave peripheral via a four-wire SPI bus. An 8-bit SPI bus width is used as a basic unit to implement a width-adaptive SPI master function. The SPI master interface includes an SPI busy flag, a pulse generation unit, a transmit data FIFO, a receive data FIFO, a clock generation unit, a transmit shift register, a receive shift register, an AND gate, and a NOT gate.

[0006] The SPI busy flag is used to feedback the status of the SPI master device interface. The SPI busy flag includes a set terminal S, a reset terminal R, and an output terminal Q, wherein the set terminal S is connected to the central processing unit through a local bus, the reset terminal R is connected to the output terminal of the AND gate, the output terminal Q is connected to the input terminal of the NOT gate, and the output terminal of the NOT gate is connected to the external SPI slave device through the MCSN signal;

[0007] The pulse generating unit includes an enable terminal EN, a start pulse output terminal pulse1, and an end pulse output terminal pulse2, wherein the enable terminal EN is connected to the output terminal Q of the SPI busy flag; the output terminal pulse2 of the end pulse is connected to an input terminal of the AND gate, and the start pulse output terminal pulse1 is connected to the clock generating unit, and the clock generating unit is connected to the external SPI slave device through the MCLK bus;

[0008] The transmit data FIFO is used to store transmit data and includes a data input terminal, a data output terminal, and an empty flag output terminal (empty), wherein the data input terminal is connected to the central processing unit via a local bus, the empty flag output terminal (empty) is connected to an input terminal of the AND gate, the data output terminal is connected to the input terminal of the transmit shift register, and the output terminal of the transmit shift register is connected to the external SPI slave device via a MOSI bus;

[0009] The received data FIFO is used to store received data and includes a data input terminal, a data output terminal and an empty flag output terminal empty, wherein the data output terminal and the empty flag output terminal empty are connected to the central processing unit through a local bus, the data input terminal is connected to the input terminal of the receiving shift register, and the output terminal of the receiving shift register is connected to the external SPI slave device through the MIOS bus;

[0010] The clock generation unit comprises an enable input terminal EN and a clock output terminal, wherein the enable input terminal EN is connected to the start pulse output terminal pulse1 of the pulse generation unit, and the clock output terminal is connected to the external SPI slave device through the MCLK signal and is connected to the trigger clock input terminals of the sending shift register and the receiving shift register;

[0011] While the sending shift register sends a signal to the external SPI slave device, the receiving shift register converts the serial data into parallel data and stores it in the receiving data FIFO. After all data transmission is completed, the empty flag input terminal empty of the sending FIFO is valid, and the SPI busy flag is reset to 0 through the AND gate. After the central processing unit reads the SPI busy flag as 0, it cyclically reads the receiving data FIFO until the empty flag output terminal empty of the receiving data FIFO is valid, and the current cycle ends. Moreover, after the start of the next communication cycle, the central processing unit splits the sending data into multiple bytes, cyclically writes them into the sending FIFO, and sets the SPI busy flag to 1, enabling the pulse generating unit to output the start pulse pulse1 and the end pulse pulse2. The start pulse pulse1 enables the clock generating unit to produce the MCLK clock signal. The MCLK clock signal drives the receiving shift register and the sending shift register to send and receive data.

[0012] Beneficial effects:

[0013] The method of the present invention completes the handover between a width-adaptive SPI master device and a CPU by setting and resetting an SPI busy flag, thereby ensuring the integrity of an SPI data packet. The method uses a single pulse signal generated by a pulse generating unit as an enabling condition to start the SPI transmission and reception of an 8-bit data basic unit, thereby achieving logical separation between a data protocol layer and a transmission layer. The method can adaptively implement 1-byte, 2-byte, 3-byte, etc. SPI master device functions, and is compatible with SPI slave device peripherals of various data protocols. The method has high flexibility and versatility, and can be widely used in industrial fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 This is the architecture diagram of the FPGA-based SPI interface expansion solution;

[0016] Figure 2 This is the architecture diagram of the SPI master device interface with adaptive width;

[0017] Figure 3 The flowchart of the working method of the SPI master device with adaptive width. DETAILED DESCRIPTION

[0018] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0019] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0020] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0021] like Figure 1 The adaptive SPI master device interface shown is based on FPGA for interaction between the central processing unit and the external SPI slave device. The SPI master device interface is connected to the central processing unit CPU through a local bus and is connected to the SPI slave device peripheral through a four-wire SPI bus. The 8-bit SPI bus width is used as the basic unit to realize the bit width adaptive SPI master device function. The SPI master device interface includes an SPI busy flag, a pulse generation unit, a transmit data FIFO, a receive data FIFO, a clock generation unit, a transmit shift register, a receive shift register, an AND gate and a NOT gate. The AND gate and the NOT gate refer to an AND gate circuit and a NOT gate circuit. The following are all represented by AND gates and NOT gates, where:

[0022] SPI busy flag, used to feedback the status of the SPI master device interface. The SPI busy flag includes a set terminal S, a reset terminal R, and an output terminal Q. The set terminal S is connected to the central processing unit through the local bus, the reset terminal R is connected to the output terminal of the AND gate, and the output terminal Q is connected to the input terminal of the NOT gate. The output terminal of the NOT gate is connected to the external SPI slave device through the MCSN signal.

[0023] The pulse generating unit includes an enable terminal EN, a start pulse output terminal pulse1, and an end pulse output terminal pulse2, wherein the enable terminal EN is connected to the output terminal Q of the SPI busy flag; the end pulse output terminal pulse2 is connected to an input terminal of the AND gate, and the start pulse output terminal pulse1 is connected to the clock generating unit. The clock generating unit is connected to the external SPI slave device through the MCLK bus;

[0024] The transmit data FIFO is used to store transmit data and includes a data input terminal, a data output terminal, and an empty flag output terminal (empty). The data input terminal is connected to the central processing unit via a local bus, the empty flag output terminal (empty) is connected to an input terminal of an AND gate, the data output terminal is connected to the input terminal of a transmit shift register, and the output terminal of the transmit shift register is connected to an external SPI slave device via a MOSI bus.

[0025] A receive data FIFO is used to store receive data and includes a data input terminal, a data output terminal, and an empty flag output terminal (empty). The data output terminal and the empty flag output terminal (empty) are connected to the central processing unit via a local bus, the data input terminal is connected to the receive shift register input terminal, and the receive shift register output terminal is connected to an external SPI slave device via a MIOS bus.

[0026] A clock generation unit, comprising an enable input terminal EN and a clock output terminal, wherein the enable input terminal EN is connected to the start pulse output terminal pulse1 of the pulse generation unit, and the clock output terminal is connected to the external SPI slave device through the MCLK signal and is connected to the trigger clock input terminals of the transmit shift register and the receive shift register;

[0027] While the sending shift register sends a signal to the external SPI slave device, the receiving shift register converts the serial data into parallel data and stores it in the receiving data FIFO. After all the data is sent, the empty flag input terminal of the sending FIFO is valid, and the SPI busy flag is reset to 0 through the AND gate. After the central processing unit reads the SPI busy flag as 0, it cyclically reads the receiving data FIFO until the empty flag output terminal of the receiving data FIFO is valid. The current cycle ends, and after the next communication cycle starts, the central processing unit splits the sending data into multiple bytes, writes them into the sending FIFO cyclically, and sets the SPI busy flag to 1, enabling the pulse generation unit to output the start pulse pulse1 and the end pulse pulse2. The start pulse pulse1 enables the clock generation unit to produce the MCLK clock signal. The MCLK clock signal drives the receiving shift register and the sending shift register to send and receive data.

[0028] When the sending shift register sends a signal to the external SPI slave device, the receiving shift register converts the serial to parallel, and after completing the data reception, the state of the output interface R is changed to 0 through the AND gate circuit. The central processing unit reads the state of the SPI busy flag as 0. At the end of the current cycle, the state of the SPI busy flag is assigned to the central processing unit as 1. The SPI busy flag is in a working state to adapt to the interaction with SPI slave devices of various data protocols.

[0029] As the specific implementation method provided in this case,

[0030] The SPI busy flag indicates whether the SPI master device interface is busy or idle. When the state is "1", it means that the SPI master device interface is busy. When the state is "0", it means that the SPI master device interface is idle.

[0031] The SPI busy flag is set by the central processing unit through the local bus and reset through the output of the AND gate. The SPI busy flag outputs the SPI chip select signal MCSN after passing through the NOT gate.

[0032] As the specific implementation method provided in this case,

[0033] The pulse generating unit further includes an enable input terminal EN, which is connected to the output terminal Q of the SPI busy flag. When the enable input terminal EN is at a high level, the pulse generating unit cyclically generates a start pulse pulse1 and an end pulse pulse2 with the 8-bit SPI bus width as a period, which are used to indicate the start and end of the 8-bit SPI bus communication;

[0034] The start pulse output terminal pulse1 of the pulse generating unit is connected to the enable input terminal EN of the clock generating unit, and the end pulse output terminal pulse2 is connected to one input terminal of the AND gate.

[0035] As the specific implementation method provided in this case,

[0036] The width of the transmit data FIFO is 8 bits, and the depth is equal to the maximum number of bytes of transmit data;

[0037] The transmit data FIFO includes a data input terminal, a data output terminal and an empty flag output terminal empty, wherein the data input terminal of the transmit data FIFO is connected to the local bus, the data output terminal of the transmit data FIFO is connected to the transmit shift register, and the empty flag output terminal empty of the transmit data FIFO is connected to an input terminal of the AND gate.

[0038] As a specific implementation provided in this case, the width of the received data FIFO is 8 bits, and the depth is equal to the maximum number of bytes of received data;

[0039] The receiving data FIFO includes a data input terminal, a data output terminal and an empty flag output terminal empty, wherein the data input terminal of the receiving data FIFO is connected to the output terminal of the receiving shift register, and the data output terminal of the receiving data FIFO and the empty flag output terminal empty of the receiving data FIFO are both connected to the local bus.

[0040] As a specific implementation method provided in this case, the clock generation unit includes an enable input terminal EN. When the enable pulse is valid, it generates an 8-bit SPI bus clock signal MCLK and simultaneously inputs it to the trigger clock terminals of the sending shift register and the receiving shift register.

[0041] As a specific implementation method provided in this case, the sending shift register is used to realize the parallel-to-serial conversion of the sending data, and includes a data input end, a data output end and a trigger clock end. The trigger clock end is used to trigger the data output end of the sending shift register to output data, and shift the output SPI serial data signal MOSI at the falling edge of the clock.

[0042] As a specific implementation method provided in this case, the receiving shift register is used to realize the serial-to-parallel conversion of the received data, and includes a data input terminal, a data output terminal and a trigger clock terminal, and shifts and collects the serial input signal MISO of the SPI at the rising edge of the clock.

[0043] It uses an 8-bit bit width to adapt to the SPI master device function, completes the handover with the CPU by setting and resetting the SPI busy flag, ensures the integrity of the SPI data packet, and uses the single pulse signal generated by the pulse generation unit as the enable condition to start the SPI transmission and reception of the 8-bit data basic unit, realizing the logical separation of the data protocol layer and the transport layer. It can adaptively implement 1-byte, 2-byte, 3-byte... SPI master device functions and adapt to SPI slave device peripherals of various data protocols. It has strong flexibility and versatility and can be widely used in industrial fields.

[0044] Secondly, a width adaptive SPI master device working method is provided. The width adaptive SPI master device working method runs in the CPU and specifically includes SPI sending operation and SPI receiving operation steps.

[0045] The SPI transmit operation includes the following steps:

[0046] Step 1: Read the SPI busy flag and determine whether the SPI busy flag is 1 (in the sending state). If the SPI busy flag is 1, it means that the SPI interface is busy, then continue with step 1, otherwise go to step 2;

[0047] Continuous access, if it is 1, continuous access, if it is 0, go to step 2;

[0048] Step 2: Split the transmitted data into multiple bytes in sequence according to the data protocol with the SPI slave device;

[0049] Step 3: Write the split data into the transmit FIFO in sequence;

[0050] Step 4: Set the SPI busy flag to 1;

[0051] The SPI receive operation includes the following steps:

[0052] Step 1: Read the SPI busy flag and determine whether the SPI busy flag is 0. If the SPI busy flag is 0, it means that the SPI interface is in idle state, then go to step 2, otherwise continue to step 1;

[0053] Step 2: Read the receive FIFO empty flag. If it is not empty, read the receive FIFO and continue with step 2. Otherwise, go to step 3.

[0054] Step 3: Parse and read data according to the data protocol with the SPI slave device.

[0055] Because the number of CPU SPI interfaces is limited and the timing when using I / O for expansion is difficult to expand, resulting in poor flexibility and versatility, more and more people use FPGA to expand the SPI interface to indirectly realize the control of the CPU to the SPI slave device. Its expansion architecture is as follows Figure 1 As shown, the CPU and FPGA are connected via a local bus, and the FPGA and SPI slave device are connected via an SPI bus, as shown in Figure 2As shown, it is specifically composed of an SPI busy flag, a pulse generation unit, a transmit data FIFO, a receive data FIFO, a clock generation unit, a transmit shift register and a receive shift register, an AND gate, and a NOT gate. Among them, the SPI busy flag is used to characterize the busy and idle states of the SPI bus interface, 1B1 indicates busy, and 1B0 indicates idle. The SPI busy flag can be set by the CPU through the local bus and can be reset by the output of the AND gate. The SPI busy flag outputs the SPI chip select signal MSCN after passing through the NOT gate; the pulse generation unit includes three pins: enable input, start pulse output, and end pulse output. When the enable input is high, the pulse generation unit generates start pulses and end pulses in a cycle with an 8-bit SPI bus width, which is used to indicate the start and end of the 8-bit SPI bus communication. The enable input of the pulse generation unit is connected to the SPI busy flag, the start pulse output is connected to the enable input of the clock generation unit, and the end pulse output is connected to the input of the AND gate; the transmit data FIFO is used to store transmit data, its width is 8 bits, and its depth is equal to the maximum number of bytes of transmit data. The port of the transmit data FIFO includes data input, data output, and empty flag output, wherein the data input is connected to the local bus, the data output is connected to the SPI bus, and the empty flag output is connected to the SPI bus. The output is connected to the output shift register, and the empty flag output is connected to another input pin of the AND gate; the receive data FIFO is used to store the received data, its bit width is 8 bits, and its depth is equal to the maximum number of bytes of the received data. The port of the receive data FIFO includes data input, data output and empty flag output, wherein the data input is connected to the output of the receive shift register, and the data output and empty flag output are both connected to the local bus; the clock generation unit includes an enable pulse input port. When the enable pulse is valid, an 8-bit SPI bus clock signal is generated and simultaneously input to the trigger clock ports of the transmit shift register and the receive shift register; the transmit shift register is used to realize parallel-to-serial conversion of the transmit data, and its port includes parallel data input, serial data output and trigger clock, and shifts and outputs the serial output signal of the SPI at the falling edge of the clock; the receive shift register is used to realize serial-to-parallel conversion of the receive data, and its port includes serial data input, parallel data output and trigger clock, and shifts and collects the serial input signal of the SPI at the rising edge of the clock.

[0056] Its working method, the width adaptive SPI master device working method runs in the CPU, specifically including SPI sending operation and SPI receiving operation, its process is as follows Figure 3 As shown in the figure, the SPI sending operation includes the following steps:

[0057] (1) Read the SPI busy flag and determine whether the SPI busy flag is 1. If the SPI busy flag is 1, it means that the SPI interface is busy, then continue to step 1, otherwise go to step 2;

[0058] (2) Split the transmitted data into multiple bytes in sequence according to the data protocol with the SPI slave device;

[0059] (3) Write the split data into the transmit FIFO in sequence;

[0060] (4) Set the SPI busy flag to 1.

[0061] The SPI receive operation includes the following steps: (1) reading the SPI busy flag and determining whether the SPI busy flag is 0. If the SPI busy flag is 0, indicating that the SPI interface is in the idle state, then go to step 2, otherwise continue to step 1; (2) reading the receive FIFO empty flag. If it is not empty, then read the receive FIFO and continue to step 2, otherwise go to step 3; (3) parsing and reading data according to the data protocol with the SPI slave device.

[0062] This article takes the 3-byte write and read operations of the JFM25512 SPI serial EEPROM memory designed and produced by Fudan Microelectronics as an example to further explain the width-adaptive SPI master device interface and its working method. The JFM25512 supports byte-by-byte access, and the maximum number of bytes can be 128.

[0063] When the CPU needs to write 0H55, 0HAA, and 0H5A to the addresses 0H0000, 0H0001, and 0H0002 of JFM25512 respectively, the steps are as follows:

[0064] Step 1: The CPU reads the SPI busy flag and determines whether the SPI busy flag is 1. If it is 1, it means that the SPI master device interface is busy. At this time, the CPU loops and queries until the SPI busy flag is 0 and then proceeds to step 2;

[0065] Step 2: The CPU writes 0H55, 0HAA, and 0H5A to the JFM25512's 0H0000, 0H0001, and 0H0002 addresses, respectively, which is equivalent to continuously writing 3 bytes of data 0H55AA5A to the 0X0000 address. According to the JFM25512 write operation protocol, the SPI operation data contains the command (0H02), address (0H0000), and data (0H55AA5A) in sequence. The CPU splits the transmitted data into 6 bytes and proceeds to step 4.

[0066] Step 4: After writing the data into the transmit FIFO in sequence, go to step 5;

[0067] Step 5: The CPU sets the SPI busy flag to 1 via the local bus, indicating the end of the CPU operation and allowing the SPI master interface to perform a transmit operation. At this point, the SPI master's transmit FIFO contains six bytes sequentially stored: 0H02, 0H00, 0H00, 0H55, 0HAA, and 0H5A. The transmit FIFO's data output is connected to the transmit shift register's data input. When the CPU sets the SPI busy flag to 1, it is fed into the NOT gate, generating an active-low SPI bus chip select signal, MCSN, initiating the SPI transmit operation. The SPI busy flag is fed into the enable pin of the pulse generator, which generates start and end pulses with a single-byte SPI bus width as a period. The start pulse is fed into the clock generator, triggering the generation of the 8-bit SPI bus clock signal, MCLK. The SPI bus clock signal, MCLK, is also fed into the clock pin of the transmit shift register, triggering the transmit shift register to shift the first byte, 0x02, from the transmit FIFO at the falling edge of MCLK, generating the SPI serial output signal, MOSI. The SPI master device loops this operation until the last byte 0H5A in the transmit FIFO is output, and the empty flag of the transmit FIFO is set to 1. When the last byte 0X5A is shifted and output, the pulse generation unit outputs the last end pulse. The empty flag of the transmit FIFO and the end pulse output by the pulse generation unit are input to the AND gate. At this time, the AND gate outputs a high-level pulse, setting the SPI busy flag to 0, and the NOT gate sets MCLK high, and the SPI send operation ends.

[0068] When the CPU needs to read the data at addresses 0H0000, 0H0001, and 0H0002 of JFM25512, the steps are as follows:

[0069] Step 1: The CPU reads the SPI busy flag and determines whether the SPI busy flag is 1. If it is 1, it means that the SPI master device interface is busy. At this time, the CPU loops and queries until the SPI busy flag is 0 and then proceeds to step 2;

[0070] Step 2: According to the read operation protocol of JFM25512, the SPI operation data includes command (0H03), address (0H0000) and data (0HXXXX, only used for padding). The CPU splits the transmit data into 6 bytes and writes them into the transmit FIFO in sequence before proceeding to step 3.

[0071] Step 3: The CPU sets the SPI busy flag to 1 via the local bus, indicating that the CPU operation is complete and the SPI master interface can perform a transmit operation. At this point, the transmit FIFO in the SPI master stores six bytes in sequence: 0H02, 0H00, 0H00, 0HXX, 0HXX, and 0HXX. The data output of the transmit FIFO is connected to the data input of the transmit shift register. When the CPU sets the SPI busy flag to 1, the SPI busy flag is input to the NOT gate, generating a low-level valid SPI bus chip select signal MCSN, starting the SPI receive operation; the SPI busy flag is input to the enable pin of the pulse generation unit, enabling the pulse generation unit to generate a start pulse and an end pulse with a single-byte SPI bus width as a period; the start pulse is input to the clock generation unit to trigger the generation of the 8-bit SPI bus clock signal MCLK; the SPI bus clock signal MCLK is simultaneously input to the clock pin of the transmit shift register, triggering the transmit shift register to shift the first byte 0X03 in the transmit FIFO and output it at the falling edge of MCLK, generating the SPI serial output signal MOSI; the SPI bus clock signal MCLK is simultaneously input to the clock pin of the receive shift register, triggering the receive shift register to shift the SPI serial data MISO into it at the rising edge of the clock, generating parallel data and writing it into the receive FIFO, completing the 1-byte SPI operation. The SPI master device loops this operation until the last byte 0HXX in the transmit FIFO is output, and the empty flag of the transmit FIFO is set to 1. When the last byte 0XXX is shifted and output, the pulse generation unit outputs the last end pulse. The empty flag of the transmit FIFO and the end pulse output by the pulse generation unit are input to the AND gate. At this time, the AND gate outputs a high-level pulse, setting the SPI busy flag to 0, and the NOT gate sets MCLK high, and the SPI send operation ends.

[0072] Step 4: The CPU reads the SPI busy flag cyclically until the SPI busy flag is 0, indicating that the SPI operation is completed, and then proceeds to step 5;

[0073] Step 5: The CPU reads the receive FIFO in a loop until the empty flag of the receive FIFO is 1;

[0074] Step 6: Analyze the read data according to the data protocol and make final confirmation.

[0075] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A width-adaptive SPI master interface for interaction between a central processing unit and an external SPI slave device based on an FPGA, characterized in that: The SPI master interface is connected to the central processing unit (CPU) via a local bus and to the SPI slave peripherals via a four-wire SPI bus. The SPI master interface uses an 8-bit SPI bus width as a basic unit to implement a bit-width adaptive SPI master function. The SPI master interface includes an SPI busy flag, a pulse generation unit, a transmit data FIFO, a receive data FIFO, a clock generation unit, a transmit shift register, a receive shift register, an AND gate, and a NOT gate. The SPI busy flag is used to feedback the status of the SPI master device interface. The SPI busy flag includes a set terminal S, a reset terminal R, and an output terminal Q, wherein the set terminal S is connected to the central processing unit through a local bus, the reset terminal R is connected to the output terminal of the AND gate, the output terminal Q is connected to the input terminal of the NOT gate, and the output terminal of the NOT gate is connected to the external SPI slave device through the MCSN signal; The pulse generating unit includes an enable terminal EN, a start pulse output terminal pulse1, and an end pulse output terminal pulse2, wherein the enable terminal EN is connected to the output terminal Q of the SPI busy flag; the output terminal pulse2 of the end pulse is connected to an input terminal of the AND gate, and the start pulse output terminal pulse1 is connected to the clock generating unit, and the clock generating unit is connected to the external SPI slave device through the MCLK bus; The transmit data FIFO is used to store transmit data and includes a data input terminal, a data output terminal, and an empty flag output terminal (empty), wherein the data input terminal is connected to the central processing unit via a local bus, the empty flag output terminal (empty) is connected to an input terminal of the AND gate, the data output terminal is connected to the input terminal of the transmit shift register, and the output terminal of the transmit shift register is connected to the external SPI slave device via a MOSI bus; The received data FIFO is used to store received data and includes a data input terminal, a data output terminal and an empty flag output terminal empty, wherein the data output terminal and the empty flag output terminal empty are connected to the central processing unit through a local bus, the data input terminal is connected to the input terminal of the receiving shift register, and the output terminal of the receiving shift register is connected to the external SPI slave device through the MIOS bus; The clock generation unit comprises an enable input terminal EN and a clock output terminal, wherein the enable input terminal EN is connected to the start pulse output terminal pulse1 of the pulse generation unit, and the clock output terminal is connected to the external SPI slave device through the MCLK signal and is connected to the trigger clock input terminals of the sending shift register and the receiving shift register; While the sending shift register sends a signal to the external SPI slave device, the receiving shift register converts the serial data into parallel data and stores it in the receiving data FIFO. After all data transmission is completed, the empty flag input terminal empty of the sending FIFO is valid, and the SPI busy flag is reset to 0 through the AND gate. After the central processing unit reads the SPI busy flag as 0, it cyclically reads the receiving data FIFO until the empty flag output terminal empty of the receiving data FIFO is valid, and the current cycle ends. Moreover, after the start of the next communication cycle, the central processing unit splits the sending data into multiple bytes, cyclically writes them into the sending FIFO, and sets the SPI busy flag to 1, enabling the pulse generating unit to output the start pulse pulse1 and the end pulse pulse2. The start pulse pulse1 enables the clock generating unit to produce the MCLK clock signal. The MCLK clock signal drives the receiving shift register and the sending shift register to send and receive data.

2. The width adaptive SPI master interface according to claim 1, wherein: The SPI busy flag indicates whether the SPI master interface is busy or idle. When the state is "1", it indicates that the SPI master interface is busy. When the state is "0", it indicates that the SPI master interface is idle. The SPI busy flag is set by the central processing unit through the local bus and reset by the output of the AND gate. The SPI busy flag outputs the SPI chip select signal MCSN after passing through the NOT gate.

3. The width adaptive SPI master interface according to claim 1, wherein: The pulse generating unit further includes an enable input terminal EN, which is connected to the output terminal Q of the SPI busy flag. When the enable input terminal EN is at a high level, the pulse generating unit cyclically generates a start pulse pulse1 and an end pulse pulse2 with an 8-bit SPI bus width as a period, for indicating the start and end of the 8-bit SPI bus communication; The start pulse output terminal pulse1 of the pulse generating unit is connected to the enable input terminal EN of the clock generating unit, and the end pulse output terminal pulse2 is connected to one input terminal of the AND gate.

4. The width adaptive SPI master device interface according to claim 1, characterized in that: The width of the transmit data FIFO is 8 bits, and the depth is equal to the maximum number of bytes of transmit data; The transmit data FIFO includes a data input terminal, a data output terminal and an empty flag output terminal empty, wherein the data input terminal of the transmit data FIFO is connected to the local bus, the data output terminal of the transmit data FIFO is connected to the transmit shift register, and the empty flag output terminal empty of the transmit data FIFO is connected to an input terminal of the AND gate.

5. The width adaptive SPI master device interface according to claim 1, characterized in that: The bit width of the received data FIFO is 8 bits, and the depth is equal to the maximum number of bytes of received data; The receive data FIFO includes a data input terminal, a data output terminal and an empty flag output terminal empty, wherein the data input terminal of the receive data FIFO is connected to the output terminal of the receive shift register, and the data output terminal of the receive data FIFO and the empty flag output terminal empty of the receive data FIFO are both connected to the local bus.

6. The width adaptive SPI master device interface according to claim 1, characterized in that: The clock generating unit comprises an enable input terminal EN. When the enable pulse is valid, it generates an 8-bit SPI bus clock signal MCLK and simultaneously inputs it into the trigger clock terminals of the transmitting shift register and the receiving shift register.

7. The width adaptive SPI master interface according to claim 1, wherein: The transmitting shift register is used to realize parallel-to-serial conversion of transmitting data, and comprises a data input terminal, a data output terminal and a trigger clock terminal, and shifts and outputs the serial data signal MOSI of SPI at the falling edge of the clock.

8. The width adaptive SPI master interface according to claim 1, wherein: The receiving shift register is used to realize serial-to-parallel conversion of received data, comprises a data input terminal, a data output terminal and a trigger clock terminal, and shifts and collects the serial input signal MISO of SPI at the rising edge of the clock.

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