A GOA unit, a circuit, a driving method thereof, and a display device

Abstract

The present application discloses a GOA unit, a circuit, a driving method thereof, and a display device, including a first capacitor and a plurality of modules. The plurality of modules include a pull-up module, a first reset module, an output module, an inverter module, a pull-down driving module, and a noise reduction module. Among them, the noise reduction module is connected to the pull-down node, a noise reduction input terminal, and the pull-up node, and is configured to input the voltage of the noise reduction input terminal to the pull-up node under the control of the pull-down node. By adding a noise reduction module to the pull-up node, during the charging stage, the pull-down node does not compete, but instead promotes the charging of the pull-up node, improving the charging effect of the pull-up node; during the reset stage, the noise reduction module can also be used to assist in discharging the pull-up node, improving the discharging effect of the pull-up node, thereby greatly improving the long-term stability of the GOA and further improving the display effect.

Description

Technical Field

[0001] This application generally relates to the field of display technology, and particularly to a GOA unit, a circuit, a driving method thereof, and a display device. Background Art

[0002] With the development of the display industry, narrow-bezel display devices have become increasingly popular. To implement a narrow-bezel display substrate, a GOA (Gate Driver on Array) unit is usually used to replace the original gate driver chip.

[0003] In existing GOA designs, an inverter is generally used to implement the pull-up of the PU (Pull Up) node and the pull-down of the PD (Pull Down) node. During the PU charging stage (INPUT stage), there is a risk that the PD node competes and pulls down the PU node, resulting in a charging failure, which affects GOA charging. In addition, during the PU charging and holding stages, there is a leakage path, causing the potential of the PU node to be insufficient, which is also likely to lead to abnormal output of the GOA and affect normal display. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a GOA unit, a circuit, a driving method thereof, and a display device, which can effectively improve the GOA charging effect and greatly enhance the long-term stability of the GOA.

[0005] In a first aspect, this application provides a GOA unit, including a first capacitor and a plurality of modules. The plurality of modules include a pull-up module, a first reset module, an output module, an inverter module, a pull-down driving module, and a noise reduction module. Among them,

[0006] A first end of the first capacitor is connected to a pull-up node, and a second end of the first capacitor is connected to a signal output terminal;

[0007] The pull-up module is connected to the pull-up node, a first voltage terminal, and a signal input terminal, and is configured to input the voltage of the first voltage terminal to the pull-up node under the control of the signal input terminal;

[0008] The first reset module is connected to a first reset signal terminal, a second voltage terminal, and the pull-up node, and is configured to input the voltage of the second voltage terminal to the pull-up node under the control of the first reset signal terminal;

[0009] The output module is connected to the pull-up node, a clock signal terminal, and the signal output terminal, and is configured to output the voltage of the clock signal terminal to the signal output terminal under the control of the pull-up node;

[0010] The inverting module is connected to the pull-up node and the pull-down node, and is configured to input a voltage with a phase opposite to that of the pull-up node to the pull-down node under the control of the pull-up node;

[0011] The pull-down driving module is connected to the third voltage terminal, the pull-down node, and the second end of the first capacitor, and is configured to input the voltage of the third voltage terminal to the second end of the first capacitor under the control of the pull-down node;

[0012] The noise reduction module is connected to the pull-down node, the noise reduction input terminal, and the pull-up node, and is configured to input the voltage of the noise reduction input terminal to the pull-up node under the control of the pull-down node.

[0013] Optionally, each of the modules includes one or more transistors. Among them, the modules in which the source-drain electrodes of the transistors are connected to the pull-up node all adopt a series circuit. The series circuit includes a secondary transistor connected in series with the transistor. In each of the series circuits, the secondary transistor and the transistor are connected in series at the holding node, and the source-drain electrode of the transistor is the first end or the second end.

[0014] Optionally, a second capacitor is further included. The first end of the second capacitor is connected to the holding node, and the second end of the second capacitor is connected to the second voltage terminal.

[0015] Optionally, the pull-up module includes a first transistor and a first-order transistor connected in series with the first transistor. The first end of the first transistor and the second end of the first-order transistor are connected to the holding node. The second end of the first transistor is connected to the pull-up node. The first end of the first-order transistor is connected to the first voltage terminal. The control terminals of the first transistor and the first-order transistor are both connected to the signal output terminal;

[0016] The first reset module includes a second transistor and a second-order transistor connected in series with the second transistor. The first end of the second transistor is connected to the pull-up node. The second end of the second transistor and the first end of the second-order transistor are connected to the holding node. The second end of the second-order transistor is connected to the second voltage terminal. The control terminals of the second transistor and the second-order transistor are both connected to the first reset signal terminal;

[0017] The output module includes a third transistor. The first end of the third transistor is connected to the clock signal terminal. The second end of the third transistor is connected to the signal output terminal. The control terminal of the third transistor is connected to the pull-up node;

[0018] The pull-down driving module includes a fourth transistor. The first end of the fourth transistor is connected to the second end of the first capacitor. The second end of the fourth transistor is connected to the third voltage terminal. The control terminal of the fourth transistor is connected to the pull-down node;

[0019] The noise reduction module includes a fifth transistor and a fifth-order transistor connected in series with the fifth transistor. A first end of the fifth transistor is connected to the pull-up node. A second end of the fifth transistor and a first end of the fifth-order transistor are connected to the holding node. A second end of the fifth-order transistor is connected to the noise reduction input terminal. Control terminals of the fifth transistor and the fifth-order transistor are both connected to the pull-down node.

[0020] Optionally, a second reset module is further included. The second reset module is connected to a third voltage terminal, the pull-up node, and a second reset signal terminal, and is configured to input a voltage of the third voltage terminal to the pull-up node under the control of the second reset signal terminal; wherein,

[0021] The second reset module includes a sixth transistor and a sixth-order transistor connected in series with the sixth transistor. A first end of the sixth transistor is connected to the pull-up node. A second end of the sixth transistor and a first end of the sixth-order transistor are connected to the holding node. A second end of the sixth-order transistor is connected to the third voltage terminal. Control terminals of the sixth transistor and the sixth-order transistor are both connected to the second reset signal terminal.

[0022] Optionally, a signal of the noise reduction input terminal is the same as one of a signal of the second voltage terminal, a signal of the third voltage terminal, and a signal of the signal input terminal.

[0023] Optionally, a first holding module is further included. The first holding module is connected to a first node, a second node, and the pull-up node, and is configured to input a voltage of the first node to the second node under the control of the pull-up node. Wherein, the transistor and the sub-transistor of the pull-up module and the transistor and the sub-transistor of the first reset module are both connected in series at the first node, the transistor and the sub-transistor of the noise reduction module are connected in series at the second node, and a first end of the second capacitor is connected to the first node or the second node.

[0024] Optionally, the first holding module includes a seventh transistor. A first end of the seventh transistor is connected to the second node. A second end of the seventh transistor is connected to the first node. A control terminal of the seventh transistor is connected to the pull-up node; wherein,

[0025] A first end of the first transistor and a second end of the first-order transistor, a second end of the second transistor and a first end of the second-order transistor are connected to the first node; a second end of the fifth transistor and a first end of the fifth-order transistor are connected to the second node.

[0026] Optionally, it further includes a third capacitor and a second holding module. The second holding module is connected to the first node, the second node, and the signal input terminal, and is configured to input the voltage of the first node to the second node under the control of the pull-up node. Wherein, the transistors and sub-transistors of the pull-up module and the transistors and sub-transistors of the first reset module are connected in series at the first node, the transistors and sub-transistors of the noise reduction module are connected in series at the second node, the first end of the second capacitor is connected to the first node, the first end of the third capacitor is connected to the second node, and the second end of the third capacitor is connected to the third voltage terminal.

[0027] Optionally, the second holding module includes an eighth transistor. The first end of the eighth transistor is connected to the second node, the second end of the eighth transistor is connected to the first node, and the control end of the eighth transistor is connected to the signal input terminal. Wherein,

[0028] The first end of the first transistor and the second end of the first sub-transistor, the second end of the second transistor and the first end of the second sub-transistor are connected to the first node; the second end of the fifth transistor and the first end of the fifth sub-transistor are connected to the second node.

[0029] Optionally, it further includes a third holding module. The third holding module is connected to the holding node, the fourth voltage terminal, and the pull-up node, and is configured to input the voltage of the fourth voltage terminal to the holding node under the control of the pull-up node.

[0030] Optionally, the third holding module includes a ninth transistor. The first end of the ninth transistor is connected to the fourth voltage terminal, the second end of the ninth transistor is connected to the holding node, and the control end of the ninth transistor is connected to the pull-up node.

[0031] In a second aspect, the present application provides a driving method for a GOA unit, using the GOA unit as described in any one of the above. The method includes a first stage, a second stage, and a third stage:

[0032] In the first stage, the signal input terminal is at a high level, the clock signal terminal is at a low level, and the pull-up module inputs the high level of the first voltage terminal to the pull-up node under the control of the signal input terminal, so that the potential of the pull-up node is raised and the potential of the pull-down node is lowered; during the process of lowering the potential of the pull-down node, the noise reduction module assists in charging the pull-up node under the control of the pull-down node;

[0033] In the second stage, the signal input terminal is at a low level, the clock signal terminal is at a high level, and the output module inputs the high level of the clock signal terminal to the signal output terminal and the second terminal of the first capacitor under the control of the pull-up node, and the potential of the pull-up node is further raised by the bootstrap of the first capacitor;

[0034] In the third stage, the first reset signal terminal is at a high level, and the first reset module inputs the low level of the second voltage terminal to the pull-up node under the control of the first reset signal terminal, so that the potential of the pull-up node is pulled down and the potential of the pull-down node is pulled up; the pull-down driving module outputs the voltage of the third voltage terminal to the signal output terminal under the control of the pull-down node; the noise reduction module performs auxiliary discharge on the pull-up node under the control of the pull-down node.

[0035] In a third aspect, the present application provides a GOA driving circuit, including at least two cascaded GOA units, and each of the GOA units is the GOA unit as described in any one of the above.

[0036] In a fourth aspect, the present application provides a display device, including the GOA unit as described in any one of the above.

[0037] The technical solutions provided in the embodiments of the present application may include the following beneficial effects:

[0038] The GOA unit provided in the embodiment of the present application adds a noise reduction module to the pull-up node, so that in the charging stage, the pull-down node does not compete, but promotes the charging of the pull-up node, improving the charging effect of the pull-up node; in the reset stage, the noise reduction module can also be used to achieve the auxiliary discharge of the pull-up node, improving the discharge effect of the pull-up node, thereby greatly improving the long-term stability of the GOA and further improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects, and advantages of the present application will become more obvious:

[0040] Figure 1 It is a schematic structural diagram of a GOA unit provided in an embodiment of the present application;

[0041] Figure 2 It is a schematic connection diagram of a GOA unit provided in an embodiment of the present application;

[0042] Figure 3 It is a timing schematic diagram of a GOA unit driving method provided in an embodiment of the present application;

[0043] Figures 4 - 6A state schematic diagram of a GOA unit provided by an embodiment of the present application;

[0044] Figure 7 A simulation effect diagram of a GOA unit provided by an embodiment of the present application;

[0045] Figures 8 - 12 A connection schematic diagram of a GOA unit provided by an embodiment of the present application;

[0046] Figure 13 A connection schematic diagram of a GOA driving circuit provided by an embodiment of the present application. Detailed implementation manners

[0047] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention, rather than limiting the invention. Additionally, it should be noted that for the convenience of description, only the parts related to the invention are shown in the drawings.

[0048] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and embodiments.

[0049] Please refer to Figure 1 , the present application provides a GOA unit, including a first capacitor C1 and a plurality of modules. The plurality of modules include a pull-up module 100, a first reset module 200, an output module 300, an inverter module 400, a pull-down driving module 500, and a noise reduction module 600. Among them,

[0050] The first end of the first capacitor C1 is connected to the pull-up node PU, and the second end of the first capacitor C1 is connected to the signal output terminal Output;

[0051] The pull-up module 100 is connected to the pull-up node PU, the first voltage terminal VDD1, and the signal input terminal Input, and is used to input the voltage of the first voltage terminal VDD1 to the pull-up node PU under the control of the signal input terminal Input;

[0052] The first reset module 200 is connected to the first reset signal terminal Reset, the second voltage terminal VSS1, and the pull-up node PU, and is used to input the voltage of the second voltage terminal VSS1 to the pull-up node PU under the control of the first reset signal terminal Reset;

[0053] The output module 300 is connected to the pull-up node PU, the clock signal terminal CLK, and the signal output terminal Output, and is used to output the voltage of the clock signal terminal CLK to the signal output terminal Output under the control of the pull-up node PU;

[0054] The inverting module 400 is connected to the pull-up node PU and the pull-down node PD, and is configured to input a voltage opposite in phase to that of the pull-up node PU to the pull-down node PD under the control of the pull-up node PU;

[0055] The pull-down driving module 500 is connected to the third voltage terminal VSS2, the pull-down node PD, and the second terminal of the first capacitor C1, and is configured to input the voltage of the third voltage terminal VSS2 to the second terminal of the first capacitor C1 under the control of the pull-down node PD;

[0056] The noise reduction module 600 is connected to the pull-down node PD, the noise reduction input terminal IN_put, and the pull-up node PU, and is configured to input the voltage of the noise reduction input terminal IN_put to the pull-up node PU under the control of the pull-down node PD.

[0057] In the charging stage of the PU node, if the noise reduction module 600 in this application does not exist, there will be a PU&PD competition hazard. When the input signal decays to a certain extent and the PU is weak and unable to pull down the PD, it will cause the PD to limit the charging of the PU, which is likely to cause abnormal output of the GOA. In this application, adding the noise reduction module 600 to the PU node enables the PD not to compete during the PU charging stage, but instead promotes the charging of the PU, improving the charging effect of the PU; in the reset stage, the noise reduction module 600 can also be used to assist in discharging the PU node, improving the discharging effect of the PU, thereby greatly enhancing the long-term stability of the GOA.

[0058] In the embodiments of this application, each of the modules includes one or more transistors. Among them, the modules in which the source and drain electrodes of the transistors are connected to the pull-up node PU all adopt a series circuit. The series circuit includes a secondary transistor connected in series with the transistor. In each of the series circuits, the secondary transistor and the transistor are both connected in series at the holding node N0, and the source and drain electrodes of the transistor are the first end or the second end.

[0059] In the PU charging and PU holding stages, if there is a leakage path, causing the potential of the PU to be insufficient, it is also likely to cause abnormal output of the GOA. In this application, all the modules related to the PU leakage are designed with two TFTs in series. The potential trend of the series node is similar to that of the PU, so as to ensure that one of the TFTs in the relevant module can be completely turned off, thus there is no leakage path.

[0060] In the present application, the type and quantity of the module connecting the source and drain to the pull-up node PU are not limited. In the embodiments of the present application, it is exemplified that the pull-up module 100, the first reset module 200, and the noise reduction module 600 all adopt a series circuit, and can be selectively set according to needs in specific applications. Of course, more module types can also be included. For example, the second reset module 700 exemplified in the present application. Of course, since all modules with the source and drain connected to PU can adopt the way of connecting two TFTs in series, one of the TFTs in the relevant sub-circuit can be completely turned off, so that there is no leakage current path in the GOA unit, improving the driving effect. The following will be described by way of examples.

[0061] In the embodiments of the present invention, the pull-up node PU, the pull-down node PD, the holding node N0, the first node N1, and the second node N2 do not represent actually existing components, but represent the convergence points of relevant circuit connections in the circuit diagram.

[0062] In the embodiments of the present invention, the control terminal of each module is connected to the gate of the thin film transistor, the input terminal is connected to the source of the thin film transistor, and the output terminal is connected to the drain of the thin film transistor. Of course, it is also possible that the control terminal of each module is connected to the gate of the thin film transistor, the input terminal is connected to the drain of the thin film transistor, and the output terminal is connected to the source of the thin film transistor. The embodiments of the present invention do not make a limitation.

[0063] In the embodiments of the present invention, the source and drain of the thin film transistor adopted can be symmetric in structure, so there can be no difference between its source and drain in structure. In the embodiments of the present disclosure, the gate of the thin film transistor is described as the control terminal. In order to distinguish the two poles (source and drain) of the transistor other than the gate, one of the poles is directly described as the first terminal and the other as the second terminal.

[0064] Embodiment 1

[0065] In this embodiment, as Figure 2 shown, the pull-up module 100 includes a first transistor M1A and a first time transistor M1B connected in series with the first transistor M1A. The first terminal of the first transistor M1A and the second terminal of the first time transistor M1B are connected to the holding node N0. The second terminal of the first transistor M1A is connected to the pull-up node PU. The first terminal of the first time transistor M1B is connected to the first voltage terminal VDD1. The control terminals of the first transistor M1A and the first time transistor M1B are both connected to the signal input terminal Input.

[0066] The first reset module 200 includes a second transistor M2A and a second-order transistor M2B connected in series with the second transistor M2A. A first end of the second transistor M2A is connected to the pull-up node PU. A second end of the second transistor M2A and a first end of the second-order transistor M2B are connected to the holding node N0. A second end of the second-order transistor M2B is connected to a second voltage terminal VSS1. Control ends of the second transistor M2A and the second-order transistor M2B are both connected to the first reset signal terminal Reset.

[0067] The output module 300 includes a third transistor M3. A first end of the third transistor M3 is connected to the clock signal terminal CLK. A second end of the third transistor M3 is connected to the signal output terminal Output. A control end of the third transistor M3 is connected to the pull-up node PU.

[0068] The pull-down driving module 500 includes a fourth transistor M4. A first end of the fourth transistor M4 is connected to a second end of a first capacitor C1. A second end of the fourth transistor M4 is connected to a third voltage terminal VSS2. A control end of the fourth transistor M4 is connected to the pull-down node PD.

[0069] The noise reduction module 600 includes a fifth transistor M5A and a fifth-order transistor M5B connected in series with the fifth transistor M5A. A first end of the fifth transistor M5A is connected to the pull-up node PU. A second end of the fifth transistor M5A and a first end of the fifth-order transistor M5B are connected to the holding node N0. A second end of the fifth-order transistor M5B is connected to the noise reduction input terminal IN_put. Control ends of the fifth transistor M5A and the fifth-order transistor M5B are both connected to the pull-down node PD.

[0070] It can be understood that in the embodiments of the present application, the specific structure of the inverting module 400 is not limited. The inverting module 400 may adopt various different inverter circuits in the prior art. In the present application, the inverting module 400 is simplified to an inverter symbol and is selected according to different devices or application scenarios in different embodiments.

[0071] Optionally, the GOA unit further includes a second reset module 700, which is used to perform a total reset on each GOA unit at the last stage of each frame display, and is selectively set according to needs in different embodiments, and the present application does not limit this. The second reset module 700 is connected to the third voltage terminal VSS2, the pull-up node PU, and the second reset signal terminal Total_Reset, and is used to input the voltage of the third voltage terminal VSS2 to the pull-up node PU under the control of the second reset signal terminal Total_Reset. In the embodiment of the present application, it is preferably that all modules with source-drain electrodes connected to PU can adopt the method of two TFTs connected in series. Therefore, the second reset module 700 also adopts a series circuit.

[0072] Specifically, the second reset module 700 includes a sixth transistor M6A and a sixth-order transistor M6B connected in series with the sixth transistor M6A. The first end of the sixth transistor M6A is connected to the pull-up node PU, the second end of the sixth transistor M6A and the first end of the sixth-order transistor M6B are connected to the holding node N0, the second end of the sixth-order transistor M6B is connected to the third voltage terminal VSS2, and the control ends of the sixth transistor M6A and the sixth-order transistor M6B are both connected to the second reset signal terminal Total_Reset.

[0073] It should be noted that the thin-film transistors TFTs in the embodiments of the present invention can all be N-type TFTs, or all be P-type TFTs, or the thin-film transistors TFTs in the embodiments are N-type TFTs and P-type TFTs. Specifically, in the embodiments of the present invention, the thin-film transistors TFTs are all N-type TFTs as an example for detailed description, and all TFTs are turned on when the gate voltage is high and turned off when the gate voltage is low.

[0074] In this embodiment, the GOA unit further includes a second capacitor C2. The first end of the second capacitor C2 is connected to the holding node N0, and the second end of the second capacitor is connected to the second voltage terminal VSS1.

[0075] In the embodiment of the present application, the voltage provided by the first voltage terminal VDD1 is a high-level voltage, and the voltages provided by the second voltage terminal VSS1 and the third voltage terminal VSS2 are low-level voltages. In the present application, the specific voltage values of the high-level voltage and the low-level voltage are not limited, and the voltage values of the second voltage terminal VSS1 and the third voltage terminal VSS2 may be the same or different. Optionally, the signal of the noise reduction input terminal IN_put is the same as one of the signals of the second voltage terminal VSS1, the third voltage terminal VSS2, and the signal input terminal Input. Depending on the device or application scenario, the noise reduction input terminal IN_put may be connected to different signals, which will be described in detail below. In the first embodiment, the signal of the noise reduction input terminal IN_put is the same as the signal of the signal input terminal Input. The noise reduction input terminal IN_put may be connected to the signal input terminal Input, or may be other active signals having the same signal as the signal input terminal Input.

[0076] The present application provides a driving method for a GOA unit. As Figure 3 shown, using the GOA unit as described in any one of the above, the method includes a first stage T1, a second stage T2, and a third stage T3:

[0077] As Figure 4 shown, in the first stage T1, the signal input terminal Input is at a high level, the clock signal terminal CLK is at a low level, and the pull-up module 100 inputs the high level of the first voltage terminal VDD1 to the pull-up node PU under the control of the signal input terminal Input, so that the potential of the pull-up node PU is raised and the potential of the pull-down node PD is lowered; during the process of lowering the potential of the pull-down node PD, the noise reduction module 600 assists in charging the pull-up node PU under the control of the pull-down node PD.

[0078] This stage is the charging stage of PU. In this stage, both the signal input terminal Input and the first voltage terminal VDD1 are at a high level. The first transistor M1A and the first sub-transistor M1B are turned on, and the high level is written into the pull-up node PU and the first capacitor C1 to achieve the charging of PU. In this stage, the node N0 also writes the high level into the second capacitor C2. The first reset signal terminal Reset is at a low level, and the second transistor M2A and the second sub-transistor M2B are turned off. In this stage, the high level of the PU node is not sufficient to fully turn on the third transistor M3. As the PU node is charged, the third transistor M3 is turned on. Since the clock signal terminal CLK is at a low level, the low level can be output to the signal output terminal Output through the third transistor M3, and the signal output terminal Output is at a low level.

[0079] Since the pull-up (PU) is at a high level, it can pull down the pull-down (PD). During the charging process of PU, the pull-down node PD cannot be immediately pulled down by PU. As Figure 3 shown by the dashed line in Figure 3 , when PD is at a high level, the fifth transistor M5A and the fifth sub-transistor M5B are turned on, and the signal at the noise reduction input terminal IN_put is the same as that at the signal input terminal Input. The noise reduction input terminal IN_put is at a high level. The fifth transistor M5A and the fifth sub-transistor M5B are used to assist in charging PU, thereby quickly pulling down PD. When PD is at a low level, the fifth transistor M5A and the fifth sub-transistor M5B are turned off. When PD is at a high level, the fourth transistor M4 in the pull-down driving module 500 is turned on, and the low level of the third voltage terminal VSS2 is output to the signal output terminal Output through the fourth transistor M4, so that the clock hold signal at the signal output terminal Output is at a low level during this stage.

[0080] As Figure 5 shown, in the second stage T2, the signal input terminal Input is at a low level, the clock signal terminal CLK is at a high level, and the output module 300 inputs the high level of the clock signal terminal CLK to the signal output terminal Output and the second terminal of the first capacitor C1 under the control of the pull-up node PU. Under the bootstrap of the first capacitor C1, the potential of the pull-up node PU is further raised.

[0081] This stage is the PU holding stage. During this stage, the clock signal terminal CLK is at a high level. Since PU is written to a high level in the first stage T1, the third transistor M3 is turned on. The high level of the clock signal terminal CLK is output to the signal output terminal Output through the third transistor M3, and at the same time, a high level is written to the second terminal of the first capacitor C1. Due to the bootstrap effect of the first capacitor C1, the PU node is further raised, so that the third transistor M3 can be kept fully turned on. The PD node remains at a low level.

[0082] Since the hold node N0 is written to a high level through the second capacitor C2 in the first stage T1, in the module where the source-drain is directly connected to the pull-up node PU during this stage, through the setting of the series circuit, it can be ensured that one of the transistors in the series remains off, preventing the leakage of PU from affecting the turn-on of the third transistor M3 and further affecting the signal output of the signal output terminal Output. In this embodiment, the Vgs of M1A, M2A, M5A, and M6A are all VGL - VGH < 0. Therefore, M1A, M2A, M5A, and M6A all remain off, greatly reducing the risk of PU leakage. It can be understood that VGL represents a low level and VGH represents a high level. Exemplarily, the VGH corresponding to M5A is the high level of the N0 node, and VGL is the low level of the PD node.

[0083] As shown Figure 6 In the third stage T3, the first reset signal terminal Reset is at a high level. Under the control of the first reset signal terminal Reset, the first reset module 200 inputs the low level of the second voltage terminal VSS1 to the pull-up node PU, causing the potential of the pull-up node PU to be pulled down and the potential of the pull-down node PD to be pulled up; the pull-down driving module 500 outputs the voltage of the third voltage terminal VSS2 to the signal output terminal Output under the control of the pull-down node PD; the noise reduction module 600 assists in discharging the pull-up node PU under the control of the pull-down node PD.

[0084] This stage is the reset stage. The first reset signal terminal Reset is at a high level. The second transistor M2A and the second transistor M2B are turned on. The second voltage terminal VSS1 is at a low level. PU discharges through the second transistor M2A and the second transistor M2B, and writes the low level to the pull-up node PU. At the same time, PD rises to a high level. The fifth transistor M5A and the fifth transistor M5B are turned on. The PU node can further discharge through the fifth transistor M5A and the fifth transistor M5B to achieve a quick reset. In addition, the holding node N0 can discharge through the second transistor M2B and the fifth transistor M5B. To achieve a quick reset of the pull-up node PU and the holding node N0 simultaneously.

[0085] It can be understood that the timing of the second reset signal terminal Total_Reset is not shown in this embodiment. The second reset signal terminal Total_Reset is used to quickly reset the pull-up node PU and the holding node N0 simultaneously at the end of each frame. Its reset method is the same as that of the first reset signal terminal Reset, and will not be elaborated herein.

[0086] In this application, by setting the noise reduction module 600 to be directly connected to the Input signal line, this connection method enables that in the charging stage of PU, PD does not compete, but instead promotes the charging of PU. It can assist in charging PU in the first stage T1 and assist in discharging PU in the third stage T3, improving the charging and discharging effects and overcoming the competition risk between the PU node and the PD node. By adopting a dual-TFT structure for each module whose source-drain is connected to PU, the leakage mirror of PU in the second stage T2 can be completely turned off, which can greatly improve the stability of GOA. As Figure 4 shows a simulation result of the circuit of a GOA unit. From top to bottom are Input, PU, Output, Reset, N1, PD. It can be seen that Figure 7 the simulation result in Figure 3 is consistent with the theoretical analysis in

[0087] Embodiment 2

[0088] The difference between this embodiment and the first embodiment is that in the first embodiment, the signal connected to the noise reduction input terminal IN_put is the signal of Input. For example, Figure 8 As shown, in this embodiment, the signal of the noise reduction input terminal IN_put is the same as one of the signals of the second voltage terminal VSS1 and the third voltage terminal VSS2. That is, the noise reduction input terminal IN_put is a low-level signal. For example, the noise reduction input terminal IN_put is connected to the third voltage terminal VSS2.

[0089] In the first stage T1, the pull-up node PU and the hold node N0 are charged to a high level. Since the pull-down node PD cannot be immediately pulled low by the PU during the charging process of the PU, the fifth transistor M5A and the fifth sub-transistor M5B are turned on. The high level of the hold node N0 can charge the PU node through M5A, which is somewhat similar to the function in the first embodiment to a certain extent. However, since M5B is connected to the low level of the noise reduction input terminal IN_put, the effect is not as good as the auxiliary charging effect of the first embodiment. In the third stage T3, the effect is the same as the auxiliary discharge effect of the first embodiment.

[0090] Embodiment Three

[0091] The difference between this embodiment and the first embodiment is that a first holding module 810 is provided at the position of the hold node N0. The series circuit between different modules is separated at the position of the hold node N0 through the first holding module 810, so that the modules with series circuits are not directly connected at the series node position, which is used to control the charging state of the hold node N0. By setting the first holding module 810, the first node N1 and the second node N2 can be connected and turned on during the second stage T2 (charging and holding stage) in the driving process, and are disconnected in the remaining stages.

[0092] For example, Figure 9 As shown, in this embodiment, the GOA unit includes a first holding module 810. The first holding module 810 is connected to the first node N1, the second node N2, and the pull-up node PU, and is used to input the voltage of the first node N1 to the second node N2 under the control of the pull-up node PU. Among them, the transistors and sub-transistors of the pull-up module 100 and the transistors and sub-transistors of the first reset module 200 are both connected in series at the first node N1, and the transistors and sub-transistors of the noise reduction module 600 are connected in series at the second node N2. The first end of the second capacitor C2 is connected to the first node N1 or the second node N2.

[0093] Specifically, the first holding module 810 includes a seventh transistor M7. The first end of the seventh transistor M7 is connected to the second node N2, the second end of the seventh transistor M7 is connected to the first node N1, and the control end of the seventh transistor M7 is connected to the pull-up node PU.

[0094] Among them, the first end of the first transistor M1A and the second end of the first sub-transistor M1B, and the second end of the second transistor M2A and the first end of the second sub-transistor M2B are connected to the first node N1; the second end of the fifth transistor M5A and the first end of the fifth sub-transistor M5B are connected to the second node N2.

[0095] In one embodiment, the first end of the second capacitor C2 is connected to the second node N2. Through the seventh transistor M7, under the control of PU, the N1 node and the N2 node can be connected in the second stage T2 (PU charging and holding stage), and the N1 node and the N2 node are disconnected in the remaining stages. In the corresponding first embodiment, maintaining the connection mode of the node N0, since one end of M1B is VDD1, there may be a risk of negative Vth offset, which in turn affects the noise reduction effect of the noise reduction module. For example, in the third stage T3, the high voltage of VDD1 reaches the PU node through M1B, N0, and M5A, affecting the discharge of PU.

[0096] In this embodiment, by setting M7 between the N1 node and the N2 node, during the driving process of the GOA unit in the first stage T1, VDD1 charges the N1 node through M1B, and VDD1 charges the PU node through M1A and M1B; the high level of Input charges the second node N2 through M5B, and the high level of Input assists in charging the PU node through M5A and M5B; the seventh transistor M7 is an N-type TFT, and the condition for the seventh transistor M7 to turn on is Vgs > Vth, where Vth is the threshold voltage. In the first stage T1, Vgs = V PU -V N0 , the Vgs of the seventh transistor M7 is approximately 0, and the seventh transistor M7 is turned off to disconnect the N1 node and the N2 node. Therefore, even if M1B is negatively biased and the PD-controlled M5A is turned on, it will not be affected through the N1 node.

[0097] In the second stage T2, PU is further pulled up, which in turn causes the seventh transistor M7 to turn on, and the N1 node and the N2 node are connected. The high levels of the N1 node and the N2 node keep M1A, M2A, M5A, and M6A all turned off, greatly reducing the leakage risk of PU. In the third stage T3, PU discharges, the seventh transistor M7 is turned off, the N1 node is reset through M2B, and the N2 node is reset through M5B, which can ensure that the charges of each node are released during reset.

[0098] In another embodiment, as Figure 10As shown, the first end of the second capacitor C2 is connected to the first node N1. Similarly, in the first stage T1, M7 is turned off, the N1 node is charged through M1B, and the PU node is charged through M1A and M1B; the high level of Input charges the second node N2 through M5B, and the high level of Input charges the PU node through M5A and M5B as an auxiliary charge. Similarly, even if M1B is negatively biased, M5A controlled by PD is turned on, and it will not be affected through the N1 node.

[0099] Embodiment 4

[0100] The difference between this embodiment and Embodiment 3 is that in this embodiment, both the N1 node and the N2 node are connected to a capacitor, and the independence of the N1 and N2 nodes can be ensured through the capacitor.

[0101] As Figure 11 shown, in this embodiment, the GOA unit includes a third capacitor and a second holding module 820. The second holding module 820 is connected to the first node N1, the second node N2, and the signal input terminal Input, and is used to input the voltage of the first node N1 to the second node N2 under the control of the pull-up node PU. Among them, the transistors and sub-transistors of the pull-up module 100 and the transistors and sub-transistors of the first reset module 200 are both connected in series at the first node N1, the transistors and sub-transistors of the noise reduction module 600 are connected in series at the second node N2, the first end of the second capacitor C2 is connected to the first node N1, the first end of the third capacitor is connected to the second node N2, and the second end of the third capacitor is connected to the third voltage terminal VSS2.

[0102] Specifically, the second holding module 820 includes an eighth transistor M8. The first end of the eighth transistor M8 is connected to the second node N2, the second end of the eighth transistor M8 is connected to the first node N1, and the control end of the eighth transistor M8 is connected to the signal input terminal Input.

[0103] Among them, the first end of the first transistor M1A and the second end of the first sub-transistor M1B, the second end of the second transistor M2A and the first end of the second sub-transistor M2B are connected to the first node N1; the second end of the fifth transistor M5A and the first end of the fifth sub-transistor M5B are connected to the second node N2.

[0104] In the first stage T1, M8 is turned on, charging the N1 node through M1B, and charging the PU node through M1A and M1B; the high level of Input charges the second node N2 through M5B, and the high level of Input assists in charging the PU node through M5A and M5B. In the second stage T2, the PU is further pulled up, which in turn causes the eighth transistor M8 to turn on, connecting the N1 node and the N2 node. The high levels of the N1 node and the N2 node keep M1A, M2A, M5A, and M6A all turned off, greatly reducing the leakage risk of the PU. In the third stage T3, the PU discharges, the eighth transistor M8 is turned off, the N1 node is reset through M2B, and the N2 node is reset through M5B, ensuring that the charges of each node are released during reset.

[0105] In this embodiment, by providing the eighth transistor M8 between the N1 node and the N2 node, the eighth transistor M8 enables the N1 node and the N2 node to be connected under the control of the PU in the second stage T2 (PU charging and holding stage), and the N1 node and the N2 node are disconnected in the remaining stages. Even if M1B is negatively biased and M5A controlled by PD is turned on, it will not be affected through the N1 node.

[0106] Embodiment Five

[0107] The difference between this embodiment and Embodiment One is that in this embodiment, by providing the ninth transistor M9 at the position of the holding node N0, the function of the second capacitor C2 is realized, and the voltage of the N0 node can be maintained in the second stage T2, ensuring that one of the series transistors remains off, preventing the leakage of the PU from affecting the turn-on of the third transistor M3 and further affecting the signal output of the signal output terminal Output.

[0108] As Figure 12 shown, in this embodiment, the GOA unit includes a third holding module 830, and the third holding module 830 is connected to the holding node N0, the fourth voltage terminal VDD2, and the pull-up node PU, and is used to input the voltage of the fourth voltage terminal VDD2 to the holding node N0 under the control of the pull-up node PU.

[0109] Specifically, the third holding module 830 includes a ninth transistor M9. The first end of the ninth transistor M9 is connected to the fourth voltage terminal VDD2, the second end of the ninth transistor M9 is connected to the holding node N0, and the control end of the ninth transistor M9 is connected to the pull-up node PU.

[0110] In the first stage T1, M9 is turned on. The node N0 is charged through M1B, and the node PU is charged through M1A and M1B. The high level of Input charges the node PU through M5A and M5B. In the second stage T2, PU is further pulled up, which in turn enables the ninth transistor M9 to be turned on. VDD2 charges the node N0 through M9. The high level of the node N0 keeps M1A, M2A, M5A, and M6A all turned off, greatly reducing the leakage risk of PU. In the third stage T3, PU discharges, the ninth transistor M9 is turned off, the node N0 is reset through M2B, and the node PU is reset through M2B and M2A, which can ensure that the charges of each node are released during reset.

[0111] As Figure 13 shown, the present application provides a GOA driving circuit, including at least two cascaded GOA units, and each of the GOA units is the GOA unit described in any of the above. The specific working principle of this GOA driving circuit is basically the same as that of the GOA unit in the above embodiment. For its specific implementation, reference can be made to the embodiment of the GOA unit above, and the repeated parts will not be elaborated here.

[0112] In the embodiment of the present application, the signal output terminal Output of the GOA unit is a feedback signal output by the cascaded GOA driving circuit to the previous stage or the next stage. In some embodiments, the feedback signal can be used as the signal input terminal Input of the next stage unit. The present application does not limit this.

[0113] The present application provides a display device, including the GOA unit described in any of the above. The display device can be: a liquid crystal panel, an electronic paper, an organic light-emitting diode (abbreviation: OLED) panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function.

[0114] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0115] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more, unless otherwise specifically defined.

[0116] Unless otherwise defined, the technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the technical field of the present invention. The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. Terms such as "arranged" as used herein may mean that one component is directly attached to another component or that one component is attached to another component through an intermediate component. Features described in one embodiment herein may be applied alone or in combination with other features to another embodiment, unless the feature is not applicable or otherwise stated in that other embodiment.

[0117] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for illustrative and explanatory purposes and are not intended to limit the present invention to the scope of the described embodiments. Those skilled in the art can understand that more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope claimed by the present invention.

Claims

1. A GOA unit, characterized in that, Comprising a first capacitor and a plurality of modules, the plurality of modules including a pull-up module, a first reset module, an output module, an inverting module, a pull-down driving module, and a noise reduction module, wherein, A first end of the first capacitor is connected to a pull-up node, and a second end of the first capacitor is connected to a signal output terminal; The pull-up module is connected to the pull-up node, a first voltage terminal, and a signal input terminal, and is configured to input the voltage of the first voltage terminal to the pull-up node under the control of the signal input terminal; The first reset module is connected to a first reset signal terminal, a second voltage terminal, and the pull-up node, and is configured to input the voltage of the second voltage terminal to the pull-up node under the control of the first reset signal terminal; The output module is connected to the pull-up node, a clock signal terminal, and the signal output terminal, and is configured to output the voltage of the clock signal terminal to the signal output terminal under the control of the pull-up node; The inverting module is connected to the pull-up node and a pull-down node, and is configured to input a voltage with a phase opposite to that of the pull-up node to the pull-down node under the control of the pull-up node; The pull-down driving module is connected to a third voltage terminal, the pull-down node, and a second end of the first capacitor, and is configured to input the voltage of the third voltage terminal to the second end of the first capacitor under the control of the pull-down node; The noise reduction module is connected to the pull-down node, a noise reduction input terminal, and the pull-up node, and is configured to input the voltage of the noise reduction input terminal to the pull-up node under the control of the pull-down node; Each of the modules includes one or more transistors, and for the modules where the source-drain electrodes of the transistors are connected to the pull-up node, series circuits are adopted. The series circuit includes a secondary transistor in series with the transistor, and in each of the series circuits, the secondary transistor and the transistor are connected in series at a holding node, and the source-drain electrode of the transistor is the first end or the second end.

2. The GOA unit according to claim 1, wherein Further comprising a second capacitor, a first end of the second capacitor is connected to the holding node, and a second end of the second capacitor is connected to the second voltage terminal.

3. The GOA unit according to claim 2, wherein The pull-up module includes a first transistor and a first sub-transistor in series with the first transistor. A first end of the first transistor and a second end of the first sub-transistor are connected to the holding node, a second end of the first transistor is connected to the pull-up node, a first end of the first sub-transistor is connected to the first voltage terminal, and the control terminals of the first transistor and the first sub-transistor are both connected to the signal output terminal; The first reset module includes a second transistor and a second sub-transistor in series with the second transistor. A first end of the second transistor is connected to the pull-up node, a second end of the second transistor and a first end of the second sub-transistor are connected to the holding node, a second end of the second sub-transistor is connected to the second voltage terminal, and the control terminals of the second transistor and the second sub-transistor are both connected to the first reset signal terminal; The output module includes a third transistor. A first end of the third transistor is connected to the clock signal terminal, a second end of the third transistor is connected to the signal output terminal, and a control terminal of the third transistor is connected to the pull-up node; The pull-down driving module includes a fourth transistor. A first end of the fourth transistor is connected to a second end of a first capacitor. A second end of the fourth transistor is connected to a third voltage terminal. A control end of the fourth transistor is connected to a pull-down node. The noise reduction module includes a fifth transistor and a fifth-order transistor connected in series with the fifth transistor. A first end of the fifth transistor is connected to the pull-up node. A second end of the fifth transistor and a first end of the fifth-order transistor are connected to the holding node. A second end of the fifth-order transistor is connected to a noise reduction input terminal. Control ends of both the fifth transistor and the fifth-order transistor are connected to the pull-down node.

4. The GOA unit according to claim 1, wherein It further includes a second reset module. The second reset module is connected to the third voltage terminal, the pull-up node, and a second reset signal terminal, and is configured to input a voltage of the third voltage terminal to the pull-up node under the control of the second reset signal terminal. Among them, the second reset module includes a sixth transistor and a sixth-order transistor connected in series with the sixth transistor. A first end of the sixth transistor is connected to the pull-up node. A second end of the sixth transistor and a first end of the sixth-order transistor are connected to the holding node. A second end of the sixth-order transistor is connected to the third voltage terminal. Control ends of both the sixth transistor and the sixth-order transistor are connected to the second reset signal terminal.

5. The GOA unit according to claim 1, wherein, A signal of the noise reduction input terminal is the same as one of the signals of the second voltage terminal, the third voltage terminal, and the signal input terminal.

6. The GOA unit according to claim 3, wherein It further includes a first holding module. The first holding module is connected to the first node, the second node, and the pull-up node, and is configured to input a voltage of the first node to the second node under the control of the pull-up node. Among them, the transistor and the sub-transistor of the pull-up module and the transistor and the sub-transistor of the first reset module are both connected in series at the first node. The transistor and the sub-transistor of the noise reduction module are connected in series at the second node. A first end of the second capacitor is connected to the first node or the second node.

7. The GOA unit according to claim 6, wherein The first holding module includes a seventh transistor. A first end of the seventh transistor is connected to the second node. A second end of the seventh transistor is connected to the first node. A control end of the seventh transistor is connected to the pull-up node. Among them, A first end of the first transistor and a second end of the first-order transistor, a second end of the second transistor and a first end of the second-order transistor are connected to the first node. A second end of the fifth transistor and a first end of the fifth-order transistor are connected to the second node.

8. The GOA unit according to claim 6, wherein It further includes a third capacitor and a second holding module. The second holding module is connected to the first node, the second node, and the signal input terminal, and is configured to input a voltage of the first node to the second node under the control of the pull-up node. Among them, the transistor and the sub-transistor of the pull-up module and the transistor and the sub-transistor of the first reset module are both connected in series at the first node. The transistor and the sub-transistor of the noise reduction module are connected in series at the second node. A first end of the second capacitor is connected to the first node. A first end of the third capacitor is connected to the second node. A second end of the third capacitor is connected to the third voltage terminal.

9. The GOA unit according to claim 8, wherein The second holding module includes an eighth transistor. A first end of the eighth transistor is connected to a second node, a second end of the eighth transistor is connected to a first node, and a control end of the eighth transistor is connected to the signal input end. Wherein, A first end of the first transistor and a second end of the first sub-transistor, and a second end of the second transistor and a first end of the second sub-transistor are connected to the first node; a second end of the fifth transistor and a first end of the fifth sub-transistor are connected to the second node.

10. The GOA unit according to claim 1, characterized in that, It further includes a third holding module. The third holding module is connected to the holding node, a fourth voltage end, and a pull-up node, and is configured to input the voltage of the fourth voltage end to the holding node under the control of the pull-up node.

11. The GOA unit according to claim 10, wherein The third holding module includes a ninth transistor. A first end of the ninth transistor is connected to the fourth voltage end, a second end of the ninth transistor is connected to the holding node, and a control end of the ninth transistor is connected to the pull-up node.

12. A driving method of a GOA unit, characterized in that, Using the GOA unit according to any one of claims 1-11, the method includes a first stage, a second stage, and a third stage: In the first stage, the signal input end is at a high level, the clock signal end is at a low level, and the pull-up module inputs the high level of the first voltage end to the pull-up node under the control of the signal input end, so that the potential of the pull-up node is raised and the potential of the pull-down node is lowered; During the process of lowering the potential of the pull-down node, the noise reduction module assists in charging the pull-up node under the control of the pull-down node; In the second stage, the signal input end is at a low level, the clock signal end is at a high level, and the output module inputs the high level of the clock signal end to the signal output end and a second end of the first capacitor under the control of the pull-up node, and the potential of the pull-up node is further raised under the bootstrap of the first capacitor; In the third stage, the first reset signal end is at a high level, and the first reset module inputs the low level of the second voltage end to the pull-up node under the control of the first reset signal end, so that the potential of the pull-up node is lowered and the potential of the pull-down node is raised; The pull-down driving module outputs the voltage of the third voltage end to the signal output end under the control of the pull-down node; The noise reduction module assists in discharging the pull-up node under the control of the pull-down node.

13. A GOA driving circuit, characterized in that, It includes at least two cascaded GOA units, and each of the GOA units is the GOA unit according to any one of claims 1-11.

14. A display device, characterized in that, It includes the GOA unit according to any one of claims 1-11.

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