A dual-power redundant latch instantaneous dose rate radiation hardened trigger in FDSOI process

Abstract

The present invention relates to a dual-power redundant latch instantaneous dose rate radiation-hardened trigger structure suitable for FDSOI processes, belonging to the technical field of radiation-resistant integrated circuit design. By adding a redundant latch structure, flip-flop output data flipping and disturbance caused by power supply collapse due to instantaneous dose rate radiation are suppressed. The redundant latch structure is powered by a power supply different from that of the trigger main structure and undergoes a layout reinforcement design. The overall circuit adopts a transistor stacking structure to improve the trigger's ability to resist instantaneous dose rate radiation. The design of the present invention is based on commercial rules, has strong operability, and is easy to implement.

Description

Technical Field

[0001] The invention relates to a dual-power redundant latch instantaneous dose rate radiation hardening trigger of an FDSOI process, belonging to the technical field of integrated circuit anti-radiation hardening. Background Art

[0002] With the development of integrated circuits in my country, semiconductor devices have been widely used in the defense field. Semiconductor devices are very sensitive to radiation, and the radiation resistance of integrated circuits has become the key to ensure the normal operation of semiconductor devices in special environments.

[0003] Integrated circuits (ICs) experience different radiation effects in different radiation environments. These effects can be categorized as transient dose rate effects, total dose effects, and single event effects. Transient dose rate radiation effects occur when gamma rays, or other radiation, strike semiconductor materials within a very short period of time, stimulating a large number of electron-hole pairs. These effects, influenced by electric fields and concentration gradients, generate photocurrents, which in turn can cause data flip-flops and disturbances in the circuit. Power supply voltage stability is crucial for the proper operation of integrated circuits. One of the most prominent manifestations of transient dose rate radiation effects in circuits is the severe disturbance of the power supply voltage, which directly impacts the proper functioning of the IC. Flip-flops are among the most basic and common components in digital circuits. Optimizing their performance under transient dose rate radiation is crucial for the application of integrated circuits in these environments.

[0004] The FDSOI (Fully Depleted Silicon-on-Insulator) process is a key technology path for continuing Moore's Law. Exceptional in low power consumption and high performance, the FDSOI process is currently widely used in sensors, automotive chips, aerospace, and other fields.

[0005] Existing instantaneous dose rate radiation hardening technologies typically modify device process parameters, such as doping concentration, resulting in high production costs, complex implementation requirements, and inability to effectively integrate with current commercial process lines. This invention proposes a dual-power supply redundant hardening structure based on commercial processes and design rules. This architecture maintains the design methodology and process for integrated circuits, is easy to implement, and offers design compatibility. Summary of the Invention

[0006] The present invention addresses the following technical issues: Overcoming the shortcomings of existing technologies, a dual-power redundant latch instantaneous dose rate radiation-hardened trigger for an FDSOI process is proposed. Based on a circuit and layout-based hardening design, a redundant latch structure controlled by a hardened power supply, VDDC, is added to suppress signal variations caused by instantaneous dose rate radiation. Because the redundant latch structure maintains simple circuit signal connections and a small footprint, VDDC power supply disturbances can be easily hardened using the shortest metal traces and the widest metal lines permitted by design rules. The overall circuit is hardened using a transistor stacking structure.

[0007] The technical solution of the present invention is:

[0008] An FDSOI process dual-power redundant latch instantaneous dose rate radiation hardened trigger, comprising: an input circuit, a master latch circuit, a transmission control circuit, a slave latch circuit, an output circuit, a first clock signal circuit CLK1, and a second clock signal circuit CLK2;

[0009] The first clock signal circuit CLK1 sends the clock signal to the slave latch circuit; the second clock signal circuit CLK2 sends the clock signal to the master latch circuit, the transmission control circuit and the slave latch circuit;

[0010] The input circuit sends the input data signal to the main latch circuit when the clock signal is at a low level; the main latch circuit sends the data signal to the transmission control circuit when the clock signal is at a low level; the main latch circuit latches the data signal when the clock signal is at a high level;

[0011] The transmission control circuit sends the data signal to the slave latch circuit when the clock signal is at a high level; the slave latch circuit sends the data signal to the output circuit when the clock signal is at a high level; the slave latch circuit latches the data signal when the clock signal is at a low level, and sends the latched data signal to the output circuit; the output circuit outputs the data signal.

[0012] Furthermore, the first clock signal circuit CLK1 includes a sixth stacked inverter INV13 and a seventh stacked inverter INV14 whose power supply is VDDC;

[0013] The sixth stacked inverter INV13 includes PMOS transistors p30 and p31, and NMOS transistors n30 and n31;

[0014] The source of the PMOS transistor p30 is connected to the power supply VDDC, and the gate receives the clock signal CLK; the source of the PMOS transistor p31 is connected to the drain of the PMOS transistor p30, and the gate receives the clock signal CLK; the source of the NMOS transistor n30 is grounded to VSS, and the gate receives the clock signal CLK; the source of the NMOS transistor n31 is connected to the drain of the NMOS transistor n30, and the gate receives the clock signal CLK, and the drain is connected to the drain of the PMOS transistor p31 to form a common node CLKCN.

[0015] The seventh stacked inverter INV14 includes PMOS transistors p32 and p33, and NMOS transistors n32 and n33;

[0016] The source of the PMOS transistor p32 is connected to the power supply VDDC, and the gate receives the signal of the common node CLKCN; the source of the PMOS transistor p33 is connected to the drain of the PMOS transistor p32, and the gate receives the signal of the common node CLKCN; the source of the NMOS transistor n32 is grounded to VSS, and the gate receives the signal of the common node CLKCN; the source of the NMOS transistor n33 is connected to the drain of the NMOS transistor n32, the gate receives the signal of the common node CLKCN, and the drain is connected to the drain of the PMOS transistor p33 to form the common node CLKCNN output.

[0017] Furthermore, the second clock signal circuit CLK2 includes an eighth stacked inverter INV15 and a ninth stacked inverter INV16 whose power supply is VDD;

[0018] The eighth stacked inverter INV15 includes PMOS transistors p34 and p35, and NMOS transistors n34 and n35;

[0019] The source of the PMOS transistor p34 is connected to the power supply VDD, and the gate receives the clock signal CLK; the source of the PMOS transistor p35 is connected to the drain of the PMOS transistor p34, and the gate receives the clock signal CLK; the source of the NMOS transistor n34 is grounded to VSS, and the gate receives the clock signal CLK; the source of the NMOS transistor n35 is connected to the drain of the NMOS transistor n34, and the gate receives the clock signal CLK, and the drain is connected to the drain of the PMOS transistor p35 to form a common node CLKN;

[0020] The ninth stacked inverter INV16 includes PMOS transistors p36 and p37, and NMOS transistors n36 and n37;

[0021] The source of the PMOS transistor p36 is connected to the power supply VDD, and the gate receives the signal of the common node CLKN; the source of the PMOS transistor p37 is connected to the drain of the PMOS transistor p36, and the gate receives the signal of the common node CLKN; the source of the NMOS transistor n36 is grounded to VSS, and the gate receives the signal of the common node CLKN; the source of the NMOS transistor n37 is connected to the drain of the NMOS transistor n36, the gate receives the signal of the common node CLKN, and the drain is connected to the drain of the PMOS transistor p37 to form a common node CLKNN output.

[0022] Further, the input circuit includes a first stacked inverter INV1 and a second stacked inverter INV2 whose power supply is VDD;

[0023] The first stacked inverter INV1 includes PMOS transistors p1 and p2, and NMOS transistors n1 and n2;

[0024] The source of the PMOS transistor p1 is connected to the power supply VDD, and the gate receives the input signal D; the source of the PMOS transistor p2 is connected to the drain of the PMOS transistor p1, and the gate receives the input signal D; the source of the NMOS transistor n1 is grounded to VSS, and the gate receives the input signal D; the source of the NMOS transistor n2 is connected to the drain of the NMOS transistor n1, and the gate receives the input signal D, and the drain is connected to the drain of the PMOS transistor p2 to form a common node N1;

[0025] The second stacked inverter INV2 includes PMOS transistors p3 and p4, and NMOS transistors n3 and n4;

[0026] The source of the PMOS transistor p3 is connected to the power supply VDD, and the gate receives the signal of the common node N1; the source of the PMOS transistor p4 is connected to the drain of the PMOS transistor p3, and the gate receives the signal of the common node N1; the source of the NMOS transistor n3 is grounded to VSS, and the gate receives the signal of the common node N1; the source of the NMOS transistor n4 is connected to the drain of the NMOS transistor n3, the gate receives the signal of the common node N1, and the drain is connected to the drain of the PMOS transistor p4 to form a common node N2.

[0027] Further, the master latch circuit includes a first clocked stacked inverter INV3, a third stacked inverter INV4 and a second clocked stacked inverter INV5 whose power supply is VDD;

[0028] The first clocked stacked inverter INV3 includes PMOS transistors p5, p6, p7, and NMOS transistors n5, n6, n7;

[0029] The source of the PMOS transistor p5 is connected to the power supply VDD, and the gate receives the signal of the common node N2; the source of the PMOS transistor p6 is connected to the drain of the PMOS transistor p5, and the gate receives the signal of the common node N2; the source of the PMOS transistor p7 is connected to the drain of the PMOS transistor p6, and the gate receives the signal of the common node CLKNN; the source of the NMOS transistor n5 is grounded to VSS, and the gate receives the signal of the common node N2; the source of the NMOS transistor n6 is connected to the drain of the NMOS transistor n5, and the gate receives the signal of the common node N2; the source of the NMOS transistor n7 is connected to the drain of the NMOS transistor n6, the gate receives the signal of the common node CLKN, and the drain is connected to the drain of the PMOS transistor p7 to form a common node N3;

[0030] The third stacked inverter INV4 includes PMOS transistors p8 and p9, and NMOS transistors n8 and n9;

[0031] The source of the PMOS transistor p8 is connected to the power supply VDD, and the gate receives the signal of the common node N3; the source of the PMOS transistor p9 is connected to the drain of the PMOS transistor p8, and the gate receives the signal of the common node N3; the source of the NMOS transistor n8 is grounded to VSS, and the gate receives the signal of the common node N3; the source of the NMOS transistor n9 is connected to the drain of the NMOS transistor n8, the gate receives the signal of the common node N3, and the drain is connected to the drain of the PMOS transistor p9, forming a common node N4.

[0032] The second clocked stacked inverter INV5 includes PMOS transistors p10, p11, p12, and NMOS transistors n10, n11, n12;

[0033] The source of the PMOS transistor p10 is connected to the power supply VDD, and the gate receives the signal of the common node N4; the source of the PMOS transistor p11 is connected to the drain of the PMOS transistor p10, and the gate receives the signal of the common node N4; the source of the PMOS transistor p12 is connected to the drain of the PMOS transistor p11, the gate receives the signal of the common node CLKN, and the drain is connected to the common node N3; the source of the NMOS transistor n10 is grounded to VSS, and the gate receives the signal of the common node N4; the source of the NMOS transistor n11 is connected to the drain of the NMOS transistor n10, and the gate receives the signal of the common node N4; the source of the NMOS transistor n12 is connected to the drain of the NMOS transistor n11, the gate receives the signal of the common node CLKNN, and the drain is connected to the common node N3.

[0034] Further, the transmission control circuit includes a third clocked stacked inverter INV6 whose power supply is VDD;

[0035] The third clock-controlled stacked inverter INV6 includes PMOS transistors p13, p14, p15, and NMOS transistors n13, n14, and n15;

[0036] The source of the PMOS transistor p13 is connected to the power supply VDD, and the gate receives the signal of the common node N4; the source of the PMOS transistor p14 is connected to the drain of the PMOS transistor p13, and the gate receives the signal of the common node N4; the source of the PMOS transistor p15 is connected to the drain of the PMOS transistor p14, and the gate receives the signal of the common node CLKN; the source of the NMOS transistor n13 is grounded to VSS, and the gate receives the signal of the common node N4; the source of the NMOS transistor n14 is connected to the drain of the NMOS transistor n13, and the gate receives the signal of the common node N4; the source of the NMOS transistor n15 is connected to the drain of the NMOS transistor n14, the gate receives the signal of the common node CLKNN, and the drain is connected to the drain of the PMOS transistor p15, forming a common node N5.

[0037] Further, the slave latch circuit includes a fourth stacked inverter INV7, a fourth clocked stacked inverter INV8, a fifth clocked stacked inverter INV9 whose power supply is VDDC, and a sixth clocked stacked inverter INV10, a fifth stacked inverter INV11 whose power supply is VDD;

[0038] The fifth clocked stacked inverter INV9 includes PMOS transistors p21, p22, p23, and NMOS transistors n21, n22, and n23;

[0039] The source of the PMOS transistor p21 is connected to the power supply VDDC, and the gate receives the signal of the common node N5; the source of the PMOS transistor p22 is connected to the drain of the PMOS transistor p21, and the gate receives the signal of the common node N5; the source of the PMOS transistor p23 is connected to the drain of the PMOS transistor p22, and the gate receives the signal of the common node CLKCN; the source of the NMOS transistor n21 is grounded to VSS, and the gate receives the signal of the common node N5; the source of the NMOS transistor n22 is connected to the drain of the NMOS transistor n21, and the gate receives the signal of the common node N5; the source of the NMOS transistor n23 is connected to the drain of the NMOS transistor n22, the gate receives the signal of the common node CLKCNN, and the drain is connected to the drain of the PMOS transistor p23 to form a common node S1;

[0040] The fourth stacked inverter INV7 includes PMOS transistors p16 and p17, and NMOS transistors n16 and n17;

[0041] The source of the PMOS transistor p16 is connected to the power supply VDDC, and the gate receives the signal of the common node S1; the source of the PMOS transistor p17 is connected to the drain of the PMOS transistor p16, the gate receives the signal of the common node S1, and the drain is connected to the common node N5; the source of the NMOS transistor n16 is grounded to VSS, and the gate receives the signal of the common node S1; the source of the NMOS transistor n17 is connected to the drain of the NMOS transistor n16, the gate receives the signal of the common node S1, and the drain is connected to the common node N5;

[0042] The fourth clock-controlled stacked inverter INV8 includes PMOS transistors p18, p19, p20, and NMOS transistors n18, n19, n20;

[0043] The source of the PMOS transistor p18 is connected to the power supply VDDC, and the gate is connected to the common node N5; the source of the PMOS transistor p19 is connected to the drain of the PMOS transistor p18, and the gate is connected to the common node N5; the source of the PMOS transistor p20 is connected to the drain of the PMOS transistor p19, the gate receives the signal of the common node CLKCNN, and the drain is connected to the common node S1; the source of the NMOS transistor n18 is grounded VSS, and the gate is connected to the common node N5; the source of the NMOS transistor n19 is connected to the drain of the NMOS transistor n18, and the gate is connected to the common node N5; the source of the NMOS transistor n20 is connected to the drain of the NMOS transistor n19, the gate receives the signal of the common node CLKCN, and the drain is connected to the common node S1.

[0044] Furthermore, from the latch circuit, the fifth stacked inverter INV11 includes PMOS transistors p27 and p28, and NMOS transistors n27 and n28;

[0045] The source of the PMOS transistor p27 is connected to the power supply VDD, and the gate receives the signal of the common node N5; the source of the PMOS transistor p28 is connected to the drain of the PMOS transistor p27, and the gate receives the signal of the common node N5; the source of the NMOS transistor n27 is grounded to VSS, and the gate receives the signal of the common node N5; the source of the NMOS transistor n28 is connected to the drain of the NMOS transistor n27, the gate receives the signal of the common node N5, and the drain is connected to the drain of the PMOS transistor p28 to form a common node S2;

[0046] The sixth clocked stacked inverter INV10 includes PMOS transistors p24, p25, p26, and NMOS transistors n24, n25, and n26;

[0047] The source of the PMOS transistor p24 is connected to the power supply VDD, and the gate receives the signal of the common node S2; the source of the PMOS transistor p25 is connected to the drain of the PMOS transistor p24, and the gate receives the signal of the common node S2; the source of the PMOS transistor p26 is connected to the drain of the PMOS transistor p25, the gate receives the signal of the common node CLKNN, and the drain is connected to the common node N5; the source of the NMOS transistor n24 is grounded to VSS, and the gate receives the signal of the common node S2; the source of the NMOS transistor n25 is connected to the drain of the NMOS transistor n24, and the gate receives the signal of the common node S2; the source of the NMOS transistor n26 is connected to the drain of the NMOS transistor n25, the gate receives the signal of the common node CLKN, and the drain is connected to the common node N5.

[0048] Further, the output circuit includes an inverter INV12 whose power supply is VDDC;

[0049] The inverter INV12 includes a PMOS transistor p29 and an NMOS transistor n29;

[0050] The source of the PMOS transistor p29 is connected to the power supply VDDC, and the gate receives the common node N5 signal; the source of the NMOS transistor n29 is grounded VSS, the gate receives the common node N5 signal, and the drain is connected to the drain of the PMOS transistor p29 to form a common node Q.

[0051] Furthermore, the metal lines between the power supply VDDC signals are routed at the shortest distance and are designed to be the widest metal lines that meet the process design rule conditions.

[0052] Compared with the prior art, the present invention has the following beneficial effects:

[0053] (1) The present invention provides a dual-power redundant latch instantaneous dose rate radiation hardened trigger for FDSOI process. By designing the power signal VDDC routing to be as close as possible and setting the metal line to the maximum width that meets the design rules, the voltage drop caused by radiation is reduced, thereby enhancing the instantaneous dose rate radiation resistance of the power supply VDDC.

[0054] (2) The present invention adds a redundant latch structure with a power supply voltage of VDDC to the conventional trigger structure, which can latch data in the structure and restore the affected nodes;

[0055] (3) The design of the present invention is based on two levels: circuit and layout, taking into account the radiation effect of power supply voltage and internal signals.

[0056] (4) The present invention suppresses the flip-flop output data flip and disturbance caused by power supply collapse caused by instantaneous dose rate radiation by adding a redundant latch structure that is powered by a reinforced power supply different from the trigger main body structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a structural diagram of the trigger of the present invention;

[0058] Figure 2 It is a schematic diagram of the clock signal circuit in the trigger of the present invention. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. It is obvious that the embodiments described are only some embodiments of the present invention, rather than all embodiments. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the invention claimed for protection, but merely to illustrate selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of the present invention.

[0060] In an embodiment of the present invention, a dual-power redundant latch instantaneous dose rate radiation hardened trigger in an FDSOI process is provided. The trigger is based on dual power supplies VDDC and VDD, and the power supply VDDC is layout-hardened, the clock circuit is redundant, and a backup redundant latch structure controlled by the reinforced power supply VDDC is added. The output circuit is controlled by the power supply VDDC. The entire circuit adopts a transistor stack structure, which enhances the trigger's ability to resist instantaneous dose rate radiation. For details, please refer to Figure 1 .

[0061] Figure 1 FIG. 1 is a schematic diagram of the overall structure of the trigger of the present invention. Figure 1 As shown, the present invention proposes a dual-power redundant latch instantaneous dose rate radiation hardened trigger of FDSOI process, comprising: an input circuit, a master latch circuit, a transmission control circuit, a slave latch circuit, an output circuit, a first clock signal circuit CLK1 and a second clock signal circuit CLK2;

[0062] The first clock signal circuit CLK1 sends the clock signal to the slave latch circuit; the second clock signal circuit CLK2 sends the clock signal to the master latch circuit, the transmission control circuit and the slave latch circuit;

[0063] The input circuit sends the input data signal to the main latch circuit when the clock signal is at a low level; the main latch circuit sends the data signal to the transmission control circuit when the clock signal is at a low level; the main latch circuit latches the data signal when the clock signal is at a high level;

[0064] The transmission control circuit sends the data signal to the slave latch circuit when the clock signal is at a high level; the slave latch circuit sends the data signal to the output circuit when the clock signal is at a high level; the slave latch circuit latches the data signal when the clock signal is at a low level, and sends the latched data signal to the output circuit; the output circuit outputs the data signal.

[0065] The following is a detailed introduction to each component circuit.

[0066] The input circuit includes a first stacked inverter INV1 and a second stacked inverter INV2 whose power supply is VDD.

[0067] The first stacked inverter INV1 includes PMOS transistors p1 and p2, and NMOS transistors n1 and n2. The source of the PMOS transistor p1 is connected to the power supply VDD, and the gate receives the input signal D. The source of the PMOS transistor p2 is connected to the drain of the PMOS transistor p1, and the gate receives the input signal D. The source of the NMOS transistor n1 is grounded to VSS, and the gate receives the input signal D. The source of the NMOS transistor n2 is connected to the drain of the NMOS transistor n1, the gate receives the input signal D, and the drain is connected to the drain of the PMOS transistor p2 to form a common node N1. The PMOS transistor p1, PMOS transistor p2, NMOS transistor n1, and NMOS transistor n2 together constitute the first stacked inverter INV1 with the power supply VDD.

[0068] The second stacked inverter INV2 includes PMOS transistors p3 and p4, and NMOS transistors n3 and n4;

[0069] The source of the PMOS transistor p3 is connected to the power supply VDD, and the gate receives the signal of the common node N1; the source of the PMOS transistor p4 is connected to the drain of the PMOS transistor p3, and the gate receives the signal of the common node N1; the source of the NMOS transistor n3 is grounded to VSS, and the gate receives the signal of the common node N1; the source of the NMOS transistor n4 is connected to the drain of the NMOS transistor n3, the gate receives the signal of the common node N1, and the drain is connected to the drain of the PMOS transistor p4 to form a common node N2. The PMOS transistors p3, p4, NMOS transistors n3, and n4 together constitute a second stacked inverter INV2 whose power supply is VDD.

[0070] The master latch circuit includes a first clock-controlled stacked inverter INV3 whose power supply is VDD, a second clock-controlled stacked inverter INV5 and a third stacked inverter INV4 whose power supply is VDD.

[0071] The first clock-controlled stacked inverter INV3 includes PMOS transistors p5, p6, p7, and NMOS transistors n5, n6, and n7; wherein the source of the PMOS transistor p5 is connected to the power supply VDD, and the gate receives the signal of the common node N2; the source of the PMOS transistor p6 is connected to the drain of the PMOS transistor p5, and the gate receives the signal of the common node N2; the source of the PMOS transistor p7 is connected to the drain of the PMOS transistor p6, and the gate receives the signal of the common node CLKNN; the source of the NMOS transistor n5 is grounded to VSS, and the gate receives the signal of the common node N 2; the source of the NMOS transistor n6 is connected to the drain of the NMOS transistor n5, and the gate receives the signal of the common node N2; the source of the NMOS transistor n7 is connected to the drain of the NMOS transistor n6, the gate receives the signal of the common node CLKN, and the drain is connected to the drain of the PMOS transistor p7 to form a common node N3. The PMOS transistors p5, PMOS transistors p6, PMOS transistors p7, NMOS transistors n5, NMOS transistors n6, and NMOS transistors n7 together constitute a first clock-controlled stacked inverter INV3 with a power supply of VDD;

[0072] The third stacked inverter INV4 includes PMOS transistors p8 and p9, and NMOS transistors n8 and n9;

[0073] The source of the PMOS transistor p8 is connected to the power supply VDD, and the gate receives the signal of the common node N3. The source of the PMOS transistor p9 is connected to the drain of the PMOS transistor p8, and the gate receives the signal of the common node N3. The source of the NMOS transistor n8 is grounded to VSS, and the gate receives the signal of the common node N3. The source of the NMOS transistor n9 is connected to the drain of the NMOS transistor n8, the gate receives the signal of the common node N3, and the drain is connected to the drain of the PMOS transistor p9, forming a common node N4. The PMOS transistors p8, PMOS transistors p9, NMOS transistors n8, and NMOS transistors n9 together constitute a third stacked inverter INV4 whose power supply is VDD.

[0074] The second clocked stacked inverter INV5 includes PMOS transistors p10, p11, p12, and NMOS transistors n10, n11, n12;

[0075] The source of the PMOS transistor p10 is connected to the power supply VDD, and the gate receives the signal from the common node N4; the source of the PMOS transistor p11 is connected to the drain of the PMOS transistor p10, and the gate receives the signal from the common node N4; the source of the PMOS transistor p12 is connected to the drain of the PMOS transistor p11, the gate receives the signal from the common node CLKN, and the drain is connected to the common node N3; the source of the NMOS transistor n10 is grounded to VSS, and the gate receives the signal from the common node N4; the source of the NMOS transistor n11 is connected to the drain of the NMOS transistor n10, and the gate receives the signal from the common node N4; the source of the NMOS transistor n12 is connected to the drain of the NMOS transistor n11, the gate receives the signal from the common node CLKNN, and the drain is connected to the common node N3. The PMOS transistors p10, p11, p12, NMOS transistors n10, nMOS transistors n11, and nMOS transistors n12 together constitute a second clock-controlled stacked inverter INV5 whose power supply is VDD.

[0076] The transmission control circuit includes a third clock-controlled stacked inverter INV6 whose power supply is VDD.

[0077] The third clock-controlled stacked inverter INV6 includes PMOS transistors p13, p14, p15, and NMOS transistors n13, n14, and n15; wherein the source of the PMOS transistor p13 is connected to the power supply VDD, and the gate receives the signal of the common node N4; the source of the PMOS transistor p14 is connected to the drain of the PMOS transistor p13, and the gate receives the signal of the common node N4; the source of the PMOS transistor p15 is connected to the drain of the PMOS transistor p14, and the gate receives the signal of the common node CLKN; the source of the NMOS transistor n13 is grounded to VSS, and the gate receives the signal of the common node N 4; the source of the NMOS transistor n14 is connected to the drain of the NMOS transistor n13, and the gate receives the signal of the common node N4; the source of the NMOS transistor n15 is connected to the drain of the NMOS transistor n14, the gate receives the signal of the common node CLKNN, and the drain is connected to the drain of the PMOS transistor p15 to form a common node N5. The PMOS transistors p13, p14, p15, NMOS transistors n13, nMOS transistors n14, and NMOS transistors n15 together constitute a third clock-controlled stacked inverter INV6 whose power supply is VDD.

[0078] The slave latch circuit includes a fourth stacked inverter INV7 , a fourth clocked stacked inverter INV8 , and a fifth clocked stacked inverter INV9 whose power supply is VDDC, and a sixth clocked stacked inverter INV10 and a fifth stacked inverter INV11 whose power supply is VDD.

[0079] The fifth clock-controlled stacked inverter INV9 includes PMOS transistors p21, p22, p23, and NMOS transistors n21, n22. n23; wherein the source of the PMOS transistor p21 is connected to the power supply VDDC, and the gate receives the signal of the common node N5; the source of the PMOS transistor p22 is connected to the drain of the PMOS transistor p21, and the gate receives the signal of the common node N5; the source of the PMOS transistor p23 is connected to the drain of the PMOS transistor p22, and the gate receives the signal of the common node CLKCN; the source of the NMOS transistor n21 is grounded to VSS, and the gate receives the signal of the common node N5; the source of the NMOS transistor n22 is connected to the drain of the NMOS transistor n21, and the gate receives the signal of the common node N5; the source of the NMOS transistor n23 is connected to the drain of the NMOS transistor n22, the gate receives the signal of the common node CLKCNN, and the drain is connected to the drain of the PMOS transistor p23 to form a common node S1. The PMOS transistors p21, PMOS transistors p22, PMOS transistors p23, NMOS transistors n21, NMOS transistors n22, and NMOS transistors n23 together constitute a fifth clock-controlled stacked inverter INV9 with the power supply VDDC;

[0080] The fourth stacked inverter INV7 includes PMOS transistors p16 and p17, and NMOS transistors n16 and n17;

[0081] The source of the PMOS transistor p16 is connected to the power supply VDDC, and the gate receives the signal from the common node S1. The source of the PMOS transistor p17 is connected to the drain of the PMOS transistor p16, the gate receives the signal from the common node S1, and the drain is connected to the common node N5. The source of the NMOS transistor n16 is grounded to VSS, and the gate receives the signal from the common node S1. The source of the NMOS transistor n17 is connected to the drain of the NMOS transistor n16, the gate receives the signal from the common node S1, and the drain is connected to the common node N5. The PMOS transistors p16, p17, NMOS transistors n16, and NMOS transistors n17 together constitute a fourth stacked inverter INV7 whose power supply is VDD.

[0082] The fourth clock-controlled stacked inverter INV8 includes PMOS transistors p18, p19, p20, and NMOS transistors n18, n19, n20;

[0083] The source of the PMOS transistor p18 is connected to the power supply VDDC, and the gate is connected to the common node N5; the source of the PMOS transistor p19 is connected to the drain of the PMOS transistor p18, and the gate is connected to the common node N5; the source of the PMOS transistor p20 is connected to the drain of the PMOS transistor p19, the gate receives the signal of the common node CLKCNN, and the drain is connected to the common node S1; the source of the NMOS transistor n18 is grounded to VSS, and the gate is connected to the common node N5; the source of the NMOS transistor n19 is connected to the drain of the NMOS transistor n18, and the gate is connected to the common node N5; the source of the NMOS transistor n20 is connected to the drain of the NMOS transistor n19, the gate receives the signal of the common node CLKCN, and the drain is connected to the common node S1. The PMOS transistors p18, PMOS transistors p19, PMOS transistors p20, NMOS transistors n18, NMOS transistors n19, and NMOS transistors n20 together constitute a fourth clock-controlled stacked inverter INV8 with the power supply VDDC.

[0084] The fifth stacked inverter INV11 includes PMOS transistors p27 and p28, and NMOS transistors n27 and n28;

[0085] The source of the PMOS transistor p27 is connected to the power supply VDD, and the gate receives the signal of the common node N5. The source of the PMOS transistor p28 is connected to the drain of the PMOS transistor p27, and the gate receives the signal of the common node N5. The source of the NMOS transistor n27 is grounded to VSS, and the gate receives the signal of the common node N5. The source of the NMOS transistor n28 is connected to the drain of the NMOS transistor n27, and the gate receives the signal of the common node N5. The drain of the NMOS transistor n28 is connected to the drain of the NMOS transistor n27 to form a common node S2. The PMOS transistors p27, p28, NMOS transistors n27, and NMOS transistors n28 together constitute a fifth stacked inverter INV11 whose power supply is VDD.

[0086] The sixth clocked stacked inverter INV10 includes PMOS transistors p24, p25, p26, and NMOS transistors n24, n25, and n26;

[0087] The source of the PMOS transistor p24 is connected to the power supply VDD, and the gate receives the signal from the common node S2; the source of the PMOS transistor p25 is connected to the drain of the PMOS transistor p24, and the gate receives the signal from the common node S2; the source of the PMOS transistor p26 is connected to the drain of the PMOS transistor p25, the gate receives the signal from the common node CLKNN, and the drain is connected to the common node N5; the source of the NMOS transistor n24 is grounded to VSS, and the gate receives the signal from the common node S2; the source of the NMOS transistor n25 is connected to the drain of the NMOS transistor n24, and the gate receives the signal from the common node S2; the source of the NMOS transistor n26 is connected to the drain of the NMOS transistor n25, the gate receives the signal from the common node CLKN, and the drain is connected to the common node N5. The PMOS transistors p24, PMOS transistors p25, PMOS transistors p26, NMOS transistors n24, NMOS transistors n25, and NMOS transistors n26 together constitute a sixth clock-controlled stacked inverter INV10 whose power supply is VDD.

[0088] The output circuit includes an inverter INV12 whose power supply is VDDC.

[0089] Inverter INV12 includes a PMOS transistor p29 and an NMOS transistor n29; the source of the PMOS transistor p29 is connected to the power supply VDDC, and the gate receives the signal of the common node N5; the source of the NMOS transistor n29 is grounded to VSS, the gate receives the signal of the common node N5, and the drain is connected to the drain of the PMOS transistor p29 to form a common node Q, and the output signal of the trigger is output at the common node Q. The PMOS transistor p29 and the NMOS transistor n29 together constitute the inverter INV12.

[0090] The clock signal circuit is divided into a first clock signal circuit CLK1 composed of a sixth stacked inverter INV13 and a seventh stacked inverter INV14 whose power supply is VDDC, and a second clock signal circuit CLK2 composed of an eighth stacked inverter INV15 and a ninth stacked inverter INV16 whose power supply is VDD. For details, please refer to Figure 2 .

[0091] like Figure 2 As shown, the clock signal circuit includes a first clock signal circuit CLK1 and a second clock signal circuit CLK2. The first clock signal circuit CLK1 includes a sixth stacked inverter INV13 and a seventh stacked inverter INV14 whose power supply is VDDC; the second clock signal circuit CLK2 includes an eighth stacked inverter INV15 and a ninth stacked inverter INV16 whose power supply is VDD.

[0092] The sixth stacked inverter INV13 includes PMOS transistors p30 and p31, and NMOS transistors n30 and n31;

[0093] The source of the PMOS transistor p30 is connected to the power supply VDDC, and the gate receives the clock signal CLK. The source of the PMOS transistor p31 is connected to the drain of the PMOS transistor p30, and the gate receives the clock signal CLK. The source of the NMOS transistor n30 is grounded to VSS, and the gate receives the clock signal CLK. The source of the NMOS transistor n31 is connected to the drain of the NMOS transistor n30, and the gate receives the clock signal CLK. The drain of the NMOS transistor n31 is connected to the drain of the PMOS transistor p31 to form a common node CLKCN. The PMOS transistors p30, p31, NMOS transistors n30, and NMOS transistors n31 together constitute a sixth stacked inverter INV13 whose power supply is VDDC.

[0094] The seventh stacked inverter INV14 includes PMOS transistors p32 and p33, and NMOS transistors n32 and n33;

[0095] The source of the PMOS transistor p32 is connected to the power supply VDDC, and the gate receives the signal of the common node CLKCN. The source of the PMOS transistor p33 is connected to the drain of the PMOS transistor p32, and the gate receives the signal of the common node CLKCN. The source of the NMOS transistor n32 is grounded to VSS, and the gate receives the signal of the common node CLKCN. The source of the NMOS transistor n33 is connected to the drain of the NMOS transistor n32, and the gate receives the signal of the common node CLKCN. The drain of the NMOS transistor n33 is connected to the drain of the NMOS transistor n32, and the gate receives the signal of the common node CLKCN. The drain of the NMOS transistor n33 is connected to the drain of the PMOS transistor p33 to form a common node CLKCNN. The PMOS transistors p32, p33, NMOS transistors n32, and NMOS transistors n33 together constitute a seventh stacked inverter INV14 whose power supply is VDDC.

[0096] The eighth stacked inverter INV15 includes PMOS transistors p34 and p35, and NMOS transistors n34 and n35;

[0097] The source of the PMOS transistor p34 is connected to the power supply VDD, and the gate receives the clock signal CLK. The source of the PMOS transistor p35 is connected to the drain of the PMOS transistor p34, and the gate receives the clock signal CLK. The source of the NMOS transistor n34 is grounded to VSS, and the gate receives the clock signal CLK. The source of the NMOS transistor n35 is connected to the drain of the NMOS transistor n34, and the gate receives the clock signal CLK. The drain of the NMOS transistor n35 is connected to the drain of the PMOS transistor p35 to form a common node CLKN. The PMOS transistors p34, p35, NMOS transistors n34, and NMOS transistors n35 together constitute an eighth stacked inverter INV15 whose power supply is VDD.

[0098] The ninth stacked inverter INV16 includes PMOS transistors p36 and p37, and NMOS transistors n36 and n37;

[0099] The source of the PMOS transistor p36 is connected to the power supply VDD, and the gate receives the signal of the common node CLKN; the source of the PMOS transistor p37 is connected to the drain of the PMOS transistor p36, and the gate receives the signal of the common node CLKN; the source of the NMOS transistor n36 is grounded to VSS, and the gate receives the signal of the common node CLKN; the source of the NMOS transistor n37 is connected to the drain of the NMOS transistor n36, the gate receives the signal of the common node CLKN, and the drain is connected to the drain of the PMOS transistor p37 to form a common node CLKNN. The PMOS transistor p36, PMOS transistor p37, NMOS transistor n36, and NMOS transistor n37 together constitute a ninth stacked inverter INV16 whose power supply is VDD.

[0100] Working principle:

[0101] See Figure 1 、 Figure 2 It can be seen that when the clock signal CLK is at a high level, the MOS transistors p7 and n7 in the master latch circuit are turned off, p12 and n12 are turned on, the first clock-controlled stacked inverter INV3 whose power supply is VDD and controlled by the second clock signal circuit CLK2 is not turned on, and the second clock-controlled stacked inverter INV5 whose power supply is VDD and controlled by the second clock signal circuit CLK2 is turned on. At this time, the master latch circuit is in a latched state; the MOS transistors p15 and n15 in the transmission control circuit are turned on, the third clock-controlled stacked inverter INV6 whose power supply is VDD and controlled by the second clock signal circuit CLK2 is turned on, and the output signal of the master latch circuit is input into the slave latch circuit;

[0102] The MOS tubes p23 and n23 in the slave latch circuit are turned on, p20, n20, p26 and n26 are turned off, the fifth clock-controlled stack inverter INV9 controlled by the first clock signal circuit CLK1 with the power supply VDDC is turned on, the fourth clock-controlled stack inverter INV8 controlled by the first clock signal circuit CLK1 with the power supply VDDC is not turned on, and the sixth clock-controlled stack inverter INV10 controlled by the second clock signal circuit CLK2 with the power supply VDD is not turned on. At this time, the slave latch circuit is in a transparent state.

[0103] When the clock signal CLK is at a low level, the MOS transistors p7 and n7 in the main latch circuit are turned on, p12 and n12 are turned off, the first clock-controlled stacked inverter INV3 whose power supply is VDD and controlled by the second clock signal circuit CLK2 is turned on, and the second clock-controlled stacked inverter INV5 whose power supply is VDD and controlled by the second clock signal circuit CLK2 is turned off. At this time, the main latch circuit is in a transparent state.

[0104] The MOS transistors p15 and n15 in the transmission control circuit are turned off, the third clock-controlled stacked inverter INV6 controlled by the second clock signal circuit CLK2 with the power supply VDD is not conductive, and the output signal of the master latch circuit cannot be input into the slave latch circuit; the MOS transistors p23 and n23 in the slave latch circuit are turned off, p20, n20, p26 and n26 are turned on, the fifth clock-controlled stacked inverter INV9 controlled by the first clock signal circuit CLK1 with the power supply VDDC is not conductive, the fourth clock-controlled stacked inverter INV8 controlled by the first clock signal circuit CLK1 with the power supply VDDC is conductive, and the sixth clock-controlled stacked inverter INV10 controlled by the second clock signal circuit CLK2 with the power supply VDD is conductive. At this time, the slave latch circuit is in a latched state.

[0105] When input signal D is high, NMOS transistors n1 and n2 are simultaneously turned on, the signal at common node N1 is low, PMOS transistors p3 and p4 are simultaneously turned on, and the signal at common node N2 is high. Clock signal CLK is low, PMOS transistors p30, p31, p34, and p35 are simultaneously turned on, the signals at common nodes CLKCN and CLKN are high, NMOS transistors n32, n33, n36, and n37 are simultaneously turned on, the signals at common nodes CLKCNN and CLKNN are low, NMOS transistors n5, n6, and n7 are simultaneously turned on, the signal at common node N3 is low, PMOS transistors p8 and p9 are simultaneously turned on, the signal at common node N4 is high, and the power supply is VDD. The third clock-controlled stacked inverter INV6, controlled by the second clock signal circuit CLK2, is not turned on, and the output signal of the master latch circuit cannot be input into the slave latch circuit.

[0106] When the clock signal CLK is high, the NMOS tubes n30, n31, n34, and n35 are turned on at the same time, the common node CLKCN and CLKN signals are low, the PMOS tubes p32, p33, p36, and p37 are turned on at the same time, the common node CLKCNN and CLKNN signals are high, the power supply is VDD, and the first clock-controlled stacked inverter INV3 controlled by the second clock signal circuit CLK2 is not turned on, and the input circuit signal cannot be input to the main latch circuit. The NMOS tubes n10, n11, and n12 are turned on at the same time, and the power supply is VDD. The second clock-controlled stacked inverter INV5 controlled by the second clock signal circuit CLK2 is turned on, and the main latch The storage circuit is in a latched state, the signals at the common nodes N3 and N4 remain unchanged, the NMOS transistors n13, n14, and n15 are turned on at the same time, the power supply is VDD, and the third clock controlled by the second clock signal circuit CLK2 controls the stacked inverter INV6 to be turned on, the master latch circuit signal is input to the slave latch circuit, the common node N5 signal is low, the PMOS transistors p21, p22, p23, p27, and p28 are turned on at the same time, the common nodes S1 and S2 signals are high, the NMOS transistors n16 and n17 are turned on at the same time, the common node N5 signal remains unchanged, the slave latch circuit is in a transparent state, the PMOS transistor p29 is turned on, and the output signal of the common node Q is high;

[0107] When the clock signal CLK is low, the PMOS tubes p30, p31, p34, and p35 are turned on at the same time, the common node CLKCN and CLKN signals are high, the NMOS tubes n32, n33, n36, and n37 are turned on at the same time, the common node CLKCNN and CLKNN signals are low, the NMOS tubes n5, n6, and n7 are turned on at the same time, the power supply is VDD, and the first clock-controlled stacked inverter INV3 controlled by the second clock signal circuit CLK2 is turned on, the MOS tubes p12 and n12 are turned off, the power supply is VDD, and the second clock-controlled stacked inverter INV5 controlled by the second clock signal circuit CLK2 is not turned on, the main latch circuit is in a transparent state, and the common node The N3 and N4 signals remain unchanged, the third clock-controlled stacked inverter INV6 controlled by the second clock signal circuit CLK2 with the power supply VDD is not conducting, the output signal of the master latch circuit cannot be input into the slave latch circuit, the common node N5 signal is at a low level and remains unchanged, the fifth clock-controlled stacked inverter INV9 controlled by the first clock signal circuit CLK1 with the power supply VDDC in the slave latch circuit is not conducting, the common nodes S1 and S2 signals remain unchanged, the NMOS tubes n18, n19, n20, n24, n25, and n26 are turned on, the common node N5 signal is at a low level and remains unchanged, the slave latch circuit is in a latched state, the PMOS tube p29 is turned on, and the output signal of the common node Q is at a high level.

[0108] When the input signal D is low, the PMOS transistors p1 and p2 are turned on at the same time, the signal at the common node N1 is high, the NMOS transistors n3 and n4 are turned on at the same time, the signal at the common node N2 is low, the clock signal CLK is low, the PMOS transistors p30, p31, p34, and p35 are turned on at the same time, the signals at the common nodes CLKCN and CLKN are high, the NMOS transistors n32, n33, n36, and n37 are turned on at the same time, the signals at the common nodes CLKCNN and CLKNN are low, the PMOS transistors p5, p6, and p7 are turned on at the same time, the signal at the common node N3 is high, the NMOS transistors n8 and n9 are turned on at the same time, the signal at the common node N4 is low, the power supply is VDD, and the third clock-controlled stacked inverter INV6 controlled by the second clock signal circuit CLK2 is not turned on, and the output signal of the master latch circuit cannot be input into the slave latch circuit;

[0109] When the clock signal CLK is high, the NMOS tubes n30, n31, n34, and n35 are turned on at the same time, the common node CLKCN and CLKN signals are low, the PMOS tubes p32, p33, p36, and p37 are turned on at the same time, the common node CLKCNN and CLKNN signals are high, the power supply is VDD, and the first clock-controlled stacked inverter INV3 controlled by the second clock signal circuit CLK2 is not turned on, and the input circuit signal cannot be input to the main latch circuit. The PMOS tubes p10, p11, and p12 are turned on at the same time, and the power supply is VDD. The second clock-controlled stacked inverter INV5 controlled by the second clock signal circuit CLK2 is turned on, and the main latch The storage circuit is in a latched state, the signals at the common nodes N3 and N4 remain unchanged, the PMOS transistors p13, p14, and p15 are turned on at the same time, the power supply is VDD, and the third clock controlled by the second clock signal circuit CLK2 controls the stacked inverter INV6 to be turned on, the master latch circuit signal is input to the slave latch circuit, the common node N5 signal is high, the NMOS transistors n21, n22, n23, n27, and n28 are turned on at the same time, the common nodes S1 and S2 signals are low, the PMOS transistors p16 and p17 are turned on at the same time, the common node N5 signal remains unchanged, the slave latch circuit is in a transparent state, the NMOS transistor n29 is turned on, and the output signal of the common node Q is low;

[0110] When the clock signal CLK is low, the PMOS tubes p30, p31, p34, and p35 are turned on at the same time, the common node CLKCN and CLKN signals are high, the NMOS tubes n32, n33, n36, and n37 are turned on at the same time, the common node CLKCNN and CLKNN signals are low, the PMOS tubes p5, p6, and p7 are turned on at the same time, the first clock-controlled stacked inverter INV3 controlled by the second clock signal circuit CLK2 with the power supply VDD is turned on, the MOS tubes p12 and n12 are turned off, the second clock-controlled stacked inverter INV5 controlled by the second clock signal circuit CLK2 with the power supply VDD is not turned on, the main latch circuit is in a transparent state, and the common node The N3 and N4 signals remain unchanged, the third clock-controlled stacked inverter INV6 controlled by the second clock signal circuit CLK2 with the power supply VDD is not conducting, the output signal of the master latch circuit cannot be input into the slave latch circuit, the common node N5 signal is at a high level and remains unchanged, and the fifth clock-controlled stacked inverter INV9 controlled by the first clock signal circuit CLK1 with the power supply VDDC in the slave latch circuit is not conducting, the common nodes S1 and S2 signals remain unchanged, the PMOS tubes p18, p19, p20, p24, p25, and p26 are turned on, the common node N5 signal is at a high level and remains unchanged, the slave latch circuit is in a latched state, the NMOS tube n29 is turned on, and the output signal of the common node Q is still at a low level.

[0111] In summary, the normal logical function of the trigger of the present invention is achieved.

[0112] When input signal D is low and clock signal CLK is high, the master latch circuit is in a latched state. The third clocked stacked inverter INV6, whose power supply is VDD and controlled by the second clock signal circuit CLK2, is turned on. The slave latch circuit is in a transparent state, with the signal at common node N4 at a low level and the signal at common node N5 at a high level. If the power supply VDD is affected by the instantaneous dose rate and is pulled low, common node N5 outputs an error signal. The slave latch structure, consisting of the sixth clocked stacked inverter INV10, whose power supply is VDD and controlled by the second clock signal circuit CLK2, and the fifth stacked inverter INV11, whose power supply is VDD, is affected and turned on, outputting an error signal that affects common node N5. At this time, since power supply VDDC is unaffected, the fourth stacked inverter INV7, whose power supply is VDDC and controlled by the first clock signal circuit CLK1, whose power supply is VDDC, pulls the signal at common node N5 high through feedback, causing it to recover.

[0113] When the input signal D is low and the clock signal CLK is low, the master latch circuit is in a transparent state. The third clocked stacked inverter INV6, whose power supply is VDD and controlled by the second clock signal circuit CLK2, is non-conductive. The signal at the common node N5 represents the data stored in the slave latch circuit and is assumed to be high. In the slave latch circuit, the slave latch structure formed by the sixth clocked stacked inverter INV10, whose power supply is VDD and controlled by the second clock signal circuit CLK2, and the fifth stacked inverter INV11, whose power supply is VDD, and the backup redundant latch structure formed by the fourth stacked inverter INV7, whose power supply is VDDC, and the fourth clocked stacked inverter INV8 and the fifth clocked stacked inverter INV9, whose power supply is VDDC and controlled by the first clock signal circuit CLK1, are in a latched state. The signals at the common nodes S1 and S2 are low. The power supply VDD signal is affected by the transient dose rate radiation and is pulled low. The slave latch structure formed by the sixth stacked inverter INV10, whose power supply is VDD and controlled by the second clock signal circuit CLK2, and the fifth stacked inverter INV11, whose power supply is VDD, is turned off, and the signal at common node N5 is pulled low. At this time, the fifth stacked inverter INV9, whose power supply is VDDC and controlled by the first clock signal circuit CLK1, is turned off, ensuring that the signal at common node S1 is not affected by the disturbance of the signal at common node N5. Common node S1 still latches the correct signal. The fourth stacked inverter INV7, whose power supply is VDDC and controlled by the first clock signal circuit CLK1, and the fourth stacked inverter INV8, whose power supply is VDDC and controlled by the first clock signal circuit CLK1, output the correct latched signal, restoring the signal at common node N5.

[0114] The input signal D is at a high level. When the clock signal CLK is at a high level, the main latch circuit is in a latched state, the third clock-controlled stacked inverter INV6 controlled by the second clock signal circuit CLK2 with a power supply of VDD is turned on, and the slave latch circuit is in a transparent state. The common node N4 signal is at a high level, the common node N5 signal is at a low level, and the common nodes S1 and S2 signals are at a high level. At this time, the power supply VDD signal is affected by the instantaneous dose rate radiation and is pulled low, and the common node S2 signal is pulled low. The signal output from the slave latch structure composed of the sixth clock-controlled stacked inverter INV10 controlled by the second clock signal circuit CLK2 with a power supply of VDD and the fifth stacked inverter INV11 with a power supply of VDD to the common node N5 is still at a low level. The circuit composed of the fourth stacked inverter INV7 whose power supply is VDDC and the fifth clock-controlled stacked inverter INV9 whose power supply is VDDC and is controlled by the first clock signal circuit CLK1 is not affected by the disturbance of the power supply VDD, and the common node S1 signal is still at a high level. At this time, the signal outputted by the fourth stacked inverter INV7 whose power supply is VDDC to the common node N5 is also at a low level.

[0115] When input signal D is high and clock signal CLK is low, the master latch circuit is in a transparent state. Third clocked stacked inverter INV6, controlled by second clock signal circuit CLK2 and powered by VDD, is non-conductive. The signal at common node N5 represents the data stored in the slave latch circuit and is assumed to be low. At this point, the slave latch circuit, consisting of sixth clocked stacked inverter INV10, controlled by second clock signal circuit CLK2 and powered by VDD, and fifth stacked inverter INV11, also powered by VDD, and the backup redundant latch structure, consisting of fourth stacked inverter INV7, powered by VDDC, and fourth and fifth clocked stacked inverters INV8 and INV9, powered by VDDC and controlled by first clock signal circuit CLK1, are in a latched state. The signals at common nodes S1 and S2 are high. If power supply VDD is affected by transient dose rate radiation and is pulled low, the signal at common node S2 is also pulled low. The fifth clock-controlled stacked inverter INV9, whose power supply is VDDC and is controlled by the first clock signal circuit CLK1, is not conductive, ensuring that the common node S1 signal is not affected by the disturbance of the common node N5 signal. The common node S1 still maintains the correct high-level signal. The backup redundant latch structure composed of the fourth stacked inverter INV7, whose power supply is VDDC, and the fourth clock-controlled stacked inverter INV8 and the fifth clock-controlled stacked inverter INV9, whose power supply is VDDC and are controlled by the first clock signal circuit CLK1, outputs a signal to the common node N5 that is still at a low level.

[0116] When connecting the power supply VDDC in the layout, it should be designed to be connected at the shortest distance. At the same time, the width of the metal line should meet the widest value of the process design rules to reduce the voltage collapse effect of the power supply voltage after being irradiated by the instantaneous dose rate.

[0117] In summary, the embodiments of the present invention have the ability to resist instantaneous dose rate radiation.

[0118] The above description is merely a preferred embodiment of the present invention, and the scope of protection of the present invention is not limited thereto. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and substitutions. Any modifications, equivalent substitutions, improvements, and the like made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A dual-power redundant latch instantaneous dose rate radiation hardened trigger for FDSOI process, characterized by include: An input circuit, a master latch circuit, a transmission control circuit, a slave latch circuit, an output circuit, a first clock signal circuit CLK1, and a second clock signal circuit CLK2; The first clock signal circuit CLK1 includes a sixth stacked inverter INV13 and a seventh stacked inverter INV14 whose power supply is VDDC; the second clock signal circuit CLK2 includes an eighth stacked inverter INV15 and a ninth stacked inverter INV16 whose power supply is VDD; The sixth stacked inverter INV13 receives the clock signal CLK sent from the outside, and transmits its output signal to the seventh stacked inverter INV14. The output signal of the seventh stacked inverter INV14 and the output signal of the sixth stacked inverter INV13 serve together as the output clock signal of the first clock signal circuit CLK1. The eighth stacked inverter INV15 receives the clock signal CLK sent from the outside, and transmits its output signal to the ninth stacked inverter INV16. The output signal of the ninth stacked inverter INV16 and the output signal of the eighth stacked inverter INV15 serve together as the output clock signal of the second clock signal circuit CLK2. The input circuit includes a first stacked inverter INV1 and a second stacked inverter INV2 with a power supply of VDD; the master latch circuit includes a first clocked stacked inverter INV3, a third stacked inverter INV4, and a second clocked stacked inverter INV5 with a power supply of VDD; the transmission control circuit includes a third clocked stacked inverter INV6 with a power supply of VDD; the slave latch circuit includes a fourth stacked inverter INV7, a fourth clocked stacked inverter INV8, a fifth clocked stacked inverter INV9 with a power supply of VDDC, and a sixth clocked stacked inverter INV10 and a fifth stacked inverter INV11 with a power supply of VDD; the output circuit includes an inverter INV12 with a power supply of VDDC; The first stacked inverter INV1 receives an input signal from the outside, and the output signal of the first stacked inverter INV1 is transmitted to the second stacked inverter INV2; the output signal of the second stacked inverter INV2 is transmitted to the first clock-controlled stacked inverter INV3, and the first clock-controlled stacked inverter INV3 also receives the output clock signal of the second clock signal circuit CLK2. The output signal of the first clock-controlled stacked inverter INV3 is transmitted to the third stacked inverter INV4, and the output signal of the third stacked inverter INV4 is transmitted to the second clock-controlled stacked inverter INV5 and the third clock-controlled stacked inverter INV6. The second clock-controlled stacked inverter INV5 and the third clock-controlled stacked inverter INV6 also receive the output clock signal of the second clock signal circuit CLK2. The output signal of the second clock-controlled stacked inverter INV5 is transmitted to the third stacked inverter INV4, and the output signal of the third clock-controlled stacked inverter INV6 is transmitted to the fifth clock-controlled stacked inverter INV9, the fifth stacked inverter INV11 and the inverter INV12. The inverter INV9 also receives the output clock signal of the first clock signal circuit CLK1. The output signal of the fifth clock-controlled stacked inverter INV9 is transmitted to the fourth stacked inverter INV7. The output signal of the fourth stacked inverter INV7 is transmitted to the fourth clock-controlled stacked inverter INV8, the fifth clock-controlled stacked inverter INV9, the fifth stacked inverter INV11 and the inverter INV12. The fourth clock-controlled stacked inverter INV8 also receives the output clock signal of the first clock signal circuit CLK1. The fourth clock-controlled stacked inverter INV8 also receives the output clock signal of the first clock signal circuit CLK1. The output signal of the inverter INV8 is transmitted to the fourth stacked inverter INV7, the output signal of the fifth stacked inverter INV11 is transmitted to the sixth clock-controlled stacked inverter INV10, the sixth clock-controlled stacked inverter INV10 also receives the output clock signal of the second clock signal circuit CLK2, the output signal of the sixth clock-controlled stacked inverter INV10 is transmitted to the fifth clock-controlled stacked inverter INV9, the fifth stacked inverter INV11 and the inverter INV12, and the output signal of the inverter INV12 is the output of the output circuit; The first clock signal circuit CLK1 sends the clock signal to the slave latch circuit; the second clock signal circuit CLK2 sends the clock signal to the master latch circuit, the transmission control circuit and the slave latch circuit; The input circuit sends the input data signal to the main latch circuit when the clock signal is at a low level; the main latch circuit sends the data signal to the transmission control circuit when the clock signal is at a low level; the main latch circuit latches the data signal when the clock signal is at a high level; The transmission control circuit sends the data signal to the slave latch circuit when the clock signal is at a high level; the slave latch circuit sends the data signal to the output circuit when the clock signal is at a high level; The slave latch circuit latches the data signal when the clock signal is at a low level, and sends the latched data signal to the output circuit; the output circuit outputs the data signal.

2. The dual-power redundant latch instantaneous dose rate radiation hardened trigger for FDSOI process according to claim 1, characterized in that: The sixth stacked inverter INV13 includes PMOS transistors p30 and p31, and NMOS transistors n30 and n31; The source of the PMOS transistor p30 is connected to the power supply VDDC, and the gate receives the clock signal CLK; the source of the PMOS transistor p31 is connected to the drain of the PMOS transistor p30, and the gate receives the clock signal CLK; the source of the NMOS transistor n30 is grounded to VSS, and the gate receives the clock signal CLK; the source of the NMOS transistor n31 is connected to the drain of the NMOS transistor n30, and the gate receives the clock signal CLK, and the drain is connected to the drain of the PMOS transistor p31 to form a common node CLKCN. The seventh stacked inverter INV14 includes PMOS transistors p32 and p33, and NMOS transistors n32 and n33; The source of the PMOS transistor p32 is connected to the power supply VDDC, and the gate receives the signal of the common node CLKCN; The source of the PMOS transistor p33 is connected to the drain of the PMOS transistor p32, and the gate receives the signal of the common node CLKCN; The source of the NMOS transistor n32 is grounded to VSS, and the gate receives the signal of the common node CLKCN; The source of the NMOS transistor n33 is connected to the drain of the NMOS transistor n32, the gate receives the signal of the common node CLKCN, and the drain is connected to the drain of the PMOS transistor p33 to form the common node CLKCNN output.

3. The dual-power redundant latch instantaneous dose rate radiation hardened trigger for FDSOI process according to claim 1, characterized in that: The eighth stacked inverter INV15 includes PMOS transistors p34 and p35, and NMOS transistors n34 and n35; The source of the PMOS transistor p34 is connected to the power supply VDD, and the gate receives the clock signal CLK; the source of the PMOS transistor p35 is connected to the drain of the PMOS transistor p34, and the gate receives the clock signal CLK; the source of the NMOS transistor n34 is grounded to VSS, and the gate receives the clock signal CLK; the source of the NMOS transistor n35 is connected to the drain of the NMOS transistor n34, and the gate receives the clock signal CLK, and the drain is connected to the drain of the PMOS transistor p35 to form a common node CLKN; The ninth stacked inverter INV16 includes PMOS transistors p36 and p37, and NMOS transistors n36 and n37; The source of the PMOS transistor p36 is connected to the power supply VDD, and the gate receives the signal of the common node CLKN; The source of the PMOS transistor p37 is connected to the drain of the PMOS transistor p36, and the gate receives the signal of the common node CLKN; the source of the NMOS transistor n36 is grounded to VSS, and the gate receives the signal of the common node CLKN; the source of the NMOS transistor n37 is connected to the drain of the NMOS transistor n36, the gate receives the signal of the common node CLKN, and the drain is connected to the drain of the PMOS transistor p37 to form a common node CLKNN output.

4. The dual-power redundant latch instantaneous dose rate radiation hardened trigger for FDSOI process according to claim 3, characterized in that: The first stacked inverter INV1 includes PMOS transistors p1 and p2, and NMOS transistors n1 and n2; The source of the PMOS transistor p1 is connected to the power supply VDD, and the gate receives the input signal D; the source of the PMOS transistor p2 is connected to the drain of the PMOS transistor p1, and the gate receives the input signal D; the source of the NMOS transistor n1 is grounded to VSS, and the gate receives the input signal D; the source of the NMOS transistor n2 is connected to the drain of the NMOS transistor n1, and the gate receives the input signal D, and the drain is connected to the drain of the PMOS transistor p2 to form a common node N1; The second stacked inverter INV2 includes PMOS transistors p3 and p4, and NMOS transistors n3 and n4; The source of the PMOS transistor p3 is connected to the power supply VDD, and the gate receives the signal of the common node N1; the source of the PMOS transistor p4 is connected to the drain of the PMOS transistor p3, and the gate receives the signal of the common node N1; the source of the NMOS transistor n3 is grounded to VSS, and the gate receives the signal of the common node N1; the source of the NMOS transistor n4 is connected to the drain of the NMOS transistor n3, the gate receives the signal of the common node N1, and the drain is connected to the drain of the PMOS transistor p4 to form a common node N2.

5. The dual-power redundant latch instantaneous dose rate radiation hardened trigger of FDSOI process according to claim 4, characterized in that: The first clocked stacked inverter INV3 includes PMOS transistors p5, p6, p7, and NMOS transistors n5, n6, n7; The source of the PMOS transistor p5 is connected to the power supply VDD, and the gate receives the signal of the common node N2; the source of the PMOS transistor p6 is connected to the drain of the PMOS transistor p5, and the gate receives the signal of the common node N2; The source of the PMOS transistor p7 is connected to the drain of the PMOS transistor p6, and its gate receives the signal from the common node CLKNN. The source of the NMOS transistor n5 is grounded to VSS, and its gate receives the signal from the common node N2. The source of the NMOS transistor n6 is connected to the drain of the NMOS transistor n5, and its gate receives the signal from the common node N2. The source of the NMOS transistor n7 is connected to the drain of the NMOS transistor n6, and its gate receives the signal from the common node CLKN. Its drain is connected to the drain of the PMOS transistor p7 to form a common node N3. The third stacked inverter INV4 includes PMOS transistors p8 and p9, and NMOS transistors n8 and n9; The source of the PMOS transistor p8 is connected to the power supply VDD, and the gate receives the signal of the common node N3; the source of the PMOS transistor p9 is connected to the drain of the PMOS transistor p8, and the gate receives the signal of the common node N3; the source of the NMOS transistor n8 is grounded to VSS, and the gate receives the signal of the common node N3; the source of the NMOS transistor n9 is connected to the drain of the NMOS transistor n8, the gate receives the signal of the common node N3, and the drain is connected to the drain of the PMOS transistor p9, forming a common node N4. The second clocked stacked inverter INV5 includes PMOS transistors p10, p11, p12, and NMOS transistors n10, n11, n12; The source of the PMOS transistor p10 is connected to the power supply VDD, and the gate receives the signal of the common node N4; the source of the PMOS transistor p11 is connected to the drain of the PMOS transistor p10, and the gate receives the signal of the common node N4; the source of the PMOS transistor p12 is connected to the drain of the PMOS transistor p11, the gate receives the signal of the common node CLKN, and the drain is connected to the common node N3; the source of the NMOS transistor n10 is grounded to VSS, and the gate receives the signal of the common node N4; the source of the NMOS transistor n11 is connected to the drain of the NMOS transistor n10, and the gate receives the signal of the common node N4; the source of the NMOS transistor n12 is connected to the drain of the NMOS transistor n11, the gate receives the signal of the common node CLKNN, and the drain is connected to the common node N3.

6. The dual-power redundant latch instantaneous dose rate radiation hardened trigger of FDSOI process according to claim 5, characterized in that: The third clock-controlled stacked inverter INV6 includes PMOS transistors p13, p14, p15, and NMOS transistors n13, n14, and n15; The source of the PMOS transistor p13 is connected to the power supply VDD, and the gate receives the signal of the common node N4; The source of the PMOS transistor p14 is connected to the drain of the PMOS transistor p13, and the gate receives the signal of the common node N4; The source of the PMOS transistor p15 is connected to the drain of the PMOS transistor p14, and the gate receives the signal of the common node CLKN; the source of the NMOS transistor n13 is grounded to VSS, and the gate receives the signal of the common node N4; the source of the NMOS transistor n14 is connected to the drain of the NMOS transistor n13, and the gate receives the signal of the common node N4; the source of the NMOS transistor n15 is connected to the drain of the NMOS transistor n14, the gate receives the signal of the common node CLKNN, and the drain is connected to the drain of the PMOS transistor p15, forming a common node N5.

7. The dual-power redundant latch instantaneous dose rate radiation hardened trigger of FDSOI process according to claim 6, characterized in that: The fifth clocked stacked inverter INV9 includes PMOS transistors p21, p22, p23, and NMOS transistors n21, n22, and n23; The source of the PMOS transistor p21 is connected to the power supply VDDC, and the gate receives the signal of the common node N5; the source of the PMOS transistor p22 is connected to the drain of the PMOS transistor p21, and the gate receives the signal of the common node N5; The source of the PMOS transistor p23 is connected to the drain of the PMOS transistor p22, and the gate receives the signal of the common node CLKCN; The source of the NMOS transistor n21 is grounded to VSS, and its gate receives a signal from the common node N5. The source of the NMOS transistor n22 is connected to the drain of the NMOS transistor n21, and its gate receives a signal from the common node N5. The source of the NMOS transistor n23 is connected to the drain of the NMOS transistor n22, and its gate receives a signal from the common node CLKCNN. Its drain is connected to the drain of the PMOS transistor p23 to form a common node S1. The fourth stacked inverter INV7 includes PMOS transistors p16 and p17, and NMOS transistors n16 and n17; The source of the PMOS transistor p16 is connected to the power supply VDDC, and the gate receives the signal of the common node S1; the source of the PMOS transistor p17 is connected to the drain of the PMOS transistor p16, the gate receives the signal of the common node S1, and the drain is connected to the common node N5; the source of the NMOS transistor n16 is grounded to VSS, and the gate receives the signal of the common node S1; the source of the NMOS transistor n17 is connected to the drain of the NMOS transistor n16, the gate receives the signal of the common node S1, and the drain is connected to the common node N5; The fourth clock-controlled stacked inverter INV8 includes PMOS transistors p18, p19, p20, and NMOS transistors n18, n19, n20; The source of the PMOS transistor p18 is connected to the power supply VDDC, and the gate is connected to the common node N5; the source of the PMOS transistor p19 is connected to the drain of the PMOS transistor p18, and the gate is connected to the common node N5; the source of the PMOS transistor p20 is connected to the drain of the PMOS transistor p19, the gate receives the signal of the common node CLKCNN, and the drain is connected to the common node S1; the source of the NMOS transistor n18 is grounded VSS, and the gate is connected to the common node N5; the source of the NMOS transistor n19 is connected to the drain of the NMOS transistor n18, and the gate is connected to the common node N5; the source of the NMOS transistor n20 is connected to the drain of the NMOS transistor n19, the gate receives the signal of the common node CLKCN, and the drain is connected to the common node S1.

8. The dual-power redundant latch instantaneous dose rate radiation hardened trigger of FDSOI process according to claim 7, characterized in that: From the latch circuit, the fifth stacked inverter INV11 includes PMOS transistors p27 and p28, and NMOS transistors n27 and n28; The source of the PMOS transistor p27 is connected to the power supply VDD, and the gate receives the signal of the common node N5; the source of the PMOS transistor p28 is connected to the drain of the PMOS transistor p27, and the gate receives the signal of the common node N5; the source of the NMOS transistor n27 is grounded to VSS, and the gate receives the signal of the common node N5; the source of the NMOS transistor n28 is connected to the drain of the NMOS transistor n27, the gate receives the signal of the common node N5, and the drain is connected to the drain of the PMOS transistor p28 to form a common node S2; The sixth clocked stacked inverter INV10 includes PMOS transistors p24, p25, p26, and NMOS transistors n24, n25, and n26; The source of the PMOS transistor p24 is connected to the power supply VDD, and the gate receives the signal of the common node S2; the source of the PMOS transistor p25 is connected to the drain of the PMOS transistor p24, and the gate receives the signal of the common node S2; the source of the PMOS transistor p26 is connected to the drain of the PMOS transistor p25, the gate receives the signal of the common node CLKNN, and the drain is connected to the common node N5; the source of the NMOS transistor n24 is grounded to VSS, and the gate receives the signal of the common node S2; the source of the NMOS transistor n25 is connected to the drain of the NMOS transistor n24, and the gate receives the signal of the common node S2; the source of the NMOS transistor n26 is connected to the drain of the NMOS transistor n25, the gate receives the signal of the common node CLKN, and the drain is connected to the common node N5.

9. The dual-power redundant latch instantaneous dose rate radiation hardened trigger of FDSOI process according to claim 8, characterized in that: The inverter INV12 includes a PMOS transistor p29 and an NMOS transistor n29; The source of the PMOS transistor p29 is connected to the power supply VDDC, and the gate receives the common node N5 signal; the source of the NMOS transistor n29 is grounded VSS, the gate receives the common node N5 signal, and the drain is connected to the drain of the PMOS transistor p29 to form a common node Q.

10. The dual-power redundant latch instantaneous dose rate radiation hardened trigger of FDSOI process according to claim 9, characterized in that: The metal lines between the power supply VDDC signals are routed at the shortest distance and are designed to be the widest metal lines that meet the process design rules.

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