Display panel and display device

Abstract

The present invention discloses a display panel and a display device, relating to the technical field of displays, including: a substrate and an array layer disposed on one side of the substrate. The array layer includes a first metal layer, an active layer, and a second metal layer. Along a first direction, the first metal layer and the second metal layer are located on both sides of the active layer, and the first direction is perpendicular to the substrate. The array layer includes at least one first transistor. The first transistor includes a first sub-transistor and a second sub-transistor connected in series. The first sub-transistor includes a first active layer located in the active layer, and the second sub-transistor includes a second active layer located in the active layer. The first active layer and the second active layer are connected. Along the first direction, the first metal layer overlaps both the first active layer and the second active layer, the second metal layer overlaps the second active layer, and does not overlap the first active layer. In this way, the on-state current of the second sub-transistor can be effectively increased, the response speed of the first transistor can be increased, and thus it is beneficial to increase the overall response speed of the product.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a display panel and a display device. Background Art

[0002] From the CRT (Cathode Ray Tube) era to the LCD (Liquid Crystal Display) era, and now to the OLED (Organic Light-Emitting Diode) display era and the LED display era, the display industry has experienced decades of development and has changed with each passing day. The display industry is closely related to our lives, from traditional mobile phones, tablets, TVs, computers to today's smart wearable devices, virtual reality devices, car displays and other electronic devices, all of which are inseparable from display technology.

[0003] In the display panel of the related art, a driving circuit is usually provided to control the display of the display panel. At present, the response speed of the display panel is closely related to the response speed of the transistor in the driving circuit. How to effectively improve the response speed of the transistor has become one of the technical problems that need to be solved urgently at this stage. Summary of the invention

[0004] In view of this, the present invention provides a display panel and a display device to improve the response speed of transistors, thereby improving the overall response speed of the display panel.

[0005] In a first aspect, the present invention provides a display panel, comprising a substrate and an array layer disposed on one side of the substrate, wherein the array layer comprises a first metal layer, an active layer and a second metal layer, wherein the first metal layer and the second metal layer are located on both sides of the active layer along a first direction, and the first direction is perpendicular to the substrate;

[0006] The array layer includes at least one first transistor, the first transistor includes a first sub-transistor and a second sub-transistor connected in series, the first sub-transistor includes a first active layer located in the active layer, the second sub-transistor includes a second active layer located in the active layer, and the first active layer and the second active layer are connected;

[0007] Along the first direction, the first metal layer overlaps both the first active layer and the second active layer, the second metal layer overlaps the second active layer, and does not overlap the first active layer.

[0008] In a second aspect, based on the same inventive concept, the present invention provides a display device, comprising the display panel provided by the first aspect of the present invention.

[0009] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0010] In the display panel and the display device provided by the present invention, the array layer includes at least one first transistor. The first transistor includes a first sub-transistor and a second sub-transistor connected in series. The active layers of the first sub-transistor and the second sub-transistor are located in the same layer and are connected to each other. Among them, the first metal layer overlaps with the first active layer in the first direction to form the gate of the first sub-transistor, and the first metal layer overlaps with the second active layer in the first direction to form the gate of the second sub-transistor. Along the first direction, the second metal layer overlaps with the second active layer and does not overlap with the first active layer. In this way, the vertical electric field of the first transistor is mainly controlled by the gate. The vertical electric field of the second sub-transistor is controlled not only by the gate but also by the second metal layer. In this way, the on-state current of the second sub-transistor can be effectively increased, which is beneficial to improving the response speed of the second sub-transistor, and further beneficial to improving the overall response speed of the display panel.

[0011] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned technical effects simultaneously.

[0012] Other features and advantages of the present invention will become clear from the following detailed description of the exemplary embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings incorporated in and constituting a part of this specification illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0014] Figure 1 Shown is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 Shown is a schematic connection diagram of a first sub-transistor and a second sub-transistor in a first transistor;

[0016] Figure 3 Shown is a top view of a first transistor included in a display panel;

[0017] Figure 4 Shown is the display panel Figure 3 A cross-sectional view of the first transistor in the AA direction in;

[0018] Figure 5 Shown is a schematic structural diagram of a transistor in the related art;

[0019] Figure 6 Shown is Figure 5 A cross-sectional view of the transistor in the BB direction in;

[0020] Figure 7 Shown is a relative positional relationship diagram of a first insulating layer, an active layer, and a second metal layer;

[0021] Figure 8 Shown is a cross-sectional view of a first transistor in the AA direction in a display panel; Figure 3 Another cross-sectional view of the first transistor in the AA direction in the display panel;

[0022] Figure 9 Shown is a top view structural diagram of a first transistor and a first electrode provided in an embodiment of the present invention;

[0023] Figure 10 Shown is Figure 9 A cross-sectional view of a transistor in the DD' direction in;

[0024] Figure 11 Shown is Figure 9 A cross-sectional view of a transistor in the CC' direction in;

[0025] Figure 12 Shown is a connection relationship diagram of a first transistor and a first electrode in a first region and a second region in a display panel;

[0026] Figure 13 Shown is a display panel Figure 3 Another cross-sectional view of the first transistor in the AA direction in the display panel;

[0027] Figure 14 Shown is a film layer structure diagram of two adjacent first transistors;

[0028] Figure 15 Shown is another film layer structure diagram of two adjacent first transistors;

[0029] Figure 16 Shown is another relative position relationship diagram of a first insulating layer, an active layer, and a second metal layer;

[0030] Figure 17 Shown is a film layer structure diagram of a display panel provided in an embodiment of the present invention;

[0031] Figure 18 Shown is a schematic diagram of a pixel driving circuit applied to a liquid crystal display panel;

[0032] Figure 19 Shown is a film layer structure diagram of a display panel provided in an embodiment of the present invention;

[0033] Figure 20 Shown is a schematic diagram of a driving circuit corresponding to an organic electroluminescent display panel;

[0034] Figure 21 Shown is a schematic structural diagram of a display device provided in an embodiment of the present invention. Detailed implementation manners

[0035] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and values set forth in these embodiments do not limit the scope of the present invention.

[0036] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way a limitation on the present invention or its application or use.

[0037] Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be regarded as part of the specification.

[0038] In all the examples shown and discussed herein, any specific values should be construed as merely exemplary and not as a limitation. Thus, other examples of the exemplary embodiments may have different values.

[0039] Various modifications and variations can be made to the present invention without departing from the spirit or scope thereof, which will be apparent to those skilled in the art. Accordingly, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by the embodiments of the present invention can be combined with each other without conflict.

[0040] It should be noted that: like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0041] Figure 1 Shown is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Figure 2 Shown is a schematic connection diagram of a first sub-transistor 11 and a second sub-transistor 12 in a first transistor 10. Figure 3 Shown is a top view of a first transistor 10 included in a display panel. Figure 4 Shown is a display panel Figure 3 A cross-sectional view of the first transistor 10 in the AA direction.

[0042] Please refer to Figures 1 to 4 , an embodiment of the present invention provides a display panel 100, including a substrate 00 and an array layer 01 disposed on one side of the substrate. The array layer 01 includes a first metal layer M1, an active layer 30, and a second metal layer M2. Along a first direction D1, the first metal layer M1 and the second metal layer M2 are located on both sides of the active layer 30, and the first direction D1 is perpendicular to the substrate 00.

[0043] The array layer 01 includes at least one first transistor 10. The first transistor 10 includes a first sub-transistor 11 and a second sub-transistor 12 connected in series. The first sub-transistor 11 includes a first active layer 31 located in the active layer 30, and the second sub-transistor 12 includes a second active layer 32 located in the active layer 30. The first active layer 31 and the second active layer 32 are connected.

[0044] Along the first direction D1, the first metal layer M1 overlaps with both the first active layer 31 and the second active layer 32, and the second metal layer M2 overlaps with the second active layer 32 and does not overlap with the first active layer 31.

[0045] It should be noted that Figure 1 Only a display panel with a rectangular structure is taken as an example for illustration, and the shape of the display panel is not limited. In some other embodiments of the present invention, the shape of the display panel can also be other shapes, such as a rounded rectangle, a circle, or other feasible shapes. Figure 1 Only the arrangement of the sub-pixels P in the display panel is schematically shown, and the actual pixel arrangement of the sub-pixels P in the display panel is not limited. Figure 3 Only the relevant film layers in the first transistor 10 are schematically shown. For example, only the active layer 30, the first metal layer M1, and the second metal layer M2 of the first transistor 10 are shown, and other film layer structures of the display panel are not shown. Figure 4 The shown embodiment can be regarded as a film layer structure at the position of the first transistor 10 in the display panel, mainly to reflect the relative position relationship of each film layer in the first transistor 10, and the actual number and size of the film layers of the display panel are not limited.

[0046] Continue to refer to Figures 1 to 4 , the display panel provided by the embodiment of the present invention includes at least one first transistor 10. The first transistor 10 includes a first sub-transistor 11 and a second sub-transistor 12. The first metal layer M1 overlaps with the first active layer 31 to form a first gate G1 of the first sub-transistor 11, and the first metal layer M1 overlaps with the second active layer 32 to form a second gate G2 of the second sub-transistor 12. Therefore, the first transistor 10 has two gates and is a transistor with a double-gate structure.

[0047] Figure 5 The figure shows a schematic structural diagram of a transistor in the related art. Figure 6 The figure shows Figure 5 a BB cross-sectional view of the transistor in Figure 5 and Figure 6, in the transistor with a double-gate structure in the related art, the active layer 30' has a U-shaped structure. The transistor includes a first sub-transistor 11' and a second sub-transistor 12'. The vertical electric fields of the first sub-transistor 11' and the second sub-transistor 12' are only controlled by the metal layer 20' where the corresponding gate is located, resulting in that the on-state currents of the two sub-transistors cannot be further increased, making the response speed of the double-gate transistor with such a structure slow, and thus the overall response speed of the display panel is slow.

[0048] In the display panel provided by the embodiment of the present invention, please refer to Figures 2 to 4 , a second metal layer M2 is introduced. Along the first direction D1, the second metal layer M2 overlaps with the second active layer 32 and does not overlap with the first active layer 31, so that the vertical electric field of the second sub-transistor 12 is controlled not only by the gate but also by the second metal layer M2. In this way, a channel is formed on the surface of the second active layer 32 facing the first metal layer M1, and another channel is formed on the surface of the second active layer 32 facing the second metal layer M2. When two channels are formed in the second sub-transistor 12, the on-state current of the second sub-transistor 12 can be effectively increased, which is beneficial to improving the response speed of the second sub-transistor 12, and further beneficial to improving the overall response speed of the first transistor 10. When the overall response speed of the first transistor 10 is improved, the overall response speed of the display panel will also be effectively improved. In addition, the vertical electric field of the first sub-transistor 11 is only controlled by the gate, so the first sub-transistor 11 can be used to control the overall threshold voltage of the first transistor 10 to ensure the stability of the first transistor 10.

[0049] Continue to refer to Figure 4 and Figure 7 , Figure 7 As shown in

[0050] Specifically, continue to refer to Figure 4 and Figure 7, this embodiment shows a solution of setting the first insulating layer J1 between the second metal layer M2 and the active layer 30 as a special-shaped structure. Specifically, an inclined surface S3 is used to connect the first surface S1 and the second surface S2 in the first insulating layer J1. Taking the substrate 00 as a reference, the first surface S1, the second surface S2, and the inclined surface S3 in the first insulating layer J1 are all surfaces of the first insulating layer J1 facing away from the substrate 00. Among them, the first surface S1 is the surface of the first insulating layer J1 closer to the substrate 00, and the second surface S2 is the surface of the first insulating layer J1 farther from the substrate 00. When setting the active layer 30, the first active layer 31 is arranged on the first surface S1 and the inclined surface S3, and the second active layer 32 is arranged on the second surface S2 and the inclined surface S3. The first active layer 31 and the second active layer 32 are connected at the inclined surface S3. Assuming that the distance between the end of the first active layer 31 far from the second active layer 32 and the end of the second active layer 32 far from the first active layer 31 is fixed, if the first active layer 31 and the second active layer 32 are arranged on the same horizontal plane, for example, when the surface of the active layer facing away from the substrate 00 is on the same plane, the total length of the first active layer 31 and the second active layer 32 is a fixed length. If the inclined surface S3 is introduced into the first insulating layer J1, the total length of the first active layer 31 and the second active layer 32 in the above limited space is extended through the inclined surface S3. When the total length of the active layer 30 becomes larger, the total length of the channels of the first sub-transistor 11 and the second sub-transistor 12 will also become larger, thereby avoiding the problem of too short channel lengths of the first sub-transistor 11 and the second sub-transistor 12. When the channel is too short, the short-channel transistor is prone to conductivity, resulting in the transistor being unable to play the role of a switch, and at the same time, it will also increase the manufacturing difficulty of the transistor. Therefore, the embodiment of the present invention extends the total length of the active layer 30 by introducing the inclined surface S3 into the first insulating layer J1, which is beneficial to ensuring the switching performance of the transistor and at the same time is beneficial to reducing the manufacturing difficulty of the transistor.

[0051] In addition, when the first insulating layer J1 is set as a special-shaped structure including the inclined surface S3 as shown in Figure 4 and Figure 7 , the active layer 30 and the channel length of the transistor are extended in a limited space, which is equivalent to reducing the space size occupied by a single first transistor 10 in the display panel in a changed direction. In the same-sized space range, more first transistors 10 can be arranged, so it is beneficial to improve the pixel density of the display panel.

[0052] It should be noted that Figure 4 and Figure 7 The embodiments shown only take the second metal layer M2 being located between the active layer 30 and the substrate 00 as an example for illustration. In some other embodiments of the present invention, the first metal layer M1 can also be located between the active layer 30 and the substrate 00. For example, please refer to Figure 8 , whereFigure 8 Display panel shown Figure 3 Another AA-direction cross-sectional view of the first transistor 10 can also form a transistor with a dual-gate structure, and is beneficial to improving the response speed of the first transistor, and is also beneficial to improving the overall response speed of the display panel.

[0053] Continue to refer Figure 4 In an optional embodiment of the present invention, the first active layer 31 includes a first doping region A1, the second active layer 32 includes a second doping region A2, the first doping region A1 is located at an end of the first active layer 31 away from the second active layer 32, and the second doping region A2 is located at an end of the second active layer 32 away from the first active layer 31; along the first direction D1, the first metal layer M1 overlaps with the first surface S1, the inclined surface S3 and the second surface S2, and the first metal layer M1 does not overlap with the first doping region A1 and the second doping region A2.

[0054] Specifically, in the display panel provided by the embodiment of the present invention, a first doping region A1 is provided in the first active layer 31, and a second doping region A2 is provided in the second active layer 32. The first doping region A1 and the second doping region A2 can be regarded as regions doped with impurity ions in the active layer 30, and the region between the first doping region A1 and the second doping region A2 in the first active layer 31 and the second active layer 32 is a non-doped channel region. Among them, along the first direction D1, the first metal layer M1 does not overlap with the first doping region A1, and the first metal layer M1 does not overlap with the second doping region A2. The region in the active layer 30 that overlaps with the first metal layer M1 along the first direction D1 can be regarded as the channel region between the first doping region A1 and the second doping region A2. One of the first doping region A1 and the second doping region A2 serves as the source of the first transistor 10, and the other serves as the drain of the first transistor 10, which is used to connect with other wirings or devices in the display panel. The connection relationship between the first doping region A1 and the second doping region A2 will be described in detail in the subsequent embodiments.

[0055] Continue to refer Figure 4 In an optional embodiment of the present invention, the display panel further includes a first electrode T1, which is located on a side of the first metal layer M1 away from the substrate, and the first electrode T1 is electrically connected to the first doping region A1 through a first connection hole K1, and the second doping region A2 is electrically connected to the second metal layer M2.

[0056] This embodiment shows a solution in which when the first electrode T1 is included in the display panel, the first doped region A1 of the first transistor 10 is electrically connected to the first electrode T1, and the second doped region A2 is electrically connected to the second metal layer M2. Specifically, the first electrode T1 is disposed on the side of the first metal layer M1 away from the substrate, and the first electrode T1 and the first metal layer M1 are isolated by an insulating layer; the first metal layer M1 and the active layer 30 are also isolated by an insulating layer. When electrically connecting the first electrode T1 to the first doped region A1, a first connection hole K1 can be formed on the insulating layer between the first electrode T1 and the first doped region A1, and the first electrode T1 and the first doped region A1 are electrically connected by using the first connection hole K1. Similarly, since the second doped region A2 and the second metal layer M2 are isolated by the first insulating layer J1, when electrically connecting the second doped region A2 to the second metal layer M2, a connection hole can be formed on the first insulating layer J1 between the second doped region A2 and the second metal layer M2, and the second doped region A2 and the second metal layer M2 are electrically connected by using the connection hole. When the first transistor 10 is turned on, the signal of the second doped region A2 can be transmitted to the first doped region A1 through the first transistor 10, and then transmitted to the first electrode T1 through the first doped region A1, thereby realizing the function of providing a driving signal to the first electrode T1. Since in the first transistor 10 provided by the embodiment of the present invention, the second sub-transistor 12 overlaps with its gate to form a channel, and the second sub-transistor 12 overlaps with the second metal layer M2 to form another channel, it is beneficial to increase the on-state current of the second sub-transistor 12, so that the on-state current of the overall first transistor 10 increases. At high currents, the voltage of the second doped region A2 can be transmitted to the first electrode T1 better and faster, so it is beneficial to improve the response speed of the display panel.

[0057] In addition, when connecting the first doped region A1 to the first electrode T1 and the second doped region A2 to the second metal layer M2, the first doped region A1 is equivalent to the drain of the first transistor 10, and the second doped region A2 is equivalent to the source of the first transistor 10. At this time, there is no overlap between the source and the drain of the first transistor 10, and the source voltage signal has less interference with the drain, so it is beneficial to reduce signal crosstalk and improve the quality of the displayed image on the display panel.

[0058] Figure 9 The following shows a top view structure diagram of the first transistor 10 and the first electrode T1 provided by the embodiment of the present invention. Figure 10 The following shows Figure 9 a cross-sectional view of the transistor in the DD' direction. Figure 11 The following shows Figure 9 a cross-sectional view of the transistor in the CC' direction. Among them, Figure 10 The difference between the shown embodiment and Figure 4 the shown embodiment lies in the different connection methods between the first transistor and the first electrode. Figure 10In the illustrated embodiment, the second doped region A2 in the first transistor is electrically connected to the first electrode T1. Figure 4 In the illustrated embodiment, the first doped region A1 in the first transistor is electrically connected to the first electrode T1.

[0059] Please refer to Figure 9 、 Figure 10 and Figure 11 , in an alternative embodiment of the present invention, the display panel further includes a first electrode T1. The first electrode T1 is located on a side of the first metal layer M1 away from the substrate 00. The first electrode T1 is electrically connected to the second doped region A2 through a second connection hole K2; the first doped region A1 is electrically connected to the second metal layer M2 through a first bridging portion 50.

[0060] This embodiment shows a scheme of electrically connecting the second doped region A2 to the first electrode T1 and electrically connecting the first doped region A1 to the second metal layer M2 when the first electrode T1 is introduced into the display panel. At this time, the second doped region A2 connected to the first electrode T1 corresponds to the drain of the first transistor 10, and the first doped region A1 connected to the second metal layer M2 corresponds to the source of the first transistor 10. The driving signal is transmitted to the second doped region A2 through the first doped region A1 and further transmitted to the first electrode T1, thereby realizing the driving of the first electrode T1. In this embodiment, the first electrode T1 layer and the first metal layer M1 are isolated by an insulating layer, and the first metal layer M1 and the active layer 30 are also isolated by an insulating layer. The first electrode T1 and the second doped region A2 are electrically connected through a second connection hole K2 penetrating the above-mentioned insulating layer. Since the first doped region A1 of the active layer 30 does not overlap with the second metal layer M2 in the first direction D1, a first bridging portion 50 is introduced into the display panel. For example, please refer to Figure 11 , the first bridging portion 50 is electrically connected to the first doped region A1 through a connection hole, and the first bridging portion 50 is electrically connected to the second metal layer M2 through another connection hole. In this way, the electrical connection between the first doped region A1 and the second metal layer M2 can be realized through the first bridging portion 50, and the signal of the second metal layer M2 connected to the first bridging portion 50 can be transmitted to the first doped region A1 through the first bridging portion 50, and then transmitted to the second doped region A2 and the first electrode T1.

[0061] In this embodiment, in the second sub-transistor 12, the first metal layer M1 and the first active layer 31 overlap to form a channel, and the second metal layer M2 and the first active layer 31 overlap to form another channel. The double-channel arrangement effectively increases the on-state current of the second sub-transistor 12, and the signal transmitted from the first sub-transistor 11 to the second sub-transistor 12 can be transmitted to the first electrode T1 more quickly and stably. Therefore, it is also beneficial to improve the response speed of the display panel.

[0062] Continue to refer toFigure 10 and Figure 11 In an alternative embodiment of the present invention, the first bridging portion 50 is disposed on the same layer as the first electrode T1, both are located in the electrode layer T. The first bridging portion 50 is electrically connected to the second metal layer M2 through the third connection hole, and is electrically connected to the first doped region A1 through the fourth connection hole K4; the second connection hole K2, the third connection hole K3, and the fourth connection hole K4 are formed in the same process.

[0063] Specifically, this embodiment shows a solution of disposing the first bridging portion 50 connecting the first doped region A1 and the second metal layer M2 in the film layer where the first electrode T1 is located. Optionally, the first bridging portion 50 and the first electrode T1 layer are made of the same material. In this way, when the first electrode T1 is fabricated in the film layer where the first electrode T1 is located, the fabrication of the first bridging portion 50 can be completed simultaneously, which is beneficial to simplifying the fabrication process when introducing the first bridging portion 50 into the display panel. In addition, when the first bridging portion 50 is disposed on the same layer as the first electrode T1, there is no need to introduce a separate film layer in the display panel to dispose the first bridging portion 50, and the interface of the film layer where the first electrode T1 is located is reused, which is also beneficial to simplifying the overall film layer structure of the display panel.

[0064] Please refer to Figure 11 , when the first bridging portion 50 is disposed on the same layer as the first electrode T1, the first bridging portion 50 is electrically connected to the second metal layer M2 through the third connection hole K3, and the first bridging portion 50 is electrically connected to the first doped region A1 through the fourth connection hole K4. Please refer to Figure 4 . The first electrode T1 is electrically connected to the second doped region A2 through the second connection hole K2. During actual fabrication, the second connection hole K2, the third connection hole K3, and the fourth connection hole K4 can be formed by using one photomask process, without introducing different photomask processes for these connection holes respectively, which is beneficial to simplifying the production process of the display panel and reducing the production cost.

[0065] Figure 12 Shown is a connection relationship diagram of the first transistor 10 and the first electrode T1 in the first region and the second region of the display panel. Please refer to Figure 12 , and in combination with Figure 4 and Figure 10 , in an alternative embodiment of the present invention, the display panel further includes a first electrode T1, and the first electrode T1 is located on the side of the first metal layer M1 away from the substrate; the display panel includes a first region Q1 and a second region Q2. The first electrode T1 in the first region Q1 is electrically connected to the first doped region A1 through the first connection hole K1, and the first electrode T1 in the second region Q1 is electrically connected to the second doped region A2 through the second connection hole K2.

[0066] It should be noted that in this embodiment, the first region and the second region mentioned may respectively refer to the display regions corresponding to a certain row or a certain column of sub-pixels in the display panel, or may also refer to the display regions corresponding to multiple rows and multiple columns of sub-pixels, such as the central display region and the peripheral display region, the upper half display region and the lower half display region, and so on. In this embodiment, only an example is given in which a certain row of sub-pixels corresponds to the first region Q1 and another row of sub-pixels corresponds to the second region Q2, but the actual positions of the first region and the second region in the display panel are not limited.

[0067] Optionally, the display panel includes a data line L1 and a scan line L2. Among them, the gate of the first transistor 10 is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected to the first electrode. In this embodiment, the first doping region of some of the first transistors 10 serves as the source, and the second doping region serves as the drain; the first doping region of the other part of the first transistors 10 serves as the drain, and the first doping region serves as the source.

[0068] In this embodiment, a scheme with different connection relationships between the first electrode T1 in the first region Q1 and the second region Q2 in the display panel and the first transistor 10 is shown. For example, in the first region Q1, among the correspondingly arranged first electrode T1 and the first transistor 10, the first electrode T1 is electrically connected to the first doping region A1 of the first transistor 10. That is to say, the first doping region A1 of the first transistor 10 in the first region Q1 corresponds to the drain of the first transistor 10. In the second region Q2, among the correspondingly arranged first electrode T1 and the first transistor 10, the first electrode T1 is electrically connected to the second doping region A2 of the first transistor 10. That is to say, the second doping region A2 of the first transistor 10 in the second region corresponds to the drain of the first transistor 10. The region with higher requirements for the picture display quality can be used as the first region Q1, and other display regions can be used as the second region Q2. In the first region Q1, since the first doping region A1 of the first transistor 10 serves as the drain and is electrically connected to the first electrode T1, along the first direction D1, the first doping region A1 does not overlap with the second metal layer M2. That is to say, the second metal layer M2 will not form a coupling capacitor with the first doping region A1, and the signal of the second metal layer M2 will not interfere with the drain signal of the first transistor 10. Therefore, it is beneficial to improve the accuracy and stability of the signal transmitted to the first electrode T1, and thus beneficial to improve the picture quality.

[0069] Figure 13 Shown is the display panel Figure 3 Another AA-direction cross-sectional view of the first transistor 10 in.

[0070] Please refer to Figure 13, in an alternative embodiment of the present invention, the display panel further includes a first electrode T1, the first electrode T1 is located on the side of the first metal layer M1 away from the substrate 00, and a second insulating layer J2 is provided between the first electrode T1 and the first metal layer M1. The surface of the second insulating layer J2 away from the substrate 00 is parallel to the substrate 00.

[0071] Specifically, when the first insulating layer J1 is set to a non-planar structure with an inclined surface S3, without special treatment, other insulating layers located on the side of the first insulating layer J1 away from the substrate will also exhibit a non-planar structure with an inclined surface S3, and the first electrode T1 will also exhibit a non-planar structure with an inclined surface S3. When the first electrode T1 is a non-planar structure, if the display panel is a liquid crystal display panel and the first electrode T1 is a pixel electrode, it may cause different electric fields acting on the liquid crystal in different regions of the pixel electrode, affecting the normal deflection of the liquid crystal; if the display panel is an organic electroluminescent display panel, the first electrode T1 is the anode 71 of the light-emitting element 70, and structures such as light-emitting materials need to be formed on the anode 71. If the anode 71 is uneven, it will also affect the display effect. Therefore, in this embodiment, the second insulating layer J2 provided between the first electrode T1 and the first metal layer M1 is improved so that the surface of the second insulating layer J2 away from the substrate 00 is a flat structure, that is, the surface of the second insulating layer J2 away from the substrate 00 is a planar structure parallel to the substrate 00. In this way, when the first electrode T1 is formed on the surface of the second insulating layer J2 away from the substrate, the first electrode T1 will also be a flat structure, and the flat first electrode T1 is more conducive to ensuring the display effect of the display panel.

[0072] Figure 14 The figure shows a layer structure diagram of two adjacent first transistors 10.

[0073] Please refer to Figure 14 , in an alternative embodiment of the present invention, at least some adjacent first transistors 10 are symmetrically arranged, the axis of symmetry is located between the two adjacent first transistors 10, and the axis of symmetry is perpendicular to the substrate.

[0074] This embodiment shows a scheme in which adjacent first transistors 10 are symmetrically arranged. The adjacent two first transistors 10 are symmetrically arranged, specifically, along the arrangement direction of the two adjacent first transistors 10, among the two adjacent first transistors 10, the two first doping regions A1 are located between the two second doping regions A2, the axis of symmetry is located between the two adjacent first doping regions A1, and is perpendicular to the substrate, that is to say, the two first sub-transistors 11 are located between the two second sub-transistors 12.

[0075] Continue to refer to Figure 14, in an alternative embodiment of the present invention, the display panel further includes a first insulating layer J1 disposed between the second metal layer M2 and the active layer 30. The first insulating layer J1 includes a first surface S1, a second surface S2, and an inclined surface S3 connecting the first surface S1 and the second surface S2. In the first insulating layer J1, the first surfaces S1 corresponding to two symmetrically arranged first transistors 10 are connected and located in the same plane, and the inclined surfaces S3 and the first surfaces S1 corresponding to two symmetrically arranged first transistors 10 jointly define a groove 60.

[0076] When two adjacent first transistors 10 are symmetrically arranged, taking the first insulating layer J1 of two symmetrically arranged first transistors 10 as an example, the arrangement of the first surface S1, the inclined surface S3, and the second surface S2 in the first insulating layer J1 is as follows: two first surfaces S1 are located in the middlemost position, the inclined surface S3 of one of the first transistors 10 is located on the side of the first surface S1 of this first transistor 10 away from the first surface S1 of the other transistor, and the second surface S2 is located on the side of the inclined surface S3 away from the first surface S1. The two symmetrically arranged first surfaces S1 are connected and located in the same plane, the two inclined surfaces S3 are opposite to each other, and together with the two first surfaces S1, they form a groove 60. In this way, the first insulating layers J1 in the two first transistors 10 jointly form a groove with a larger area, and a groove with a larger area is easier to fabricate. When electrically connecting the first doping region A1 of the first transistor 10 to the first electrode T1, when the connection hole between the first doping region A1 and the first electrode T1 is disposed in the region corresponding to the groove with a larger area, it is easier to realize the positioning of the connection hole, which is beneficial to simplifying the manufacturing process of the display panel.

[0077] Figure 15 Shown is another film layer structure diagram of two adjacent first transistors 10.

[0078] Please refer to Figure 15 , in an alternative embodiment of the present invention, among two adjacent first transistors 10, along the arrangement direction of the two first transistors 10, the first sub-transistor 11 in one of the first transistors 10 is located between two second sub-transistors 12.

[0079] This embodiment shows a scheme in which adjacent transistors are arranged in a repeated manner with the same structure. That is to say, the sub-transistors in two adjacent first transistors 10 are arranged in the order of second sub-transistor 12 - first sub-transistor 11 - second sub-transistor 12 - first sub-transistor 11. In this implementation manner, the first transistors 10 with the same structure are arranged repeatedly, which is beneficial to simplifying the overall manufacturing process of the display panel.

[0080] In an alternative embodiment of the present invention, both the first active layer 31 and the second active layer 32 include oxides. Thus, both the first sub-transistor 11 and the second sub-transistor 12 in the first transistor 10 are embodied as oxide transistors. The above-mentioned oxides include, for example, IGZO (indium gallium zinc oxide) or IGZTO (indium gallium zinc tin oxide). Oxide transistors have a relatively large bandgap, and electrons are not easily excited, so the leakage current is small. Therefore, when the first transistor 10 is an oxide transistor, the signal provided to the first electrode T1 via the first transistor 10 will be more accurate and stable, which is more conducive to improving the display quality of the display panel.

[0081] Please refer to Figure 3 , in an alternative embodiment of the present invention, along the first direction D1, the orthographic projections of the first active layer 31 and the second active layer 32 on the substrate are in a straight line.

[0082] As mentioned in this embodiment, the orthographic projections of the first active layer 31 and the second active layer 32 on the substrate are in a straight line, which means that the orthographic projection of the active layer 30 formed by the first active layer 31 and the second active layer 32 as a whole on the substrate is in a straight line. When the first active layer 31 in the first transistor 10 is set to be in a straight line, compared with the active layer 30 with a special-shaped structure, the active layer 30 in a straight line has a simple structure and is easier to fabricate.

[0083] Continue to refer to Figure 7 , in an alternative embodiment of the present invention, in the same first transistor 10, the length of the active layer 30 on the second surface S2 is L1, the length of the active layer 30 on the inclined surface S3 is L2, and the length of the active layer 30 on the first surface S1 is L3, where L1 + L2 + L3 > 1 μm.

[0084] This embodiment respectively shows the lengths of the active layer 30 provided on the first surface S1, the second surface S2, and the inclined surface S3 of the first insulating layer J1. When the total length of the first active layer 31 in the first transistor 10 is set to be less than 1 μm, the channel length of the first transistor 10 will be too small. When the channel length of the first transistor 10 is too small, the channel will become conductive, resulting in the first transistor 10 being unable to function as a switch. In the present invention, when the length of the active layer 30 in the first transistor 10 is set to be greater than 1 μm, it is beneficial to increase the channel length of the first transistor 10 and avoid the problem of the channel of the first transistor 10 becoming conductive, thereby ensuring the switching performance of the first transistor 10.

[0085] Please combine Figure 4 and Figure 7, in an alternative embodiment of the present invention, L1 + L3 > 0.5 μm. Wherein, L1 > 0, L3 > 0. In this embodiment, the sum of the lengths of the active layers 30 provided on the second surface S2 and the first surface S1 is further defined. When the sum of the lengths of the active layers 30 on the two surfaces is greater than 0.5 μm, a certain overlapping area is formed between the second metal layer M2 and the active layer 30 to form the channel of the second sub-transistor 12, so as to increase the on-state current of the second sub-transistor 12 and improve the overall response speed of the first transistor 10. Moreover, when the sum of the lengths of the active layers 30 on the two surfaces is greater than 0.5 μm, and L1 > 0, L3 > 0, it is also beneficial to ensure that one end of the gate of the first metal layer M1 is located on the flat first surface S1, and the other end is located on the flat second surface S2. If the end of the gate is formed on the inclined surface S3, it is difficult to control the width of the gate layer in the exposure process, so it is difficult to ensure the performance of the first transistor 10. Therefore, when one end of the gate is provided on the first surface S1 and the other end is provided on the second surface S2, it is ensured that both ends of the gate are located on flat surfaces, and the width of the gate can be better controlled in the process, thereby ensuring the overall performance of the first transistor 10.

[0086] When L1 + L3 > 0.5 μm, optionally, L2 > 0.5 μm, which is beneficial to ensure that the overall channel length of the first transistor 10 is greater than 1 μm and avoid the problem of channel conduction of the first transistor 10.

[0087] Along the first direction D1, the distance between the first surface S1 and the second surface S2 is H. Optionally, 500 nm ≤ H ≤ 2700 nm. The larger the value of H, the larger the corresponding L2 will be, the longer the overall channel length of the first transistor 10 will be, the less likely the channel of the first transistor 10 is to conduct, and the uniformity of the first transistors 10 on the display panel will also be improved, which is beneficial to improving the overall brightness uniformity of the display panel.

[0088] Figure 16 Shown is another relative positional relationship diagram of the first insulating layer J1, the active layer 30, and the second metal layer M2.

[0089] Please combine Figure 4 and Figure 16, in an alternative embodiment of the present invention, L1 > L3. When the length L1 of the active layer 30 on the second surface S2 is greater than the length L3 of the active layer 30 on the first surface S1, it is beneficial to increase the length of the active layer 30 in the second sub-transistor 12, thereby facilitating an increase in the channel length of the second sub-transistor 12. In this way, it is equivalent to increasing the proportion of the second sub-transistor 12 in the first transistor 10. Since the second sub-transistor 12 has two channels and is simultaneously controlled by the first metal layer M1 and the second metal layer M2, it is beneficial to increase the on-state current of the second sub-transistor 12. When the proportion of the second sub-transistor 12 in the first transistor 10 increases, the on-state current will be further enhanced, which is conducive to further improving the overall on-state current of the first transistor 10, and thus conducive to further enhancing the response speed of the entire display panel.

[0090] Please refer to Figure 4 and Figure 7 , in an alternative embodiment of the present invention, L1 < L3. Specifically, this embodiment shows a scheme where the length L1 of the active layer 30 on the second surface S2 is less than the length L3 of the active layer 30 on the first surface S1. This is equivalent to increasing the length of the active layer 30 in the first sub-transistor 11 and increasing the proportion of the first sub-transistor 11 in the first transistor 10. Since only the first metal layer M1 overlaps with the active layer 30 in the first sub-transistor 11, that is, the channel of the first sub-transistor 11 is only controlled by the gate, the first sub-transistor 11 can effectively control the threshold voltage of the entire first transistor 10. When the proportion of the first sub-transistor 11 in the first transistor 10 increases, the stability of the threshold voltage of the first transistor 10 can be effectively ensured, which is conducive to improving the overall display stability of the display panel.

[0091] Optionally, in the first transistor 10 provided by the embodiments of the present invention, the thickness of the second metal layer M2 is D0, where 200 nm ≤ D0 ≤ 900 nm. The thicker the film layer of the second metal layer M2, the lower the resistance of the trace located in the second metal layer M2, the smaller the voltage drop of the trace, and the more conducive it is to improving the display uniformity of the display panel. Moreover, the thicker the film layer of the second metal layer M2, the more conducive it is to increasing the overlapping area between the second metal layer M2 and the active layer 30. Therefore, the on-state current of the second sub-transistor 12 can be better improved, which is conducive to improving the overall on-state current of the first transistor 10. If the thickness of the second metal layer M2 is too large, for example, greater than 900 nm, the film stress will also increase, which is not conducive to mass production. Optionally, D0 = 420 nm.

[0092] Figure 17 The following shows a film layer structure diagram of the display panel provided by the embodiments of the present invention. This embodiment is described by taking the display panel as a liquid crystal panel as an example. Figure 18The figure shows a schematic diagram of a pixel driving circuit applied to a liquid crystal display panel.

[0093] Please refer to Figure 17 , in an alternative embodiment of the present invention, the display panel is a liquid crystal panel, and the display panel further includes a pixel electrode T0 disposed on the side of the first metal layer M1 away from the substrate and a pixel driving circuit connected to the pixel electrode. The pixel driving circuit includes the first transistor 10 in the foregoing embodiment, and the first transistor 10 is electrically connected to the pixel electrode T0. The pixel electrode T mentioned in this embodiment is the first electrode T1 mentioned in the present invention. The pixel driving circuit in the liquid crystal panel may refer to the driving circuit in the related art, such as Figure 18 the circuit shown. The embodiments of the present invention do not specifically limit this. In some other embodiments of the present invention, the pixel driving circuit may further include two or more transistors.

[0094] Specifically, when the display panel is a liquid crystal display panel, the display panel includes a first substrate 101 and a second substrate 102 disposed opposite to each other and liquid crystal filled between the first substrate 101 and the second substrate 102. Optionally, the first transistor 10 is located on the first substrate 101, and the first electrode T1 connected to the first transistor 10 is also located on the first substrate 101. The display panel further includes a second electrode T2 disposed opposite to the first electrode T1. In this embodiment, the case where the second electrode T2 is located on the second substrate 101 is taken as an example for description. In some other embodiments of the present invention, the second electrode T2 may also be located on the first substrate 101. When different voltages are provided for the first electrode T1 and the second electrode T2 respectively, the electric field between the first electrode T1 and the second electrode will be able to drive the liquid crystal to deflect, realizing the display function of the display panel. When the first transistor 10 is applied to a liquid crystal display panel, since the first transistor 10 is a transistor with a double-gate structure and the second sub-transistor 12 therein has two channels, it is beneficial to increase the overall on-state current of the first transistor 10, so it is beneficial to increase the overall response speed of the liquid crystal display panel; at the same time, since the first sub-transistor 11 has one channel and is only controlled by the gate, the first sub-transistor 11 can control the overall threshold voltage of the first transistor 10 to ensure the stability of the device.

[0095] It should be noted that when the pixel driving circuit applied to the liquid crystal display panel includes two transistors, the structures of the two transistors can both adopt the structure of the first transistor 10 provided by the present invention to increase the overall response speed of the display panel and improve the stability of the device at the same time.

[0096] Figure 19 The figure shows a layer structure diagram of a display panel provided by an embodiment of the present invention. In this embodiment, the display panel is taken as an organic electroluminescent display panel for example for description. Figure 20The figure shows a schematic diagram of a driving circuit corresponding to an organic electroluminescent display panel. In this embodiment, only a pixel driving circuit with a 7T1C (7 transistors and 1 capacitor) structure is taken as an example for illustration, but the actual structure of the pixel driving circuit is not limited. In some other embodiments of the present invention, the pixel driving circuit may also be embodied in other structures, which are not limited in the present invention, such as 8T1C or 8T2C, etc.

[0097] The pixel circuit includes a driving transistor T0, 6 switching transistors, and a storage capacitor C0. The 6 switching transistors are respectively transistors T01 to T06. Optionally, the gate of the driving transistor T0 is connected to the first node N1, the first pole is connected to the second node N2, the second pole is connected to the third node N3, and the light-emitting element 70 is connected in series between the fourth node N4 and the second power supply terminal PVEE. The transistor T01 is connected in series between the first reset terminal VreD1 and the first node N1, and the transistor T02 is connected in series between the data signal line DL and the second node N2; the transistor T03 is connected in series between the first node N1 and the third node N3; the transistor T04 is connected in series between the second reset terminal Vref2 and the fourth node N4; the transistor T05 is connected in series between the first power supply terminal PVDD and the second node N2, and the transistor T06 is connected in series between the third node N3 and the fourth node N4; the storage capacitor C0 is connected in series between the first power supply terminal PVDD and the first node N1.

[0098] Optionally, continue to refer to Figure 8 and Figure 11The working stages of the pixel circuit include a first reset stage, a second reset stage, a data writing stage and a light emitting stage. In the first reset stage, the transistor T01 is turned on in response to the on-level of the first control terminal S1, and the reset signal of the first reset terminal VreD1 is transmitted to the first node N1; in the second reset stage, the transistor T04 is turned on in response to the on-level of the fourth control terminal S4, and the reset signal of the second reset terminal Vref2 is transmitted to the fourth node N4, so as to reset the anode 301 of the light emitting element 70; in the data writing stage, the transistor T02 is turned on in response to the on-level of the second control terminal S2, the transistor T03 is turned on in response to the on-level of the third control terminal S2, the data signal on the data signal line DL is transmitted to the second node N2, the signal of the second node N2 is transmitted to the third node N3 through the driving transistor T0, and the signal of the third node N3 is transmitted to the first node N1. In the light-emitting stage, transistor T05 and transistor T06 are turned on in response to the signal of the light-emitting control signal terminal Emit, and the signal on the first power signal line PVDD is transmitted to transistor T05 through the first power terminal, and the first driving transistor T0 transmits the driving signal to the light-emitting element 70 to drive the light-emitting element 70 to emit light. It should be noted that the first reset stage and the second reset stage can be carried out simultaneously or in different time periods, and the reset voltages of the first reset stage and the second reset stage can be the same or different, and the embodiment of the present invention does not specifically limit this. When the reset voltages are the same, the first reset terminal VreD1 and the second reset terminal Vref2 can be reflected as the same signal terminal. The working process of the above-mentioned pixel driving circuit is also only for illustrative purposes and does not limit the actual working process of the pixel driving circuit of the present invention.

[0099] It should be noted that the above-mentioned pixel driving circuit and working process are only for illustration and do not limit the pixel driving circuit and working process actually included in the display panel.

[0100] Please refer to Figure 4 , Figure 19 and Figure 20 In an optional embodiment of the present invention, the display panel includes a light emitting element 70 and a pixel driving circuit connected to the light emitting element 70, the light emitting element 70 includes an anode 71, a light emitting layer 72 and a cathode 73, along the first direction D1, the light emitting layer 72 is located between the anode 71 and the cathode 73, and the anode 71 is located on the side of the light emitting layer 72 facing the substrate 00; the pixel driving circuit includes a driving transistor T0 and at least one switching transistor (T01-T06), and the at least one switching transistor is a first transistor 10. In this embodiment, the anode 71 of the light emitting element 70 can be regarded as the first electrode T1 mentioned in the above embodiment.

[0101] When at least one switching transistor in the driving circuit corresponding to the organic electroluminescent display panel adopts the structure of the first transistor 10 mentioned in the foregoing embodiments, it is beneficial to improve the problem of leakage current generated by the transistor in the pixel driving circuit, thereby being beneficial to improving the accuracy and stability of the signal provided to the light-emitting element 70. Moreover, since the first transistor 10 is a transistor with a double-gate structure and the second sub-transistor 12 therein has two channels, it is beneficial to increase the overall on-state current of the first transistor 10, so it is beneficial to improve the overall response speed of the liquid crystal display panel; at the same time, since the first sub-transistor 11 has one channel and is only controlled by the gate, the first sub-transistor 11 can control the overall threshold voltage of the first transistor 10 to ensure the stability of the device.

[0102] In the above embodiments, only the transistor connected to the first node in the pixel driving circuit is taken as an example of the first transistor 10 for illustration. When the transistor connected to the first node is set as the first transistor 10, it is beneficial to reduce the influence of the leakage current of these transistors on the signal of the first node, so it is beneficial to improve the stability and accuracy of the signal of the first node, and further more beneficial to improve the accuracy of the signal provided to the light-emitting element 70.

[0103] In an alternative embodiment of the present invention, in the above driving circuit, each switching transistor is the first transistor 10. In this way, the leakage current problem of each switching transistor in the pixel driving circuit is reduced, and the response speed of each switching transistor is improved, so it is beneficial to further improve the overall response speed of the display panel.

[0104] Based on the same inventive concept, the present invention also provides a display device. Figure 21 Shown is a schematic structural diagram of a display device provided by an embodiment of the present invention. The display device includes the display panel 100 provided by the above embodiments of the present invention.

[0105] It can be understood that the display device 200 provided by the embodiments of the present invention can be a mobile phone, a tablet computer, a computer, a television, a vehicle-mounted display device, or other display devices with display functions and touch functions. The present invention does not make specific limitations on this. The display device provided by the embodiments of the present invention has the beneficial effects of the display panel provided by the embodiments of the present invention. For specific descriptions of the display panel, reference can be made to the above embodiments. Details will not be described herein again.

[0106] It can be seen from the above embodiments that the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

[0107] In the display panel and the display device provided by the present invention, the array layer includes at least one first transistor. The first transistor includes a first sub-transistor and a second sub-transistor connected in series. The active layers of the first sub-transistor and the second sub-transistor are located in the same layer and are connected to each other. Among them, the first metal layer overlaps with the first active layer in the first direction to form the gate of the first sub-transistor, and the first metal layer overlaps with the second active layer in the first direction to form the gate of the second sub-transistor. Along the first direction, the second metal layer overlaps with the second active layer and does not overlap with the first active layer. In this way, the vertical electric field of the first transistor is mainly controlled by the gate. The vertical electric field of the second sub-transistor is controlled not only by the gate but also by the second metal layer. Thus, the on-state current of the second sub-transistor can be effectively increased, which is beneficial to improving the response speed of the second sub-transistor and further beneficial to improving the overall response speed of the display panel.

[0108] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of the present invention. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, It includes a substrate and an array layer disposed on one side of the substrate. The array layer includes a first metal layer, an active layer, and a second metal layer. Along a first direction perpendicular to the substrate, the first metal layer and the second metal layer are located on both sides of the active layer. The array layer includes at least one first transistor. The first transistor includes a first sub-transistor and a second sub-transistor connected in series. The first sub-transistor includes a first active layer located in the active layer, and the second sub-transistor includes a second active layer located in the active layer. The first active layer and the second active layer are connected. Along the first direction, the first metal layer overlaps with both the first active layer and the second active layer, and the second metal layer overlaps with the second active layer and does not overlap with the first active layer. Along the first direction, the second metal layer is located between the active layer and the substrate. The display panel further includes a first insulating layer disposed between the second metal layer and the active layer. The first insulating layer includes a first surface on the side away from the substrate, a second surface, and an inclined surface connecting the first surface and the second surface. Along the first direction, the distance between the first surface and the substrate is less than the distance between the second surface and the substrate. At least a part of the first active layer is located on the first surface, at least a part of the second active layer is located on the second surface, and the first active layer and the second active layer are connected at the inclined surface. In the same first transistor, the length of the active layer on the second surface is L1, the length of the active layer on the inclined surface is L2, and the length of the active layer on the first surface is L3, where L1 + L2 + L3 > 1 μm.

2. The display panel according to claim 1, characterized in that, The first active layer includes a first doping region, and the second active layer includes a second doping region. The first doping region is located at one end of the first active layer away from the second active layer, and the second doping region is located at one end of the second active layer away from the first active layer. Along the first direction, the first metal layer overlaps with the first surface, the inclined surface, and the second surface, and does not overlap with the first doping region and the second doping region.

3. The display panel according to claim 2, wherein The display panel further includes a first electrode located on the side of the first metal layer away from the substrate. The first electrode is electrically connected to the first doping region through a first connection hole, and the second doping region is electrically connected to the second metal layer.

4. The display panel according to claim 2, wherein The display panel further includes a first electrode located on the side of the first metal layer away from the substrate. The first electrode is electrically connected to the second doping region through a second connection hole; the first doping region is electrically connected to the second metal layer through a first bridging portion.

5. The display panel according to claim 4, characterized in that, The first bridging portion is disposed on the same layer as the first electrode. The first bridging portion is electrically connected to the second metal layer through a third connection hole and electrically connected to the first doping region through a fourth connection hole. The second connection hole, the third connection hole, and the fourth connection hole are formed in the same process.

6. The display panel according to claim 2, wherein The display panel further includes a first electrode, wherein the first electrode is located on a side of the first metal layer away from the substrate; The display panel includes a first region and a second region, the first electrode in the first region is electrically connected to the first doping region through a first connection hole, and the first electrode in the second region is electrically connected to the second doping region through a second connection hole.

7. The display panel according to claim 1, wherein The display panel further includes a first electrode, which is located on a side of the first metal layer away from the substrate. A second insulating layer is disposed between the first electrode and the first metal layer, and a surface of the second insulating layer away from the substrate is parallel to the substrate.

8. The display panel according to claim 1, wherein At least some of the adjacent two first transistors are symmetrically arranged, with a symmetry axis located between the adjacent two first transistors, and the symmetry axis is perpendicular to the substrate.

9. The display panel according to claim 8, wherein The display panel further includes a first insulating layer disposed between the second metal layer and the active layer, the first insulating layer including a first surface, a second surface, and an inclined surface connecting the first surface and the second surface; In the first insulating layer, the first surfaces corresponding to the two symmetrically arranged first transistors are connected and located in the same plane, and the inclined surfaces corresponding to the two symmetrically arranged first transistors and the first surface jointly define a groove.

10. The display panel according to claim 1, wherein Among two adjacent first transistors, along the arrangement direction of the two first transistors, the first sub-transistor in one of the first transistors is located between two second sub-transistors.

11. The display panel according to claim 1, wherein, The first active layer and the second active layer each include oxide.

12. The display panel according to claim 1, wherein Along the first direction, the orthographic projections of the first active layer and the second active layer on the substrate are in a straight line shape.

13. The display panel according to claim 1, wherein L1+L3>0.5μm.

14. The display panel according to claim 1, wherein L1>L3.

15. The display panel according to claim 1, characterized in that, L1<L3.

16. The display panel according to claim 1, wherein The display panel is a liquid crystal panel, and further comprises a pixel electrode disposed on a side of the first metal layer away from the substrate and a pixel driving circuit connected to the pixel electrode, wherein the pixel driving circuit comprises the first transistor, and the first transistor is electrically connected to the pixel electrode.

17. The display panel according to claim 1, wherein The display panel includes a light-emitting element and a pixel driving circuit connected to the light-emitting element, the light-emitting element includes an anode, a light-emitting layer and a cathode, along the first direction, the light-emitting layer is located between the anode and the cathode, and the anode is located on the side of the light-emitting layer facing the substrate; the pixel driving circuit includes a driving transistor and at least one switching transistor, at least one of the switching transistors is the first transistor.

18. The display panel according to claim 17, wherein Each of the switch transistors is the first transistor.

19. A display device, characterized in that, The display panel comprises any one of claims 1 to 18.

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