Heavy hex connection topology to linear physical layout

Abstract

Systems and techniques are provided to facilitate mapping heavy-hexagonal qubit connectivity topologies to linear physical qubit layouts. In various embodiments, the device may include a qubit array on a substrate. In several aspects, the qubit array may include one or more first qubit patches. In various cases, the one or more first qubit patches may have a first shape. In various cases, the qubit array may also include one or more second qubit patches. In various cases, the one or more second qubit patches may have a second shape. In various aspects, the one or more first qubit patches may be combined with the one or more second qubit patches. In different embodiments, the qubit array may exhibit a linear physical layout. In various embodiments, the one or more first qubit patches combined with the one or more second qubit patches can form a heavy-hexagonal qubit connectivity topology in the linear physical layout of the qubit array. In different embodiments, one of the one or more first qubit patches may have twelve qubits and twelve inter-qubit connectivity buses. In various cases, one of the one or more second qubit patches may have twelve qubits and twelve inter-qubit connectivity buses. In various embodiments, adjacent qubit blocks in a heavy-hexagonal qubit connectivity topology can share three qubits. In various embodiments, a qubit block in a heavy-hexagonal qubit connectivity topology can be adjacent to four qubit blocks having a different shape than the qubit block. In various cases, the qubit block can be adjacent to two qubit blocks having the same shape as the qubit block.

Description

Technical Field

[0001] This topic discloses information about qubit connection topologies, and more specifically about mapping heavy-hex qubit connection topologies to linear physical qubit layouts. Summary of the Invention

[0002] The following overview is provided to offer a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, devices, systems, computer-implemented methods, apparatuses, and / or computer program products are described that facilitate mapping heavy-hexagonal qubit connectivity topologies to linear physical qubit layouts.

[0003] According to one or more embodiments, a device is provided. In various embodiments, the device may include a quantum dot array on a substrate. In several aspects, the quantum dot array may include one or more first quantum bit tiles. In various cases, the one or more first quantum bit tiles may have a first shape. In various cases, the quantum dot array may also include one or more second quantum bit tiles. In various cases, the one or more second quantum bit tiles may have a second shape. In various aspects, the one or more first quantum bit tiles may be combined with the one or more second quantum bit tiles. In different embodiments, the quantum dot array may exhibit a linear physical layout. In various embodiments, the one or more first quantum bit tiles combined with the one or more second quantum bit tiles may form a heavy-hexagonal qubit connection topology in the linear physical layout of the quantum dot array. In different embodiments, one of the one or more first quantum bit tiles may have twelve qubits and twelve inter-qubit connection buses. In various cases, one of the one or more second quantum bit tiles may have twelve qubits and twelve inter-qubit connection buses. In various embodiments, adjacent qubit blocks in a heavy-hexagonal qubit connectivity topology can share three qubits. In various embodiments, a qubit block in the heavy-hexagonal qubit connectivity topology can be adjacent to four qubit blocks having a different shape than the qubit block. In various cases, the qubit block can be adjacent to two qubit blocks having the same shape as the qubit block.

[0004] According to one or more embodiments, a method is provided. The method may include forming a quantum dot array on a substrate. In various aspects, the quantum dot array may include one or more first quantum bit patches. In various cases, the one or more first quantum bit patches may have a first shape. In various cases, the quantum dot array may also include one or more second quantum bit patches. In various cases, the one or more second quantum bit patches may have a second shape. In various aspects, the one or more first quantum bit patches may be combined with the one or more second quantum bit patches. In different embodiments, the quantum dot array may exhibit a linear physical layout. In various embodiments, the one or more first quantum bit patches combined with the one or more second quantum bit patches may form a heavy-hexagonal qubit connectivity topology in the linear physical layout of the quantum dot array. In different embodiments, one of the one or more first quantum bit patches may have twelve qubits and a twelve-qubit inter-connection bus. In various cases, one of the one or more second quantum bit patches may have twelve qubits and a twelve-qubit inter-connection bus. In various embodiments, adjacent quantum bit patches in the heavy-hexagonal qubit connectivity topology may share three qubits. In various embodiments, a qubit block in a heavy-hexagonal qubit connectivity topology can be adjacent to four qubit blocks having a different shape than the qubit block. In various cases, the qubit block can be adjacent to two qubit blocks having the same shape as the qubit block.

[0005] According to one or more embodiments, an apparatus is provided. In various embodiments, the apparatus may include a qubit array on a substrate. In various cases, the qubit array may exhibit a linear physical qubit arrangement. In various aspects, the qubit array may include a plurality of first qubit tiles having a first shape, the plurality of first qubit tiles being joined with a plurality of second qubit tiles having a second shape. In various embodiments, the plurality of first qubit tiles joined with the plurality of second qubit tiles may form a heavy-hexagonal qubit connectivity topology in the linear physical qubit arrangement of the qubit array. Attached Figure Description

[0006] Figure 1 A block diagram of an exemplary non-limiting heavy-hexagonal qubit interconnect topology implemented using a heavy-hexagonal physical qubit layout is shown.

[0007] Figure 2 A block diagram of an exemplary non-limiting qubit map block according to one or more embodiments described herein is shown, the qubit map block having a first shape that facilitates mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0008] Figure 3 A block diagram of an exemplary non-limiting qubit map block according to one or more embodiments described herein is shown, the qubit map block having a second shape that facilitates mapping a heavy hexagonal qubit connection topology to a linear physical qubit layout.

[0009] Figure 4 A block diagram of an exemplary non-limiting quantum structure according to one or more embodiments described herein is shown, which facilitates mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0010] Figure 5 A block diagram of an exemplary non-limiting quantum structure according to one or more embodiments described herein is shown, the quantum structure having a qubit map block that facilitates mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0011] Figure 6 A block diagram of an exemplary non-limiting quantum structure according to one or more embodiments described herein is shown, the quantum structure having qubit map blocks that facilitates mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0012] Figure 7 A block diagram of an exemplary non-limiting quantum structure according to one or more embodiments described herein is shown. The quantum structure has qubit blocks assembled with qubit blocks of different shapes. The qubit structure facilitates mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0013] Figure 8 A block diagram of an example non-limiting quantum structure according to one or more embodiments described herein is shown, the quantum structure having qubit blocks assembled from qubit blocks of different shapes, the quantum structure facilitating the mapping of a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0014] Figure 9 A block diagram of an example non-limiting quantum structure according to one or more embodiments described herein is shown, the quantum structure having qubit blocks assembled from qubit blocks of different shapes, the quantum structure facilitating the mapping of a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0015] Figure 10 A flowchart illustrating an exemplary non-limiting method according to one or more embodiments described herein is shown, which assists in mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0016] Figure 11 A block diagram of an example, non-limiting operating environment is shown, which may facilitate the description of one or more embodiments herein. Detailed Implementation

[0017] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being bound by any express or implied information presented in the foregoing Background or Summary of the Invention or Detailed Description sections.

[0018] One or more embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals are always used to denote the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent in various cases that one or more of the described embodiments may be practiced without these specific details.

[0019] Modern quantum computing systems can implement quantum error-correcting codes as a method of error suppression. Specifically, a quantum computing system may include one or more quantum chips on which two-dimensional lattices, arrays, arrangements, and / or layouts of qubits are physically located. In various cases, the qubits in such two-dimensional lattices, arrays, arrangements, and / or layouts can be interconnected via any suitable number and / or arrangement of inter-qubit interconnection buses (e.g., microwave resonators). In various cases, quantum error-correcting codes can be defined on such two-dimensional lattices, arrays, arrangements, and / or layouts of qubits, and the design of any particular quantum error-correcting code can depend on the underlying interconnection topology (also referred to as "connectivity") of the qubits in the two-dimensional lattice, array, arrangement, and / or layout (e.g., it can depend on the number and / or arrangement of the inter-qubit interconnection buses in the two-dimensional lattice, array, arrangement, and / or layout).

[0020] Note that, in various aspects, the qubit connectivity topology can be separate from and / or different from the physical qubit lattice, array, arrangement, and / or layout. Specifically, the physical lattice, array, arrangement, and / or layout of qubits on a quantum chip can describe how these qubits are physically positioned and / or placed on the quantum chip (e.g., arranged in a rectangular grid, circular grid, polygonal grid, irregular grid) and / or can describe the physical shape and / or the physical distance traversed by the inter-qubit connectivity buses connecting the qubits on the quantum chip (e.g., these inter-qubit connectivity buses can be straight, curved, long, short). Conversely, the connectivity topology of qubits on a quantum chip can describe how the qubits are connected to each other, regardless of the physical location and / or position of the qubits on the quantum chip and / or the physical shape and / or physical distance traversed by the inter-qubit connectivity buses. For example, consider a quantum computing chip with four qubits: qubit 1, qubit 2, qubit 3, and qubit 4. Furthermore, suppose qubit 1 is coupled to qubit 3, which is coupled to qubit 2, and qubit 4. This is a specific interconnection topology for four qubits on a quantum chip (e.g., 1-3-2-4). Note that this specific interconnection topology does not depend on the physical location and / or position of the four qubits on the quantum chip, and / or on the physical shape of the interconnecting bus connecting the four qubits on the quantum chip and / or the physical distance it traverses. In other words, these four qubits can have this specific interconnection topology (e.g., 1-3-2-4) regardless of whether the four qubits are physically arranged in the shape of a square, rectangle, trapezoid, rhombus, straight line, and / or curve, and regardless of whether the four qubits are physically close to each other and / or physically spaced apart by micrometers, millimeters, centimeters, and / or decimeters. This non-limiting, illustrative example helps to highlight the difference between the interconnection topology of a set of interconnected qubits and the physical layout and / or arrangement of that set of interconnected qubits.

[0021] In various cases, heavy hexagonal interconnect topologies can be an attractive option for implementing quantum error-correcting codes. In various instances, heavy hexagonal interconnect topologies can be physically implemented using heavy hexagonal physical lattices, arrays, arrangements, and / or layouts of qubits. In several aspects, heavy hexagonal physical grids, arrays, arrangements, and / or layouts of qubits can be formed by physically positioning and / or placing these qubits within the shape of a hexagonal grid on the quantum chip (e.g., these qubits can be physically arranged according to a pieced-together hexagonal grid, wherein each hexagon in the grid has a total of twelve qubits, wherein the qubits are physically positioned / placed at each vertex of the hexagon and physically positioned / placed along each line segment and / or segment of the hexagon, and wherein adjacent hexagons share qubits and / or inter-qubit interconnect buses).

[0022] In various instances, while a heavy-hexagonal interconnect topology may be desirable for the execution of quantum error-correcting codes, the heavy-hexagonal physical lattice, array, arrangement, and / or layout of qubits may include a significant amount of wasted space on the quantum chip. Specifically, the physical surface region of the quantum chip within, surrounded by, and / or confined by each hexagon of the hexagonal grid can be unused (e.g., empty portions of surface regions that could be used for other qubits and / or other circuit components) and can therefore be considered wasted real estate. Thus, from the perspective of fabrication and / or quantum chip real estate, the heavy-hexagonal physical lattice, array, arrangement, and / or layout of qubits may be spatially inefficient and / or suboptimal. In various cases, systems and / or techniques capable of addressing one or more of these technical problems may be required.

[0023] Various embodiments of the present invention can solve one or more of these technical problems. Specifically, various embodiments of the present invention can provide systems and / or techniques that can facilitate mapping heavy-hexagonal qubit interconnection topologies to linear physical qubit layouts. As mentioned above, heavy-hexagonal qubit interconnection topologies may be desirable for the implementation of quantum error-correcting codes, but from the perspective of fabrication and / or quantum chip real estate, heavy-hexagonal physical qubit layouts (e.g., physical hexagonal grids) may be spatially inefficient. Conversely, linear physical qubit layouts (e.g., cases where qubits are physically located on a quantum chip in a linear grid with regular and / or repeating rows and columns) can be spatially more efficient than heavy-hexagonal physical qubit layouts. Specifically, since linear grids consist of regular and / or repeating rows and columns of qubits, linear grids can densely fill the inner surface region of a quantum chip with qubits, which is typically not used by hexagonal grids. In other words, a linear physical qubit layout can help minimize the layout surface area of ​​a quantum chip (e.g., it can help to arrange qubits more densely on the quantum chip, resulting in less unused and therefore wasted space). Furthermore, minimizing the layout surface area in this way can help reduce and / or save manufacturing costs (e.g., it may be easier and / or cheaper to fabricate a linear qubit grid than a hexagonal qubit grid), can help match transmission line lengths to the permissible frequency range (e.g., more densely packed qubits can be connected by shorter inter-qubit interconnect buses, and shorter inter-qubit interconnect buses can exhibit more and / or higher resonant frequencies within the desired operating band), and / or can help avoid parasitic radio frequency modes associated with the size of the quantum chip (e.g., since qubits themselves can be more densely packed on the quantum chip when using a linear physical layout, a wider range of the physical size of the quantum chip itself can become available, and thus a quantum chip size that helps to avoid and / or minimize parasitic losses can be achieved). Furthermore, this linear physical qubit layout can be highly regular, meaning that quantum circuits designed on this layout can be easily scaled up and / or scaled down based on the desired size of the quantum chip. This can help minimize the number of different quantum circuit structures that need to be simulated during research and development. Therefore, implementing a heavy-hexagonal qubit connection topology in a linear physical qubit layout allows for the execution of advanced quantum error-correcting codes without the spatial inefficiencies associated with heavy-hexagonal physical qubit layouts.

[0024] The inventors of various embodiments of the present invention recognized how a heavy-hexagonal qubit interconnect topology can be mapped to a linear physical qubit layout. Specifically, in various cases, linear qubit arrays can be formed on a quantum substrate (e.g., a silicon wafer). In various cases, the linear qubit array can be a square, rectangular, and / or orthogonal two-dimensional array of qubits, such that the qubits are arranged in regular and / or repeating rows and columns on the quantum substrate. In several aspects, inter-qubit interconnect buses can be strategically placed between qubits in the linear qubit array to define a first set of qubit blocks having a first shape and a second set of qubit blocks having a second shape, wherein the first shape differs from the second shape. In various cases, each of the first set of qubit blocks can represent a heavy-hexagonal unit cell. Similarly, in various cases, each of the second set of qubit blocks can represent a heavy-hexagonal unit cell. In various cases, the first and second sets of qubit blocks can be combined in a linear qubit matrix, such that the qubits on the quantum chip are physically positioned in regular and / or repeating rows and columns and collectively exhibit a heavy hexagonal interconnection topology. In some cases, a qubit block may include multiple qubits (e.g., twelve qubits) connected together in a specific arrangement, shape, and / or manner (e.g., each qubit in the qubit block is connected to two adjacent qubits in the qubit block, thereby forming a closed-loop qubit block). In some cases, two or more sets of qubit blocks of different shapes can be combined to map the heavy hexagonal interconnection topology to a linear physical qubit layout.

[0025] Various embodiments of the present invention can be employed to solve inherently highly technical problems (e.g., mapping heavy-hexagonal qubit connectivity topologies to linear physical qubit layouts) using hardware and / or software. These problems are not abstract and cannot be performed by humans as a set of mental actions. In fact, various embodiments of the present invention can constitute real-world physical quantum structures that can be fabricated on real-world quantum substrates to realize heavy-hexagonal qubit connectivity topologies with linear physical qubit layouts. Such real-world physical quantum structures are certainly not abstract, not laws of nature, and not natural phenomena. Furthermore, various embodiments of the present invention can integrate the teachings disclosed herein into practical applications. Indeed, in various embodiments, the disclosed teachings can facilitate the fabrication of quantum chips that can implement quantum error-correcting codes using heavy-hexagonal connectivity topologies but lack the spatial inefficiencies typically associated with heavy-hexagonal physical qubit layouts. Specifically, since the disclosures herein teach how to achieve a heavy-hexagonal qubit interconnect topology using a linear physical qubit layout, these disclosures can facilitate the fabrication of quantum chips with a more densely packed qubit configuration than those achieving a heavy-hexagonal physical qubit layout. Therefore, embodiments of the invention can facilitate the creation of quantum chips with less wasted chip real estate but still usable for implementing heavy-hexagonal-based quantum error-correcting codes. As described above, reducing the amount of wasted surface area on the quantum chip in this way can lead to a proportional cost reduction, make it easier to keep the resonant frequencies of the transmission lines and / or inter-qubit interconnect buses within the desired operating range, and / or help reduce the number of parasitic radio frequency modes. In other words, embodiments of the invention can facilitate the fabrication of quantum chips exhibiting improved quantum performance. Therefore, embodiments of the invention constitute a concrete and practical technical improvement in the field of quantum interconnect topologies.

[0026] The teachings disclosed herein are based on inherent geometry, and therefore the accompanying drawings and / or illustrations can aid in understanding various embodiments of the invention. In all respects, the accompanying drawings and / or illustrations are exemplary, non-limiting, and not necessarily drawn to scale.

[0027] Figure 1 A block diagram of an exemplary, non-limiting, heavy-hexagonal qubit interconnect topology implemented using a heavy-hexagonal physical qubit layout 100 is shown. As illustrated, the heavy-hexagonal physical qubit layout 100 may include a plurality of qubits 110-178 (e.g., Figure 1 (As shown by the black dots), these multiple qubits can be connected via multiple qubit interconnect buses ( Figure 1The black lines between adjacent qubits indicate that they are coupled together. As shown in the figure, qubits 110-178 can be coupled together in various ways, so that they are physically arranged and / or laid out according to a hexagonal grid pattern. In other words, qubits 110-178 can be physically arranged and / or coupled to form four qubit blocks 102-108, each of which has a hexagonal physical shape. Furthermore, the four qubit blocks 102-108 can be physically hexagonal and can be combined to form a hexagonal physical qubit layout 100.

[0028] As shown in the figure, in various cases, each of the four qubit slices 102-108 can include twelve qubits and twelve interconnecting buses between qubits. Specifically, qubit block 102 can be composed of qubits 110, 112, 114, 116, 118, 174, 172, 170, 168, 166, 162, and 164. As shown in the figure, qubit 110 can be considered as the first vertex of qubit block 102, qubit 114 as the second vertex, qubit 118 as the third vertex, qubit 172 as the fourth vertex, qubit 168 as the fifth vertex, and qubit 162 as the sixth vertex. Furthermore, as shown, qubit 110 can be coupled to qubit 112 via an inter-qubit interconnection bus, qubit 112 can be coupled to qubit 114 via an inter-qubit interconnection bus, qubit 114 can be coupled to qubit 116 via an inter-qubit interconnection bus, qubit 116 can be coupled to qubit 118 via an inter-qubit interconnection bus, qubit 118 can be coupled to qubit 174 via an inter-qubit interconnection bus, and qubit 174 can be coupled to qubit 118 via an inter-qubit interconnection bus. 172, qubit 172 can be coupled to qubit 170 via an inter-qubit connection bus, qubit 170 can be coupled to qubit 168 via an inter-qubit connection bus, qubit 168 can be coupled to qubit 166 via an inter-qubit connection bus, qubit 166 can be coupled to qubit 162 via an inter-qubit connection bus, qubit 162 can be coupled to qubit 164 via an inter-qubit connection bus, and qubit 164 can be coupled to qubit 110 via an inter-qubit connection bus. In some cases, the qubit connection topology can be represented as 110-112-114-116-118-174-172-170-168-166-162-164-110.

[0029] Similarly, qubit block 104 can be composed of qubits 158, 160, 162, 166, 168, 178, 146, 148, 150, 152, 154, and 156. As shown in the figure, qubit 158 ​​can be considered as the first vertex of qubit block 104, qubit 162 as the second vertex, qubit 168 as the third vertex, qubit 146 as the fourth vertex, qubit 150 as the fifth vertex, and qubit 154 as the sixth vertex. Furthermore, as shown, qubit 158 ​​can be coupled to qubit 160 via an inter-qubit connection bus, qubit 160 can be coupled to qubit 162 via an inter-qubit connection bus, qubit 162 can be coupled to qubit 166 via an inter-qubit connection bus, qubit 166 can be coupled to qubit 168 via an inter-qubit connection bus, qubit 168 can be coupled to qubit 178 via an inter-qubit connection bus, qubit 178 can be coupled to qubit 146 via an inter-qubit connection bus, qubit 146 can be coupled to qubit 148 via an inter-qubit connection bus, qubit 148 can be coupled to qubit 150 via an inter-qubit connection bus, qubit 150 can be coupled to qubit 152 via an inter-qubit connection bus, qubit 152 can be coupled to qubit 154 via an inter-qubit connection bus, qubit 154 can be coupled to qubit 156 via an inter-qubit connection bus, and qubit 156 can be coupled to qubit 158 ​​via a qubit connection bus. In some cases, the qubit connection topology can be represented as 158-160-162-166-168-178-146-148-150-152-154-158.

[0030] Similarly, qubit block 106 can be composed of qubits 118, 120, 122, 124, 126, 128, 130, 132, 134, 176, 172, and 174. As shown in the figure, qubit 118 can be considered as the first vertex of qubit block 106, qubit 122 as the second vertex, qubit 126 as the third vertex, qubit 130 as the fourth vertex, qubit 134 as the fifth vertex, and qubit 172 as the sixth vertex. Furthermore, as shown, qubit 118 can be coupled to qubit 120 via an inter-qubit connection bus, qubit 120 can be coupled to qubit 122 via an inter-qubit connection bus, qubit 122 can be coupled to qubit 124 via an inter-qubit connection bus, qubit 124 can be coupled to qubit 126 via an inter-qubit connection bus, qubit 126 can be coupled to qubit 128 via an inter-qubit connection bus, qubit 128 can be coupled to qubit 130 via an inter-qubit connection bus, qubit 130 can be coupled to qubit 132 via an inter-qubit connection bus, qubit 132 can be coupled to qubit 134 via an inter-qubit connection bus, qubit 134 can be coupled to qubit 176 via an inter-qubit connection bus, qubit 176 can be coupled to qubit 172 via an inter-qubit connection bus, qubit 172 can be coupled to qubit 174 via an inter-qubit connection bus, and qubit 174 can be coupled to qubit 118 via a qubit connection bus. In some cases, the qubit connection topology can be represented as 118-120-122-124-126-128-130-132-134-176-172-174-118.

[0031] Similarly, qubit block 108 can be composed of qubits 168, 170, 172, 176, 134, 136, 138, 140, 142, 144, 146, and 178. As shown in the figure, qubit 168 can be considered as the first vertex of qubit block 108, qubit 172 as the second vertex, qubit 134 as the third vertex, qubit 138 as the fourth vertex, qubit 142 as the fifth vertex, and qubit 146 as the sixth vertex. Furthermore, as shown, qubit 168 can be coupled to qubit 170 via an inter-qubit connection bus, qubit 170 can be coupled to qubit 172 via an inter-qubit connection bus, qubit 172 can be coupled to qubit 176 via an inter-qubit connection bus, qubit 176 can be coupled to qubit 134 via an inter-qubit connection bus, qubit 134 can be coupled to qubit 136 via an inter-qubit connection bus, qubit 136 can be coupled to qubit 138 via an inter-qubit connection bus, qubit 138 can be coupled to qubit 140 via an inter-qubit connection bus, qubit 140 can be coupled to qubit 142 via an inter-qubit connection bus, qubit 142 can be coupled to qubit 144 via an inter-qubit connection bus, qubit 144 can be coupled to qubit 146 via an inter-qubit connection bus, qubit 146 can be coupled to qubit 178 via an inter-qubit connection bus, and qubit 178 can be coupled to qubit 168 via a qubit connection bus. In some cases, this qubit connection topology can be represented as 168-170-172-176-134-136-138-140-142-144-178-168.

[0032] As shown in the figure, in various situations, adjacent qubit blocks in the heavy-hexagonal physical qubit layout 100 can share qubits and / or can share inter-qubit connection buses. For example, as shown, qubit block 102 can share qubits 162, 166, and 168 with qubit block 104. Furthermore, qubit block 102 can share the inter-qubit connection bus that couples qubit 162 to qubit 166 and the inter-qubit connection bus that couples qubit 166 to qubit 168 with qubit block 104. As another example, qubit block 102 can share qubits 172, 174, and 118 with qubit block 106. Furthermore, qubit block 102 can share the inter-qubit connection bus that couples qubit 172 to qubit 174 and the inter-qubit connection bus that couples qubit 174 to qubit 118 with qubit block 106. As yet another example, qubit block 102 can share qubits 168, 170, and 172 with qubit block 108. Furthermore, qubit block 102 can share with qubit block 108 the inter-qubit connection bus that couples qubit 168 to qubit 170 and the inter-qubit connection bus that couples qubit 170 to qubit 172. In different embodiments, any given qubit block in the heavy-hexagonal physical qubit layout 100 can share three qubits and / or two inter-qubit connections with any adjacent qubit block in the heavy-hexagonal physical qubit layout 100.

[0033] In various aspects, qubits 110-178 can be any suitable type and / or any combination of suitable qubit devices (e.g., any suitable superconducting qubit device, such as charge qubits, flux qubits, phase qubits and / or transmon qubits, and / or any suitable non-superconducting qubit device). In various aspects, the inter-qubit connection bus can be any suitable device and / or any suitable combination of devices for electrically coupling two or more qubits together (e.g., microwave resonator, direct coupler, capacitive coupler, waveguide).

[0034] In various embodiments, as described above, the heavy-hexagonal physical qubit layout 100 can present a heavy-hexagonal qubit interconnection topology. That is, each of the qubit blocks 102-108 can consist of twelve qubits, which are coupled into a closed loop via twelve inter-qubit interconnection buses, wherein adjacent qubit blocks can share three qubits and two inter-qubit interconnection buses with each other. As described above, this heavy-hexagonal qubit interconnection topology is desirable for the implementation of heavy-hexagonal-based quantum error correction codes. However, also as described above and as... Figure 1As shown, while the hexagonal qubit interconnect topology is ideal in a topological sense, the hexagonal physical qubit layout 100 is not spatially efficient in a physical sense (e.g., as mentioned above, the interconnect topology differs from the physical layout). Specifically, there is a significant amount of wasted space in the middle and / or interior of each of the qubit blocks 102-108. In other words, the interior region of each of the qubit blocks 102-108, which can be considered as a surface region of a quantum substrate (not shown) that could be effectively used to support other qubits and / or other quantum circuit devices, is not actually used efficiently due to the hexagonal physical arrangement of the hexagonal physical quantum layout 100 (e.g., due to the physical hexagonal shape of the qubit blocks 102-108, a large amount of space in each qubit block 102-108 is left unused and / or wasted).

[0035] In various aspects, the inventors of the various embodiments of the present invention recognized that such wasted space may be caused by the fact that qubits 110-178 are physically located and / or arranged according to a hexagonal grid, and because qubits 110-178 are not physically located and / or arranged according to a denser linear grid (e.g., qubits 110-178 are physically arranged in the shape of a patchwork hexagon, and not physically arranged in regular and / or repeating rows and columns in the heavy-hexagonal physical qubit layout 100). Therefore, the inventors of the various embodiments of the present invention recognized that this space inefficiency can be eliminated by physically arranging qubits 110-178 according to a denser linear grid rather than a less dense hexagonal grid (e.g., qubits 110-178 are arranged in regular and / or repeating rows and columns rather than in hexagonal physical layouts). In other words, the inventors of the various embodiments of the present invention determined how to shape qubit tiles 102-108 such that they can be implemented within a linear physical grid while still presenting a heavy-hexagonal interconnected topology.

[0036] More specifically, the inventors of the various embodiments of the present invention have determined that... Figure 2 and Figure 3 The quantum bit maps of specific shapes shown can be pieced together to map a hexagonal interconnected topology to a linear physical layout.

[0037] Figure 2 A block diagram of an exemplary non-limiting qubit map 200 according to one or more embodiments described herein is shown. The qubit map has a first shape that can assist in mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout. As shown, in several aspects, the qubit map 200 may include twelve qubits connected via a twelve-qubit interconnect bus. Figure 2The shapes shown are coupled together. More specifically, qubit block 200 may include qubits 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, and 224. In some embodiments, any other suitable number of qubits may be incorporated into qubit block 200. As shown in the figure, qubit 202 can be coupled to qubit 204 via the inter-qubit connection bus. Qubit 204 can be coupled to qubit 206 via the inter-qubit connection bus. Qubit 206 can be coupled to qubit 208 via the inter-qubit connection bus. Qubit 208 can be coupled to qubit 210 via the inter-qubit connection bus. Qubit 210 can be coupled to qubit 212 via the inter-qubit connection bus. Qubit 212 can be coupled to qubit 214 via the inter-qubit connection bus. Qubit 214 can be coupled to qubit 216 via the inter-qubit connection bus. Qubit 216 can be coupled to qubit 218 via the inter-qubit connection bus. Qubit 218 can be coupled to qubit 220 via the inter-qubit connection bus. Qubit 220 can be coupled to qubit 222 via the inter-qubit connection bus. Qubit 222 can be coupled to qubit 224 via the inter-qubit connection bus. Furthermore, qubit 224 can be coupled to qubit 202 via the inter-qubit connection bus. In all respects, this qubit connection topology can be called 202-204-206-208-210-212-214-216-218-220-222-224-202.

[0038] As shown in the figure, in various embodiments, the qubits 202-224 of the qubit block 200 can be physically positioned and / or arranged according to a linear grid. Specifically, in various aspects, the linear grid can be defined by columns 226-234 and rows 236-240, and in various cases, the qubits 202-224 of the qubit block 200 can be physically positioned and / or arranged along columns 226-234 and along rows 236-240. In various cases, columns 226-234 can be regularly spaced (e.g., in...). Figure 2 The horizontal rows can be separated by any suitable regularity, while rows 236-240 can be spaced regularly (e.g., in...). Figure 2(Separated vertically in any suitable pattern). As shown, columns 226-234 can be parallel to each other. Similarly, rows 236-240 can be parallel to each other. As shown, columns 226-234 can be orthogonal and / or perpendicular to rows 236-240. In different instances, as shown, qubits 202, 224, and 222 can be physically positioned along column 226; qubits 204, 218, and 220 can be physically positioned along column 228; qubits 206 and 216 can be physically positioned along column 230; qubits 208, 210, and 214 can be physically positioned along column 232; and qubit 212 can be physically positioned along column 234. In several respects, as shown, qubits 202, 204, 206, and 208 can be physically located along row 236; qubits 224, 218, 216, 210, and 212 can be physically located along row 238; and qubits 222, 220, and 214 can be physically located along row 240.

[0039] In various cases, the horizontal and / or vertical spacing separating columns 226-234 and rows 236-240 can be selected and / or chosen based on any suitable design criteria. For example, in some cases, columns 226-234 and rows 236-240 can be physically arranged such that qubits 202-224 are densely packed together (e.g., such that qubits 202-224 are physically as close as possible to each other without undesirable quantum interference). This dense packing of qubits 202-224 ensures that qubit block 200 does not span unnecessarily large amounts of surface area (e.g., unlike the hexagonal shape of qubit blocks 102-108), which helps ensure that qubit block 200 contains very little wasted space and / or very little wasted quantum chip real estate.

[0040] Note that qubit block 200 can have a different physical shape than qubit blocks 102-108. That is, qubit block 200 has a specific irregular physical shape. Figure 2As shown in the figure, qubit blocks 102-108 each have a hexagonal physical shape. However, note that, as shown, qubit block 200 does exhibit the same qubit connectivity topology as each of qubit blocks 102-108 (e.g., again, the connectivity topology can differ from the physical shape / layout). That is, qubit block 200 can include twelve qubits, where each qubit is coupled to two adjacent qubits, thereby forming a twelve-qubit closed loop, just like each of qubit blocks 102-108. As shown, each qubit in qubit block 200 can be coupled to the nearest neighboring qubit (e.g., the nearest neighboring qubit in the north, south, east, and / or west direction from that given qubit) and / or can be coupled to the next nearest neighboring qubit (e.g., the nearest neighboring qubit in the diagonal direction from that given qubit). In summary, under various conditions, qubit block 200 can be considered as a heavy-hexagonal unit (e.g., qubit block 200 can exhibit the same connectivity topology as qubit blocks 102-108, although it does not have the same hexagonal physical shape / layout as qubit blocks 102-108). In various aspects, the specific irregular physical shape exhibited by qubit block 200 can be referred to as a duck shape (e.g., qubit block 200 can be considered to be roughly similar to an inverted duck graphic).

[0041] Figure 3 A block diagram of an exemplary non-limiting qubit map 300 according to one or more embodiments described herein is shown. The qubit map has a second shape that facilitates mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout. As shown, in several aspects, the qubit map 300 may include twelve qubits connected via a twelve-qubit interconnect bus. Figure 3The shapes shown are coupled together. More specifically, qubit block 300 may include qubits 302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, and 324. In some embodiments, any other suitable number of qubits may be incorporated into qubit block 300. As shown in the figure, qubit 302 can be coupled to qubit 304 via the inter-qubit connection bus. Qubit 304 can be coupled to qubit 306 via the inter-qubit connection bus. Qubit 306 can be coupled to qubit 308 via the inter-qubit connection bus. Qubit 308 can be coupled to qubit 310 via the inter-qubit connection bus. Qubit 310 can be coupled to qubit 312 via the inter-qubit connection bus. Qubit 312 can be coupled to qubit 314 via the inter-qubit connection bus. Qubit 314 can be coupled to qubit 316 via the inter-qubit connection bus. Qubit 316 can be coupled to qubit 318 via the inter-qubit connection bus. Qubit 318 can be coupled to qubit 320 via the inter-qubit connection bus. Qubit 320 can be coupled to qubit 322 via the inter-qubit connection bus. Qubit 322 can be coupled to qubit 324 via the inter-qubit connection bus. Qubit 324 can be coupled to qubit 302 via the inter-qubit connection bus. In all respects, this qubit connection topology can be called 302-304-306-310-312-314-316-318-320-322-324-302.

[0042] As shown in the figure, in different embodiments, the qubits 302-324 of the qubit block 300 can be physically positioned and / or arranged according to a linear grid. Specifically, in various aspects, the linear grid can be defined by columns 326-332 and rows 334-340, and in various cases, the qubits 302-324 of the qubit block 300 can be physically positioned and / or arranged along columns 326-332 and along rows 334-340. In various cases, columns 326-332 can be regularly spaced (e.g., in...). Figure 3 (separated horizontally by any suitable regular interval), and rows 334 to 340 may be regularly spaced (e.g., in...). Figure 3(Separated vertically by any suitable rule). As shown, columns 326-332 can be parallel to each other. Similarly, rows 334-340 can be parallel to each other. As shown, columns 326-332 can be orthogonal to and / or perpendicular to rows 334-340. In different instances, as shown, qubits 302, 324, and 322 can be physically positioned along column 326; qubits 304 and 320 can be physically positioned along column 328; qubits 308, 306, 316, and 318 can be physically positioned along column 330; and qubits 310, 312, and 314 can be physically positioned along column 332. In different aspects, as shown, qubits 308 and 310 can be physically located along row 334; qubits 302, 306, and 312 can be physically located along row 336; qubits 324, 304, 316, and 314 can be physically located along row 338; and qubits 322, 320, and 318 can be physically located along row 340.

[0043] In various cases, the horizontal and / or vertical spacing separating columns 326-332 from rows 334-340 can be selected and / or chosen based on any suitable design criteria. For example, in some cases, columns 326-332 and rows 334-340 can be physically arranged such that qubits 302-324 are densely packed together (e.g., physically close together, because they can practically and / or actually avoid experiencing unwanted quantum interference with each other). This dense packing of qubits 302-324 can ensure that qubit blocks 300 do not span unnecessarily large amounts of surface area (e.g., unlike the hexagonal shape of qubit blocks 102-108), which helps ensure that qubit blocks 300 contain very little wasted space and / or very little wasted quantum chip real estate.

[0044] Note that qubit block 300 can have a different physical shape than qubit blocks 102-108. That is, qubit block 300 has a specific irregular physical shape. Figure 3As shown in the figure, each of the qubit patches 102-108 has a hexagonal physical shape. However, note that, as shown, qubit patch 300 does exhibit the same qubit connection topology as each of the qubit patches 102-108 (e.g., again, the connection topology can differ from the physical shape / layout). That is, qubit patch 300 can include twelve qubits, where each qubit is coupled to two adjacent qubits, thereby forming a twelve-qubit closed loop, just like each of the qubit patches 102-108. As shown, each qubit in qubit patch 300 can be connected to the nearest neighboring qubit (e.g., the nearest neighboring qubit in the north, south, east, and / or west direction from the given qubit) and / or can be connected to the next nearest neighboring qubit (e.g., the nearest neighboring qubit in the diagonal direction from the given qubit). In summary, under various conditions, qubit block 300 can be considered as a heavy-hexagonal unit (e.g., qubit block 300 can exhibit the same connectivity topology as qubit blocks 102-108, although it does not have the same hexagonal physical shape / layout as qubit blocks 102-108). In various aspects, the specific irregular physical shape exhibited by qubit block 300 can be referred to as a cow shape (e.g., qubit block 300 can be considered to roughly resemble a tilted cow graphic).

[0045] In various embodiments, as shown in the following figures, multiple qubit blocks 200 may be combined with multiple qubit blocks 300 in a linear grid to form a linear physical qubit layout that still generally exhibits a heavy-hexagonal qubit interconnect topology.

[0046] Figure 4 A block diagram of an exemplary non-limiting quantum structure 400 according to one or more embodiments described herein is shown, which can assist in mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0047] In various embodiments, the quantum structure 400 may include a quantum substrate 402. In various aspects, the quantum substrate 402 may be any suitable quantum substrate (e.g., a silicon wafer). In various cases, Figure 4 This can be considered a top view of the quantum substrate 402. In various aspects, the quantum substrate 402 can physically support a quantum dot array 404. In various aspects, the quantum dot array 404 can be a linear grid of qubits fabricated on the surface of the quantum substrate 402 (qubits in... Figure 4(Represented by black dots). In other words, the quantum dot array 404 can be arranged according to one or more columns AN and one or more rows 1-13. In different aspects, the qubits of the quantum dot array 404 can be specified by their column and row indices (e.g., qubit A1 can be the top-left qubit in the quantum dot array 404, qubit N1 can be the top-right qubit in the quantum dot array 404, qubit A13 can be the bottom-left qubit in the quantum dot array 404, and qubit N13 can be the bottom-right qubit in the quantum dot array 404).

[0048] Although Figure 4 The quantum dot array 404 is depicted as having 182 qubits, but this is merely exemplary and not limiting. In several respects, the quantum dot array 404 can have any suitable number of qubits (e.g., different rows of the quantum dot array 404 can have different numbers of qubits, and / or different columns of the quantum dot array 404 can have different numbers of qubits). Although Figure 4 The quantum dot array 404 is depicted as having 14 columns (e.g., AN), but this is merely exemplary and not limiting. In various cases, the quantum dot array 404 can have any suitable number of columns. Although Figure 4 The quantum dot array 404 is depicted as having 13 rows (e.g., 1-13), but this is merely exemplary and not limiting. In various cases, the quantum dot array 404 can have any suitable number of rows.

[0049] As explained herein, multiple qubit blocks 200 can be combined with multiple qubit blocks 300 within a qubit array 404. In various respects, this combination can present a heavy-hexagonal qubit connection topology while also presenting a linear physical qubit layout.

[0050] Figure 5 A block diagram of an exemplary non-limiting quantum structure 500 according to one or more embodiments described herein is shown, the quantum structure having qubit map blocks that can assist in mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0051] As shown in the figure, qubit block 502 can create an inter-qubit connection bus between different qubits (in... Figure 5(Represented by black lines) and generated within the qubit array 404. For example, qubit block 502 can be formed by coupling qubit J1 to qubit K1, coupling qubit K1 to qubit L1, coupling qubit L1 to qubit M1, coupling qubit M1 to qubit M2, coupling qubit M2 to qubit N2, coupling qubit N2 to qubit M3, coupling qubit M3 to qubit L2, coupling qubit L2 to qubit K2, coupling qubit K2 to qubit K3, coupling qubit K3 to qubit J3, coupling qubit J3 to qubit J2, and coupling qubit J2 to qubit J1. In various cases, qubit block 502 can therefore be considered to have the following qubit connection topology: J1-K1-L1-M1-M2-N2-M3-L2-K2-K3-J3-J2-J1. In various cases, as shown in the figure, qubit block 502 can present the duck shape of qubit block 200.

[0052] Figure 6 A block diagram of an exemplary non-limiting quantum structure 600 according to one or more embodiments described herein is shown, the quantum structure having qubit map blocks that can assist in mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0053] As shown in the figure, additional duck-shaped qubit blocks with qubit block 200 can be formed in qubit matrix 404. Specifically, in various cases, qubit blocks 602-606 can be fabricated in qubit matrix 404, as shown by creating inter-qubit interconnect buses between various qubits. For example, as shown in the figure, qubit block 602 can have a qubit interconnect topology G2-H2-I2-J2-J3-K3-J4-I3-H3-H4-G4-G3-G2, qubit block 604 can have a qubit interconnect topology D3-E3-F3-G3-G4-H4-G5-F4-E4-E5-D5-D4-D3, and qubit block 606 can have a qubit interconnect topology A4-B4-C4-D4-D5-E5-D6-C5-B5-B6-A6-A5-A4. As shown in the figure, under various conditions, qubit blocks 502 and 602 can share qubits J2, J3, and K3, and / or can also share the inter-qubit connection bus that couples qubit J2 to qubit J3 and the inter-qubit connection bus that couples qubit J3 to qubit K3. In various aspects, qubit blocks 602 and 604 can share qubits G3, G4, and H4, and / or can also share the inter-qubit connection bus that couples qubit G3 to qubit G4 and the inter-qubit connection bus that couples qubit G4 to qubit H4. Under various conditions, qubit blocks 604 and 606 can share qubits D4, D5, and E5, and / or can also share the inter-qubit connection bus that couples qubit D4 to qubit D5 and the inter-qubit connection bus that couples qubit D5 to qubit E5. In various cases, as shown, qubit blocks 602-606 can each present the duck shape of qubit block 200.

[0054] Figure 7 A block diagram of an exemplary non-limiting quantum structure 700 according to one or more embodiments described herein is shown. The quantum structure has qubit map blocks assembled from qubit pieces of different shapes, which can facilitate mapping of a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0055] As shown in the figure, a qubit block 702 can be created within a qubit array 404 by fabricating inter-qubit interconnection buses between different qubits. For example, qubit block 702 can have a qubit interconnection topology I3-J4-K3-K2-L2-L3-L4-K4-K5-J5-I5-I4-I3. In various cases, as shown, qubit block 702 and qubit block 502 can share qubits K3, K2, and L2, and / or can also share the inter-qubit interconnection bus that couples qubit K3 to qubit K2 and the inter-qubit interconnection bus that couples qubit K2 to qubit L2. In different aspects, qubit block 702 and qubit block 602 can share qubits I3, J4, and K3, and / or can also share the inter-qubit interconnection bus that couples qubit I3 to qubit J4 and the inter-qubit interconnection bus that couples qubit J4 to qubit K3. In various cases, as shown, qubit block 702 can display the cow shape of qubit block 300.

[0056] Figure 8 A block diagram of an exemplary non-limiting quantum structure 800 according to one or more embodiments described herein is shown. The quantum structure has qubit blocks assembled from qubit blocks of different shapes, which facilitates mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0057] As shown in the figure, additional qubit blocks with cow-shaped qubit blocks 300 can be formed in the qubit matrix 404. Specifically, in various cases, qubit blocks 802-804 can be fabricated in the qubit matrix 404, as shown by creating an inter-qubit interconnect bus between various qubits. For example, as shown in the figure, qubit block 802 can have a qubit interconnect topology F4-G5-H4-H3-I3-I4-I5-H5-H6-G6-F6-F5-F4, and qubit block 804 can have a qubit interconnect topology C5-D6-E5-E4-F4-F5-F6-E6-E7-D7-C7-C6-C5. As shown in the figure, under various conditions, qubit blocks 802 and 702 can share qubits I3, I4, and I5, and / or can also share the inter-qubit connection bus that couples qubit I3 to qubit I4, and the inter-qubit connection bus that couples qubit I4 to qubit I5. In different aspects, qubit blocks 802 and 602 can share qubits H4, H3, and I3, and / or can also share the inter-qubit connection bus that couples qubit H4 to qubit H3 and the inter-qubit connection bus that couples qubit H3 to qubit I3. Under various conditions, qubit blocks 802 and 604 can share qubits F4, G5, and H4, and / or can also share the inter-qubit connection bus that couples qubit F4 to qubit G5 and the inter-qubit connection bus that couples qubit G5 to qubit H4. In various cases, qubit blocks 802 and 804 can share qubits F4, F5, and F6, and / or may also share the inter-qubit connection bus coupling qubit F4 to qubit F5 and the inter-qubit connection bus coupling qubit F5 to qubit F6. In several aspects, qubit blocks 804 and 604 can share qubits E5, E4, and F4, and / or may also share the inter-qubit connection bus coupling qubit E5 to qubit E4 and the inter-qubit connection bus coupling qubit E4 to qubit F4. In various cases, qubit blocks 804 and 606 can share qubits C5, D6, and E5, and / or may also share the inter-qubit connection bus coupling qubit C5 to qubit D6 and the inter-qubit connection bus coupling D6 to qubit E5. In various cases, as shown in the figure, qubit blocks 802-804 can each exhibit the bull-shaped form of qubit block 300.

[0058] In general, as shown in the figure, duck-shaped qubit blocks (e.g., qubit blocks 502, 602, 604, and 606) can be combined with cow-shaped qubit blocks (e.g., qubit blocks 702, 802, and 804) within the linear grid of the qubit matrix 404. In various cases, this checkerboard arrangement pattern can be extended to any suitable size, such as... Figure 9 As shown in the image.

[0059] Figure 9 A block diagram of an exemplary non-limiting quantum structure 900 according to one or more embodiments described herein is shown. The quantum structure has a qubit map block assembled from qubit blocks of different shapes, which facilitates mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0060] As shown in the figure, in various embodiments... Figure 4-8 The checkerboard pattern depicted can be extended to any suitable size as needed (e.g., it can depend on the size and / or dimensions of the qubit array 404). In various cases, qubit blocks 902-926 can be fabricated in the qubit array 404 by creating inter-qubit interconnect buses between various qubits. As shown, qubit blocks 902-906 and 916-920 can present the duck-shaped form of qubit block 200, and qubit blocks 908-914 and 922-926 can present the cow-shaped form of qubit block 300.

[0061] As shown, multiple qubit blocks with duck-shaped forms (e.g., qubit blocks 502, 602-606, 902-906, and 916-920) can be combined within qubit block array 404 with multiple qubit block arrays with cow-shaped forms (e.g., qubit blocks 702, 802-804, 908-914, and 922-926). Since qubit block array 404 is arranged according to a linear grid (e.g., columns AN and rows 1-13), the multiple qubit blocks with duck-shaped forms combined with the multiple qubit blocks with cow-shaped forms can be collectively considered to demonstrate a linear physical qubit layout (e.g., the qubits constituting all of these depicted qubit blocks are physically positioned and / or arranged along orthogonal rows and columns).

[0062] However, as shown in the figure, multiple qubit blocks in a duck-shaped configuration, which are assembled with multiple qubit blocks of a cow-shaped configuration, still collectively exhibit a heavy-hexagonal qubit connectivity topology. This can be verified by comparing the qubit connectivity topology of qubit matrix 404 with that exhibited by the heavy-hexagonal physical qubit layout 100. For example, consider qubit blocks 102, 104, 106, and 108 in the heavy-hexagonal physical qubit layout 100, and without loss of generality consider qubit blocks 910, 918, 908, and 916 in qubit matrix 404. As mentioned above... Figure 1 As explained, qubit block 102 can have twelve qubits coupled in a closed loop via twelve inter-qubit interconnect buses, and can share three qubits (and / or two inter-qubit interconnect buses) with each of its adjacent neighboring qubit blocks. That is, qubit block 102 can share three qubits with qubit block 104 (e.g., 162, 166, and 168), qubit block 102 can share three qubits with qubit block 106 (e.g., 172, 174, and 118), and qubit block 102 can share three qubits with qubit block 108 (e.g., 168, 170, and 172). Similarly, as... Figure 9 As shown, qubit block 910 can have twelve qubits coupled in a closed loop via twelve inter-qubit connection buses, and can share three qubits (and / or two inter-qubit connection buses) with each of its adjacent neighboring qubit blocks. That is, qubit block 910 can share three qubits with qubit block 918 (e.g., G9, H9, and I9), qubit block 910 can share three qubits with qubit block 908 (e.g., J8, J7, and J6), and qubit block 910 can share three qubits with qubit block 916 (e.g., I9, I8, and J8).

[0063] In addition, as mentioned above Figure 1 As explained, qubit block 104 can have twelve qubits coupled in a closed loop via twelve inter-qubit interconnect buses, and can share three qubits (and / or two inter-qubit interconnect buses) with each of its adjacent neighboring qubit blocks. That is, qubit block 104 can share three qubits with qubit block 102 (e.g., 162, 166, and 168), and qubit block 104 can share three qubits with qubit block 108 (e.g., 146, 178, and 168). Similarly, as... Figure 9As shown, qubit block 918 can have twelve qubits coupled in a closed loop via twelve inter-qubit connection buses, and can share three qubits (and / or two inter-qubit connection buses) with each of its adjacent neighboring qubit blocks. That is, qubit block 918 can share three qubits (e.g., G9, H9, and I9) with qubit block 910, and qubit block 918 can share three qubits (e.g., J10, I10, and I9) with qubit block 916.

[0064] In addition, as mentioned above Figure 1 As explained, qubit block 106 can have twelve qubits coupled in a closed loop via twelve inter-qubit interconnect buses, and can share three qubits (and / or two inter-qubit interconnect buses) with each of its adjacent neighboring qubit blocks. That is, qubit block 106 can share three qubits with qubit block 102 (e.g., 172, 174, and 118), and qubit block 106 can share three qubits with qubit block 108 (e.g., 172, 176, and 134). Similarly, as... Figure 9 As shown, qubit block 908 can have twelve qubits coupled in a closed loop via twelve inter-qubit connection buses, and can share three qubits (and / or two inter-qubit connection buses) with each of its adjacent neighboring qubit blocks. That is, qubit block 908 can share three qubits (e.g., J8, J7, and J6) with qubit block 910, and qubit block 908 can share three qubits (e.g., J8, K8, and L8) with qubit tile 916.

[0065] In addition, as mentioned above Figure 1 As explained, qubit block 108 can have twelve qubits coupled in a closed loop via twelve inter-qubit interconnect buses, and can share three qubits (and / or two inter-qubit interconnect buses) with each of its adjacent neighboring qubit blocks. That is, qubit block 108 can share three qubits with qubit block 104 (e.g., 146, 178, and 168), qubit block 108 can share three qubits with qubit block 102 (e.g., 168, 170, and 172), and qubit block 108 can share three qubits with qubit block 106 (e.g., 172, 176, and 134). Similarly, as... Figure 9As shown, qubit 916 can have twelve qubits coupled in a closed loop via twelve inter-qubit interconnect buses, and can share three qubits (and / or two inter-qubit interconnect buses) with each of its adjacent adjacent qubit slices. That is, qubit block 916 can share three qubits with qubit block 918 (e.g., J10, I10, and I9), qubit block 916 can share three qubits with qubit block 910 (e.g., I9, I8, and J8), and qubit block 916 can share three qubits with qubit block 908 (e.g., J8, K8, and L8).

[0066] In summary, this could mean that qubit blocks 910, 918, 908, and 916, when assembled, can correspond topologically to qubit blocks 102, 104, 106, and 108, respectively (e.g., qubit block 910 can be topologically similar to qubit block 102, qubit block 918 can be topologically similar to qubit block 104, qubit block 908 can be topologically similar to qubit block 106, and qubit block 916 can be topologically similar to qubit block 108). Since qubit blocks 910, 918, 908, and 916 are topologically similar to qubit blocks 102, 104, 106, and 108, respectively, and since qubit blocks 102, 104, 106, and 108 collectively exhibit a heavy-hexagonal qubit connection topology, qubit blocks 910, 918, 908, and 916 also collectively exhibit a heavy-hexagonal qubit connection topology, although qubit blocks 910, 918, 908, and 916 are not physically shaped, laid out, and / or arranged as hexagons. Furthermore, because the above comparison is performed without loss of generality, it can be shown that although there are no hexagonal qubit blocks, Figure 9 The entire assembled qubit pattern depicted in the image collectively reveals a hexagonal qubit interconnect topology.

[0067] In other words, the above discussion shows that, in various embodiments, multiple duck-shaped (as defined herein) qubit blocks can be combined with multiple cow-shaped (as defined herein) qubit blocks to ultimately form a qubit array exhibiting both a heavy-hexagonal qubit connectivity topology and a linear physical qubit layout. That is, the qubits in qubit array 404 can be physically arranged in columns AN and rows 1-13 (e.g., forming a linear physical layout) rather than physically arranged in a square-combined hexagonal shape (e.g., forming a hexagonal physical layout). However, due to the combination of duck-shaped and cow-shaped qubit blocks, the qubits in qubit array 404 still collectively exhibit a heavy-hexagonal qubit connectivity topology. Because qubit array 404 exhibits a heavy-hexagonal qubit connectivity topology, heavy-hexagonal-based quantum error correction codes can be executed on qubit array 404 as desired. Furthermore, because the quantum dot array 404 is physically constructed according to a linear physical qubit layout, which is the opposite of a hexagonal physical qubit layout, the quantum dot array 404 can have and / or contain less unused / wasted space, less unused / wasted quantum chip real estate, and / or less unused / wasted surface area of ​​the quantum substrate 402. Therefore, the manufacturing cost associated with the quantum structure 900 can be reduced, the resonant frequency of the inter-qubit interconnect bus implemented within the quantum structure 900 can be more easily controlled and / or kept within the desired operating range, and / or the parasitic radio frequency modes of the quantum structure 900 can be reduced.

[0068] In some cases, various generalizable properties of the quantum bit array 404 in the quantum structure 900 can be determined. For example, in different aspects, each qubit block in the quantum bit array 404, whether duck-shaped or cow-shaped, can include twelve qubits coupled in a closed-loop manner via a twelve-qubit interconnect bus. Furthermore, in various cases, adjacent qubit blocks in the quantum bit array 404, whether duck-shaped or cow-shaped, can share three qubits and / or two inter-qubit interconnect buses with each other. Additionally, in various cases, if a given qubit block in the quantum bit array 404 is completely surrounded by adjacent qubit blocks (e.g., if the given qubit block is inside the quantum bit array 404 and not on the edge and / or periphery of the quantum bit array 404), then the given qubit block can be adjacent to six qubit blocks. For example, as... Figure 9As shown, qubit block 912 is completely surrounded by a total of six neighboring qubit blocks (e.g., 906, 904, 910, 918, 920, and 914). Conversely, qubit block 914 can be considered not completely surrounded by neighboring qubit blocks because it is adjacent to fewer than six qubit blocks (e.g., 914 is adjacent only to 906, 912, and 920). Furthermore, in several aspects, if a given qubit block in the qubit array 404 is completely surrounded by neighboring qubit blocks, then that given qubit block can be adjacent to four qubit blocks having a different shape than that given qubit block, and that given qubit block can be adjacent to two qubit blocks having the same shape as that given qubit block. For example, as... Figure 9 As shown, qubit block 912 is completely surrounded by qubit blocks 906, 904, 910, 918, 920, and 914, and qubit block 912 has a cow-shaped shape. As shown, four of these adjacent qubit blocks have a duck-shaped shape (e.g., 906, 904, 918, and 920), and two of these adjacent qubit blocks have a cow-shaped shape (e.g., 910 and 914).

[0069] In various aspects, the assembly of duck-shaped qubit blocks with cow-shaped qubit blocks, as described herein, can be regular and repeatable. That is, in various cases, the assembly of duck-shaped qubit blocks with cow-shaped qubit blocks can be continued, expanded, and / or scaled to any suitable size and / or dimension of the qubit matrix 404. In other words, various embodiments of the present invention can facilitate the fabrication of linear qubit grids of any size exhibiting a heavy-hexagonal qubit connection topology.

[0070] In various cases, once the desired grid size and / or patch size is reached, unused qubits surrounding the quantum dot array 404 (e.g., quantum dot array 404 not included in any quantum dot patch) can be moved and / or removed to clean up and / or improve edge efficiency. In some cases, additional auxiliary qubits can be added around the edges of the quantum dot array 404.

[0071] Notice, Figure 4-9 This is merely illustrative and not restrictive. In various cases, Figure 4-9The exact order in which the various quantum computing components (e.g., qubits, qubit interconnect buses) are fabricated is not necessarily shown. For example, in some cases, the qubits themselves may be formed on the quantum substrate 402 before the qubit interconnect buses are formed on the quantum substrate 402. In other cases, the qubit interconnect buses and / or other quantum circuits may be formed on the quantum substrate 402 before the qubits are formed on the quantum substrate 402. In still other cases, any other suitable fabrication and / or fabrication sequence may be implemented. In all cases, any suitable microfabrication and / or nanofabrication techniques may be implemented to create the quantum substrate 402, the qubits in the quantum dot array 404, and / or the qubit interconnect buses in the quantum dot array 404, which produce the assembled qubit sheets described herein (e.g., deposition, evaporation, etching, photolithography).

[0072] Figure 10 A flowchart of an exemplary non-limiting method 1000 according to one or more embodiments described herein is shown, which can assist in mapping a heavy-hexagonal qubit connection topology to a linear physical qubit layout.

[0073] In various embodiments, action 1002 may include obtaining (e.g., and / or forming) a substrate (e.g., 402) through a quantum fabrication apparatus.

[0074] In various cases, action 1004 may include forming a quantum dot array on a substrate using a quantum fabrication device (e.g., 404). In various cases, the quantum dot array may include one or more first qubit blocks (e.g., 502, 602-606, 902-906, 916-920) having a first shape (e.g., a duck-shaped shape of 200), joined with one or more second qubit blocks (e.g., 702, 802-804, 908-914, 922-926) having a second shape (e.g., a cow-shaped shape of 300). In various aspects, the quantum dot array may exhibit a linear physical layout (e.g., columns AN and / or rows 1-13). In various cases, one or more first qubit blocks joined with one or more second qubit blocks may form a heavy-hexagonal qubit interconnection topology within the linear physical layout of the quantum dot array. In various embodiments, one of the one or more first qubit blocks may have twelve qubits and a twelve-qubit interconnection bus. Similarly, in various cases, one of the one or more second qubit blocks can have twelve qubits and twelve inter-qubit interconnect buses. In various cases, adjacent qubit blocks in a heavy-hexagonal qubit interconnect topology can share three qubits and / or two inter-qubit interconnect buses. In various cases, a qubit block in a heavy-hexagonal qubit interconnect topology can be adjacent to four qubit blocks with a different shape than the qubit block, and can be adjacent to two qubit blocks with the same shape as the qubit block.

[0075] The various embodiments discussed above teach how duck-shaped and cow-shaped qubit maps can be combined to form a linear physical qubit matrix exhibiting a heavy-hexagonal qubit connectivity topology. However, in various cases, other shapes can be implemented to form a linear physical qubit matrix exhibiting a heavy-hexagonal qubit connectivity topology. For example, in several aspects, if two or more sets of qubit maps of different shapes are physically shaped such that each qubit map is in a closed loop of interconnected qubits, such that adjacent qubit maps share three qubits and two-qubit connections, and / or such that a qubit map can have up to six adjacent qubit maps, then two or more sets of qubit maps of different shapes can be combined to form a linear physical qubit matrix exhibiting a heavy-hexagonal qubit connectivity topology.

[0076] In various implementations, a heavy-hexagonal qubit grid can be a grid of qubits consisting of multiple hexagons, with qubits located at the vertices of each hexagon, and additional qubits located on each line segment between the vertices of each hexagon. In various cases, quantum error-correcting codes can be used to improve the fidelity of quantum computers. In various instances, the heavy-hexagonal code can be a quantum error correction code designed to operate on a topology in which the qubits exhibit a heavy-hexagonal interconnected topology. In circuit quantum electrodynamics, quantum chips (e.g., quantum computing chips and / or quantum processing chips) with a heavy-hexagonal qubit interconnected topology can be used to implement quantum error-correcting codes for error correction. Such a heavy-hexagonal qubit interconnected topology can be facilitated by a heavy-hexagonal physical qubit layout. However, a heavy-hexagonal physical qubit layout can be spatially inefficient, potentially leading to increased manufacturing costs, wasted quantum chip real estate, transmission of undesirable line resonant frequencies, and / or the presence of parasitic radio frequency modes.

[0077] Various embodiments of the present invention can address one or more of these technical problems by providing a linear physical qubit layout that is denser and / or spatially more efficient than a heavy-hexagonal physical qubit layout, while still exhibiting a heavy-hexagonal qubit connectivity topology. In various cases, qubits can be placed on a linear (e.g., square, rectangular, orthogonal) grid on a quantum substrate, and two geometrical primitive qubit tiles, each representing a heavy-hexagonal unit (e.g., two basic and / or non-reducible qubit tiles with different geometries), can be joined, tiled, and / or interlocked as described herein. By joining, tiling, and / or interlocking these geometrical primitive qubit tiles, linear physical qubit grids of any suitable size and / or dimension exhibiting a heavy-hexagonal qubit connectivity topology can be created. Once the desired size of the linear grid is arranged using tiles, qubits around the edges, perimeters, and / or peripheries can be moved and / or removed to clean up edge efficiency. In some cases, additional auxiliary qubits can be added around the edges, perimeters, and / or peripheries. In other words, dangling qubits and / or buses at the edges of tiles can be moved to unused adjacent areas to further compress the layout. In various cases, linear physical qubit layouts can be denser and / or more regular than hexagonal physical qubit layouts, which can lead to performance benefits and / or reduced costs associated with quantum computing systems.

[0078] To provide additional context for the various embodiments described herein Figure 11The following discussion is intended to provide a general description of a suitable computing environment 1100 in which various embodiments of the embodiments described herein may be implemented. Although the embodiments have been described above in the general context of computer-executable instructions that can run on one or more computers, those skilled in the art will recognize that the embodiments may also be implemented in combination with other program modules and / or as a combination of hardware and software.

[0079] Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks or implement specific abstract data types. Furthermore, those skilled in the art will understand that the methods of this invention can be implemented using other computer system configurations, including single-processor or multi-processor computer systems, microcomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, and personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, each of which can be operatively coupled to one or more associated devices.

[0080] The embodiments illustrated herein can also be practiced in a distributed computing environment, where certain tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules can reside in both local and remote memory storage devices.

[0081] Computing devices typically include a variety of media, which may include computer-readable storage media, machine-readable storage media, and / or communication media, these two terms being used herein to distinguish themselves from each other. A computer-readable storage medium or a machine-readable storage medium can be any available storage medium accessible by a computer, and includes volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, a computer-readable storage medium or a machine-readable storage medium may be implemented in conjunction with any method or technique used for storing information such as computer-readable or machine-readable instructions, program modules, structured data, or unstructured data.

[0082] Computer-readable storage media may include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, optical disc read-only memory (CDROM), digital versatile disc (DVD), Blu-ray disc (BD) or other optical disc storage, magnetic tape cassettes, magnetic tape, disk storage or other magnetic storage devices, solid-state drives or other solid-state storage devices, or other tangible and / or non-transitory media that can be used to store desired information. In this regard, the terms “tangible” or “non-transitory” as used herein with respect to storage devices, memories, or computer-readable media shall be understood to exclude only the propagation of transient signals themselves as a modifier, and shall not waive the rights to all standard storage devices, memories, or computer-readable media that do not only propagate transient signals themselves.

[0083] Computer-readable storage media can be accessed by one or more local or remote computing devices, for example via access requests, queries or other data retrieval protocols, in order to perform various operations on the information stored on the media.

[0084] Communication media typically embody computer-readable instructions, data structures, program modules, or other structured or unstructured data in the form of data signals such as modulated data signals, such as carrier waves or other transmission mechanisms, and include any information transmission or delivery medium. The term "modulated data signal" or multiple signals refers to signals whose one or more characteristics are set or altered in a manner that encodes information in one or more signals. By way of example and not limitation, communication media include wired media, such as wired networks or direct-wire connections, and wireless media, such as acoustic, RF, infrared, and other wireless media.

[0085] Refer again Figure 11 An example environment 1100 for implementing various embodiments of the aspects described herein includes a computer 1102, which includes a processing unit 1104, system memory 1106, and a system bus 1108. The system bus 1108 couples system components, including but not limited to system memory 1106, to the processing unit 1104. The processing unit 1104 can be any of a variety of commercially available processors. Dual-microprocessor and other multiprocessor architectures may also be used as the processing unit 1104.

[0086] System bus 1108 can be any of several types of bus architectures, which can also interconnect to memory buses (with or without memory controllers), peripheral buses, and local buses using any of the various commercially available bus architectures. System memory 1106 includes ROM 1110 and RAM 1112. The Basic Input / Output System (BIOS) can be stored in non-volatile memory such as ROM, erasable programmable read-only memory (EPROM), EEPROM, etc., where the BIOS contains basic routines that help pass information between components within computer 1102, such as during startup. RAM 1112 can also include high-speed RAM such as static RAM for caching data.

[0087] Computer 1102 also includes an internal hard disk drive (HDD) 1114 (e.g., EIDE, SATA), one or more external storage devices 1116 (e.g., floppy disk drive (FDD) 1116, memory stick or flash drive reader, memory card reader, etc.), and a drive 1120, such as a solid-state drive or optical disc drive, which can read from or write to a disk 1122 such as a CD-ROM, DVD, BD, etc. Alternatively, if a solid-state drive is involved, disk 1122 is not included, unless it is separate. Although the internal HDD 1114 is shown as being located within computer 1102, the internal HDD 1114 can also be configured for external use in a suitable chassis (not shown). Additionally, although not shown in environment 1100, a solid-state drive (SSD) may be used in addition to or in place of HDD 1114. HDD 1114, external storage device 1116, and drive 1120 can be connected to system bus 1108 via HDD interface 1124, external storage interface 1126, and drive interface 1128, respectively. Interface 1124 for the external drive implementation may include at least one or both of Universal Serial Bus (USB) and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technologies. Other external drive connection technologies are within the scope of the embodiments described herein.

[0088] The drive and its associated computer-readable storage medium provide non-volatile storage of data, data structures, computer-executable instructions, etc. For computer 1102, the drive and storage medium accommodate storage of any data in a suitable digital format. Although the above description of computer-readable storage media refers to corresponding types of storage devices, those skilled in the art will understand that other types of computer-readable storage media, whether currently existing or developed in the future, may also be used in the example operating environment, and furthermore, any such storage medium may contain computer-executable instructions for performing the methods described herein.

[0089] Multiple program modules may be stored in the drive and RAM 1112, including an operating system 1130, one or more application programs 1132, other program modules 1134, and program data 1136. All or part of the operating system, application programs, modules, and / or data may also be cached in RAM 1112. The systems and methods described herein can be implemented using various commercially available operating systems or combinations of operating systems.

[0090] Computer 1102 may optionally include emulation technology. For example, a system hypervisor (not shown) or other intermediary may emulate a hardware environment for operating system 1130, and the emulated hardware may optionally be different from that of the operating system. Figure 11The hardware shown, in such an embodiment, may include an operating system 1130 that can comprise one of a plurality of virtual machines (VMs) hosted on computer 1102. Furthermore, the operating system 1130 may provide a runtime environment, such as the Java Runtime Environment (JVM) or the .NET Framework, for application 1132. A runtime environment is a consistent execution environment that allows application 1132 to run on any operating system that includes a runtime environment. Similarly, the operating system 1130 may support containers, and application 1132 may be in the form of a container, which is a lightweight, standalone, executable software package that includes, for example, code, runtime, system tools, system libraries, and setup for the application.

[0091] Furthermore, computer 1102 can be enabled using a security module, such as a Trusted Processing Module (TPM). For example, with a TPM, the boot component hashes the next boot component at boot time and waits for the result to match the security value before loading the next boot component. This process can occur at any layer of the computer 1102's code execution stack, for example, at the application execution level or the operating system (OS) kernel level, thus achieving security at any code execution level.

[0092] Users can input commands and information into computer 1102 through one or more wired / wireless input devices, such as keyboard 1138, touchscreen 1140, and directional devices such as mouse 1142. Other input devices (not shown) may include microphones, infrared (IR) remote controls, radio frequency (RF) remote controls, or other remote controls, joysticks, virtual reality controllers and / or virtual reality headsets, gaming pads, pens, image input devices (e.g., cameras), gesture sensor input devices, visual motion sensor input devices, emotion or face detection devices, biometric input devices (e.g., fingerprint or iris scanners), etc. These and other input devices are typically connected to processing unit 1104 via input device interface 1144, which can be coupled to system bus 1108, but may also be connected via other interfaces such as parallel ports, IEEE 1394 serial ports, gaming ports, USB ports, IR interfaces, etc. Interfaces, etc.

[0093] Monitor 1146 or other types of display devices may also be connected to system bus 1108 via an interface such as video adapter 1148. In addition to monitor 1146, computers typically include other peripheral output devices (not shown), such as speakers, printers, etc.

[0094] Computer 1102 can operate in a networked environment using logical connections to one or more remote computers (such as remote computer 1150) via wired and / or wireless communications. Remote computer 1150 can be a workstation, server computer, router, personal computer, laptop computer, microprocessor-based entertainment device, peer-to-peer device, or other common network node, and typically includes many or all of the elements described relative to computer 1102, but for simplicity only memory / storage device 1152 is shown. The depicted logical connections include wired / wireless connections to a local area network (LAN) 1154 and / or a larger network, such as a wide area network (WAN) 1156. Such LAN and WAN networking environments are common in offices and companies and facilitate enterprise-wide computer networks such as intranets, all of which can be connected to global communication networks such as the Internet.

[0095] When used in a LAN network environment, computer 1102 can be connected to local area network 1154 via a wired and / or wireless communication network interface or adapter 1158. Adapter 1158 facilitates wired or wireless communication with LAN 1154, which may also include a wireless access point (AP) configured thereon for communicating with adapter 1158 in wireless mode.

[0096] When used in a WAN network environment, computer 1102 may include modem 1160, or may be connected to a communication server on WAN 1156 via other means, to establish communication over WAN 1156, such as over the Internet. Modem 1160, which may be built-in or external and wired or wireless, may be connected to system bus 1108 via input device interface 1144. In a networked environment, program modules described relative to computer 1102 or parts thereof may be stored in remote memory / storage device 1152. It is understood that the network connection shown is illustrative, and other means of establishing communication links between computers may be used.

[0097] When used in a LAN or WAN networking environment, computer 1102 can access cloud storage systems or other network-based storage systems as a supplement to or replacement for external storage device 1116 as described above, such as, but not limited to, network virtual machines providing storage or processing of one or more aspects of information. Typically, the connection between computer 1102 and the cloud storage system can be established, for example, on LAN 1154 or WAN 1156 via adapter 1158 or modem 1160, respectively. When computer 1102 is connected to the associated cloud storage system, external storage interface 1126 can, with the aid of adapter 1158 and / or modem 1160, manage the storage provided by the cloud storage system as if it were other types of external storage. For example, external storage interface 1126 can be configured to provide access to cloud storage sources as if these sources were physically connected to computer 1102.

[0098] Computer 1102 may be operable to communicate with any wireless device or entity operatively configured for wireless communication, such as a printer, scanner, desktop and / or laptop computer, portable data assistant, communications satellite, any device or location associated with a wirelessly detectable tag (e.g., telephone booth, newsstand, store shelf, etc.), and telephone. This may include Wi-Fi and Technology. Therefore, communication can be a predefined structure like a regular network, or simply temporary communication between at least two devices.

[0099] This invention can be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures with instructions recorded thereon, and any suitable combinations of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

[0100] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or via a network, such as the Internet, a local area network (LAN), a wide area network (WAN), and / or a wireless network, to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the respective computing / processing device. Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(e.g., Smalltalk, C++, etc.) and procedural programming languages ​​(e.g., the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing state information from the computer-readable program instructions.

[0101] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of manufacture comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. The computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational actions to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0102] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a non-consecutive order as shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0103] Although the subject matter has been described above in the general context of computer-executable instructions of a computer program product running on one or more computers, those skilled in the art will recognize that this disclosure can also be implemented in conjunction with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will understand that the computer implementation methods of the present invention can be implemented using other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The aspects shown can also be practiced in a distributed computing environment in which tasks are performed by remote processing devices linked via a communication network. However, some, if not all, aspects of this disclosure can be practiced on a standalone computer. In a distributed computing environment, program modules can reside in both local and remote memory storage devices.

[0104] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities related to an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. For illustration, an application running on a server and a server itself can both be components. One or more components may reside within a process and / or a thread of execution, and components may reside on a single computer and / or be distributed across two or more computers. In another example, a corresponding component may be executable from various computer-readable media on which various data structures are stored. These components may communicate via local and / or remote processes, for example, based on signals having one or more data packets (e.g., data from a component via which it interacts with a local system, another component in a distributed system, and / or with other systems via a network such as the Internet). As another example, a component can be a device having specific functions provided by mechanical parts operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In this case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As yet another example, a component can be a device that provides specific functions through electronic components rather than mechanical parts, wherein the electronic components can include a processor or other device to execute software or firmware that at least partially endows the electronic components with the functions. In one aspect, the component can be emulated via a virtual machine, for example within a cloud computing system.

[0105] Furthermore, the term "or" is intended to indicate an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to indicate any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing instances. Furthermore, unless otherwise specified or clear from the context to refer to the singular form, the articles "a" and "an" as used in this specification and figures should generally be interpreted as meaning "one or more". As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, instance, or illustration. To avoid ambiguity, the subject matter disclosed herein is not limited to these examples. Moreover, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor does it exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0106] As used herein, the term "processor" can refer to virtually any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can employ nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user equipment. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as “storage,” “memory,” “database,” “database,” and virtually any other information storage component relating to the operation and function of a component are used to refer to a “memory component,” an entity embodied in memory, or a component that includes memory. It should be understood that the memory and / or memory components described herein may be volatile memory or non-volatile memory, or may include both. By way of illustration and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may be used as external cache memory. By way of illustration and not limitation, RAM may be available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus, etc. RAM (DRRAM), Direct Rambus Dynamic RAM (DRDRAM), and Rambus Dynamic RAM (RDRAM).

[0107] The above description includes only examples of systems and computer-implemented methods. It is certainly impossible to describe every conceivable combination of components or computer-implemented methods in order to describe this disclosure; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, with regard to the use of the terms "comprising," "having," "possessing," etc., in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a similar manner to how the term "comprising" is interpreted when used as a transitional word in the claims.

[0108] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A device for a qubit interconnect topology, comprising: A quantum dot array (404) on a substrate, wherein the quantum dot array presents a linear physical layout, the quantum dot array comprising one or more first quantum bit blocks (502, 602-606, 902-906, 916-920) having a first shape, the first quantum bit blocks being combined with one or more second quantum bit blocks (702, 802-804, 908-914, 922-926) having a second shape; Wherein, the qubit block (200) in the one or more first qubit blocks (502, 602-606, 902-906, 916-920) includes a first qubit (202), a second qubit (204), a third qubit (206), a fourth qubit (208), a fifth qubit (210), a sixth qubit (212), a seventh qubit (214), an eighth qubit (216), a ninth qubit (218), a tenth qubit (220), an eleventh qubit (222), and a twelfth qubit (224), wherein the first qubit (202) is coupled to the second qubit (204) via an inter-qubit connection bus, the second A qubit (204) is coupled to the third qubit (206) via an inter-qubit bus. The third qubit (206) is coupled to the fourth qubit (208) via an inter-qubit bus. The fourth qubit (208) is coupled to the fifth qubit (210) via an inter-qubit bus. The fifth qubit (210) is coupled to the sixth qubit (212) via an inter-qubit bus. The sixth qubit (212) is coupled to the seventh qubit (214) via an inter-qubit bus. The seventh qubit (214) is coupled to the eighth qubit (216) via an inter-qubit bus. The eighth qubit (216) is coupled to the... An inter-qubit connection bus is coupled to the ninth qubit (218), the ninth qubit (218) is coupled to the tenth qubit (220) via the inter-qubit connection bus, the tenth qubit (220) is coupled to the eleventh qubit (222) via the inter-qubit connection bus, the eleventh qubit (222) is coupled to the twelfth qubit (224) via the inter-qubit connection bus, and the twelfth qubit (224) is coupled to the first qubit (202) via the inter-qubit connection bus; wherein, the qubits (202-224) of the qubit block (200) are physically placed and / or positioned according to a linear grid, wherein the linear grid... The grid is defined by columns (226-234) and rows (236-240), wherein the first qubit (202), the twelfth qubit (224), and the eleventh qubit (222) are physically positioned along the first column (226); the second qubit (204), the ninth qubit (218), and the tenth qubit (220) are physically positioned along the second column (228); the third qubit (206) and the eighth qubit (216) are physically positioned along the third column (230); and the fourth qubit (208), the fifth qubit (210), and the seventh qubit (214) are physically positioned along the fourth column (232).Furthermore, the sixth qubit (212) is physically positioned along the fifth column (234), wherein the first qubit (202), the second qubit (204), the third qubit (206), and the fourth qubit (208) are physically positioned along the first row (236); the twelfth qubit (224), the ninth qubit (218), the eighth qubit (216), the fifth qubit (210), and the sixth qubit (212) are physically positioned along the second row (238); and the eleventh qubit (222), the tenth qubit (220), and the seventh qubit (214) are physically positioned along the third row (240); The qubit block (300) in the one or more second qubit blocks (702, 802-804, 908-914, 922-926) includes a first qubit (302), a second qubit (304), a third qubit (306), a fourth qubit (308), a fifth qubit (310), a sixth qubit (312), a seventh qubit (314), an eighth qubit (316), a ninth qubit (318), a tenth qubit (320), an eleventh qubit (322), and a twelfth qubit (324). The first qubit (302) is coupled to the second qubit (304) via an inter-qubit connection bus, and the second qubit (304) is coupled to the third qubit (322) via an inter-qubit connection bus. 06), the third qubit (306) is coupled to the fourth qubit (308) via an inter-qubit connection bus, the fourth qubit (308) is coupled to the fifth qubit (310) via an inter-qubit connection bus, the fifth qubit (310) is coupled to the sixth qubit (312) via an inter-qubit connection bus, the sixth qubit (312) is coupled to the seventh qubit (314) via an inter-qubit connection bus, the seventh qubit (314) is coupled to the eighth qubit (316) via an inter-qubit connection bus, and the eighth qubit (316) is coupled to the ninth qubit (318) via an inter-qubit connection bus. The ninth qubit (318) is coupled to the tenth qubit (320) via an inter-qubit connection bus, the tenth qubit (320) is coupled to the eleventh qubit (322) via an inter-qubit connection bus, the eleventh qubit (322) is coupled to the twelfth qubit (324) via an inter-qubit connection bus, and the twelfth qubit (324) is coupled to the first qubit (302) via an inter-qubit connection bus, wherein the qubits (302-324) of the qubit patch (300) are physically positioned and / or arranged according to a rectangular grid. The rectangular grid is defined by columns (326-332) and rows (334-340), and the first qubit (302), the twelfth qubit (324), and the eleventh qubit (322) are physically positioned along the first column (326); the second qubit (304) and the tenth qubit (320) are physically positioned along the second column (328); the fourth qubit (308), the third qubit (306), the eighth qubit (316), and the ninth qubit (318) are physically positioned along the third column (330).Furthermore, the fifth qubit (310), the sixth qubit (312), and the seventh qubit (314) are physically positioned along the fourth column (332), wherein the fourth qubit (308) and the fifth qubit (310) are physically positioned along the first row (334); the first qubit (302), the third qubit (306), and the sixth qubit (312) are physically positioned along the second row (336); the twelfth qubit (324), the second qubit (304), the eighth qubit (316), and the seventh qubit (314) are physically positioned along the third row (338); and the eleventh qubit (322), the tenth qubit (320), and the ninth qubit (318) are physically positioned along the fourth row (340). Furthermore, the one or more first qubit blocks, which are combined with the one or more second qubit blocks, form a heavy-hexagonal qubit connection topology in the linear physical layout of the qubit matrix.

2. The device according to claim 1, wherein adjacent qubit blocks in the heavy-hexagonal qubit connection topology share three qubits.

3. The device of claim 2, wherein the qubit block in the heavy-hexagonal qubit connection topology is adjacent to four qubit blocks having a different shape from the qubit block, and is adjacent to two qubit blocks having the same shape as the qubit block.

4. A method for qubit interconnect topology, comprising: A quantum dot array (404) is formed on a substrate, wherein the quantum dot array has a linear physical layout, the quantum dot array includes one or more first quantum bit blocks (502, 602-606, 902-906, 916-920) having a first shape, and the first quantum bit blocks are combined with one or more second quantum bit blocks (702, 802-804, 908-914, 922-926) having a second shape; Wherein, the qubit block (200) in the one or more first qubit blocks (502, 602-606, 902-906, 916-920) includes a first qubit (202), a second qubit (204), a third qubit (206), a fourth qubit (208), a fifth qubit (210), a sixth qubit (212), a seventh qubit (214), an eighth qubit (216), a ninth qubit (218), a tenth qubit (220), an eleventh qubit (222), and a twelfth qubit (224), wherein the first qubit (202) is coupled to the second qubit (204) via an inter-qubit connection bus, the second A qubit (204) is coupled to the third qubit (206) via an inter-qubit bus. The third qubit (206) is coupled to the fourth qubit (208) via an inter-qubit bus. The fourth qubit (208) is coupled to the fifth qubit (210) via an inter-qubit bus. The fifth qubit (210) is coupled to the sixth qubit (212) via an inter-qubit bus. The sixth qubit (212) is coupled to the seventh qubit (214) via an inter-qubit bus. The seventh qubit (214) is coupled to the eighth qubit (216) via an inter-qubit bus. The eighth qubit (216) is coupled to the... An inter-qubit connection bus is coupled to the ninth qubit (218), the ninth qubit (218) is coupled to the tenth qubit (220) via the inter-qubit connection bus, the tenth qubit (220) is coupled to the eleventh qubit (222) via the inter-qubit connection bus, the eleventh qubit (222) is coupled to the twelfth qubit (224) via the inter-qubit connection bus, and the twelfth qubit (224) is coupled to the first qubit (202) via the inter-qubit connection bus; wherein, the qubits (202-224) of the qubit block (200) are physically placed and / or positioned according to a linear grid, wherein the linear grid... The grid is defined by columns (226-234) and rows (236-240), wherein the first qubit (202), the twelfth qubit (224), and the eleventh qubit (222) are physically positioned along the first column (226); the second qubit (204), the ninth qubit (218), and the tenth qubit (220) are physically positioned along the second column (228); the third qubit (206) and the eighth qubit (216) are physically positioned along the third column (230); and the fourth qubit (208), the fifth qubit (210), and the seventh qubit (214) are physically positioned along the fourth column (232).Furthermore, the sixth qubit (212) is physically positioned along the fifth column (234), wherein the first qubit (202), the second qubit (204), the third qubit (206), and the fourth qubit (208) are physically positioned along the first row (236); the twelfth qubit (224), the ninth qubit (218), the eighth qubit (216), the fifth qubit (210), and the sixth qubit (212) are physically positioned along the second row (238); and the eleventh qubit (222), the tenth qubit (220), and the seventh qubit (214) are physically positioned along the third row (240); The qubit block (300) in the one or more second qubit blocks (702, 802-804, 908-914, 922-926) includes a first qubit (302), a second qubit (304), a third qubit (306), a fourth qubit (308), a fifth qubit (310), a sixth qubit (312), a seventh qubit (314), an eighth qubit (316), a ninth qubit (318), a tenth qubit (320), an eleventh qubit (322), and a twelfth qubit (324). The first qubit (302) is coupled to the second qubit (304) via an inter-qubit connection bus, and the second qubit (304) is connected via an inter-qubit connection bus. The bus is coupled to the third qubit (306), the third qubit (306) is coupled to the fourth qubit (308) via the inter-qubit connection bus, the fourth qubit (308) is coupled to the fifth qubit (310) via the inter-qubit connection bus, the fifth qubit (310) is coupled to the sixth qubit (312) via the inter-qubit connection bus, the sixth qubit (312) is coupled to the seventh qubit (314) via the inter-qubit connection bus, the seventh qubit (314) is coupled to the eighth qubit (316) via the inter-qubit connection bus, and the eighth qubit (316) is coupled to the fifth qubit (310) via the inter-qubit connection bus. 16) Coupled to the ninth qubit (318) via an inter-qubit connection bus, the ninth qubit (318) is coupled to the tenth qubit (320) via an inter-qubit connection bus, the tenth qubit (320) is coupled to the eleventh qubit (322) via an inter-qubit connection bus, the eleventh qubit (322) is coupled to the twelfth qubit (324) via an inter-qubit connection bus, and the twelfth qubit (324) is coupled to the first qubit (302) via an inter-qubit connection bus, wherein the qubits (302-324) of the qubit block (300) are arranged according to... A rectangular grid is used for physical positioning and / or placement, wherein the rectangular grid is defined by columns (326-332) and rows (334-340), and wherein the first qubit (302), the twelfth qubit (324), and the eleventh qubit (322) are physically positioned along the first column (326); the second qubit (304) and the tenth qubit (320) are physically positioned along the second column (328); and the fourth qubit (308), the third qubit (306), the eighth qubit (316), and the ninth qubit (318) are physically positioned along the third column (330).Furthermore, the fifth qubit (310), the sixth qubit (312), and the seventh qubit (314) are physically positioned along the fourth column (332), wherein the fourth qubit (308) and the fifth qubit (310) are physically positioned along the first row (334); the first qubit (302), the third qubit (306), and the sixth qubit (312) are physically positioned along the second row (336); the twelfth qubit (324), the second qubit (304), the eighth qubit (316), and the seventh qubit (314) are physically positioned along the third row (338); and the eleventh qubit (322), the tenth qubit (320), and the ninth qubit (318) are physically positioned along the fourth row (340). Furthermore, the one or more first qubit blocks, which are assembled with the one or more second qubit tiles, form a heavy-hexagonal qubit connection topology in the linear physical layout of the qubit dot array.

5. The method of claim 4, wherein adjacent qubit blocks in the heavy-hexagonal qubit connection topology share three qubits.

6. The method of claim 5, wherein the qubit block in the heavy-hexagonal qubit connection topology is adjacent to four qubit blocks having a different shape from the qubit block, and is adjacent to two qubit blocks having the same shape as the qubit block.

7. An apparatus for a qubit interconnect topology, comprising: A qubit array on a substrate, the qubit array exhibiting a linear physical qubit arrangement, and the qubit array comprising one or more first qubit blocks having a first shape, the one or more first qubit blocks being combined with one or more second qubit blocks having a second shape; Wherein, the qubit block (200) in the one or more first qubit blocks (502, 602-606, 902-906, 916-920) includes a first qubit (202), a second qubit (204), a third qubit (206), a fourth qubit (208), a fifth qubit (210), a sixth qubit (212), a seventh qubit (214), an eighth qubit (216), a ninth qubit (218), a tenth qubit (220), an eleventh qubit (222), and a twelfth qubit (224), wherein the first qubit (202) is coupled to the second qubit (204) via an inter-qubit connection bus, the second A qubit (204) is coupled to the third qubit (206) via an inter-qubit bus. The third qubit (206) is coupled to the fourth qubit (208) via an inter-qubit bus. The fourth qubit (208) is coupled to the fifth qubit (210) via an inter-qubit bus. The fifth qubit (210) is coupled to the sixth qubit (212) via an inter-qubit bus. The sixth qubit (212) is coupled to the seventh qubit (214) via an inter-qubit bus. The seventh qubit (214) is coupled to the eighth qubit (216) via an inter-qubit bus. The eighth qubit (216) is coupled to the... An inter-qubit connection bus is coupled to the ninth qubit (218), the ninth qubit (218) is coupled to the tenth qubit (220) via the inter-qubit connection bus, the tenth qubit (220) is coupled to the eleventh qubit (222) via the inter-qubit connection bus, the eleventh qubit (222) is coupled to the twelfth qubit (224) via the inter-qubit connection bus, and the twelfth qubit (224) is coupled to the first qubit (202) via the inter-qubit connection bus; wherein, the qubits (202-224) of the qubit block (200) are physically placed and / or positioned according to a linear grid, wherein the linear grid... The grid is defined by columns (226-234) and rows (236-240), wherein the first qubit (202), the twelfth qubit (224), and the eleventh qubit (222) are physically positioned along the first column (226); the second qubit (204), the ninth qubit (218), and the tenth qubit (220) are physically positioned along the second column (228); the third qubit (206) and the eighth qubit (216) are physically positioned along the third column (230); and the fourth qubit (208), the fifth qubit (210), and the seventh qubit (214) are physically positioned along the fourth column (232).Furthermore, the sixth qubit (212) is physically positioned along the fifth column (234), wherein the first qubit (202), the second qubit (204), the third qubit (206), and the fourth qubit (208) are physically positioned along the first row (236); the twelfth qubit (224), the ninth qubit (218), the eighth qubit (216), the fifth qubit (210), and the sixth qubit (212) are physically positioned along the second row (238); and the eleventh qubit (222), the tenth qubit (220), and the seventh qubit (214) are physically positioned along the third row (240); The qubit block (300) in the one or more second qubit blocks (702, 802-804, 908-914, 922-926) includes a first qubit (302), a second qubit (304), a third qubit (306), a fourth qubit (308), a fifth qubit (310), a sixth qubit (312), a seventh qubit (314), an eighth qubit (316), a ninth qubit (318), a tenth qubit (320), an eleventh qubit (322), and a twelfth qubit (324). The first qubit (302) is coupled to the second qubit (304) via an inter-qubit connection bus, and the second qubit (304) is coupled to the third qubit (322) via an inter-qubit connection bus. 06), the third qubit (306) is coupled to the fourth qubit (308) via an inter-qubit connection bus, the fourth qubit (308) is coupled to the fifth qubit (310) via an inter-qubit connection bus, the fifth qubit (310) is coupled to the sixth qubit (312) via an inter-qubit connection bus, the sixth qubit (312) is coupled to the seventh qubit (314) via an inter-qubit connection bus, the seventh qubit (314) is coupled to the eighth qubit (316) via an inter-qubit connection bus, and the eighth qubit (316) is coupled to the ninth qubit (318) via an inter-qubit connection bus. The ninth qubit (318) is coupled to the tenth qubit (320) via an inter-qubit connection bus, the tenth qubit (320) is coupled to the eleventh qubit (322) via an inter-qubit connection bus, the eleventh qubit (322) is coupled to the twelfth qubit (324) via an inter-qubit connection bus, and the twelfth qubit (324) is coupled to the first qubit (302) via an inter-qubit connection bus, wherein the qubits (302-324) of the qubit patch (300) are physically positioned and / or arranged according to a rectangular grid. The rectangular grid is defined by columns (326-332) and rows (334-340), and the first qubit (302), the twelfth qubit (324), and the eleventh qubit (322) are physically positioned along the first column (326); the second qubit (304) and the tenth qubit (320) are physically positioned along the second column (328); the fourth qubit (308), the third qubit (306), the eighth qubit (316), and the ninth qubit (318) are physically positioned along the third column (330).Furthermore, the fifth qubit (310), the sixth qubit (312), and the seventh qubit (314) are physically positioned along the fourth column (332), wherein the fourth qubit (308) and the fifth qubit (310) are physically positioned along the first row (334); the first qubit (302), the third qubit (306), and the sixth qubit (312) are physically positioned along the second row (336); the twelfth qubit (324), the second qubit (304), the eighth qubit (316), and the seventh qubit (314) are physically positioned along the third row (338); and the eleventh qubit (322), the tenth qubit (320), and the ninth qubit (318) are physically positioned along the fourth row (340). Furthermore, the one or more first qubit blocks, which are combined with the one or more second qubit blocks, form a heavy-hexagonal qubit connection topology in the linear physical qubit arrangement of the qubit array.

8. The apparatus according to claim 7, wherein, The qubit block (200) in the one or more first qubit blocks (502, 602-606, 902-906, 916-920) further includes: a first coupling between the first qubit (202) and the second qubit (204), a second coupling between the second qubit (204) and the third qubit (206), a third coupling between the third qubit (206) and the fourth qubit (208), and a third coupling between the fourth qubit (208) and the third qubit (202). The fourth coupling between the five qubits (210), the fifth coupling between the fifth qubit (210) and the sixth qubit (212), the sixth coupling between the sixth qubit (212) and the seventh qubit (214), the seventh coupling between the seventh qubit (214) and the eighth qubit (216), the eighth coupling between the eighth qubit (216) and the ninth qubit (218), and the coupling between the ninth qubit (218) and the tenth qubit (220). The ninth coupling between the tenth qubit (220) and the eleventh qubit (222), the eleventh coupling between the eleventh qubit (222) and the twelfth qubit (224), and the twelfth coupling between the twelfth qubit (224) and the first qubit (202); wherein the first coupling is linear with the second coupling, wherein the second coupling is linear with the third coupling, wherein the third coupling is orthogonal with the fourth coupling, wherein the fourth coupling is orthogonal with the fifth coupling, wherein the fifth coupling and the sixth coupling are arranged at an acute angle, wherein the sixth coupling is orthogonal with the seventh coupling, wherein the seventh coupling and the eighth coupling are arranged at an obtuse angle, wherein the eighth coupling is orthogonal with the ninth coupling, wherein the ninth coupling is orthogonal with the tenth coupling, wherein the tenth coupling is orthogonal with the eleventh coupling, wherein the eleventh coupling and the twelfth coupling are linear, and wherein the twelfth coupling is orthogonal with the first coupling.

9. The apparatus according to claim 8, wherein, The one or more second qubit blocks (702, 802-804, 908-914, ... The qubit block (300) in (922-926) further includes: a first coupling between the first qubit (302) and the second qubit (304), a second coupling between the second qubit (304) and the third qubit (306), a third coupling between the third qubit (306) and the fourth qubit (308), a fifth coupling between the fourth qubit (308) and the fifth qubit (310), a sixth coupling between the sixth qubit (312) and the seventh qubit (314), a seventh coupling between the seventh qubit (314) and the eighth qubit (316), an eighth coupling between the eighth qubit (316) and the ninth qubit (318), a ninth coupling between the ninth qubit (318) and the tenth qubit (320), and a coupling between the tenth qubit (320) and the eleventh qubit (320). 2) The tenth coupling between the eleventh qubit (322) and the eleventh qubit (324), and the twelfth coupling between the twelfth qubit (324) and the first qubit (302); wherein the first coupling is orthogonal to the second coupling, wherein the second coupling and the third coupling are arranged at an obtuse angle, wherein the third coupling is orthogonal to the fourth coupling, wherein the fourth coupling is orthogonal to the fifth coupling, wherein the fifth coupling is linearly related to the sixth coupling, wherein the sixth coupling is orthogonal to the seventh coupling, wherein the seventh coupling is orthogonal to the eighth coupling, wherein the eighth coupling is orthogonal to the ninth coupling, wherein the ninth coupling is linearly related to the tenth coupling, wherein the tenth coupling is orthogonal to the eleventh coupling, wherein the eleventh coupling and the twelfth coupling are substantially linearly related, and wherein the twelfth coupling is arranged at an acute angle to the first coupling.

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