Display panel, display device

Abstract

A display panel and a display device, wherein the display panel includes a pixel driving circuit, and the pixel driving circuit includes a driving transistor (T3), a first transistor (T1), and a second transistor (T2). The display panel further includes: a substrate, a first conductive layer, a third conductive layer, and a first connection portion (41). The first conductive layer includes a first conductive portion (11), and the first conductive portion (11) is used to form the gate of the driving transistor (T3). The third conductive layer includes a first gate line (3Re1) and a second gate line (3G1). The orthographic projection of the first gate line (3Re1) on the substrate and the orthographic projection of the second gate line (3G1) on the substrate both extend along a first direction (X), and the orthographic projection of the first conductive portion (11) on the substrate is located between the orthographic projection of the first gate line (3Re1) on the substrate and the orthographic projection of the second gate line (3G1) on the substrate. The first connection portion (41) is connected to the first conductive portion (11) through a via (H1) and connects the first pole of the first transistor (T1) and the first pole of the second transistor (T2). Wherein, the orthographic projection of the first connection portion (41) on the substrate is located between the orthographic projection of the first gate line (3Re1) on the substrate and the orthographic projection of the second gate line (3G1) on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] In the related art, a pixel driving circuit can be formed by using low temperature polycrystalline oxide (LTPO) technology. The LTPO technology forms a pixel driving circuit by combining an N-type metal oxide transistor and a P-type low temperature polycrystalline silicon transistor. However, in the pixel driving circuit formed by the LTPO technology, when the N-type metal oxide transistor is turned off, it will have a pulling-down effect on the gate of the driving transistor, thereby affecting the charging of the gate of the driving transistor.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art.

[0004] Disclosed Content

[0005] According to one aspect of the present disclosure, a display panel is provided. The display panel includes a pixel driving circuit, and the pixel driving circuit includes a driving transistor, a first transistor, and a second transistor. The gate of the first transistor is connected to a first gate line, and the first pole is connected to the gate of the driving transistor. The gate of the second transistor is connected to a second gate line, the first pole is connected to the gate of the driving transistor, and the second pole is connected to the second pole of the driving transistor. The driving transistor is a P-type transistor, and the first transistor and the second transistor are N-type transistors. The display panel further includes: a substrate, a first conductive layer, a third conductive layer, and a first connection portion. The first conductive layer is located on one side of the substrate, and the first conductive layer includes a first conductive portion for forming the gate of the driving transistor. The third conductive layer is located on one side of the substrate, and the third conductive layer includes the first gate line and the second gate line. The orthographic projection of the first gate line on the substrate and the orthographic projection of the second gate line on the substrate both extend in a first direction, and the orthographic projection of the first conductive portion on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the second gate line on the substrate. The first connection portion is connected to the first conductive portion through a via hole, and is connected to the first pole of the first transistor and the first pole of the second transistor. Wherein, the orthographic projection of the first connection portion on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the second gate line on the substrate.

[0006] In an exemplary embodiment of the present disclosure, the third conductive layer is located on a side of the first conductive layer away from the substrate, and the display panel further includes: a fourth conductive layer located on a side of the third conductive layer away from the substrate, and the fourth conductive layer includes the first connection portion.

[0007] In an exemplary embodiment of the present disclosure, the display panel further includes: a second active layer located between the third conductive layer and the first conductive layer, the second active layer includes a first active portion, the first active portion includes a first sub-active portion, a second sub-active portion, and a third sub-active portion connected between the first sub-active portion and the second sub-active portion, the first sub-active portion is configured to form a channel region of the first transistor, and the second sub-active portion is configured to form a channel region of the second transistor; the first connection portion is connected to the third sub-active portion through a via.

[0008] In an exemplary embodiment of the present disclosure, the third sub-active portion includes: a first extension portion, a positive projection of the first extension portion on the substrate extends along a second direction, and at least a part of the positive projection of the first extension portion on the substrate is disposed opposite to a positive projection of the first conductive portion on the substrate in a first direction, and the second direction intersects with the first direction; at least a part of the positive projection of the first connection portion on the substrate extends along the first direction, and the first connection portion is connected to the first extension portion through a via.

[0009] In an exemplary embodiment of the present disclosure, a positive projection of the second sub-active portion on the substrate and a positive projection of the first conductive portion on the substrate are located on the same side of a positive projection of the second gate line on the substrate.

[0010] In an exemplary embodiment of the present disclosure, a positive projection of the second sub-active portion on the substrate is located on a side of a positive projection of the first extension portion on the substrate in the first direction, and the positive projection of the second sub-active portion on the substrate is located on a side of the positive projection of the first extension portion on the substrate facing the positive projection of the first conductive portion on the substrate; the third conductive layer further includes: a first protrusion portion connected to the second gate line, a positive projection of the first protrusion portion on the substrate covers the second sub-active portion, and at least a part of the first protrusion portion is configured to form a first gate of the second transistor; wherein, the positive projection of the first protrusion portion on the substrate is located between the positive projection of the second gate line on the substrate and the positive projection of the first connection portion on the substrate.

[0011] In an exemplary embodiment of the present disclosure, the first active portion further includes: a fourth sub-active portion, the fourth sub-active portion being connected to an end of the second sub-active portion away from the third sub-active portion; in a second direction, a positive projection of the fourth sub-active portion on the substrate is located between a positive projection of the first conductive portion on the substrate and a positive projection of the second gate line on the substrate, and the second direction intersects with the first direction.

[0012] In an exemplary embodiment of the present disclosure, the display panel further includes: a first active layer, the first active layer being located between the substrate and the first conductive layer, the first active layer including a third active portion, the third active portion being configured to form a channel region of the driving transistor; wherein, a positive projection of the third active portion on the substrate extends along a second direction, and the second direction intersects with the first direction.

[0013] In an exemplary embodiment of the present disclosure, a size of a positive projection of the first conductive portion on the substrate in the first direction is smaller than its size in the second direction.

[0014] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a gate of the fourth transistor being connected to a third gate line, and a second pole being connected to a first pole of the driving transistor; the first conductive layer further includes the third gate line, and a positive projection of the third gate line on the substrate is located on a side of a positive projection of the first gate line on the substrate away from a positive projection of the first conductive portion on the substrate.

[0015] In an exemplary embodiment of the present disclosure, the display panel further includes: a fifth conductive layer, the fifth conductive layer being located on a side of the fourth conductive layer away from the substrate, the fifth conductive layer including a power supply line, and a positive projection of the power supply line on the substrate covers a positive projection of the first active portion on the substrate.

[0016] In an exemplary embodiment of the present disclosure, the power supply line includes: a first power supply line, a second power supply line, a positive projection of the first power supply line on the substrate extends along the first direction; the second power supply line is connected to the first power supply line, and a positive projection of the second power supply line on the substrate extends along a second direction, and the second direction intersects with the first direction.

[0017] In an exemplary embodiment of the present disclosure, a positive projection of the first power supply line on the substrate is located between a positive projection of the first conductive portion on the substrate and a positive projection of the second gate line on the substrate.

[0018] In an exemplary embodiment of the present disclosure, the display panel further includes: a second active layer located between the third conductive layer and the first conductive layer. The second active layer includes a first active portion, and the first active portion includes a fourth sub-active portion, a second sub-active portion, a first extension portion, and a first sub-active portion connected in sequence. The first sub-active portion is configured to form the channel region of the first transistor, and the second sub-active portion is configured to form the channel region of the second transistor; the orthographic projection of the fourth sub-active portion on the substrate, and the orthographic projection of the second sub-active portion on the substrate are sequentially distributed in the first direction, and the orthographic projection of the first extension portion on the substrate and the orthographic projection of the first sub-active portion on the substrate are distributed in the second direction; the orthographic projection of the first power supply line on the substrate covers the orthographic projection of the fourth sub-active portion on the substrate and the orthographic projection of the second sub-active portion on the substrate; the orthographic projection of the second power supply line on the substrate covers the orthographic projection of the first extension portion on the substrate and the orthographic projection of the first sub-active portion on the substrate.

[0019] In an exemplary embodiment of the present disclosure, the second pole of the first transistor is connected to the first initial signal line. The display panel further includes a light-emitting unit, and the pixel driving circuit further includes a fourth transistor and a seventh transistor. The gate of the fourth transistor is connected to the third gate line, and the second pole is connected to the first pole of the driving transistor. The first pole of the seventh transistor is connected to the first electrode of the light-emitting unit, and the second pole is connected to the second initial signal line; the first conductive layer further includes: a fourth gate line, and the orthographic projection of the fourth gate line on the substrate extends along the first direction, and a partial structure of the fourth gate line is configured to form the gate of the seventh transistor; the display panel further includes: a second conductive layer and a third conductive layer. The second conductive layer is located between the third conductive layer and the first conductive layer, and the second conductive layer includes the first initial signal line. The orthographic projection of the first initial signal line on the substrate extends along the first direction, and the orthographic projection of the first initial signal line on the substrate is located on a side of the orthographic projection of the third gate line on the substrate away from the orthographic projection of the first conductive portion on the substrate; the third conductive layer is located between the second conductive layer and the fourth conductive layer, and the third conductive layer includes the second initial signal line. The orthographic projection of the second initial signal line on the substrate extends along the first direction, and the orthographic projection of the second initial signal line on the substrate is located on a side of the orthographic projection of the fourth gate line on the substrate away from the orthographic projection of the first conductive portion on the substrate.

[0020] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit adjacent in a second direction, the second direction intersecting the first direction; a positive projection of a first initial signal line in the first pixel driving circuit on the substrate at least partially coincides with a positive projection of a second initial signal line in the second pixel driving circuit on the substrate.

[0021] In an exemplary embodiment of the present disclosure, the first initial signal line in the first pixel driving circuit includes a second conductive portion; the fourth conductive layer further includes: a second connection portion, the second connection portion connecting the second conductive portion through a via and connecting the second pole of the first transistor; a positive projection of the second conductive portion in the first pixel driving circuit on the substrate does not overlap with a positive projection of the second initial signal line in the second pixel driving circuit on the substrate.

[0022] In an exemplary embodiment of the present disclosure, the first initial signal line in the first pixel driving circuit includes: a fourth extension portion, a fifth extension portion, and a seventh extension portion. The orthographic projection of the fourth extension portion on the substrate extends along the first direction; in the same row of pixel driving circuits, the distance between the orthographic projection of the fifth extension portion on the substrate and the orthographic projection of the third gate line on the substrate in the second direction is less than the distance between the orthographic projection of the fourth extension portion on the substrate and the orthographic projection of the third gate line on the substrate in the second direction. The fifth extension portion includes a first sub-extension portion and a second sub-extension portion; the seventh extension portion is connected between the first sub-extension portion and the fourth extension portion. The second initial signal line in the second pixel driving circuit includes: a ninth extension portion, a tenth extension portion, and a twelfth extension portion. The orthographic projection of the ninth extension portion on the substrate extends along the first direction, and the orthographic projection of the ninth extension portion on the substrate at least partially overlaps with the orthographic projection of the fourth extension portion on the substrate; the tenth extension portion is connected to the ninth extension portion, and the orthographic projection of the tenth extension portion on the substrate extends along the first direction. In the same row of pixel driving circuits, the distance between the orthographic projection of the tenth extension portion on the substrate and the orthographic projection of the fourth gate line on the substrate in the second direction is greater than the distance between the orthographic projection of the ninth extension portion on the substrate and the orthographic projection of the fourth gate line on the substrate in the second direction. The orthographic projection of the tenth extension portion on the substrate at least partially overlaps with the orthographic projection of the second sub-extension portion on the substrate, and the orthographic projection of the tenth extension portion on the substrate does not overlap with the orthographic projection of the first sub-extension portion on the substrate; the twelfth extension portion is connected between the tenth extension portion and the ninth extension portion, and the included angle between the orthographic projection of the twelfth extension portion on the substrate and the orthographic projection of the tenth extension portion on the substrate is greater than the included angle between the orthographic projection of the seventh extension portion on the substrate and the orthographic projection of the fifth extension portion on the substrate; the seventh extension portion forms the second conductive portion.

[0023] In an exemplary embodiment of the present disclosure, the second initial signal line in the second pixel driving circuit further includes: an eighth extension portion and an eleventh extension portion. The orthographic projection of the eighth extension portion on the substrate extends along the first direction. The tenth extension portion is connected between the eighth extension portion and the ninth extension portion. In the same row of pixel driving circuits, the distance between the orthographic projection of the tenth extension portion on the substrate and the orthographic projection of the fourth gate line on the substrate in the second direction is greater than the distance between the orthographic projection of the eighth extension portion on the substrate and the orthographic projection of the fourth gate line on the substrate in the second direction; the eleventh extension portion is connected between the tenth extension portion and the eighth extension portion; the first initial signal line in the first pixel driving circuit further includes: a third extension portion and a sixth extension portion. The orthographic projection of the third extension portion on the substrate extends along the first direction. The fifth extension portion is connected between the third extension portion and the fourth extension portion. The distance between the orthographic projection of the fifth extension portion on the substrate and the orthographic projection of the third gate line on the substrate in the second direction is less than the distance between the orthographic projection of the third extension portion on the substrate and the orthographic projection of the third gate line on the substrate in the second direction, and at least a part of the orthographic projection of the eighth extension portion on the substrate coincides with the orthographic projection of the third extension portion on the substrate; the sixth extension portion is connected between the fifth extension portion and the third extension portion, and at least a part of the orthographic projection of the eleventh extension portion on the substrate coincides with the orthographic projection of the sixth extension portion on the substrate; the display panel further includes a first active layer, the first active layer is located between the substrate and the first conductive layer, and the first active layer includes: a seventh active portion and an eighth active portion. The seventh active portion is used to form the channel region of the seventh transistor; the eighth active portion is connected to one side of the seventh active portion. The orthographic projection of the eighth active portion on the substrate is located between the orthographic projection of the eleventh extension portion on the substrate and the orthographic projection of the twelfth extension portion on the substrate. In the first direction, the orthographic projection of the eighth active portion on the substrate is located between the orthographic projection of the sixth extension portion on the substrate and the orthographic projection of the seventh extension portion on the substrate, and the orthographic projection of the eighth active portion on the substrate is oppositely arranged with the orthographic projection of the eleventh extension portion on the substrate in the first direction; the fourth conductive layer further includes: a third connection portion, and the third connection portion is connected to the eighth active portion and the eleventh extension portion through vias respectively.

[0024] In an exemplary embodiment of the present disclosure, the size of the orthographic projection of the eleventh extension portion on the substrate in the first direction is greater than the size of the orthographic projection of the tenth extension portion on the substrate in the second direction.

[0025] In an exemplary embodiment of the present disclosure, a partial structure of the first gate line is configured to form a first gate of the first transistor. The display panel further includes: a second conductive layer located between the first conductive layer and the second active layer. The second conductive layer includes: a fifth gate line, a sixth gate line, and a second protrusion. A positive projection of the fifth gate line on the substrate extends along the first direction. The positive projection of the fifth gate line on the substrate at least partially overlaps with the positive projection of the first gate line on the substrate, and the fifth gate line is connected to the first gate line through a via. A partial structure of the fifth gate line is configured to form a second gate of the first transistor; the positive projection of the sixth gate line on the substrate extends along the first direction. The positive projection of the sixth gate line on the substrate at least partially overlaps with the positive projection of the second gate line on the substrate, and the sixth gate line is connected to the second gate line through a via; the second protrusion is connected to the sixth gate line. The positive projection of the second protrusion on the substrate at least partially overlaps with the positive projection of the first protrusion on the substrate. At least a partial structure of the second protrusion is configured to form a second gate of the second transistor. Wherein, a positive projection of the first connection portion on the substrate is located between the positive projection of the fifth gate line on the substrate and the positive projection of the sixth gate line on the substrate.

[0026] In an exemplary embodiment of the present disclosure, a positive projection of the first connection portion on the substrate extends along the first direction.

[0027] According to one aspect of the present disclosure, a display device is provided, which includes the above-mentioned display panel.

[0028] It should be understood that the above general description and subsequent detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0030] Figure 1 is a schematic circuit diagram of a pixel driving circuit in the related art;

[0031] Figure 2 is Figure 1 a timing diagram of each node in a driving method of a pixel driving circuit;

[0032] Figure 3 is the structural layout of the display panel in the related art;

[0033] Figure 4 is the structural layout of the display panel in an exemplary embodiment of the present disclosure;

[0034] Figure 5 is Figure 4 the structural layout of the first conductive layer in

[0035] Figure 6 is Figure 4 the structural layout of the third conductive layer in

[0036] Figure 7 is Figure 4 the structural layout of the fourth conductive layer in

[0037] Figure 8 is Figure 4 the structural layout of the second active layer in

[0038] Figure 9 is Figure 4 the structural layout of the first active layer in

[0039] Figure 10 is the structural layout of the display panel in another exemplary embodiment of the present disclosure;

[0040] Figure 11 is Figure 10 the structural layout of the first active layer in

[0041] Figure 12 is Figure 10 the structural layout of the first conductive layer in

[0042] Figure 13 is Figure 10 the structural layout of the second conductive layer in

[0043] Figure 14 is Figure 10 the structural layout of the second active layer in

[0044] Figure 15 is Figure 10 the structural layout of the third conductive layer in

[0045] Figure 16 is Figure 10 the structural layout of the fourth conductive layer in

[0046] Figure 17 is Figure 10 the structural layout of the fifth conductive layer in

[0047] Figure 18 isFigure 10 The structural layout of the first active layer and the first conductive layer in

[0048] Figure 19 is Figure 10 The structural layout of the first active layer, the first conductive layer, and the second conductive layer in

[0049] Figure 20 is Figure 10 The structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in

[0050] Figure 21 is Figure 10 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in

[0051] Figure 22 is Figure 10 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in

[0052] Figure 23 is Figure 10 The partial cross-sectional view along the dashed line A in

[0053] Figure 24 The simulation timing diagram of each node in the display panel of the present disclosure and the display panel in the related art. Specific embodiments

[0054] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote the same or similar structures, and thus their detailed description will be omitted.

[0055] The terms "a", "an", and "the" are used to denote the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to denote an open inclusion meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0056] As Figure 1As shown in the figure, it is a schematic circuit diagram of a pixel driving circuit in the related art. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first pole of the fourth transistor T4 is connected to the data signal terminal Da, the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2; the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first pole of the second transistor T2 is connected to the node N, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1; the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T3, the second pole is connected to the first pole of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the second pole of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the first pole of the first transistor T1 is connected to the node N, the second pole is connected to the first initial signal terminal Vinit1, the gate is connected to the first reset signal terminal Re1, and the capacitor C is connected between the first power supply terminal VDD and the node N. The pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED can be connected between the second pole of the sixth transistor T6 and the second power supply terminal VSS. Among them, the first transistor T1 and the second transistor T2 can be N-type transistors. For example, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors. The N-type metal oxide transistor has a small leakage current, so that during the light-emitting stage, the node N can be prevented from leaking electricity through the first transistor T1 and the second transistor T2. At the same time, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors. For example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon transistors. The P-type low-temperature polycrystalline silicon transistor has a high carrier mobility, which is beneficial to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to the actual situation.

[0057] As Figure 2 shown, it is Figure 1Timing diagrams of each node in a driving method of a pixel driving circuit. Among them, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of this pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light-emitting stage t4. In the first reset stage t1: the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. In the compensation stage t2: the first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Da outputs a driving signal to write a voltage Vdata + Vth to the node N, where Vdata is the voltage of the driving signal and Vth is the threshold voltage of the driving transistor T3. In the second reset stage t3, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6. In the light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata + Vth stored in the capacitor C. According to the driving transistor output current formula I = (μWCox / 2L)(Vgs - Vth) 2 , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current I of the driving transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 . This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. It should be understood that Figure 1 The pixel driving circuit shown may also have other driving methods. For example, both the first transistor T1 and the seventh transistor T7 can be reset in the first reset stage, so that the second reset stage can be omitted in this driving method.

[0058] As Figure 3 shown, it is the structural layout of a display panel in the related art. This display panel may include Figure 1 the pixel driving circuit shown. As Figure 3 shown, this display panel includes a gate line 01, a connection part 02, and a gate 03. Among them, a part of the structure of the gate line 01 is used to form Figure 1the gate of the second transistor T2 in, the gate line 01 can be used to provide Figure 1 the first gate driving signal terminal G1 in, the gate 03 is used to form Figure 1 the gate of the driving transistor T3 in, the connecting portion 02 is connected between the gate 03 and the first pole of the second transistor T2. As Figure 2 shown, at the end of the compensation stage t2, the potential of the first gate driving signal terminal G1 changes from high level to low level, that is, the potential of the gate line 01 changes from high level to low level. As Figure 3 shown, there is an overlap between the gate line 01 and the connecting portion 02, and the gate line 01 and the connecting portion 02 can form a parallel plate capacitor structure. When the potential of the gate line 01 changes from high level to low level, under the coupling action of this parallel plate capacitor structure, the potential of the connecting portion 02 drops accordingly, and the potential of the gate 03 also drops, resulting in insufficient writing of the data signal to the gate of the driving transistor.

[0059] Based on this, this exemplary embodiment provides a display panel, as Figure 4 、 5 、6, and 7 show, Figure 4 is the structural layout diagram of an exemplary embodiment of the display panel of the present disclosure, Figure 5 is Figure 4 the structural layout diagram of the first conductive layer in, Figure 6 is Figure 4 the structural layout diagram of the third conductive layer in, Figure 7 is Figure 4The structural layout of the fourth conductive layer. The display panel may include a pixel driving circuit, and the pixel driving circuit may include a driving transistor T3, a first transistor T1, and a second transistor T2. The gate of the first transistor T1 is connected to a first gate line 3Re1, and a first pole is connected to the gate of the driving transistor T3. The gate of the second transistor T2 is connected to a second gate line 3G1, a first pole is connected to the gate of the driving transistor T3, and a second pole is connected to the second pole of the driving transistor. The driving transistor T3 is a P-type transistor, and the first transistor T1 and the second transistor T2 are N-type transistors. The display panel further includes: a substrate, a first conductive layer, a third conductive layer, and a fourth conductive layer. The first conductive layer may be located on one side of the substrate, and the first conductive layer may include a first conductive portion 11, and the first conductive portion 11 may be used to form the gate of the driving transistor T3. The third conductive layer may be located on a side of the first conductive layer away from the substrate, and the third conductive layer includes the first gate line 3Re1 and the second gate line 3G1. The orthographic projection of the first gate line 3Re1 on the substrate and the orthographic projection of the second gate line 3G1 on the substrate may both extend along a first direction X, and the orthographic projection of the first conductive portion 11 on the substrate is located between the orthographic projection of the first gate line 3Re1 on the substrate and the orthographic projection of the second gate line 3G1 on the substrate. The fourth conductive layer may be located on one side of the substrate, and the fourth conductive layer may include a first connection portion 41. The first connection portion 41 may be connected to the first conductive portion 11 through a via H1 and is connected to the first pole of the first transistor and the first pole of the second transistor. Wherein, the orthographic projection of the first connection portion 41 on the substrate may be located between the orthographic projection of the first gate line 3Re1 on the substrate and the orthographic projection of the second gate line 3G1 on the substrate.

[0060] In this exemplary embodiment, by disposing the orthographic projection of the first conductive portion 11 on the substrate between the orthographic projection of a gate line 3Re1 on the substrate and the orthographic projection of the second gate line 3G1 on the substrate, the orthographic projection of the first connection portion 41 on the substrate can be disposed between the orthographic projection of the first gate line 3Re1 on the substrate and the orthographic projection of the second gate line 3G1 on the substrate. That is, the overlap between the orthographic projection of the first connection portion 41 on the substrate and the orthographic projection of the second gate line 3G1 on the substrate is avoided, thereby reducing the coupling effect of the second gate line 3G1 on the gate of the driving transistor, that is, improving the above problem of insufficient writing of the data signal.

[0061] In this exemplary embodiment, the pixel driving circuit may be as Figure 1As shown, it should be understood that in other exemplary embodiments, the pixel driving circuit of the display panel in this exemplary embodiment may also have other structures. In other exemplary embodiments, the substrate substrate, the first conductive layer, the third conductive layer, and the fourth conductive layer may also have other relative arrangement relationships, and the first connection portion 41 may also be located on other conductive layers. For example, the first connection portion 41 may also be located on the third conductive layer, etc.

[0062] In this exemplary embodiment, the display panel may further include a second active layer, as Figure 4 、 8 shown, Figure 8 is Figure 4 the layout of the structure of the second active layer in

[0063] In this exemplary embodiment, as Figure 4 、 8As shown, the third sub-active part 713 may include: a first extension part 7131. The orthographic projection of the first extension part 7131 on the substrate may extend along a second direction Y, and at least part of the orthographic projection of the first extension part 7131 on the substrate may be disposed opposite to the orthographic projection of the first conductive part on the substrate in a first direction X. The second direction Y may intersect the first direction X. For example, the second direction Y may be perpendicular to the first direction X. The orthographic projection of the first connection part 41 on the substrate may extend along the first direction X, and the first connection part 41 may be connected to the first extension part 7131 through a via H2. Among them, that at least part of the orthographic projection of the first extension part 7131 on the substrate is disposed opposite to the orthographic projection of the first conductive part on the substrate in the first direction X may be understood as: the area covered by the infinite movement of at least part of the orthographic projection of the first extension part 7131 on the substrate in the first direction X coincides with the area covered by the infinite movement of the orthographic projection of the first conductive part 11 on the substrate in the first direction X. It should be understood that in other exemplary embodiments, the first connection part 41 and the third sub-active part 713 may also have other relative positional relationships. For example, at least part of the structure of the third sub-active part 713 in the orthographic projection on the substrate may be located on one side of the orthographic projection of the first conductive part on the substrate in the second direction Y. Correspondingly, the orthographic projection of the first connection part 41 on the substrate may extend along the second direction Y.

[0064] In this exemplary embodiment, as Figure 4 , 8 shown, the orthographic projection of the second sub-active part 712 on the substrate and the orthographic projection of the first conductive part 11 on the substrate may be located on the same side of the orthographic projection of the second gate line 3G1 on the substrate. This setting may facilitate the connection between the second sub-active part 712 and the channel region of the driving transistor located below the first conductive part 11, so as to connect the second pole of the second transistor T2 and the second pole of the driving transistor T3.

[0065] In this exemplary embodiment, the positive projection of the second sub-active portion 712 on the substrate may be located on one side of the positive projection of the first extension portion 7131 on the substrate in the first direction X, and the positive projection of the second sub-active portion 712 on the substrate may be located on the side of the positive projection of the first extension portion 7131 on the substrate facing the positive projection of the first conductive portion 11 on the substrate. A partial structure of the first gate line 3Re1 may be used to form the top gate (first gate) of the first transistor. The third conductive layer may further include: a first protrusion 31, the first protrusion 31 may be connected to the second gate line 3G1, the positive projection of the first protrusion 31 on the substrate may cover the second sub-active portion 712, and at least a partial structure of the first protrusion 31 may be used to form the top gate (first gate) of the second transistor T2. Wherein, the positive projection of the first protrusion 31 on the substrate may be located between the positive projection of the second gate line 3G1 on the substrate and the positive projection of the first connection portion 41 on the substrate. This setting can enable the second sub-active portion 712 and the first conductive portion 11 to be on the same side of the second gate line 3G1.

[0066] In this exemplary embodiment, the display panel further includes a first active layer, as Figure 4 , 9 shown, Figure 9 is Figure 4 the structural layout of the first active layer in Figure 9 . The first active layer may be located between the substrate and the first conductive layer. The first active layer may include a third active portion 63, and the third active portion 63 may be used to form the channel region of the driving transistor T3. Wherein, as Figure 9 shown, the positive projection of the third active portion 63 on the substrate may extend along the second direction Y. It should be noted that the positive projection of A on the substrate extends along direction B, which can be understood as: the positive projection of A on the substrate as a whole extends along direction B, that is, the positive projection of A on the substrate may extend linearly or bend along direction B. As Figure 9 described, the first active layer may further include an active portion 61 connected to the third active portion 63. The above setting can enable the positive projection of the active portion 61 on the substrate to be located on one side of the positive projection of the first conductive portion 11 on the substrate in the second direction. In this exemplary embodiment, as Figure 4 , 8As shown, the first active part 71 may further include: a fourth sub-active part 714, and the fourth sub-active part 714 may be connected to an end of the second sub-active part 712 away from the third sub-active part 713. And in the second direction Y, the orthographic projection of the fourth sub-active part 714 on the substrate may be located between the orthographic projection of the first conductive part 11 on the substrate and the orthographic projection of the second gate line 3G1 on the substrate. The third active part 63 may be connected to the fourth sub-active part 714 through the active part 61 to connect the second pole of the second transistor T2 and the second pole of the driving transistor T3, and this setting can improve the integration degree of the pixel driving circuit. In this exemplary embodiment, the size of the orthographic projection of the first conductive part 11 on the substrate in the first direction is smaller than its size in the second direction.

[0067] In this exemplary embodiment, as Figure 4 shown, the orthographic projection of the fourth sub-active part 714 on the substrate and the orthographic projection of a partial structure of the first conductive part on the substrate are oppositely arranged in the second direction Y, that is, the area covered by the orthographic projection of the fourth sub-active part 714 on the substrate moving infinitely in the second direction coincides with the area covered by the orthographic projection of a partial structure of the first conductive part on the substrate moving infinitely in the second direction Y. It should be understood that in other exemplary embodiments, the orthographic projection of the fourth sub-active part 714 on the substrate may also be non-oppositely arranged with the orthographic projection of the first conductive part on the substrate in the second direction Y.

[0068] In this exemplary embodiment, the display panel may further include a second conductive layer and a fifth conductive layer, wherein the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be sequentially stacked. As Figures 10 - 22 shown, Figure 10 is the structural layout diagram in another exemplary embodiment of the display panel disclosed in this disclosure, Figure 11 is Figure 10 the structural layout diagram of the first active layer in Figure 12 is Figure 10 the structural layout diagram of the first conductive layer in Figure 13 is Figure 10 the structural layout diagram of the second conductive layer in Figure 14 is Figure 10 the structural layout diagram of the second active layer in Figure 15 is Figure 10 the structural layout diagram of the third conductive layer in Figure 16 is Figure 10 the structural layout diagram of the fourth conductive layer in Figure 17 is Figure 10 the structural layout diagram of the fifth conductive layer in Figure 18 is Figure 10The structural layout of the first active layer and the first conductive layer in Figure 19 is Figure 10 The structural layout of the first active layer, the first conductive layer, and the second conductive layer in Figure 20 is Figure 10 The structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in Figure 21 is Figure 10 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in Figure 22 is Figure 10 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in Figure 10 The display panel shown may have Figure 4 all the structures of the display panel shown.

[0069] As Figure 10 , 11 , as shown in 18, the first active layer may further include: a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, and a seventh active portion 67. The fourth active portion 64 may be used to form the channel region of the fourth transistor T4, the fifth active portion 65 may be used to form the channel region of the fifth transistor T5, the sixth active portion may be used to form the channel region of the sixth transistor T6, and the seventh active portion 67 may be used to form the channel region of the seventh transistor T7. Among them, the first active layer may be formed of polycrystalline silicon. Correspondingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polycrystalline silicon transistors.

[0070] As Figure 10 , 12 , as shown in 18, the first conductive layer may further include a third gate line G2, a fourth gate line Re2, and an enable signal line EM. Among them, the orthographic projection of the third gate line G2 on the substrate, the orthographic projection of the fourth gate line Re2 on the substrate, and the orthographic projection of the enable signal line EM on the substrate may all extend along the first direction X. The orthographic projection of the third gate line G2 on the substrate may cover the orthographic projection of the fourth active portion 64 on the substrate. A partial structure of the third gate line G2 may be used to form the gate of the fourth transistor T4. The third gate line G2 may provide Figure 1 the second gate driving signal terminal G2 in Figure 1The second reset signal terminal Re2 in. The positive projection of the enable signal line EM on the substrate can cover the positive projection of the fifth active portion 65 on the substrate and the positive projection of the sixth active portion 66 on the substrate. A partial structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, and another partial structure of the enable signal line EM can be used to form the gate of the sixth transistor T6. The enable signal line EM can be used to provide Figure 1 The enable signal terminal EM in. The positive projection of the third gate line G2 on the substrate, the positive projection of the first conductive portion 11 on the substrate, the positive projection of the enable signal line EM on the substrate, and the positive projection of the fourth gate line Re2 on the substrate can be sequentially distributed in the second direction Y. The first conductive portion 11 can also be used to form Figure 1 One electrode of the capacitor C in. Wherein, the display panel can conduct the first active layer with the first conductive layer as a mask, that is, the region covered by the first conductive layer can form the channel region of the transistor, and the region not covered by the first conductive layer can form the conductor structure.

[0071] Such as Figure 10 、 13 As shown in FIGS. 19, the second conductive layer may include a first initial signal line Vinit1, a fifth gate line 2Re1, a sixth gate line 2G1, a conductive portion 22, and a second protrusion 21. The positive projection of the fifth gate line 2Re1 on the substrate, the positive projection of the sixth gate line 2G1 on the substrate, and the positive projection of the first initial signal line Vinit1 on the substrate can all extend along the first direction X. Among them, the second protrusion 21 can be connected to the sixth gate line 2G1. A partial structure of the fifth gate line 2Re1 can be used to form the bottom gate (second gate) of the first transistor T1; a partial structure of the second protrusion 21 can be used to form the bottom gate (second gate) of the second transistor; the first initial signal line Vinit1 can be used to provide Figure 1 The first initial signal terminal in. Such as Figure 13 As shown in FIG., the first initial signal line Vinit1 located on the side of the fifth gate line 2Re1 away from the conductive portion 22 is used to provide the first initial signal terminal to the pixel driving circuit of this row, and the first initial signal line Vinit1 located on the side of the sixth gate line 2G1 away from the conductive portion 22 is used to provide the first initial signal terminal to the pixel driving circuit of the next row. Such as Figure 19As shown, in the same row of pixel driving circuits, the positive projection of the first initial signal line Vinit1 on the substrate is located on the side of the positive projection of the third gate line G2 on the substrate away from the first conductive part 11. The first initial signal line Vinit1 may include: a third extension V3, a sixth extension V6, a fifth extension V5, a seventh extension V7, and a fourth extension V4 connected in sequence. The positive projection of the third extension V3 on the substrate, the positive projection of the fourth extension V4 on the substrate, and the positive projection of the fifth extension V5 on the substrate may all extend along the first direction X. The fifth extension V5 may include a first sub-extension V51 and a second sub-extension V52, and the first sub-extension V51 is connected between the second sub-extension V52 and the seventh extension V7. As Figure 19 shown, in the same row of pixel driving circuits, the positive projection of the first initial signal line Vinit1 on the substrate is located on the side of the positive projection of the third gate line G2 on the substrate away from the first conductive part 11. In the same row of pixel driving circuits, the distance in the second direction Y between the positive projection of the fifth extension V5 on the substrate and the positive projection of the third gate line G2 on the substrate may be less than the distance in the second direction Y between the positive projection of the fourth extension V4 on the substrate and the positive projection of the third gate line G2 on the substrate; and the distance in the second direction Y between the positive projection of the fifth extension V5 on the substrate and the positive projection of the third gate line G2 on the substrate may be less than the distance in the second direction Y between the positive projection of the third extension V3 on the substrate and the positive projection of the third gate line G2 on the substrate. Wherein, the distance in the second direction Y between the positive projection of structure C on the substrate and the positive projection of structure D on the substrate may refer to the distance between the adjacent two sides of the positive projection of structure C on the substrate and the positive projection of structure D on the substrate in the second direction Y, that is, the positive projection of the sixth extension V6 on the substrate, the positive projection of the fifth extension V5 on the substrate, and the positive projection of the seventh extension V7 on the substrate form a concave structure facing the side of the positive projection of the third gate line G2 on the substrate. The positive projection of the conductive part 22 on the substrate may at least partially coincide with the positive projection of the first conductive part 11 on the substrate, and the conductive part 22 may be used to form Figure 1 the other electrode of the capacitor C in

[0072] As Figure 10 、 14 、20 shown, the second active layer is the same as Figure 8 the second active layer structure shown. The material of the second active layer may be formed of indium gallium zinc oxide. Correspondingly, the first transistor T1 and the second transistor T2 may be N-type oxide transistors.

[0073] As shown in Figure 10 , 15 , Figure 21, in the third conductive layer, the orthographic projection of the first gate line 3Re1 on the substrate may at least partially overlap with the orthographic projection of the fifth gate line 2Re1 on the substrate; the orthographic projection of the second gate line 3G1 on the substrate may at least partially overlap with the orthographic projection of the sixth gate line 2G1 on the substrate. For example, any segment of the orthographic projection of the first gate line 3Re1 on the substrate in its extending manner may at least partially overlap with the orthographic projection of the fifth gate line 2Re1 on the substrate; any segment of the orthographic projection of the second gate line 3G1 on the substrate in its extending manner may at least partially overlap with the orthographic projection of the sixth gate line 2G1 on the substrate. The first gate line 3Re1 and the fifth gate line 2Re1 may be connected through a via, and the via may be located in the border area of the display panel; the second gate line 3G1 and the sixth gate line 2G1 may be connected through a via, and the via may be located in the border area of the display panel. The orthographic projection of the second protrusion 21 on the substrate may at least partially overlap with the orthographic projection of the first protrusion 31 on the substrate. In addition, the third conductive layer may further include a second initial signal line Vinit2, and the second initial signal line Vinit2 may be used to provide Figure 1 the second initial signal terminal in Figure 15 . The second initial signal line Vinit2 located on the side of the second gate line 3G1 away from the first gate line 3Re1 in Figure 20 is used to provide the second initial signal terminal to the pixel driving circuit of the current row. The second initial signal line Vinit2 located on the side of the first gate line 3Re1 away from the second gate line 3G1 in Figure 21 is used to provide the second initial signal terminal to the pixel driving circuit of the previous row. As shown in

[0074] As shown in Figure 21 , the orthographic projection of the first gate line 3Re1 on the substrate may be located between the orthographic projection of the third gate line G2 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate. The first gate line 3Re1 may shield the noise influence of the third gate line G2 on the first conductive portion, thereby reducing the pull-up influence of the third gate line G2 on the first conductive portion 11 at the end of the threshold compensation stage t2. As shown in Figure 21As shown, the second initial signal line Vinit2 may include an eighth extension portion V8, an eleventh extension portion V11, a tenth extension portion V10, a twelfth extension portion V12, and a ninth extension portion V9 connected in sequence, and the orthographic projection of the eighth extension portion V8 on the substrate, the orthographic projection of the ninth extension portion V9 on the substrate, and the orthographic projection of the tenth extension portion V10 on the substrate may all extend along the first direction X. In the same row of pixel driving circuits, the distance between the orthographic projection of the tenth extension portion V10 on the substrate and the orthographic projection of the fourth gate line Re2 on the substrate in the second direction Y may be greater than the distance between the orthographic projection of the ninth extension portion on the substrate and the orthographic projection of the fourth gate line Re2 on the substrate in the second direction Y, and the distance between the orthographic projection of the tenth extension portion V10 on the substrate and the orthographic projection of the fourth gate line Re2 on the substrate may be greater than the distance between the orthographic projection of the eighth extension portion on the substrate and the orthographic projection of the fourth gate line Re2 on the substrate in the second direction Y. That is, the eleventh extension portion V11 is projected on the substrate, the tenth extension portion V10 is projected on the substrate, and the twelfth extension portion V12 is projected on the substrate to form a concave structure away from the side of the fourth gate line Re2 being projected on the substrate. The display panel can use the third conductive layer as a mask to perform conductor processing on the second active layer, that is, the area covered by the third conductive layer forms the channel area of ​​the transistor, and the area not covered by the third conductive layer forms a conductor structure.

[0075] like Figure 21As shown, the positive projection of the ninth extension V9 in the pixel driving circuit of the previous row on the substrate can at least partially overlap with the positive projection of the fourth extension V4 in the pixel driving circuit of the current row on the substrate. For example, any segment of the positive projection of the ninth extension V9 in the pixel driving circuit of the previous row on the substrate in its extending direction can at least partially overlap with the positive projection of the fourth extension V4 in the pixel driving circuit of the current row on the substrate. The positive projection of the tenth extension V10 in the pixel driving circuit of the previous row on the substrate can at least partially overlap with the positive projection of the second sub-extension V52 in the pixel driving circuit of the current row on the substrate. For example, any segment of the positive projection of the tenth extension V10 in the pixel driving circuit of the previous row on the substrate in its extending direction can at least partially overlap with the positive projection of the second sub-extension V52 in the pixel driving circuit of the current row on the substrate, and the positive projection of the tenth extension V10 in the pixel driving circuit of the previous row on the substrate does not overlap with the positive projection of the first sub-extension V51 in the pixel driving circuit of the current row on the substrate. The positive projection of the eighth extension V8 in the pixel driving circuit of the previous row on the substrate can at least partially overlap with the positive projection of the third extension V3 in the pixel driving circuit of the current row on the substrate. For example, any segment of the positive projection of the eighth extension V8 in the pixel driving circuit of the previous row on the substrate in its extending direction can at least partially overlap with the positive projection of the third extension V3 in the pixel driving circuit of the current row on the substrate. The positive projection of the eleventh extension V11 in the pixel driving circuit of the previous row on the substrate can at least partially overlap with the positive projection of the sixth extension V6 in the pixel driving circuit of the current row on the substrate. For example, any segment of the positive projection of the eleventh extension V11 in the pixel driving circuit of the previous row on the substrate in its extending direction can at least partially overlap with the positive projection of the sixth extension V6 in the pixel driving circuit of the current row on the substrate. In this exemplary embodiment, the second initial signal line in the pixel driving circuit of the previous row and the first initial signal line in the pixel driving circuit of the current row are at least partially overlapped, so as to reduce the light-shielding effect of the first initial signal line and the second initial signal line on the pixel panel, and at the same time improve the integration degree of the pixel driving circuit in the second direction and reduce the size of the pixel driving circuit in the second direction.

[0076] As Figure 13 , 15As shown, the included angle β between the orthographic projection of the twelfth extension V12 on the substrate and the orthographic projection of the tenth extension V10 on the substrate can be greater than the included angle α between the orthographic projection of the seventh extension V7 on the substrate and the orthographic projection of the fifth extension V5 on the substrate. Thus, the seventh extension V7 may not be covered by the second initial signal line Vinit2, and the seventh extension V7 can be connected to the second pole of the first transistor through the connection part located in the fourth conductive layer.

[0077] As Figure 11 , 15 , 21 shows, the first active layer may further include an eighth active part 68, and the eighth active part 68 is connected to a side of the seventh active part 67 away from the sixth active part 66. In the first direction X, the orthographic projection of the eighth active part 68 on the substrate may be located between the orthographic projection of the eleventh extension V11 on the substrate and the orthographic projection of the twelfth extension V12 on the substrate, and the orthographic projection of the eighth active part 68 on the substrate may be located between the orthographic projection of the sixth extension V6 on the substrate and the orthographic projection of the seventh extension V7 on the substrate. And at least part of the orthographic projection of the eighth active part 68 on the substrate may be oppositely arranged in the first direction X with at least part of the orthographic projection of the eleventh extension V11 on the substrate. That is, at least part of the orthographic projection of the eighth active part 68 on the substrate may be located within the concave structure formed by the orthographic projection of the eleventh extension V11 on the substrate, the orthographic projection of the tenth extension V10 on the substrate, and the orthographic projection of the twelfth extension V12 on the substrate. At the same time, at least part of the orthographic projection of the eighth active part 68 on the substrate may be located within the concave structure formed by the orthographic projection of the sixth extension V6 on the substrate, the orthographic projection of the fifth extension V5 on the substrate, and the orthographic projection of the seventh extension V7 on the substrate. This setting can facilitate the connection of the eighth active part 68 to the eleventh extension V11 through the connection part located in the fourth conductive layer, and can improve the integration degree of the pixel driving circuit.

[0078] As Figure 10 , 16 , 22 shows, the fourth conductive layer may further include: a third connection part 43, a second connection part 42, connection parts 44, 45, 46, 47, and a data line Da. Among them, the data line Da can be used to provide Figure 1 the data signal terminal in, and the orthographic projection of the data line Da on the substrate may extend along the second direction Y. The third connection part 43 can be connected to the eleventh extension V11 through a via H3 and connected to the eighth active part 68 through a via H4 to connect the second pole of the seventh transistor and the second initial signal terminal. As Figure 15As shown, the size of the positive projection of the eleventh extension V11 on the substrate in the first direction X may be greater than the size of the positive projection of the tenth extension V10 on the substrate in the second direction Y. Setting the size of the eleventh extension V11 to be larger in the first direction X facilitates the connection of the eleventh extension V11 to the via H3. In addition, in other exemplary embodiments, the third connection portion 43 may also be connected to the tenth extension V10. If the third connection portion 43 is connected to the tenth extension V10, correspondingly, the tenth extension V10 needs to have a larger size in the second direction, and this connection method will increase the size of the pixel driving circuit in the second direction. Since in this exemplary embodiment, the third active portion 63 extends along the second direction and the driving transistor T3 has a larger size in the second direction Y, connecting the third connection portion 43 to the eleventh extension V11 can reduce the size of the pixel driving circuit in the second direction to a certain extent, so as to reserve sufficient space for arranging the driving transistor T3. The second connection portion 42 can be connected to the second active layer at one end of the first sub-active portion 711 away from the second sub-active portion 712 through the via H5, and can be connected to the seventh extension V7 through the via H6 to connect the first initial signal terminal and the second pole of the first transistor. The connection portion 44 can be connected to the conductive portion 22 through the via H7. The connection portion 45 can be connected to the active portion 61 through the via H8 and can be connected to the fourth sub-active portion 714 through the via H9 to connect the second pole of the second transistor and the second pole of the driving transistor. The connection portion 46 can be connected to the first active layer on one side of the fifth active portion 65 through the via H10 to connect the first pole of the fifth transistor. The connection portion 47 can be connected to the first active layer between the sixth active portion 66 and the seventh active portion 67 through the via H12 to connect the second pole of the sixth transistor and the first pole of the seventh transistor. The data line Da can be connected to the first active layer on the side of the fourth active portion 64 away from the third active portion 63 through the via H13 to connect the first pole of the fourth transistor and the data signal terminal. The positive projection of the via H1 on the substrate may be located within the positive projection of the opening 221 on the substrate to avoid the conductive structure in the via H1 being electrically connected to the conductive portion 22.

[0079] As Figure 10 , 17 shown, the fifth conductive layer may include a power supply line VDD and a conductive portion 51. The power supply line VDD may include: a first power supply line VDD1 and a second power supply line VDD2. The positive projection of the first power supply line VDD1 on the substrate may extend along the first direction X; the second power supply line VDD2 may be connected to the first power supply line VDD1, and the positive projection of the second power supply line VDD2 on the substrate may extend along the second direction Y. As Figure 14As shown, the orthographic projection of the fourth sub-active part 714 on the substrate and the orthographic projection of the second sub-active part 712 on the substrate can be sequentially distributed in the first direction X, and the orthographic projection of the first extension part 7131 on the substrate and the orthographic projection of the first sub-active part 411 on the substrate can be distributed in the second direction Y. As Figure 10 shown, the orthographic projection of the first power supply line VDD1 on the substrate can cover the orthographic projection of the fourth sub-active part 714 on the substrate and the orthographic projection of the second sub-active part 712 on the substrate; the orthographic projection of the second power supply line VDD2 on the substrate can cover the orthographic projection of the first extension part 7131 on the substrate and the orthographic projection of the first sub-active part 711 on the substrate. The power supply line VDD covering the first active part 71 can prevent the characteristics of the first transistor T1 and the second transistor T2 from changing under the action of light. The power supply line VDD can be connected to the connection part 44 through the via hole H11 to connect one electrode of the capacitor C. The first power supply line VDD1 and the second power supply line VDD2 in this exemplary embodiment can form a grid structure to reduce the voltage drop on the power supply line itself. The conductive part 51 can be connected to the power supply line (not shown) on its left side and connected to the connection part 46 through the via hole H14 to connect the first pole of the fifth transistor.

[0080] As Figure 10 , 17 shown, the orthographic projection of the first power supply line VDD1 on the substrate can be located between the orthographic projection of the first conductive part 11 on the substrate and the orthographic projection of the second gate line 3G1 on the substrate; at the same time, the orthographic projection of the first power supply line VDD1 on the substrate can be located between the orthographic projection of the first conductive part 11 on the substrate and the orthographic projection of the sixth gate line 2G1 on the substrate. The first power supply line VDD1 can shield the noise influence of the sixth gate line 2G1 and the second gate line 3G1 on the first conductive part 11.

[0081] As Figure 23 shown, for Figure 10Partial cross-sectional view along the dashed line A. The display panel may further include: a first buffer layer 82, a first insulating layer 83, a second insulating layer 84, a third insulating layer 85, a second buffer layer 86, a fourth insulating layer 87, a first dielectric layer 88, a second dielectric layer 89, and a first planarization layer 90. The substrate 81, the first buffer layer 82, the first active layer, the first insulating layer 83, the first conductive layer, the second insulating layer 84, the second conductive layer, the third insulating layer 85, the second buffer layer 86, the second active layer, the fourth insulating layer 87, the third conductive layer, the first dielectric layer 88, the second dielectric layer 89, the fourth conductive layer, the first planarization layer 90, and the fifth conductive layer are sequentially stacked. The buffer layer 82 may include at least one of a silicon oxide layer and a silicon nitride layer. The first insulating layer 83, the second insulating layer 84, the third insulating layer 85, the second buffer layer 86, the fourth insulating layer 87, the first dielectric layer 88, and the second dielectric layer 89 may be silicon oxide layers. The material of the first planarization layer may be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), spin-on glass (SOG), and other materials. The substrate 81 may include a glass substrate, a barrier layer, and a polyimide layer that are sequentially stacked, and the barrier layer may be an inorganic material. The materials of the fourth conductive layer and the fifth conductive layer may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a laminate, etc., or may be a titanium / aluminum / titanium laminate. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a laminate, etc. The display panel may further include: a second planarization layer, an anode layer, a pixel defining layer, a support layer, etc.

[0082] As Figure 24 shown, it is a simulation timing diagram of each node in the display panel of the present disclosure and the display panel in the related art. Among them, Re1 represents the timing diagram of the first reset signal terminal, G1 represents the timing diagram of the first gate driving signal terminal, G2 represents the timing diagram of the second gate driving signal terminal, EM represents the timing diagram of the enable signal terminal, 01 represents the timing diagram of node N in the related art, and 02 represents the timing diagram of node N in the present exemplary embodiment. As Figure 24As shown, the display panel in this exemplary embodiment and the related art adopt the same driving method, which includes: a reset stage t1, a compensation stage t2, a buffer stage t3, and a light-emitting stage t4. In the reset stage t1: the first reset signal terminal, the enable signal terminal, and the second gate driving signal terminal output high levels, the second reset signal terminal and the first gate driving signal terminal output low levels, T1 and T7 are turned on, the first initial signal terminal Vinit1 resets the node N, and the second initial signal terminal Vinit2 resets one electrode of the light-emitting unit. In the compensation stage t2: the first gate driving signal terminal G1, the enable signal terminal, and the second reset signal terminal output high levels, the first reset signal terminal outputs a low level, and at least part of the period in the compensation stage, the second gate driving signal terminal G2 outputs a low level, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal Da writes a compensation voltage to the node N. In the buffer stage: the first gate driving signal terminal and the first reset signal terminal output low levels, the second gate driving signal terminal, the second reset signal terminal, and the enable signal terminal output high levels, and the voltage of the first gate driving signal terminal changes from a high level to a low level, so that the first gate driving signal terminal will pull down the voltage of the node N, from Figure 24 It can be seen that the downward floating of the node N of the display panel provided in this exemplary embodiment is smaller than that of the node N in the related art, so that the display effect of the display panel can be improved to a certain extent. In the light-emitting stage t4: the enable signal terminal, the first gate driving signal terminal, and the first reset signal terminal output low-level signals, the second gate driving signal terminal and the second reset signal terminal output high levels, the fifth transistor and the sixth transistor are turned on, and the light-emitting unit emits light. It should be noted that in the compensation stage t2, the effective duration (high-level duration) of G1 can be greater than the effective duration (low-level duration) of G2. One effective pulse of the second gate driving signal terminal G2 can drive one row of pixel driving circuits, and one effective pulse of the first gate driving signal terminal G1 can drive multiple rows of pixel driving circuits.

[0083] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a display device such as a mobile phone, a tablet computer, or a television.

[0084] After considering the specification and practicing the content disclosed herein, those skilled in the art will easily think of other embodiments of the present disclosure. This application aims to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the claims.

[0085] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only defined by the appended claims.

Claims

1. A display panel, wherein, The display panel includes a pixel driving circuit, and the pixel driving circuit includes a driving transistor, a first transistor, and a second transistor. The gate of the first transistor is connected to a first gate line, and a first pole thereof is connected to the gate of the driving transistor. The gate of the second transistor is connected to a second gate line, a first pole thereof is connected to the gate of the driving transistor, and a second pole thereof is connected to a second pole of the driving transistor. The driving transistor is a P-type transistor, and the first transistor and the second transistor are N-type transistors. The display panel further includes: a substrate; a first conductive layer located on one side of the substrate. The first conductive layer includes a first conductive portion for forming the gate of the driving transistor; a third conductive layer located on one side of the substrate. The third conductive layer includes the first gate line and the second gate line. The orthogonal projections of the first gate line and the second gate line on the substrate both extend along a first direction, and the orthogonal projection of the first conductive portion on the substrate is located between the orthogonal projection of the first gate line on the substrate and the orthogonal projection of the second gate line on the substrate; a first connection portion. The first connection portion is connected to the first conductive portion through a via hole and is connected to the first poles of the first transistor and the second transistor; wherein the orthogonal projection of the first connection portion on the substrate is located between the orthogonal projection of the first gate line on the substrate and the orthogonal projection of the second gate line on the substrate; the third conductive layer is located on a side of the first conductive layer away from the substrate. The display panel further includes: a fourth conductive layer located on a side of the third conductive layer away from the substrate. The fourth conductive layer includes the first connection portion; the display panel further includes: a second active layer located between the third conductive layer and the first conductive layer. The second active layer includes a first active portion. The first active portion includes a first sub-active portion, a second sub-active portion, and a third sub-active portion connected between the first sub-active portion and the second sub-active portion. The first sub-active portion is used to form the channel region of the first transistor, and the second sub-active portion is used to form the channel region of the second transistor; the first connection portion is connected to the third sub-active portion through a via hole.

2. The display panel according to claim 1, wherein, The third sub-active portion includes: a first extension portion. The orthogonal projection of the first extension portion on the substrate extends along a second direction, and at least a part of the orthogonal projection of the first extension portion on the substrate is oppositely arranged in the first direction with the orthogonal projection of the first conductive portion on the substrate. The second direction intersects with the first direction; at least a part of the orthogonal projection of the first connection portion on the substrate extends along the first direction, and the first connection portion is connected to the first extension portion through a via hole.

3. The display panel according to claim 2, wherein, The orthogonal projection of the second sub-active portion on the substrate and the orthogonal projection of the first conductive portion on the substrate are located on the same side of the orthogonal projection of the second gate line on the substrate.

4. The display panel according to claim 3, wherein, The positive projection of the second sub-active portion on the substrate is located on one side of the positive projection of the first extension portion on the substrate in the first direction, and the positive projection of the second sub-active portion on the substrate is located on the side of the positive projection of the first extension portion on the substrate facing the positive projection of the first conductive portion on the substrate; The third conductive layer further includes: A first protrusion portion connected to the second gate line. The positive projection of the first protrusion portion on the substrate covers the second sub-active portion, and at least a part of the structure of the first protrusion portion is used to form the first gate of the second transistor; Wherein, the positive projection of the first protrusion portion on the substrate is located between the positive projection of the second gate line on the substrate and the positive projection of the first connection portion on the substrate.

5. The display panel according to claim 3, wherein, The first active portion further includes: A fourth sub-active portion connected to one end of the second sub-active portion away from the third sub-active portion; In the second direction, the positive projection of the fourth sub-active portion on the substrate is located between the positive projection of the first conductive portion on the substrate and the positive projection of the second gate line on the substrate, and the second direction intersects with the first direction.

6. The display panel according to claim 1, wherein, The display panel further includes: A first active layer located between the substrate and the first conductive layer. The first active layer includes a third active portion for forming the channel region of the driving transistor; Wherein, the positive projection of the third active portion on the substrate extends along the second direction, and the second direction intersects with the first direction.

7. The display panel according to claim 6, wherein, The size of the positive projection of the first conductive portion on the substrate in the first direction is smaller than its size in the second direction.

8. The display panel according to claim 1, wherein, The pixel driving circuit further includes a fourth transistor, the gate of the fourth transistor is connected to the third gate line, and the second pole is connected to the first pole of the driving transistor; The first conductive layer further includes the third gate line. The positive projection of the third gate line on the substrate is located on the side of the positive projection of the first gate line on the substrate away from the positive projection of the first conductive portion on the substrate.

9. The display panel according to claim 1, wherein, The display panel further includes: A fifth conductive layer located on the side of the fourth conductive layer away from the substrate. The fifth conductive layer includes a power supply line, and the positive projection of the power supply line on the substrate covers the positive projection of the first active portion on the substrate.

10. The display panel according to claim 9, wherein, The power supply line includes: A first power supply line, the positive projection of the first power supply line on the substrate extends along the first direction; A second power supply line connected to the first power supply line. The positive projection of the second power supply line on the substrate extends along the second direction, and the second direction intersects with the first direction.

11. The display panel according to claim 10, wherein, The positive projection of the first power supply line on the substrate is located between the positive projection of the first conductive portion on the substrate and the positive projection of the second gate line on the substrate.

12. The display panel according to claim 10, wherein, The display panel further includes: The second active layer is located between the third conductive layer and the first conductive layer. The second active layer includes a first active portion, and the first active portion includes a fourth sub-active portion, a second sub-active portion, a first extension portion, and a first sub-active portion that are connected in sequence. The first sub-active portion is used to form the channel region of the first transistor, and the second sub-active portion is used to form the channel region of the second transistor; The orthographic projections of the fourth sub-active portion and the second sub-active portion on the substrate are sequentially distributed in the first direction, and the orthographic projections of the first extension portion and the first sub-active portion on the substrate are sequentially distributed in the second direction; The orthographic projection of the first power supply line on the substrate covers the orthographic projections of the fourth sub-active portion and the second sub-active portion on the substrate; The orthographic projection of the second power supply line on the substrate covers the orthographic projections of the first extension portion and the first sub-active portion on the substrate.

13. The display panel according to claim 1, wherein, The second pole of the first transistor is connected to the first initial signal line. The display panel further includes a light-emitting unit. The pixel driving circuit further includes a fourth transistor and a seventh transistor. The gate of the fourth transistor is connected to the third gate line, and the second pole is connected to the first pole of the driving transistor. The first pole of the seventh transistor is connected to the first electrode of the light-emitting unit, and the second pole is connected to the second initial signal line; The first conductive layer further includes: A fourth gate line, the orthographic projection of the fourth gate line on the substrate extends along the first direction, and a partial structure of the fourth gate line is used to form the gate of the seventh transistor; The display panel further includes: A second conductive layer is located between the third conductive layer and the first conductive layer. The second conductive layer includes the first initial signal line. The orthographic projection of the first initial signal line on the substrate extends along the first direction. In the same row of pixel driving circuits, the orthographic projection of the first initial signal line on the substrate is located on the side away from the orthographic projection of the first conductive portion on the substrate with respect to the orthographic projection of the third gate line on the substrate; The third conductive layer includes the second initial signal line. The orthographic projection of the second initial signal line on the substrate extends along the first direction. In the same row of pixel driving circuits, the orthographic projection of the second initial signal line on the substrate is located on the side away from the orthographic projection of the first conductive portion on the substrate with respect to the orthographic projection of the fourth gate line on the substrate.

14. The display panel according to claim 13, wherein, The display panel includes a plurality of the pixel driving circuits. The plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit that are adjacent in the second direction, and the second direction intersects with the first direction; The orthographic projection of the first initial signal line in the first pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second initial signal line in the second pixel driving circuit on the substrate.

15. The display panel according to claim 14, wherein, The first initial signal line in the first pixel driving circuit includes a second conductive portion; The fourth conductive layer further includes: A second connection portion, the second connection portion is connected to the second conductive portion through a via and is connected to the second pole of the first transistor; The orthographic projection of the second conductive portion in the first pixel driving circuit on the substrate does not overlap with the orthographic projection of the second initial signal line in the second pixel driving circuit on the substrate.

16. The display panel according to claim 15, wherein, The first initial signal line in the first pixel driving circuit includes: A fourth extension portion, the orthographic projection on the substrate extends along the first direction; A fifth extension portion, connected to the fourth extension portion, the orthographic projection of the fifth extension portion on the substrate extends along the first direction. In the same row of pixel driving circuits, the distance between the orthographic projection of the fifth extension portion on the substrate and the orthographic projection of the third gate line on the substrate in the second direction is less than the distance between the orthographic projection of the fourth extension portion on the substrate and the orthographic projection of the third gate line on the substrate in the second direction. The fifth extension portion includes a first sub-extension portion and a second sub-extension portion; A seventh extension portion, connected between the first sub-extension portion and the fourth extension portion; The second initial signal line in the second pixel driving circuit includes: A ninth extension portion, the orthographic projection on the substrate extends along the first direction, and the orthographic projection of the ninth extension portion on the substrate at least partially coincides with the orthographic projection of the fourth extension portion on the substrate; A tenth extension portion, connected to the ninth extension portion, the orthographic projection of the tenth extension portion on the substrate extends along the first direction. In the same row of pixel driving circuits, the distance between the orthographic projection of the tenth extension portion on the substrate and the orthographic projection of the fourth gate line on the substrate in the second direction is greater than the distance between the orthographic projection of the ninth extension portion on the substrate and the orthographic projection of the fourth gate line on the substrate in the second direction. The orthographic projection of the tenth extension portion on the substrate at least partially coincides with the orthographic projection of the second sub-extension portion on the substrate, and the orthographic projection of the tenth extension portion on the substrate does not overlap with the orthographic projection of the first sub-extension portion on the substrate; A twelfth extension portion, connected between the tenth extension portion and the ninth extension portion, and the included angle between the orthographic projection of the twelfth extension portion on the substrate and the orthographic projection of the tenth extension portion on the substrate is greater than the included angle between the orthographic projection of the seventh extension portion on the substrate and the orthographic projection of the fifth extension portion on the substrate; The seventh extension portion forms the second conductive portion.

17. The display panel according to claim 16, wherein, The second initial signal line in the second pixel driving circuit further includes: The eighth extension portion has a positive projection on the substrate extending along the first direction. The tenth extension portion is connected between the eighth extension portion and the ninth extension portion. In the same row of pixel driving circuits, the distance between the positive projection of the tenth extension portion on the substrate and the positive projection of the fourth gate line on the substrate in the second direction is greater than the distance between the positive projection of the eighth extension portion on the substrate and the positive projection of the fourth gate line on the substrate in the second direction; The eleventh extension portion is connected between the tenth extension portion and the eighth extension portion; The first initial signal line in the first pixel driving circuit further includes: The third extension portion has a positive projection on the substrate extending along the first direction. The fifth extension portion is connected between the third extension portion and the fourth extension portion. The distance between the positive projection of the fifth extension portion on the substrate and the positive projection of the third gate line on the substrate in the second direction is less than the distance between the positive projection of the third extension portion on the substrate and the positive projection of the third gate line on the substrate in the second direction, and at least part of the positive projection of the eighth extension portion on the substrate coincides with the positive projection of the third extension portion on the substrate; The sixth extension portion is connected between the fifth extension portion and the third extension portion. At least part of the positive projection of the eleventh extension portion on the substrate coincides with the positive projection of the sixth extension portion on the substrate; The display panel further includes a first active layer, and the first active layer is located between the substrate and the first conductive layer. The first active layer includes: The seventh active portion is used to form the channel region of the seventh transistor; The eighth active portion is connected to one side of the seventh active portion. In the first direction, the positive projection of the eighth active portion on the substrate is located between the positive projection of the eleventh extension portion on the substrate and the positive projection of the twelfth extension portion on the substrate. The positive projection of the eighth active portion on the substrate is located between the positive projection of the sixth extension portion on the substrate and the positive projection of the seventh extension portion on the substrate, and the positive projection of the eighth active portion on the substrate is oppositely arranged with the positive projection of the eleventh extension portion on the substrate in the first direction; The fourth conductive layer further includes: The third connection portion, and the third connection portion is connected to the eighth active portion and the eleventh extension portion through vias respectively.

18. The display panel according to claim 17, wherein, The size of the positive projection of the eleventh extension portion on the substrate in the first direction is greater than the size of the positive projection of the tenth extension portion on the substrate in the second direction.

19. The display panel according to claim 4, wherein, A partial structure of the first gate line is used to form the first gate of the first transistor. The display panel further includes: a second conductive layer, and the second conductive layer is located between the first conductive layer and the second active layer. The second conductive layer includes: A fifth gate line, a positive projection of the fifth gate line on the substrate extends along the first direction, the positive projection of the fifth gate line on the substrate at least partially coincides with the positive projection of the first gate line on the substrate, and the fifth gate line is connected to the first gate line through a via hole. A partial structure of the fifth gate line is configured to form a second gate of the first transistor; A sixth gate line, a positive projection of the sixth gate line on the substrate extends along the first direction, the positive projection of the sixth gate line on the substrate at least partially coincides with the positive projection of the second gate line on the substrate, and the sixth gate line is connected to the second gate line through a via hole; A second protrusion is connected to the sixth gate line. A positive projection of the second protrusion on the substrate at least partially coincides with a positive projection of the first protrusion on the substrate. At least a partial structure of the second protrusion is configured to form a second gate of the second transistor; Wherein, a positive projection of the first connection portion on the substrate is located between the positive projection of the fifth gate line on the substrate and the positive projection of the sixth gate line on the substrate.

20. The display panel according to claim 1, wherein, The positive projection of the first connection portion on the substrate extends along the first direction.

21. A display device, wherein, A display panel according to any one of claims 1-20.

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