Linear regulator and power supply device

Abstract

The application discloses a linear regulator and a power supply device. The linear regulator comprises a power tube, a control module and a feedback adjustment module. The power tube has a current conduction path coupled between a power supply voltage and an output voltage and a control terminal receiving a control voltage. The control module is used for generating the control voltage. The feedback adjustment module is coupled with the output voltage and a reference voltage and used for providing a feedback adjustment signal to the control module based on the output voltage and the reference voltage. The control module adjusts the control voltage based on the feedback adjustment signal to stabilize the output voltage at the reference voltage. The linear regulator can realize stable voltage output, has simple structure, good performance and small required layout area and can meet the requirements of most occasions in a chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a linear regulator and power supply device. BACKGROUND

[0002] Low Dropout Regulator (LDO) is also called linear regulator or series regulator, through which an unstable input voltage can be converted into an adjustable DC output voltage, so as to serve as a power supply for other systems.

[0003] Linear regulator has the advantages of simple circuit structure, small chip area occupation and low noise, and has become an important part of power management chip. Linear regulator can provide high-precision and low-noise power supply for noise-sensitive circuits such as analog-to-digital conversion circuit and radio frequency circuit, and is widely used in system-on-chip.

[0004] However, the existing linear regulator circuit has the problems of greatly limited output range of output voltage, complex structure, large layout area occupation, etc., which is not conducive to the miniaturization development of system-on-chip.

[0005] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems in the prior art. SUMMARY

[0006] In order to solve the above technical problems, the present application provides a linear regulator and power supply device, which can realize stable voltage output, simple structure, good performance and small layout area, and can be integrated in the chip.

[0007] According to an aspect of an embodiment of the present application, a linear regulator is provided, comprising: a power transistor having a current conduction path coupled between a supply voltage and an output voltage and a control terminal receiving a control voltage; a control module for generating the control voltage; and a feedback adjustment module coupled with the output voltage and a reference voltage, for providing a feedback adjustment signal to the control module based on the output voltage and the reference voltage, the control module adjusting the control voltage based on the feedback adjustment signal to stabilize the output voltage at the reference voltage.

[0008] Optionally, the feedback adjusting module comprises: a first transistor, a first end of which is coupled with the reference voltage, a control end and a second end of which are coupled with each other; a first current source, a first end of which is coupled with the second end of the first transistor, and a second end of which is grounded; a second transistor, a first end of which is coupled with the output voltage, and a control end of which is coupled with the control end of the first transistor; and a second current source, a first end of which is coupled with a second end of the second transistor, and a second end of which is grounded, wherein a common node of the second transistor and the second current source is used to output the feedback adjusting signal.

[0009] Optionally, the control module comprises: a third current source and a third transistor coupled between the power supply voltage and the ground, wherein a common node of the third current source and the third transistor is used to output the control voltage, and a control end of the third transistor is used to receive the feedback adjusting voltage.

[0010] Optionally, a ratio of the first transistor and the second transistor is 1:k, wherein k is an integer greater than 0.

[0011] Optionally, a current ratio of the first current source and the second current source is 1:k.

[0012] Optionally, the power tube is an enhancement mode NMOS transistor or a depletion mode NMOS transistor.

[0013] Optionally, the power tube is a high-voltage device or a low-voltage device.

[0014] Optionally, the first transistor to the third transistor are low-voltage devices.

[0015] Optionally, the first transistor and the second transistor are low-voltage enhancement mode PMOS transistors, and the third transistor is a low-voltage enhancement mode NMOS transistor.

[0016] According to another aspect of the embodiment of the present application, a power supply device is provided, comprising the linear regulator described above, which is used to convert a power supply voltage into a stable output voltage.

[0017] The linear regulator disclosed in the present application comprises a power tube, a control module and a feedback adjusting module to form a negative feedback loop, and the feedback adjusting signal generated according to the output voltage is used to adjust the control voltage of the power tube, thereby realizing feedback adjustment of the output voltage, optimizing the circuit structure, and being beneficial to improving the feedback adjustment speed and adjustment accuracy of the linear regulator.

[0018] A stable capacitor is arranged at the output end of the linear regulator, thereby further realizing stable output of the output voltage.

[0019] The linear regulator adopts less transistors, and simplifies the structure of the linear regulator while ensuring good performance.

[0020] The size of the linear regulator is determined by the requirement of current capacity only, and the area waste caused by design of other factors is avoided, and the optimal design of the linear regulator layout is realized.

[0021] It should be noted that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0022] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application, taken in conjunction with the accompanying drawings.

[0023] Figure 1 A schematic block diagram of the linear regulator provided by the embodiment of the present application is shown;

[0024] Figure 2 A schematic circuit diagram of the linear regulator provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein in the specification merely for the purpose of describing the specific embodiments of the present application, and are not intended to limit the present application.

[0027] Below, the present application will be described in detail with reference to the drawings.

[0028] Figure 1 A schematic block diagram of the linear regulator provided by the embodiment of the present application is shown. As shown in the figure, Figure 1 In the embodiment, the linear regulator 100 includes a power tube Mpwr, a control module 110, a feedback adjustment module 120, and a voltage stabilizing capacitor Co.

[0029] The power tube Mpwr is the main output tube of the chip, and has a current conduction path coupled between the power supply voltage VCC and the output voltage Vout, and a control terminal receiving the control voltage Vctrl.

[0030] In the embodiment, the power transistor Mpwr is an NMOS transistor (wherein the first end is a drain terminal and the second end is a source terminal), the first end of which is coupled to a power supply voltage VCC, the second end is coupled to an output terminal of the output voltage Vout, and the control terminal (for example, the gate terminal of the MOS transistor) is coupled to the control module 110 to receive the control voltage Vctrl.

[0031] The feedback adjustment module 120 is coupled to the output voltage Vout and the reference voltage VREF, and is configured to provide a feedback adjustment signal Vadj to the control module 110 based on the output voltage Vout and the reference voltage VREF, and the control module 110 adjusts the control voltage Vctrl based on the feedback adjustment signal Vadj to stabilize the output voltage Vout at the same potential as the reference voltage VREF.

[0032] It can be understood that the control voltage Vctrl received by the control terminal of the power transistor Mpwr controls the conduction degree of the power transistor Mpwr, for example, when the control voltage Vctrl increases, the gate-source voltage of the power transistor Mpwr increases, and the current in the power transistor Mpwr increases to charge the voltage stabilizing capacitor Co and raise the output voltage Vout.

[0033] In the embodiment, the power transistor Mpwr, the control module 110 and the feedback adjustment module 120 together form a negative feedback loop. The feedback adjustment module 120 detects the potential change of the output voltage Vout, and outputs a corresponding feedback adjustment signal Vadj to the control module 110 according to the potential change. The control module 110 adjusts the voltage of the control terminal of the power transistor Mpwr according to the feedback adjustment signal Vadj, thereby changing the potential of the output terminal of the power transistor Mpwr, and achieving negative feedback adjustment of the output voltage Vout to stabilize the output voltage Vout at the same potential as the reference voltage VREF.

[0034] The voltage stabilizing capacitor Co is coupled between the output terminal of the output voltage Vout and the ground, and is configured to stabilize the output of the output voltage Vout.

[0035] In the embodiment, the feedback adjustment module outputs a feedback adjustment signal to the control module according to the voltage change of the output terminal of the power transistor, and the control module adjusts the voltage of the control terminal of the power transistor according to the feedback adjustment signal, thereby achieving feedback adjustment and stable output of the output voltage of the power transistor, i.e., the output voltage of the linear regulator, with fast adjustment speed, high precision, simple structure and good performance.

[0036] Figure 2 A schematic circuit diagram of the linear regulator provided by the embodiment of the application is shown.

[0037] As Figure 2As shown, in the embodiment, the control module 110 includes a current source I3 and a transistor M3, which are coupled between a power supply voltage VCC and ground, and a common node (i.e., node C) of the two is coupled to a control terminal of the power transistor Mpwr for outputting the control voltage Vctrl.

[0038] In some embodiments, the transistor M3 is a low-voltage device, and for example, the transistor M3 can be a low-voltage enhancement-mode NMOS transistor. A first end (drain terminal) of the transistor M3 is coupled to one end of the current source I3 away from the power supply voltage VCC, a second end (source terminal) of the transistor M3 is coupled to ground, and a control end (gate terminal) of the transistor M3 is coupled to the feedback adjustment signal Vadj. The feedback adjustment signal Vadj is used to feedback control the potential of the control voltage Vctrl by adjusting the gate-source voltage of the transistor M3.

[0039] The feedback adjustment module 120 includes a transistor M1, a transistor M2, a current source I1, and a current source I2. The first end of the transistor M1 is coupled to a reference voltage VREF, the second end is coupled to the first end of the current source I1, and the second end of the current source I1 is grounded. The first end of the transistor M2 is coupled to an output end of the output voltage Vout, the control end is coupled to the node A of the control end and the second end of the transistor M1, the second end is coupled to the first end of the current source I2, and the second end of the current source I2 is grounded. The common node (i.e., node B) between the transistor M2 and the current source I2 is used to output the feedback adjustment signal Vadj.

[0040] In some embodiments, the transistors M1 and M2 are low-voltage devices, and for example, the transistors M1 and M2 can be implemented by low-voltage enhancement-mode PMOS transistors, the first end of which is a source terminal and the second end is a drain terminal.

[0041] In this embodiment, transistors Ml and M2 operate in the saturation region, and the transistor size ratio of transistors Ml and M2 is 1 :k, where k is an integer greater than 1. The current ratio of current sources II and I2 is also 1 :k. Therefore, when the negative feedback loop composed of transistors M2, M3, and power transistor Mpwr is turned on, the static bias potential of output voltage Vout is equal to reference voltage VREF. When the circuit is in a dynamic state, for example, when output voltage Vout decreases, the gate-source voltage VGS_M2 of transistor M2 decreases because the potential of node A does not change. When the current in transistor M2 is less than the current provided by current source I2, the potential of node B is pulled down (i.e., feedback adjustment signal Vadj decreases), which in turn causes the gate-source voltage VGS_M3 of transistor M3 to decrease, the current flowing through transistor M3 to decrease, and the potential of node C to be pulled up (i.e., control voltage Vctrl is pulled up), which causes the gate-source voltage VGS_M4 of transistor M4 to increase, the current flowing through transistor M4 to charge voltage regulating capacitor Co, and output voltage Vout to increase. Similarly, when output voltage Vout increases, the negative feedback loop pulls down the potential of node C, and eventually stabilizes the potential of output voltage Vout at reference voltage VREF.

[0042] The power tube Mpwr can be implemented by an enhancement mode NMOS transistor or a depletion mode NMOS transistor, which can be a high-voltage device or a low-voltage device. A person skilled in the art can select the type of the transistor of the power tube Mpwr according to actual needs, and the circuit structure and characteristics remain unchanged. In some embodiments, the power tube Mpwr is a high-voltage device. For example, the power tube Mpwr can be implemented by a high-voltage depletion mode NMOS transistor. The linear regulator has a wide output voltage range, which can be obtained through the following analysis. In this embodiment, the maximum voltage Vout_max of the output voltage Vout of the linear regulator is less than min(VCC-VDS_Mpwr, VCC-VGS_Mpwr-VDS_I3), where VDS_Mpwr is the voltage difference between the drain and the source of the power tube Mpwr, VDS_I3 is the voltage difference between the drain and the source of the bias current generating tube in the current source I3, and VGS_Mpwr is the voltage difference between the gate and the source of the power tube Mpwr. Since the power tube Mpwr is a depletion mode NMOS transistor, the threshold voltage VTH is less than 0, that is, the minimum gate-source voltage of the power tube Mpwr can be negative, and the drain-source voltage VDS_Mpwr of the power tube Mpwr is much greater than VDS_I3. Thus, VCC-VDS_Mpwr is less than VCC-VGS_Mpwr-VDS_I3, that is, the maximum voltage Vout_max of the output voltage Vout is less than VCC-VDS_Mpwr. Therefore, the output voltage range of the linear regulator in this embodiment is mainly determined by the load current and the size of the power tube Mpwr, and is not limited by the circuit structure. Thus, a wide output voltage range can be achieved.

[0043] Further, in the linear regulator disclosed in this embodiment, the size of the power tube Mpwr is determined according to the current capacity required by the circuit; the current sources I1-I3 can use bias current generating tubes, which are low-voltage tubes and have small layout areas or sizes; and the transistors M1-M3 are low-voltage tubes and thus have small layout areas or sizes. Therefore, it can be known comprehensively that the size or layout area of the linear regulator in this embodiment is almost determined by the sizes of the power tube Mpwr and the voltage stabilizing capacitor Co, that is, by the current requirement of the circuit. No layout area is wasted due to any other factors or design, and the linear regulator has a simple structure and a small number of transistors, and further realizes the optimal design of the layout area.

[0044] The application further discloses a power supply device for providing a supply voltage. The power supply device comprises the linear regulator as described above, to realize stable output of the supply voltage.

[0045] In conclusion, the linear regulator disclosed in the embodiment can realize stable voltage output, has simple structure, good performance, less required transistors, can realize optimization of layout design, and meets the requirements of most occasions in a chip. The output voltage of the final output does not change with temperature and process angle of the transistor, and the voltage stability is stronger.

[0046] It should be noted that, in this document, the terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof are intended to cover non-exclusive inclusions, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or inherent to such a process, method, article, or device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of other identical elements in the process, method, article, or device including the element.

[0047] Finally, it should be noted that: obviously, the above embodiments are only examples for clearly illustrating the present application, and are not limitations on the embodiments. Based on the above description, other different forms of changes or variations can also be made by those of ordinary skill in the art. Here, it is not necessary and impossible to enumerate all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A linear regulator comprising: a power transistor having a current conduction path coupled between a supply voltage and an output voltage and a control terminal receiving a control voltage; a control module configured to generate the control voltage; and a feedback adjustment module coupled to the output voltage and a reference voltage, configured to provide a feedback adjustment signal to the control module based on the output voltage and the reference voltage, the control module being configured to adjust the control voltage based on the feedback adjustment signal to stabilize the output voltage at the reference voltage, wherein the feedback adjustment module comprises: a first transistor having a first terminal coupled to the reference voltage, a control terminal and a second terminal coupled to each other; a first current source having a first terminal coupled to the second terminal of the first transistor and a second terminal coupled to ground; a second transistor having a first terminal coupled to the output voltage and a control terminal coupled to the control terminal of the first transistor; and a second current source having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to ground, wherein a common node of the second transistor and the second current source is configured to output the feedback adjustment signal, a ratio of the first transistor to the second transistor is 1:k, and a current ratio of the first current source to the second current source is 1:k, wherein k is an integer greater than 0, the control module comprises: a third current source and a third transistor coupled between the supply voltage and ground, wherein a common node of the third current source and the third transistor is configured to output the control voltage, and a control terminal of the third transistor is configured to receive the feedback adjustment voltage, wherein the power transistor is a depletion-mode NMOS transistor, and a voltage difference between the supply voltage and a drain-source voltage of the power transistor is less than a voltage difference between the supply voltage and a gate-source voltage of the power transistor and a bias current of the third current source. The power transistor is a high-voltage device or a low-voltage device.

2. The linear adjuster of claim 1, wherein, The first transistor to the third transistor are low-voltage devices.

3. The linear adjuster of claim 1, wherein, The first transistor and the second transistor are low-voltage enhancement-mode PMOS transistors, and the third transistor is a low-voltage enhancement-mode NMOS transistor.

4. The linear adjuster of claim 3, wherein, 5.A power supply apparatus comprising: the linear regulator of any one of claims 1-4, the linear regulator being configured to convert a supply voltage to a stabilized output voltage. ​

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