High power supply rejection ratio low dropout linear regulator circuit with dynamic bias current

Abstract

The application relates to the field of analog integrated circuit design, and discloses a high-power-supply-suppression-ratio low-voltage-difference linear voltage stabilizer circuit with a dynamic bias current, which comprises a power tube, a two-stage operational amplifier, a voltage feedback loop, a current feedback loop, a Vds matching loop and an RC filter circuit, characterized in that the input stage and the second stage of the operational amplifier are separated from the power supply of the power tube, the input stage works in a small-ripple AVDD voltage domain, the LDO circuit has a higher PSRR in a low-frequency band, the second stage and the power tube work in a large-ripple Vin voltage domain, the Vds matching loop and the RC filter circuit are used to ensure the mirror precision of the power tube current, and the PSRR of the LDO circuit in a medium-high-frequency band is improved.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit design, and in particular to a design technique for a low dropout linear regulator (LDO). Background Technology

[0002] With the continuous development of electronic technology, more and more electronic devices are placing higher demands on power supply circuits. Especially in applications such as high-precision analog circuits and radio frequency circuits, power supply noise directly affects system performance. Low-dropout regulators (LDOs) are widely used in these fields due to their advantages such as low noise and fast response.

[0003] However, traditional LDO circuits still have some limitations. First, the power supply rejection ratio (PSRR) of an LDO typically drops sharply at high frequencies, making it difficult to effectively suppress high-frequency noise interference from switching power supplies or load transients. Second, to improve PSRR and load transient response, the bias current of the LDO usually needs to be increased, but this leads to increased static power consumption and reduced efficiency. Furthermore, traditional LDO circuits use a single power supply, with the operational amplifier and power transistor sharing a noisy power supply, which limits the improvement of PSRR in the mid-to-high frequency range.

[0004] To address the aforementioned issues, a novel LDO design is urgently needed. This design should achieve high PSRR performance across the entire operating frequency band, with a significant improvement in power supply rejection capability, particularly in the mid-to-high frequency range of the LDO. Simultaneously, the new design should minimize quiescent power consumption while ensuring good load transient response. Summary of the Invention

[0005] The purpose of this application is to provide a high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current to solve the problems mentioned in the background art.

[0006] This application discloses a high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current, comprising:

[0007] The first power transistor MP has its source connected to the first power supply voltage Vin, its gate connected to the control voltage output by the operational amplifier, and its drain outputting the load voltage Vout.

[0008] The first operational amplifier includes an input stage and a second stage. The input stage includes a differential input pair, one end of which is connected to a reference voltage Vref and the other end is connected to a feedback voltage Vfb. The operating power supply of the input stage is a second power supply voltage AVDD, and the operating power supply of the second stage is the first power supply voltage. The second power supply voltage is a low-ripple power supply, and the first power supply voltage is a high-ripple power supply.

[0009] A voltage feedback loop is used to feed back the feedback voltage after the load voltage is divided to the input stage of the first operational amplifier;

[0010] The current feedback loop includes a Vds matching loop and an RC filter circuit. The Vds matching loop is configured to monitor the drain-source voltage of the first power transistor and control its current. The RC filter circuit includes a first MOSFET M8 and a first resistor R1 to improve the current mirror accuracy.

[0011] The first load is connected to the drain of the first power transistor;

[0012] The input stage operates in the second power supply voltage domain to ensure high PSRR in the low-frequency range, while the second stage and the first power transistor operate in the first power supply voltage domain. The Vds matching loop and the RC filter circuit ensure high PSRR in the mid-to-high frequency range.

[0013] In a preferred embodiment, the gate of the first power transistor is connected to the gates of the second MOSFET M7 and the third MOSFET M9, and its drain is connected to the upper end of the first ESR resistor Resr and the second feedback resistor Rf1 of the first load.

[0014] In a preferred embodiment, the input stage of the first operational amplifier includes:

[0015] The sources of the fourth MOSFET M1 and the fifth MOSFET M2 are shorted and connected to the negative terminal of the first current source I1 and the drain of the sixth MOSFET M14.

[0016] The gate of the fourth MOS transistor is connected to the reference voltage, and the drain is connected to the gate and drain of the seventh MOS transistor M3 and the left end of the second resistor R4.

[0017] The gate of the fifth MOS transistor is connected to the feedback voltage, and the drain is connected to the right end of the second resistor, the drain of the eighth MOS transistor M4, and the gate of the ninth MOS transistor M5.

[0018] The gate and drain of the seventh MOS transistor are shorted, and the sources of the seventh MOS transistor and the eighth MOS transistor are shorted and grounded;

[0019] The gate of the ninth MOS transistor is connected to the right end of the second resistor, the source is grounded, and the drain is connected to the drain of the tenth MOS transistor M10 and the gate of the third MOS transistor.

[0020] In a preferred embodiment, the voltage feedback loop includes:

[0021] The second feedback resistor Rf1 has its upper end connected to the load voltage and its lower end connected to the feedback voltage and the upper end of the third feedback resistor Rf2.

[0022] The third feedback resistor has its upper end connected to the feedback voltage and its lower end grounded.

[0023] In a preferred embodiment, in the current feedback loop:

[0024] The gates of the second MOS transistor, the third MOS transistor, and the first power transistor are shorted together, and the current mirror ratio is 1:1. They are connected to the drain of the tenth MOS transistor and connected to the lower end of the third resistor R. The upper end of the third resistor is connected to the first power supply voltage.

[0025] The sources of the second MOSFET, the third MOSFET, and the first power transistor are connected to the first power supply voltage;

[0026] The drain of the second MOSFET is connected to the negative terminal of the second current source I2, the source of the eleventh MOSFET M6, and the negative input terminal of the second operational amplifier amp1.

[0027] The drain of the third MOS transistor is connected to the negative terminal of the third current source I3, the source of the tenth MOS transistor, and the negative input terminal of the third operational amplifier amp2;

[0028] The drain and gate of the twelfth MOS transistor M11 are shorted and connected to the drain of the eleventh MOS transistor and the right end of the first resistor, while the source is grounded.

[0029] The gate of the thirteenth MOSFET M12 is connected to the gate of the first MOSFET and the left end of the first resistor, and its source is grounded.

[0030] The drain and gate of the fourteenth MOS transistor M13 are shorted to the drain of the thirteenth MOS transistor, and the source is connected to the second power supply voltage.

[0031] The gates of the sixth MOS transistor and the fourteenth MOS transistor are shorted together, with a current mirror ratio of k:1. The source is connected to the second power supply voltage, and the drain is connected to the source of the fourth MOS transistor and the fifth MOS transistor.

[0032] In a preferred embodiment, the Vds matching loop includes:

[0033] The positive input terminals of both the second and third operational amplifiers are connected to the load voltage.

[0034] The eleventh MOS transistor has its source connected to the inverting input terminal of the second operational amplifier and short-circuited to the lower end of the second current source and the drain of the second MOS transistor. Its drain is connected to the drain of the twelfth MOS transistor, and its gate is connected to the output terminal of the second operational amplifier.

[0035] The source of the tenth MOS transistor is connected to the inverting input terminal of the third operational amplifier and short-circuited to the lower end of the third current source and the drain of the third MOS transistor. The drain of the tenth MOS transistor is connected to the drain of the ninth MOS transistor, and the gate is connected to the output terminal of the third operational amplifier.

[0036] In a preferred embodiment, in the RC filter circuit:

[0037] The gate of the first MOS transistor is shorted to the gate of the thirteenth MOS transistor and connected to the left end of the first resistor;

[0038] The source and drain of the first MOSFET are both grounded;

[0039] The right end of the first resistor is connected to the gate of the twelfth MOS transistor.

[0040] In a preferred embodiment, the first load includes:

[0041] The first ESR resistor Resr has its upper end connected to the load voltage and its lower end connected to the upper end of the first capacitor CL.

[0042] The lower end of the first capacitor is grounded;

[0043] The first output resistor Ro has its upper end connected to the load voltage and its lower end grounded.

[0044] In a preferred embodiment, the input stage is operated in the second power supply voltage domain, and the second stage and the first power transistor are operated in the first power supply voltage domain. This ensures that the low dropout linear regulator (LDO) has a high PSRR in the low-frequency range and also improves the PSRR in the mid-to-high frequency range.

[0045] The high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current proposed in this application has the following advantages:

[0046] By placing the input stage and the second stage of the first op-amp 15 in different power supply domains—that is, the input stage operates in the low-ripple domain of the second power supply voltage AVDD, while the second stage and the first power transistor MP11 operate in the high-ripple domain of the first power supply voltage Vin—a high PSRR is ensured for the LDO in the low-frequency range. This power supply separation design protects the input stage from power supply ripple interference when handling the reference voltage Vref and the feedback voltage Vfb.

[0047] The introduction of a current feedback loop 13, including a Vds matching loop 14 and an RC filter circuit 12, significantly improves the PSRR performance of the LDO in the mid-to-high frequency range. For example... Figure 4 As shown, in the mid-frequency range of 10kHz to 2MHz, the PSRR of the proposed solution is significantly better than that of the traditional method. This is mainly due to the precise control of the drain-source voltage of the first power transistor MP11 by the Vds matching loop, and the improved current mirror accuracy by the RC filter circuit.

[0048] Simulation results show that the LDO of this application achieves a PSRR of over 40dB across the entire frequency band under the operating conditions of dropout voltage Vin-Vout = 150mV and output current IL = 250mA. Compared with traditional LDOs, this application not only ensures high PSRR in the low-frequency band but also improves PSRR in the mid-to-high frequency band.

[0049] This application solves the problem of insufficient mid-to-high frequency PSRR performance caused by the shared power supply of the op-amp 15 input stage and the second stage in traditional LDOs by using a structure with separate power supplies for the first op-amp 15 input stage and the second stage.

[0050] By using the Vds matching loop 14 and the RC filter circuit 12 composed of the first MOSFET M8 and the first resistor R1, the mirror accuracy of the current of the first power transistor MP11 is ensured, effectively improving the PSRR of the LDO circuit in the mid-to-high frequency range.

[0051] In summary, this application, based on a high PSRR LDO design with dynamic bias current, achieves high PSRR performance across the entire frequency band through the optimized configuration of the first operational amplifier 15 with separate power supply and current feedback loop 13, especially improving PSRR performance in the mid-to-high frequency band, providing a better solution for electronic systems that require high-quality power supply.

[0052] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0053] Figure 1 This is a schematic diagram illustrating an application scenario of a high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current according to an embodiment of this application.

[0054] Figure 2 This is a system block diagram of a high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current according to an embodiment of this application.

[0055] Figure 3 This is a circuit schematic of a high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current according to an embodiment of this application.

[0056] Figure 4 This is a simulation comparison of the PSRR performance of a high power supply rejection ratio (PSRR) and low dropout linear regulator circuit with dynamic bias current according to an embodiment of this application, and a conventional LDO circuit. Detailed Implementation

[0057] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0058] Explanation of some concepts:

[0059] Dynamic bias current refers to the technique in LDO circuits that dynamically adjusts the bias current according to the load and operating conditions. Its purpose is to optimize the power supply rejection ratio (PSRR) while ensuring low static power consumption.

[0060] High PSRR (High Power Supply Rejection Ratio) refers to the LDO's ability to suppress input power supply ripple and noise. It is usually expressed in decibels (dB) and is an important indicator for measuring the performance of a voltage regulator.

[0061] A low dropout linear regulator (LDO) is a linear regulator with a small input-output voltage difference. It is characterized by low dropout voltage and is suitable for power supply systems with strict voltage ripple requirements.

[0062] The operational amplifier (op-amp) in this application is divided into an input stage and a second stage. The input stage receives a reference voltage Vref and a feedback voltage Vfb, while the second stage works with a power transistor to control the load current.

[0063] Separate power supply, in this application, refers to connecting the input stage, the second stage, and the power transistor of the operational amplifier to different power supply domains. The input stage operates in the low-ripple second power supply AVDD domain, while the second stage and the power transistor operate in the high-ripple first power supply Vin domain, thereby reducing the interference of power supply ripple on sensitive signals.

[0064] The current feedback loop, in this application, refers to the closed-loop control network used to acquire and feedback the output current status of the LDO. It includes a Vds matching loop and an RC filter circuit to accurately control the operating status of the power transistor and improve the PSRR in the mid-to-high frequency range.

[0065] The Vds matching loop, in this application, refers to the loop that monitors the drain-source voltage of the power transistor. Through the feedback control of the operational amplifier, it achieves precise regulation of the power transistor current, ensuring the accuracy of the current mirror and thus improving the PSRR in the mid-to-high frequency range.

[0066] In this application, an RC filter circuit refers to a filter network composed of a MOSFET (such as M8) and a resistor (such as R1) used to filter out high-frequency ripple in the input power supply and improve the current mirror accuracy.

[0067] The following is a brief summary of some of the innovative aspects of this application:

[0068] This application, through in-depth analysis of the limitations of traditional LDO circuits in PSRR performance at different frequency bands, creatively proposes a heterogeneous differential input stage design based on dual power supply domain separation, combined with nonlinear dynamic current feedback technology. Specifically, the input stage of the first operational amplifier 15 operates in the voltage domain of the second power supply voltage AVDD (i.e., low ripple power supply), while the second stage and the first power transistor MP11 operate in the voltage domain of the first power supply voltage Vin (high ripple power supply). This power supply separation architecture, which defies conventional design intuition, produces a complex nonlinear synergistic effect with the Vds matching loop 14 and the current feedback loop 13 formed by the RC filter circuit 12 composed of the first MOSFET M8 and the first resistor R1.

[0069] Under this multi-level collaborative mechanism, the high-purity reference signal obtained by the input stage in the AVDD domain is precisely amplified by the second stage. Combined with the real-time monitoring and dynamic compensation adjustment of the drain-source voltage of the first power transistor MP11 by the current feedback loop 13, the key performance indicator of a full-band PSRR greater than 40dB is achieved under harsh operating conditions of Vin-Vout = 150mV and IL = 250mA. This technical solution, which combines heterogeneous voltage domain isolation with precise current feedback, breaks through the inherent technical contradiction between low-frequency high PSRR and mid-to-high-frequency PSRR in traditional LDO structures. While taking into account multiple performance indicators, it achieves a qualitative leap in overall performance, demonstrating the multi-dimensional innovation of this application in system architecture, circuit topology, and working principle.

[0070] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0071] In this application's specification, to make the description clearer and more concise, some technical features are represented using English letter codes. It should be clarified that the technical features represented solely by letter codes in this application have the same meaning as the corresponding technical features represented by their Chinese names plus letter codes. For example, "Vin" and "first power supply voltage Vin" refer to the same technical feature, and "AVDD" and "second power supply voltage AVDD" refer to the same technical feature. Other similar technical features represented by English letter codes are also equivalent to their corresponding technical features represented by their Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented solely by letter codes as equivalent to their corresponding technical features represented by their Chinese names plus letter codes. The technical features involving English letter codes include, but are not limited to:

[0072] Low dropout linear regulator (LDO);

[0073] Power supply rejection ratio (PSRR);

[0074] First power transistor MP;

[0075] First power supply voltage Vin;

[0076] Load voltage Vout;

[0077] Reference voltage Vref;

[0078] Feedback voltage Vfb;

[0079] Second power supply voltage AVDD;

[0080] First MOSFET M8;

[0081] First resistor R1;

[0082] Second MOSFET M7;

[0083] Third MOSFET M9;

[0084] First ESR resistor Resr; Second feedback resistor Rf1; Fourth MOSFET M1;

[0085] Fifth MOSFET M2;

[0086] First current source I1;

[0087] The sixth MOSFET, M14;

[0088] The seventh MOSFET, M3;

[0089] Second resistor R4;

[0090] The eighth MOSFET, M4;

[0091] Ninth MOSFET M5;

[0092] The tenth MOSFET, M10;

[0093] Third feedback resistor Rf2; Second current source I2;

[0094] Eleventh MOSFET M6; Second op-amp amp1;

[0095] Third current source I3;

[0096] Third op-amp amp2;

[0097] 12th MOSFET M11; 13th MOSFET M12; 14th MOSFET M13;

[0098] First capacitor CL;

[0099] First output resistance Ro;

[0100] The third resistor is R.

[0101] The first embodiment of this application relates to a high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current, comprising:

[0102] The first power transistor MP11 has its source connected to the first power supply voltage Vin, its gate connected to the control voltage output by the operational amplifier, and its drain outputting the load voltage Vout. The first operational amplifier 15 includes an input stage and a second stage. The input stage includes a differential input pair, one end connected to a reference voltage Vref, and the other end connected to a feedback voltage Vfb. The input stage operates on a second power supply voltage AVDD, and the second stage operates on the first power supply voltage Vin. The second power supply voltage AVDD is a low-ripple power supply, and the first power supply voltage Vin is a high-ripple power supply. A voltage feedback loop 16 is used to feed back the feedback voltage Vfb, obtained by dividing the load voltage Vout, to the input stage of the first operational amplifier 15. The current feedback loop 13 includes a Vds matching loop 14 and an RC filter circuit 12. The Vds matching loop 14 is configured to monitor the drain-source voltage of the first power transistor 11 and control its current. The RC filter circuit 12 includes a first MOSFET M8 and a first resistor R1 to improve current mirror accuracy. A first load 17 is connected to the drain of the first power transistor 11. The input stage operates in the second power supply voltage AVDD voltage domain to ensure high PSRR in the low-frequency range. The second stage and the first power transistor 11 operate in the first power supply voltage Vin voltage domain. The Vds matching loop 14 and the RC filter circuit 12 ensure high PSRR in the mid-to-high frequency range.

[0103] Optional, see Figure 3 The gate of the first power transistor MP11 is connected to the gates of the second MOSFET M7 and the third MOSFET M9, and its drain is connected to the upper end of the first ESR resistor Resr and the second feedback resistor Rf1 of the first load 17.

[0104] Optional, see Figure 3 The input stage of the first operational amplifier 15 includes:

[0105] The sources of the fourth MOSFET M1 and the fifth MOSFET M2 are shorted and connected to the negative terminal of the first current source I1 and the drain of the sixth MOSFET M14.

[0106] The gate of the fourth MOS transistor M1 is connected to the reference voltage Vref, and the drain is connected to the gate and drain of the seventh MOS transistor M3 and the left end of the second resistor R4.

[0107] The gate of the fifth MOS transistor M2 is connected to the feedback voltage Vfb, and the drain is connected to the right end of the second resistor R4, the drain of the eighth MOS transistor M4, and the gate of the ninth MOS transistor M5.

[0108] The gate and drain of the seventh MOS transistor M3 are shorted, and the sources of the seventh MOS transistor M3 and the eighth MOS transistor M4 are shorted and grounded.

[0109] The gate of the ninth MOS transistor M5 is connected to the right end of the second resistor R4, the source is grounded, and the drain is connected to the drain of the tenth MOS transistor M10 and the gate of the third MOS transistor M9.

[0110] Optional, see Figure 3 The voltage feedback loop 16 includes:

[0111] The second feedback resistor Rf1 has its upper end connected to the load voltage Vout and its lower end connected to the feedback voltage Vfb and the upper end of the third feedback resistor Rf2.

[0112] The third feedback resistor Rf2 has its upper end connected to the feedback voltage Vfb and its lower end grounded.

[0113] Optional, see Figure 3 In the current feedback loop 13:

[0114] The gates of the second MOSFET M7, the third MOSFET M9, and the first power transistor MP are shorted together, with a current mirror ratio of 1:1. They are connected to the drain of the tenth MOSFET M10 and connected to the lower end of the third resistor R. The upper end of the third resistor R is connected to the first power supply voltage Vin.

[0115] The sources of the second MOSFET M7, the third MOSFET M9, and the first power transistor MP are connected to the first power supply voltage Vin;

[0116] The drain of the second MOSFET M7 is connected to the negative terminal of the second current source I2, the source of the eleventh MOSFET M6, and the negative input terminal of the second operational amplifier amp1.

[0117] The drain of the third MOS transistor M9 is connected to the negative terminal of the third current source I3, the source of the tenth MOS transistor M10, and the negative input terminal of the third operational amplifier amp2.

[0118] The drain and gate of the twelfth MOS transistor M11 are shorted and connected to the drain of the eleventh MOS transistor M6 and the right end of the first resistor R1, while the source is grounded.

[0119] The gate of the thirteenth MOSFET M12 is connected to the gate of the first MOSFET M8 and the left end of the first resistor R1, and the source is grounded.

[0120] The drain and gate of the fourteenth MOSFET M13 are shorted to the drain of the thirteenth MOSFET M12, and the source is connected to the second power supply voltage AVDD.

[0121] The gates of the sixth MOS transistor M14 and the fourteenth MOS transistor M13 are shorted, with a current mirror ratio of k:1. The source is connected to the second power supply voltage AVDD, and the drain is connected to the source of the fourth MOS transistor M1 and the fifth MOS transistor M2.

[0122] Optional, see Figure 3 The Vds matching loop 14 includes:

[0123] The positive input terminals of the second operational amplifier amp1 and the third operational amplifier amp2 are both connected to the load voltage Vout;

[0124] The eleventh MOS transistor M6 has its source connected to the inverting input terminal of the second operational amplifier amp1 and short-circuited to the lower end of the second current source I2 and the drain of the second MOS transistor M7. Its drain is connected to the drain of the twelfth MOS transistor M11, and its gate is connected to the output terminal of the second operational amplifier amp1.

[0125] The source of the tenth MOS transistor M10 is connected to the inverting input terminal of the third operational amplifier amp2 and short-circuited to the lower end of the third current source I3 and the drain of the third MOS transistor M9. The drain of the tenth MOS transistor M10 is connected to the drain of the ninth MOS transistor M5, and the gate is connected to the output terminal of the third operational amplifier amp2.

[0126] Optionally, in the RC filter circuit 12:

[0127] The gate of the first MOS transistor M8 is shorted to the gate of the thirteenth MOS transistor M12 and connected to the left end of the first resistor R1.

[0128] The source and drain of the first MOSFET M8 are both grounded;

[0129] The right end of the first resistor R1 is connected to the gate of the twelfth MOS transistor M11.

[0130] Optional, see Figure 3 The first load 17 includes:

[0131] The first ESR resistor Resr has its upper end connected to the load voltage Vout and its lower end connected to the upper end of the first capacitor CL.

[0132] The lower end of the first capacitor CL is grounded;

[0133] The first output resistor Ro has its upper end connected to the load voltage Vout and its lower end grounded.

[0134] Optional, see Figure 3 , Figure 4 By operating the input stage in the voltage domain of the second power supply voltage AVDD, and operating the second stage and the first power transistor 11 in the voltage domain of the first power supply voltage Vin, the LDO is guaranteed to have high PSRR in the low-frequency range, and the PSRR in the mid-to-high frequency range is also improved.

[0135] To make the technical solution of the present invention clearer and more understandable, it is now combined with Figures 1 to 4 Preferred embodiments of the present invention will be described in detail, but it should be understood that the described embodiments are merely exemplary and not restrictive.

[0136] Figure 1 This is a schematic diagram illustrating an application scenario of the high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current in this embodiment. For example... Figure 1 As shown, a 5V voltage is converted to 1.95V via a DC / DC switching power supply, and then further regulated to 1.8V output via the high PSRR LDO circuit of this application. The ripple of the 1.95V output voltage of the DC / DC switching power supply is ±20mV, and the operating frequency is 1MHz. Because the LDO of this application has a high power supply rejection ratio (PSRR), the 1.95V voltage can be regulated to a stable 1.8V output voltage, with its ripple controlled within 0.5mV. In the specific application scenario described in the disclosure, the DC / DC switching power supply operates at 1MHz, the PSRR of the LDO of this application is 40dB, the output current Iout is 500mA, the dropout voltage (the difference between the first power supply voltage Vin and the load voltage Vout) is 150mV, and the output filtering section includes a 4.7uF first capacitor CL1 and a 2.2uF second capacitor CL2. At this point, a PSRR of 40dB is equivalent to a ripple attenuation ratio of 100. Therefore, a ±20mV ripple from the input 1.95V voltage, after passing through the LDO circuit of this application, can be suppressed to within 0.2mV at the output 1.8V voltage. It should be noted that... Figure 1 The two-stage regulated output circuit from 5V to 1.8V shown is just one typical application scenario of this application. Those skilled in the art will understand that the high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current of this application can be applied to various occasions that require a low ripple stable output voltage.

[0137] Figure 2 This is a circuit system block diagram of a high power supply rejection ratio, low dropout linear regulator circuit with dynamic bias current in this embodiment. (See diagram for example.) Figure 2As shown, the LDO system designed in this application mainly includes a first power transistor 11, a first operational amplifier 15, a voltage feedback loop 16, a current feedback loop 13, and a first load 17. The current feedback loop 13 further includes a Vds matching loop 14 and an RC filter circuit 12. The source of the first power transistor 11 is connected to the first power supply voltage Vin, the gate is connected to the control voltage output by the first operational amplifier 15, and the drain outputs the load voltage Vout to the first load 17. The first operational amplifier 15 includes an input stage and a second stage. The input stage receives the differential input signal of the reference voltage Vref and the feedback voltage Vfb. The second stage amplifies the differential input signal and outputs the control voltage of the gate of the first power transistor 11. The input stage uses the second power supply voltage AVDD, while the second stage uses the first power supply voltage Vin. The second power supply voltage AVDD is a low-ripple power supply, while the first power supply voltage Vin is a high-ripple power supply. The voltage feedback loop 16 is used to feed back the feedback voltage Vfb obtained by dividing the load voltage Vout to the input stage of the first operational amplifier 15, forming a voltage feedback closed-loop control. In the current feedback loop 13, the Vds matching loop 14 is used to monitor the drain-source voltage of the first power transistor 11 and control its current, while the RC filter circuit 12 is used to ensure the mirror accuracy of the power transistor current, thereby improving the PSRR of the LDO circuit in the mid-to-high frequency range. The innovation of this application lies in supplying the input stage and the second stage of the first operational amplifier 15 with different power supplies. The input stage operates in the low-ripple second power supply voltage AVDD domain, ensuring that the LDO has a high PSRR in the low-frequency range; while the second stage and the first power transistor 11 operate in the high-ripple first power supply voltage Vin domain. Through the synergistic effect of the Vds matching loop 14 and the RC filter circuit 12, the PSRR performance of the LDO in the mid-to-high frequency range is improved.

[0138] Figure 3 This is a preferred circuit schematic of a high power supply rejection ratio, low dropout linear regulator circuit with dynamic bias current in this embodiment. (See diagram below.) Figure 3As shown, the LDO circuit of this application mainly includes: a first power transistor MP11, a first operational amplifier 15, a voltage feedback loop 16, a current feedback loop 13, and a first load 17. The first power transistor MP11 is a P-channel MOSFET, with its source connected to the first power supply voltage Vin. Its gate is connected to the gates of the second MOSFET M7 and the third MOSFET M9, jointly receiving the control voltage output from the operational amplifier. Its drain outputs the load voltage Vout and is connected to the upper end of the first ESR resistor Resr and the second feedback resistor Rf1 of the first load 17. The input stage of the first operational amplifier 15 uses a differential input pair composed of the fourth MOSFET M1 and the fifth MOSFET M2. The gate of M1 is connected to the reference voltage Vref, and the gate of M2 is connected to the feedback voltage Vfb. The sources of both are short-circuited and connected to the negative terminal of the first current source I1 and the drain of the sixth MOSFET M14. The drain of the fourth MOSFET M1 is connected to the gate and drain of the seventh MOSFET M3 and the left end of the second resistor R4, respectively. The drain of the fifth MOSFET M2 is connected to the right end of the second resistor R4, the drain of the eighth MOSFET M4, and the gate of the ninth MOSFET M5. The sources of the seventh MOSFET M3 and the eighth MOSFET M4 are both grounded, and the gate and drain of M3 are shorted. The source of the ninth MOSFET M5 is grounded, and its drain is connected to the drain of the tenth MOSFET M10 and the gate of the third MOSFET M9, respectively, forming the second stage input of the first operational amplifier 15. The voltage feedback loop 16 is implemented through the second feedback resistor Rf1 and the third feedback resistor Rf2. The upper end of Rf1 is connected to the load voltage Vout, and the lower end is connected to the feedback voltage Vfb and the upper end of Rf2. The lower end of Rf2 is grounded. Rf1 and Rf2 act as a voltage divider, dividing Vout and feeding it back to the input of the first operational amplifier 15. The current feedback loop 13 includes a Vds matching loop 14 and an RC filter circuit 12. The gates of the second MOSFET M7, the third MOSFET M9, and the first power transistor MP are shorted, with a current mirror ratio of 1:1:n. These are connected to the drain of the tenth MOSFET M10 and the lower end of the third resistor R, the upper end of which is connected to the first power supply voltage Vin. The sources of M7, M9, and MP are all connected to the first power supply voltage Vin. The drain of M7 is connected to the negative terminal of the second current source I2, the source of the eleventh MOSFET M6, and the negative input terminal of the second operational amplifier amp1. The drain of M9 is connected to the negative terminal of the third current source I3, the source of M10, and the negative input terminal of the third operational amplifier amp2. The drain and gate of the twelfth MOSFET M11 are shorted, connected to the drain of M6 and the right end of the first resistor R1, with its source grounded. The gate of the thirteenth MOSFET M12 is connected to the gate of the first MOSFET M8 and the left end of R1, with its source grounded. The drain and gate of the fourteenth MOSFET M13 are shorted and connected to the drain of M12, while the source is connected to the second power supply voltage AVDD. The gates of M14 and M13 are shorted, and the current mirror ratio is k:1. The source is connected to AVDD, and the drain is connected to the source of M1 and M2.In the Vds matching loop 14, the non-inverting inputs of the second operational amplifier amp1 and the third operational amplifier amp2 are both connected to the load voltage Vo. The source of M6 and the drain of M7 are both connected to the inverting input of amp1, the drain of M6 is connected to the drain of M11, and the gate is connected to the output of amp1. Similarly, the source of M10 and the drain of M9 are both connected to the inverting input of amp2, the drain of M10 is connected to the drain of M5, and the gate is connected to the output of amp2. In the RC filter circuit 12, the gate of the first MOSFET M8 is connected to the gate of M12 and the left end of the first resistor R1, with both its source and drain grounded. The right end of R1 is connected to the gate of M11. The first load 17 includes a first ESR resistor Resr, a first capacitor CL, and a first output resistor Ro. The upper end of Resr is connected to the load voltage Vo, and the lower end is connected to the upper end of CL, with the lower end of CL grounded. The upper end of Ro is also connected to the load voltage Vo, and the lower end is grounded. The innovation of this application lies in using different power supplies for the input stage of the first operational amplifier 15 and the second stage, and combining the Vds matching and RC filter circuit in the current feedback loop 13 to improve the PSRR performance of the LDO in the mid-to-high frequency range while ensuring high PSRR at low frequencies.

[0139] Figure 4 This is a simulation comparison of the PSRR performance of the high power supply rejection ratio (PSRR) and low dropout linear regulator circuit with dynamic bias current in this embodiment with that of a conventional LDO circuit. Figure 4 As shown, the horizontal axis represents frequency, and the vertical axis represents power supply rejection ratio (PSRR), in dB. The curve labeled "Conventional Method" represents the PSRR simulation results of the prior art LDO circuit, while the curve labeled "Method of This Application" represents the PSRR simulation results of the LDO circuit of this application. The simulation conditions were: full-band PSRR performance when Vin-Vout = 150mV and IL = 250mA. Figure 4Simulation results show that in the low-frequency range (0-10kHz) and high-frequency range (>2MHz), the PSRR performance of the LDO in this application is basically equivalent to that of existing LDOs. However, in the mid-frequency range (10kHz-2MHz), the PSRR performance of the proposed solution is significantly better than that of the traditional method, and the power supply rejection ratio is significantly improved. The main reason for this result is that this application adopts a structure with separate power supplies for the input stage and the second stage of the first operational amplifier 15, and introduces a current feedback loop 13 containing a Vds matching loop 14 and an RC filter circuit 12 at the first power transistor 11. In the low-frequency range, the input stage operates in the domain of the second power supply voltage AVDD with small ripple, thereby achieving a higher PSRR. In the mid-to-high frequency range, the second stage and the first power transistor operate in the domain of the first power supply voltage Vin with larger ripple, but the Vds matching loop and the RC filter circuit ensure the mirror accuracy of the POWER transistor current, thereby improving the PSRR of the LDO circuit in the mid-to-high frequency range. Simulation results show that when the LDO of this application operates at a low DropOut voltage Vin-Vout = 150mV and IL = 250mA, the PSRR is greater than 40dB across the entire frequency band, confirming the effectiveness of the design scheme of this application.

[0140] Working principle:

[0141] The working principle of the LDO circuit in this application is as follows: (Refer to...) Figure 3The input stage of the first op-amp 15 consists of a differential input pair formed by the fourth MOSFET M1 and the fifth MOSFET M2. Their sources are shorted and connected to the negative terminal of the first current source I1 and the drain of the sixth MOSFET M14. The input stage operates in the second power supply voltage AVDD domain. AVDD is a low-ripple power supply, ensuring good immunity to power supply ripple interference when receiving the reference voltage Vref and feedback voltage Vfb, thus enabling the LDO to achieve a high PSRR in the low-frequency range. The second stage of the first op-amp 15 is driven by the ninth MOSFET M5. Its gate is driven by the output of the differential pair M1 and M2 through a current mirror load formed by M3 and M4. The second stage operates in the first power supply voltage Vin domain, which is a high-ripple power supply. The drain of M5 is connected to the drain of the tenth MOSFET M10 and the gate of the third MOSFET M9, transmitting the control signal to the gate of the first power transistor MP11 to achieve linear regulation of the LDO. In voltage feedback loop 16, the second feedback resistor Rf1 and the third feedback resistor Rf2 divide the load voltage Vout to generate a feedback voltage Vfb, which is fed back to the gate of the input stage M2 of the first operational amplifier 15. This Vfb is then compared differentially with the reference voltage Vref to achieve closed-loop regulation of the LDO output voltage. Current feedback loop 13 includes a Vds matching loop 14 and an RC filter circuit 12. The Vds matching loop 14 is implemented using the second operational amplifier amp1 and the third operational amplifier amp2. Specifically, the positive input terminal of amp1 is connected to the load voltage Vo, and the negative input terminal is connected to the lower end of the second current source I2, the drain of the second MOSFET M7, and the source of the eleventh MOSFET M6. The gate of M6 is connected to the output terminal of amp1, forming negative feedback. Similarly, the positive input terminal of amp2 is connected to the load voltage Vo, and the negative input terminal is connected to the lower end of the third current source I3, the drain of the third MOSFET M9, and the source of the tenth MOSFET M10. The gate of M10 is connected to the output terminal of amp2, also forming negative feedback. This configuration ensures that the drain-source voltages of M6 and M10 match the drain-source voltage of the first power transistor MP. In the RC filter circuit 12, the gate of the first MOSFET M8 is shorted to the gate of the thirteenth MOSFET M12 and connected to the left end of the first resistor R1, with its source and drain grounded. The right end of the first resistor R1 is connected to the gate of the twelfth MOSFET M11. M8 and R1 form an RC low-pass filter, filtering out high-frequency noise in the current signal and further improving the current mirror accuracy. The gates of the second MOSFET M7, the third MOSFET M9, and the first power transistor MP are shorted, with a current mirror ratio of 1:1:n, ensuring that the gate-source voltages of the three are the same, forming an accurate current mirror relationship. The current mirror is composed of the fourteenth MOSFET M13 and the sixth MOSFET M14, with a ratio of k:1, providing a stable bias current for the input stage.By placing the input stage of the first operational amplifier 15 in the domain of the second power supply voltage AVDD with low ripple, and placing the second stage and the first power transistor MP in the domain of the first power supply voltage Vin, and by using the Vds matching loop 14 and the RC filter circuit 12 to ensure the mirror accuracy of the power transistor current, the LDO of this application achieves a PSRR performance of over 40dB across the entire frequency band, with a particularly improved PSRR performance in the mid-to-high frequency band of 10kHz-2MHz.

[0142] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0143] like Figure 2 As shown, the high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current in this example includes a power transistor 11, a two-stage operational amplifier 15, a voltage feedback loop 16, and a current feedback loop 13. The current feedback loop 13 includes a Vds matching loop 14, an RC filter circuit 12, and a load 17. The main control system includes the power transistor 11 and the two-stage operational amplifier 15; through the voltage feedback loop 16 and the current feedback loop 13, dual closed-loop control of voltage and current of the main control system is achieved.

[0144] The circuit diagram of this example, featuring a high power supply rejection ratio and low dropout linear regulator with dynamic bias current, is as follows: Figure 3 As shown, the power supply of the five-transistor op-amp is separated from the power supplies of the second-stage op-amp and the power transistors. The five-transistor op-amp operates in the AVDD voltage domain, where AVDD is a low-ripple power supply to ensure a high PSRR for the LDO circuit in the low-frequency range. The second-stage op-amp and the power transistors operate in the Vin voltage domain, where Vin is a high-ripple power supply. A Vds matching loop and an RC filter circuit consisting of MOSFET M8 and resistor R1 ensure the current mirror accuracy of the power transistors, thereby improving the PSRR of the LDO circuit in the mid-to-high frequency range. Simulation results show that the LDO in this example operates at a low DropOut voltage Vin-Vout = 150mV and IL = 250mA, with a PSRR greater than 40dB across the entire frequency range.

[0145] Furthermore, such as Figure 3 As shown, in this example of a high power supply rejection ratio (PSRR) and low dropout linear regulator circuit with dynamic bias current, the power supply of the five-transistor op-amp is separated from the power supply of the second-stage op-amp and the power transistor. The five-transistor op-amp operates in the AVDD (low-ripple power supply) voltage domain to ensure that the LDO circuit has a high PSRR in the low-frequency range. The second-stage op-amp and the power transistor operate in the Vin (high-ripple power supply) voltage domain. Through the Vds matching loop and the RC filter circuit composed of MOSFET M8 and resistor R1, the current mirror accuracy of the power transistor is ensured, thereby improving the PSRR of the LDO circuit in the mid-to-high frequency range.

[0146] The power transistor MP11 has its source connected to the power supply Vin, its gate connected to the gates of MOSFETs M7 and M9, its drain connected to the output Vout of the LDO, the upper end of resistor Rf1, the upper end of ESR resistor Resr, and the upper end of the output resistor.

[0147] The structure of the two-stage operational amplifier 15 includes: input transistors M1 and M2; the sources of MOSFETs M1 and M2 are shorted and connected to the negative terminal of current I1 and the drain of M14; the gate of MOSFET M1 is connected to Vref voltage, and the drain of MOSFET M1 is connected to the gate and drain of M3 and the left end of resistor R4; the gate of MOSFET M2 is connected to Vfb voltage, and the drain of MOSFET M2 is connected to the right end of resistor R4, the drain of MOSFET M4, and the gate of MOSFET M5; the gate and drain of MOSFET M3 are shorted, and the sources of MOSFETs M3 and M4 are shorted and grounded; the gate of MOSFET M5 is connected to the right end of resistor R4, the source of MOSFET M5 is grounded, and the drain of MOSFET M5 is connected to the drain of MOSFET M10 and the gate of MOSFET M9.

[0148] The voltage feedback loop has a structure including: the upper end of resistor Rf1 is connected to Vout, the lower end is connected to the voltage Vfb and the upper end of resistor Rf2; the lower end of resistor Rf2 is grounded.

[0149] The current feedback loop 13 includes the following structure: the gates of MOSFETs M7, M9, and MP are shorted together, with a current mirror ratio of 1:1, connected to the drain of MOSFET M10, and also connected to the lower end of resistor R. The upper end of resistor R is connected to the power supply Vin. The sources of MOSFETs M7, M9, and MP are connected to the power supply Vin. The gate of MOSFET M7 is connected to the negative terminal of current mirror I2, the source of MOSFET M6, and the negative input terminal of op-amp amp1. The drain of MOSFET M9 is connected to the negative terminal of current mirror I3, the source of MOSFET M10, and the negative input terminal of op-amp amp2. The drain and gate of MOSFET M11 are shorted together and connected to MOSFET M10. The drain of transistor M6 is connected to the right end of resistor R1; the source of MOSFET M11 is grounded; the gate of MOSFET M12 is connected to the gate of MOSFET M8 and the left end of resistor R1; the source of MOSFET M12 is grounded, and the current mirror ratio of MOSFETs M11 and M12 is 1:1; the drain and gate of MOSFET M13 are shorted to the drain of MOSFET M12, and the source of MOSFET M13 is connected to power supply AVDD; the gates of MOSFETs M14 and M13 are shorted, and the current mirror ratio is k:1; the source of MOSFET M14 is connected to power supply AVDD; the drain of MOSFET M14 is connected to the sources of MOSFETs M1 and M2.

[0150] The Vds matching loop 14 has the following structure: the source of MOSFET M6 is connected to the inverting input of op-amp amp1, and the lower end of current source I2 and the drain of MOSFET M7 are shorted; the drain of MOSFET M6 is connected to the drain of MOSFET M11, and the gate of MOSFET M6 is connected to the upper output of op-amp amp1; the non-inverting input of op-amp amp1 is connected to the output Vo of LDO; similarly, the source of MOSFET M10 is connected to the inverting input of op-amp amp2, and the lower end of current source I3 and the drain of MOSFET M9 are shorted; the drain of MOSFET M10 is connected to the drain of MOSFET M5, and the gate of MOSFET M10 is connected to the upper output of op-amp amp2; the non-inverting input of op-amp amp2 is connected to the output Vo of LDO.

[0151] The RC filter circuit 12 has the following structure: the gate of MOSFET M8 is connected to the gate of MOSFET M12 and shorted to the left end of resistor R1; the source and drain of MOSFET M8 are both grounded; and the right end of resistor R1 is connected to the gate of MOSFET M11.

[0152] Load 17 has the following structure: the upper end of the ESR resistor Resr is connected to the output Vo of the LDO, and the lower end of Resr is connected to the upper end of the capacitor; the lower end of the capacitor is connected to ground; the upper end of the output resistor Ro is connected to the output Vo of the LDO; and the lower end of the output resistor Ro is grounded.

[0153] Simulation results are as follows Figure 4 As shown in the figure, the simulation results of the traditional method and the technical solution in this example are compared. It can be seen from the figure that the PSRR of the two methods are similar in the low frequency band (0-10kHz) and the high frequency band (>2MHz). In the mid frequency band (10kHz-2MHz), the PSRR of the method in this design is significantly higher than that of the traditional method, and the PSRR is significantly improved.

[0154] Compared with existing technologies, the beneficial effects of this example are as follows:

[0155] Unlike traditional dynamically biased current LDO circuits, this example separates the power supply of the five-transistor op-amp from the power supply of the second-stage op-amp and the power transistors, ensuring that the LDO has high PSRR in the low-frequency range.

[0156] It also improved the PSRR in the mid-to-high frequency range.

[0157] The above embodiments have the following technical effects:

[0158] By placing the input stage and the second stage of the first op-amp 15 in different power supply domains—that is, the input stage operates in the low-ripple domain of the second power supply voltage AVDD, while the second stage and the first power transistor MP11 operate in the high-ripple domain of the first power supply voltage Vin—a high PSRR is ensured for the LDO in the low-frequency range. This power supply separation design protects the input stage from power supply ripple interference when handling the reference voltage Vref and the feedback voltage Vfb.

[0159] The introduction of a current feedback loop 13, including a Vds matching loop 14 and an RC filter circuit 12, significantly improves the PSRR performance of the LDO in the mid-to-high frequency range. For example... Figure 4 As shown, in the mid-frequency range of 10kHz to 2MHz, the PSRR of the proposed solution is significantly better than that of the traditional method. This is mainly due to the precise control of the drain-source voltage of the first power transistor MP11 by the Vds matching loop, and the improved current mirror accuracy by the RC filter circuit.

[0160] Simulation results show that the LDO of this application achieves a PSRR of over 40dB across the entire frequency band under the operating conditions of dropout voltage Vin-Vout = 150mV and output current IL = 250mA. Compared with traditional LDOs, this application not only ensures high PSRR in the low-frequency band but also improves PSRR in the mid-to-high frequency band.

[0161] This application solves the problem of insufficient mid-to-high frequency PSRR performance caused by the shared power supply of the op-amp 15 input stage and the second stage in traditional LDOs by using a structure with separate power supplies for the first op-amp 15 input stage and the second stage.

[0162] By using the Vds matching loop 14 and the RC filter circuit 12 composed of the first MOSFET M8 and the first resistor R1, the mirror accuracy of the current of the first power transistor MP11 is ensured, effectively improving the PSRR of the LDO circuit in the mid-to-high frequency range.

[0163] In summary, this application, based on a high PSRR LDO design with dynamic bias current, achieves high PSRR performance across the entire frequency band through the optimized configuration of the first operational amplifier 15 with separate power supply and current feedback loop 13, especially improving PSRR performance in the mid-to-high frequency band, providing a better solution for electronic systems that require high-quality power supply.

[0164] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0165] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current, characterized in that, include: The first power transistor (MP) has its source connected to the first power supply voltage (Vin), its gate connected to the control voltage output by the operational amplifier, and its drain outputting the load voltage (Vout). The first operational amplifier includes an input stage and a second stage. The input stage includes a differential input pair, one end of which is connected to a reference voltage (Vref) and the other end of which is connected to a feedback voltage (Vfb). The operating power supply of the input stage is a second power supply voltage (AVDD), and the operating power supply of the second stage is the first power supply voltage. The second power supply voltage is a low-ripple power supply, and the first power supply voltage is a high-ripple power supply. A voltage feedback loop is used to feed back the feedback voltage after the load voltage is divided to the input stage of the first operational amplifier; The current feedback loop includes a Vds matching loop and an RC filter circuit. The Vds matching loop is configured to monitor the drain-source voltage of the first power transistor and control its current. The RC filter circuit includes a first MOSFET (M8) and a first resistor (R1) to improve the current mirror accuracy. The first load is connected to the drain of the first power transistor; The input stage operates in the second power supply voltage domain to ensure high PSRR in the low-frequency range, while the second stage and the first power transistor operate in the first power supply voltage domain. The Vds matching loop and the RC filter circuit ensure high PSRR in the mid-to-high frequency range. The input stage of the first op-amp includes: The sources of the fourth MOSFET (M1) and the fifth MOSFET (M2) are shorted and connected to the negative terminal of the first current source (I1) and the drain of the sixth MOSFET (M14). The positive terminal of the first current source (I1) is connected to the second power supply voltage (AVDD). The gate of the fourth MOS transistor is connected to the reference voltage, and the drain is connected to the gate and drain of the seventh MOS transistor (M3) and the left end of the second resistor (R4). The gate of the fifth MOS transistor is connected to the feedback voltage, and the drain is connected to the right end of the second resistor, the drain of the eighth MOS transistor (M4), and the gate of the ninth MOS transistor (M5). The gate and drain of the seventh MOS transistor are shorted, and the sources of the seventh MOS transistor and the eighth MOS transistor are shorted and grounded; The gate of the ninth MOS transistor is connected to the right end of the second resistor, the source is grounded, and the drain is connected to the drain of the tenth MOS transistor (M10) and the gate of the third MOS transistor (M9). In the current feedback loop: The gates of the second MOSFET (M7), the third MOSFET (M9), and the first power transistor (MP) are shorted together, with a current mirror ratio of 1:1:n. They are connected to the drain of the tenth MOSFET (M10) and connected to the lower end of the third resistor (R). The upper end of the third resistor is connected to the first power supply voltage. The sources of the second MOS transistor, the third MOS transistor, and the first power transistor are connected to the first power supply voltage; The drain of the second MOSFET is connected to the negative terminal of the second current source (I2), the source of the eleventh MOSFET (M6), and the negative input terminal of the second operational amplifier (amp1). The positive terminal of the second current source (I2) is connected to the first power supply voltage (Vin). The drain of the third MOS transistor is connected to the negative terminal of the third current source (I3), the source of the tenth MOS transistor, and the negative input terminal of the third operational amplifier (amp2). The positive terminal of the third current source (I3) is connected to the first power supply voltage (Vin). The drain and gate of the twelfth MOS transistor (M11) are shorted and connected to the drain of the eleventh MOS transistor and the right end of the first resistor (R1), while the source is grounded. The gate of the thirteenth MOSFET (M12) is connected to the gate of the first MOSFET (M8) and the left end of the first resistor, and the source is grounded; The drain and gate of the fourteenth MOS transistor (M13) are shorted to the drain of the thirteenth MOS transistor, and the source is connected to the second power supply voltage. The gates of the sixth MOS transistor (M14) and the fourteenth MOS transistor (M13) are shorted, the current mirror ratio is k:1, the source is connected to the second power supply voltage, and the drain is connected to the source of the fourth MOS transistor and the fifth MOS transistor. The Vds matching loop includes: The positive input terminals of both the second operational amplifier (amp1) and the third operational amplifier (amp2) are connected to the load voltage; The eleventh MOS transistor (M6) has its source connected to the inverting input terminal of the second operational amplifier and short-circuited to the negative terminal of the second current source and the drain of the second MOS transistor. Its drain is connected to the drain of the twelfth MOS transistor, and its gate is connected to the output terminal of the second operational amplifier. The source of the tenth MOS transistor (M10) is connected to the inverting input terminal of the third operational amplifier and short-circuited to the negative terminal of the third current source and the drain of the third MOS transistor. Its drain is connected to the drain of the ninth MOS transistor, and its gate is connected to the output terminal of the third operational amplifier. In the RC filter circuit: The gate of the first MOS transistor (M8) is shorted to the gate of the thirteenth MOS transistor (M12) and connected to the left end of the first resistor (R1); The source and drain of the first MOSFET (M8) are both grounded; The right end of the first resistor (R1) is connected to the gate of the twelfth MOS transistor (M11).

2. The high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current as described in claim 1, characterized in that, The voltage feedback loop includes: The second feedback resistor (Rf1) has its upper end connected to the load voltage and its lower end connected to the feedback voltage and the upper end of the third feedback resistor (Rf2). The third feedback resistor has its upper end connected to the feedback voltage and its lower end grounded.

3. The high power supply rejection ratio and low dropout linear regulator circuit with dynamic bias current as described in claim 1, characterized in that, The first load includes: The first ESR resistor (Resr) has its upper end connected to the load voltage and its lower end connected to the upper end of the first capacitor (CL). The lower end of the first capacitor is grounded; The first output resistor (Ro) has its upper end connected to the load voltage and its lower end grounded.

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