Touch display detection chip series connection synchronization device and touch display device

Abstract

A touch display detection chip series synchronization device includes a master detection chip and a slave detection chip. The master detection chip includes a first phase-locked loop connected to a first clock signal input pin; a first frequency divider connected to the output of the first phase-locked loop; and a first synchronous register connected to the output of the first frequency divider and a first start signal input pin. The slave detection chip includes a second phase-locked loop connected to a second clock signal input pin; a second frequency divider connected to the output of the second phase-locked loop; and a second register connected to the output of the second frequency divider and a second start signal input pin.

Description

Technical Field

[0001] The present invention relates to the technical field of touch display detection, and particularly to a touch display detection chip series synchronization device and a touch display device. Background Art

[0002] In known patent documents, such as the touch screen detection chip combination and terminal device with the Chinese patent publication number CN210037999 U, it has been disclosed that a series-connected main detection chip and slave detection chips are applied to a touch screen. As Figure 1 shown in the schematic diagram of the existing touch screen detection, wherein the main detection chip 1 and the slave detection chip 2 are both chips of the same specification, and they use the master / slave configuration selection to play different roles. For example, when the M / S pins of chips 1 and 2 are at the power supply potential, these chips 1 and 2 are configured as the main detection chip 1, and when the M / S pins of chips 1 and 2 are at the ground potential, then these chips are configured as the slave detection chip 2. In addition, since a touch screen 5 is detected by two separate chips 1 and 2, the main detection chip 1 and the slave detection chip 2 need to communicate through a clock signal (CLK) and a start signal (Start) to achieve the state of simultaneously starting to detect the touch screen 5.

[0003] To achieve synchronization between the main detection chip 1 and the slave detection chip 2, as Figure 1 shown, the main detection chip 1 respectively sends the clock signal and the start signal to the main detection chip 1 and the slave detection chip 2 via wires 12, 11 and wires 22, 21 provided on a flexible printed circuit (FPC), and phase-locked loops PLL are respectively provided in the main detection chip 1 and the slave detection chip 2 to provide a frequency-up conversion function for frequency-raising the low-speed clock signals received by the main detection chip 1 and the slave detection chip 2 respectively, so that the main detection chip 1 and the slave detection chip 2 can respectively use the frequency-raised frequency as the system clock to drive their respective microcontrollers MCU to perform touch detection.

[0004] Figure 2A Show a timing diagram of the foregoing existing touch screen detection, wherein Main_clk_m is the system clock output by the phase-locked loop of the main detection chip 1, Main_clk_s is the system clock output by the phase-locked loop of the slave detection chip 2, Scan_start_m is the start signal of the main detection chip 1, and Scan_start_s is the start signal of the slave detection chip 2. As Figure 2AAs shown by the dashed arrows 201 and 202, when the rising edge or falling edge of the system clocks Main_clk_m and Main_clk_s can stably and correctly strike and read the start signals Scan_start_m and Scan_start_s, the system is in a synchronous state.

[0005] However, in actual applications, due to errors in the material and line width of the wires 21 and 11 themselves, variations in the load of the printed circuit flexible board, and differences in the phase delays of the phase-locked loops (PLLs) in the master and slave detection chips 1 and 2, the phase relationship among the system clock Main_clk_m of the master detection chip 1, the system clock Main_clk_s of the slave detection chip 2, the start signal Scan_start_m of the master detection chip 1, and the start signal Scan_start_s of the slave detection chip 2 becomes unpredictable. Refer to Figure 2B Figure 5 shows another timing diagram of the aforementioned existing touch screen detection, which illustrates that the rising edge or falling edge of the system clocks Main_clk_m and Main_clk_s cannot stably and correctly strike and read the start signals Scan_start_m and Scan_start_s, thus resulting in jitter of the system clock and start signals, causing the system to be in an asynchronous state. Among them, as Figure 2B shown, the solid line of the waveform represents the original ( Figure 2A ) timing, while the dashed line of the waveform represents the system clock Main_clk_m of the jittery master detection chip 1, the system clock Main_clk_s of the slave detection chip 2, the start signal Scan_start_m of the master detection chip 1, and the start signal Scan_start_s of the slave detection chip 2. Among them, the rising edge of the system clock Main_clk_m of the master detection chip 1 may be advanced due to jitter (as shown by the dashed rising edge 203), while the start signal Scan_start_m of the master detection chip 1 is delayed in rising due to jitter (as shown by the dashed rising edge 204), resulting in the system clock Main_clk_m of the master detection chip 1 being unable to correctly strike the start signal Scan_start_m of the master detection chip 1 (as shown by the dashed arrow 205), but having to wait until the rising edge of the next system clock Main_clk_m to correctly strike the start signal Scan_start_m (as shown by the dashed arrow 206). However, before that, the system clock Main_clk_s of the slave detection chip 2 has already struck the start signal Scan_start_s of the slave detection chip 2 (as shown by the dashed arrow 207), thus failing to achieve synchronization, causing an error in the touch detection start timing. Therefore, noise will be generated during touch, and in severe cases, it will lead to incorrect touch discrimination.

[0006] Therefore, there are still many deficiencies in the series synchronization design of existing touch display detection chips, and it is necessary to improve them. Summary of the Invention

[0007] The main object of the present invention is to provide a touch display detection chip series synchronization device and a touch display device, which can achieve a synchronization effect by means of low-cost and high-tolerance technologies, and can reduce the occurrence of non-synchronization caused by external factors.

[0008] According to a feature of the present invention, a touch display detection chip series synchronization device is proposed, which includes a main detection chip and a slave detection chip. The main detection chip includes: a first start signal output pin; a first start signal input pin connected to the first start signal output pin via an external wire; a first clock signal output pin; a first clock signal input pin connected to the first clock signal output pin via an external wire; a first phase-locked loop having an input connected to the first clock signal input pin and an output; a first frequency divider having an input connected to the output of the first phase-locked loop and an output; a first start register having a data input connected to the clock signal input by the first clock signal input pin and a data output connected to the first start signal output pin; and a first synchronization register having a clock input connected to the output of the first frequency divider, a data input connected to the first start signal input pin, and a data output. The slave detection chip includes: a second start signal input pin connected to the first start signal output pin via an external wire; a second clock signal input pin connected to the first clock signal output pin via an external wire; a second phase-locked loop having an input connected to the second clock signal input pin and an output; a second frequency divider having an input connected to the output of the second phase-locked loop and an output; and a second synchronization register having a clock input connected to the output of the second frequency divider, a data input connected to the second start signal input pin, and a data output.

[0009] According to another feature of the present invention, a touch display detection chip series synchronization device is provided, which includes a main detection chip and a slave detection chip. The main detection chip includes: a first start signal output pin; a first start signal input pin connected to the first start signal output pin via an external wire; a first clock signal output pin; a first clock signal input pin connected to the first clock signal output pin via an external wire; a first phase-locked loop having an input connected to the first clock signal input pin and an output; a first start register having a data input connected to the clock signal input by the first clock signal input pin and a data output connected to the first start signal output pin; a first pre-stage synchronization register having a clock input connected to the clock signal input by the first clock signal input pin, a data input connected to the start signal input by the first start signal input pin, and a data output; and a first post-stage synchronization register having a clock input connected to the output of the first phase-locked loop, a data input connected to the data output of the first pre-stage synchronization register, and a data output. The slave detection chip includes: a second start signal input pin connected to the first start signal output pin via an external wire; a second clock signal input pin connected to the first clock signal output pin via an external wire; a second phase-locked loop having an input connected to the second clock signal input pin and an output; a second pre-stage synchronization register having a clock input connected to the clock signal input by the second clock signal input pin, a data input connected to the start signal input by the second start signal input pin, and a data output; and a second post-stage synchronization register having a clock input connected to the output of the second phase-locked loop, a data input connected to the data output of the second pre-stage synchronization register, and a data output.

[0010] According to another feature of the present invention, a touch display device is provided, which includes a touch screen and a touch display detection chip series synchronization device. The touch display detection chip series synchronization device is connected to the touch screen to perform touch detection on the touch screen. The touch display detection chip series synchronization device includes a main detection chip and a slave detection chip. The main detection chip includes: a first start signal output pin; a first start signal input pin connected to the first start signal output pin via an external wire; a first clock signal output pin; a first clock signal input pin connected to the first clock signal output pin via an external wire; a first phase-locked loop having an input connected to the first clock signal input pin and an output for outputting a first system clock; a first microcontroller connected to the output of the first phase-locked loop and driven by the first system clock to perform touch detection; a first frequency divider having an input connected to the output of the first phase-locked loop and an output; a first start register having a data input connected to the clock signal input by the first clock signal input pin and a data output connected to the first start signal output pin; and a first synchronization register having a clock input connected to the output of the first frequency divider, a data input connected to the first start signal input pin, and a data output. The slave detection chip includes: a second start signal input pin connected to the first start signal output pin via an external wire; a second clock signal input pin connected to the first clock signal output pin via an external wire; a second phase-locked loop having an input connected to the second clock signal input pin and an output for outputting a second system clock; a second microcontroller connected to the output of the second phase-locked loop and driven by the second system clock to perform touch detection; a second frequency divider having an input connected to the output of the second phase-locked loop and an output; and a second synchronization register having a clock input connected to the output of the second frequency divider, a data input connected to the second start signal input pin, and a data output.

[0011] According to another feature of the present invention, a touch display device is provided, which includes a touch screen and a touch display detection chip series synchronization device. The touch display detection chip series synchronization device is connected to the touch screen to perform touch detection on the touch screen. The touch display detection chip series synchronization device includes a main detection chip and a slave detection chip. The main detection chip includes: a first start signal output pin; a first start signal input pin connected to the first start signal output pin via an external wire; a first clock signal output pin; a first clock signal input pin connected to the first clock signal output pin via an external wire; a first phase-locked loop having an input connected to the first clock signal input pin and an output for outputting a first system clock; a first microcontroller connected to the output of the first phase-locked loop and driven by the first system clock to perform touch detection; a first start register having a data input connected to the clock signal input by the first clock signal input pin and a data output connected to the first start signal output pin; a first pre-stage synchronization register having a clock input connected to the clock signal input by the first clock signal input pin, a data input connected to the start signal input by the first start signal input pin, and a data output; and a first post-stage synchronization register having a clock input connected to the output of the first phase-locked loop, a data input connected to the data output of the first pre-stage synchronization register, and a data output. The slave detection chip includes: a second start signal input pin connected to the first start signal output pin via an external wire; a second clock signal input pin connected to the first clock signal output pin via an external wire; a second phase-locked loop having an input connected to the second clock signal input pin and an output for outputting a second system clock; a second microcontroller connected to the output of the second phase-locked loop and driven by the second system clock to perform touch detection; a second pre-stage synchronization register having a clock input connected to the clock signal input by the second clock signal input pin, a data input connected to the start signal input by the second start signal input pin, and a data output; and a second post-stage synchronization register having a clock input connected to the output of the second phase-locked loop, a data input connected to the data output of the second pre-stage synchronization register, and a data output.

[0012] The above summary and the following detailed description are exemplary in nature and are intended to further illustrate the scope of the patent application of the present invention. Other objects and advantages of the present invention will be described in the subsequent description and drawings. Brief Description of the Drawings

[0013] Figure 1 It is a schematic diagram of the existing touch screen detection.

[0014] Figure 2A Show a timing diagram of existing touch screen detection.

[0015] Figure 2B Show another timing diagram of existing touch screen detection.

[0016] Figure 3 Schematic diagram of an embodiment of the touch display device of the present invention.

[0017] Figure 4 Reference timing diagram of the touch display detection chip series synchronization device of the present invention.

[0018] Figure 5 Show the circuit structure of a frequency divider according to an embodiment of the present invention.

[0019] Figure 6 is Figure 5 The operation waveform diagram of the frequency divider.

[0020] Figure 7 Schematic diagram showing another embodiment of the touch display detection chip series synchronization device of the present invention.

[0021] In the figure, the main detection chip 1, 31

[0022] The slave detection chip 2, 32

[0023] The touch screen 5, 35

[0024] Wires 11, 12, 21, 22

[0025] The start signal output pin Start_out

[0026] The start signal input pin Start_in

[0027] The clock signal output pin CLK_out

[0028] The clock signal input pin CLK_in

[0029] Phase-locked loop PLL

[0030] Microcontroller MCU

[0031] Dashed arrows 201, 202, 205, 206, 207

[0032] Rising edges 203, 204

[0033] Touch display detection chip series synchronization device 30

[0034] Frequency divider DIV

[0035] Registers REG_sync, REG_sync1, REG_sync2, REG_start

[0036] Clock inputs 315, 315-1, 315-2, 325, 325-1, 325-2

[0037] Data inputs 313, 316, 316-1, 316-2, 326, 326-1, 326-2

[0038] Data outputs 314, 317, 317-1, 317-2, 327, 327-1, 327-2

[0039] Fixed latency time FL

[0040] Adjustable tolerance range PM

[0041] JK flip-flops 501, 502, 503 Detailed implementation

[0042] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the implementation of the present invention and are not used to limit the present invention.

[0043] Figure 3 The figure shows a schematic diagram of the touch display device of the present invention. The touch display device includes a touch screen 35 and a touch display detection chip series synchronization device 30. The touch display detection chip series synchronization device 30 is connected to the touch screen 35 to perform touch detection on the touch screen 5. Among them, the touch display detection chip series synchronization device 30 includes a main detection chip 31 and at least one slave detection chip 32. The main detection chip 31 and at least one slave detection chip 32 communicate with each other through a clock signal (CLK) and a start signal (Start) to achieve the state of simultaneously starting to detect the touch screen 35. In addition, in the description of the present invention, it is taken as an example that the touch display detection chip series synchronization device 30 includes a main detection chip 31 and a slave detection chip 32 for easy understanding, but the present invention is not limited thereto. That is to say, two or more detection chips, one main detection chip and one or more slave detection chips, or other suitable configuration methods can be used according to the needs.

[0044] In an embodiment of the present invention, the main detection chip 31 has a start signal output pin Start_out, a start signal input pin Start_in, a clock signal output pin CLK_out, a clock signal input pin CLK_in, a phase-locked loop PLL, a frequency divider DIV, a start register REG_start, a synchronization register REG_sync, and a microcontroller MCU. The slave detection chip 32 has the same structure as the main detection chip 31. The slave detection chip 32 also has a start signal output pin Start_out, a start signal input pin Start_in, a clock signal output pin CLK_out, a clock signal input pin CLK_in, a phase-locked loop PLL, a frequency divider DIV, a start register REG_start, a synchronization register REG_sync, and a microcontroller MCU.

[0045] In the aforementioned main detection chip 31, the data input 313 of the start register REG_start is connected to the clock signal input by the clock signal input pin CLK_in. The data output 314 of the start register REG_start is connected to the start signal output pin Start_out to output a start signal to the start signal output pin Start_out. Therefore, the start signal output of the main detection chip 31 is of the same frequency as its clock signal input. The input of the phase-locked loop PLL is connected to the clock signal input pin CLK_in, the output of the phase-locked loop PLL is connected to the microcontroller MCU, the input of the frequency divider DIV is connected to the output of the phase-locked loop PLL, and the output of the frequency divider DIV is connected to the clock input 315 of the synchronization register REG_sync. The data input 316 of the synchronization register REG_sync is connected to the start signal input pin Start_in to generate a synchronization output signal Sync_out at the data output 317 according to the output of the frequency divider DIV. Among them, the synchronization output signal Sync_out of the main detection chip 31 is of the same frequency as the output of its phase-locked loop PLL. In an embodiment, the aforementioned synchronization register REG_sync or start register REG_start can be a flip-flop circuit, for example, it can be implemented by an RS flip-flop, a D flip-flop, a JK flip-flop, a T flip-flop, etc.

[0046] Similarly, in the aforementioned detection chip 32, the input of the phase-locked loop PLL is connected to the clock signal input pin CLK_in, the output of the phase-locked loop PLL is connected to the microcontroller MCU, the input of the frequency divider DIV is connected to the output of the phase-locked loop PLL, and the output of the frequency divider DIV is connected to the clock input 325 of the synchronous register REG_sync. The data input 326 of the synchronous register REG_sync is connected to the start signal input pin Start_in to generate a synchronous output signal Sync_out at the data output 327 according to the output of the frequency divider DIV. Among them, the synchronous output signal Sync_out of the detection chip 32 has the same frequency as the output of its phase-locked loop PLL. In an embodiment, the aforementioned synchronous register REG_sync can be a flip-flop circuit, for example, it can be implemented by an RS flip-flop, a D flip-flop, a JK flip-flop, a T flip-flop, etc.

[0047] The start signal output pin Start_out of the main detection chip 31 is connected to the middle area between the main detection chip 31 and the adjacent slave detection chip 32, and is respectively connected to the start signal input pin Start_in of the main detection chip 31 and the start signal input pin Start_in of the slave detection chip 32. Thus, the start signal output from the start signal output pin Start_out of the main detection chip 31 is sent to the start signal input pin (Start_in) of the main detection chip 31 and the start signal input pin (Start_in) of the slave detection chip 32 via the wire 22 and the wire 21 on the flexible printed circuit (FPC) disposed outside the main and slave detection chips 31, 32. Similarly, the clock signal output pin (CLK_out) of the main detection chip 31 is connected to the middle area between the main detection chip 31 and the adjacent slave detection chip 32, and is respectively connected to the clock signal input pin CLK_in of the main detection chip 31 and the clock signal input pin CLK_in of the slave detection chip 32. Thus, the clock signal output from the clock signal output pin CLK_out of the main detection chip 31 is sent to the clock signal input pin (CLK_in) of the main detection chip 31 and the clock signal input pin CLK_in of the slave detection chip 32 via the wire 12 and the wire 11 on the flexible printed circuit (FPC) disposed outside the main and slave detection chips 31, 32. Accordingly, the start signal output of the slave detection chip 32 has the same frequency as its clock signal input.

[0048] With the structures of the main detection chip 31 and the slave detection chip 32 of the present invention, refer to Figure 4The timing diagram shown, where CLK_in is the clock signal input to the phase-locked loop PLL, Main_clk_out is the clock output by the phase-locked loop PLL, Main_clk_out / n is the divided clock output by the divider DIV, Start_in is the input start signal, Sync_out is the synchronous output signal generated by the register (REG). Among them, since Main_clk_out / n is obtained by digitally dividing Main_clk_out by the divider DIV (n is an integer greater than 1), so Main_clk_out / n and Main_clk_out belong to the same time domain. Based on the characteristics of the phase-locked loop PLL, since there is a fixed magnification (i.e., Main_clk_out = p × CLK_in, p is an integer greater than 1) and a fixed latency FL between the clock signal (CLK_in) input to the phase-locked loop PLL and the clock Main_clk_out output by the phase-locked loop (PLL), the programmable margin PM is used to complete the synchronization of the cascading technology.

[0049] Please refer to again Figure 3 , the clock signal output from the clock signal output pin CLK_out of the main detection chip 31 is respectively input to the phase-locked loop PLL of the main detection chip 31 and the phase-locked loop PLL of the slave detection chip 32 via the clock signal input pin CLK_in of the main detection chip 31 and the clock signal input pin CLK_in of the slave detection chip 32. The start signal output from the start signal output pin Start_out of the main detection chip 31 is respectively input to the synchronous register REG_sync of the main detection chip 31 and the synchronous register REG_sync of the slave detection chip 32 via the start signal input pin Start_in of the main detection chip 31 and the start signal input pin Start_in of the slave detection chip 32.

[0050] In the main detection chip 31, the phase-locked loop PLL generates the system clock Main_clk_out (= p × CLK_in) according to the input clock signal (CLK_in). The system clock Main_clk_out then generates the divided clock Mclk_n (= Main_clk_out / n) via the frequency divider DIV. The divided clock Mclk_n is input to the clock input 315 of the synchronous register REG_sync, and then triggers the start signal Start_in to be synchronized, thereby achieving the synchronization effect. Similarly, in the slave detection chip 32, the phase-locked loop generates the system clock Main_clk_out (= p × CLK_in) according to the input clock signal CLK_in. The system clock Main_clk_out then generates the divided clock Mclk_n (= Main_clk_out / n) via the frequency divider DIV. The divided clock Mclk_n is input to the clock input 325 of the synchronous register REG_sync, and then triggers the start signal Start_in to be synchronized, thereby achieving the synchronization effect.

[0051] The aforementioned frequency divider DIV can be implemented by at least one flip flop, and the frequency division effect is achieved by the characteristic that the flip flop has two stable states. Figure 5 Shows the circuit structure of a frequency divider (DIV) according to an embodiment of the present invention. Among them, this frequency divider DIV is composed of m JK flip flops, where m is an integer greater than 1. The figure shows a first JK flip flop 501, a second JK flip flop 502, and a third JK flip flop 503. The J inputs and K inputs of all JK flip flops are connected to a high potential. The signal S to be frequency-divided (such as the system clock Main_clk_out) is input to the clock terminal CK of the first JK flip flop 501. The Q1 output of the first JK flip flop 501 serves as a first frequency-divided output and is connected to the clock terminal CK of the second JK flip flop 502; the Q2 output of the second JK flip flop 502 serves as a second frequency-divided output and is connected to the clock terminal CK of the third JK flip flop 503; the Q3 output of the third JK flip flop 503 serves as a third frequency-divided output and can be connected to the clock terminal CK of the next-stage JK flip flop by analogy. Taking this frequency divider DIV as an example, as Figure 6 shown in the waveform diagram, frequency division operations such as dividing by 2, dividing by 4, and dividing by 8 can be performed on the signal S to be frequency-divided, and the frequency-divided signals, such as Q1, Q2, and Q3, can be obtained.

[0052] The touch display detection chip series synchronization device of this embodiment respectively uses the phase-locked loops of the master detection chip and the slave detection chip to generate the system clock main_clk_out, and then uses a frequency division circuit implemented by at least one flip-flop to generate the frequency-divided clock Mclk_n. By tapping the start signal Start_in that needs to be synchronized, the synchronization effect is achieved. Among them, the register circuit REG can be controlled to tap at the positive edge or the negative edge. The device can set a single clock domain internally, which can be easily controlled by an EDA tool (such as prime-time) during the design phase to ensure the correct timing. The single clock domain defines that Main_clk_out is n times the frequency of Mclk_n, and the two belong to the same clock domain group. The delay of the external printed circuit flexible board (FPC) can be adjusted by selecting different frequency division ratios through the multiplication ratio relationship of the phase-locked loop PLL and the frequency divider DIV, thereby improving the tolerance. The internal signals Sync_out of the master and slave chips are stable synchronization start signals.

[0053] Figure 7 FIG. shows a schematic diagram of another embodiment of the touch display detection chip series synchronization device of the present invention. Among them, the touch display detection chip series synchronization device 30 includes a master detection chip 31 and at least one slave detection chip 32. The master detection chip 31 has a start signal output pin Start_out, a start signal input pin Start_in, a clock signal output pin CLK_out, a clock signal input pin CLK_in, a phase-locked loop PLL, a start register REG_start, a pre-stage synchronization register REG_sync1, a post-stage synchronization register REG_sync2, and a microcontroller MCU. The slave detection chip 32 has the same structure as the master detection chip 31. The slave detection chip 32 also has a start signal output pin Start_out, a start signal input pin Start_in, a clock signal output pin CLK_out, a clock signal input pin CLK_in, a phase-locked loop PLL, a start register REG_start, a pre-stage synchronization register REG_sync1, a post-stage synchronization register REG_sync2, and a microcontroller MCU.

[0054] The difference between this embodiment and the previous one is that the main detection chip 31 or the slave detection chip 32 has two synchronous registers (the pre-stage synchronous register REG_sync1 and the post-stage synchronous register REG_sync2), rather than just a single synchronous register. Therefore, the following description will focus on this difference, and the operations of the remaining identical parts (the start signal output pin Start_out, the start signal input pin Start_in, the clock signal output pin CLK_out, the clock signal input pin CLK_in, the start register REG_start, and the microcontroller MCU) can be learned from the description of the previous embodiment, so they will not be elaborated here.

[0055] In the aforementioned main detection chip 31, the input of the phase-locked loop PLL is connected to the clock signal input pin CLK_in. The clock input 315-1 of the pre-stage synchronous register REG_sync1 is connected to the clock signal input from the clock signal input pin CLK_in. The data input 316-1 of the pre-stage synchronous register REG_sync1 is connected to the start signal input from the start signal input pin Start_in. The data output 317-1 of the pre-stage synchronous register REG_sync1 is connected to the data input 316-2 of the post-stage synchronous register REG_sync2. The clock input 315-2 of the post-stage synchronous register REG_sync2 is connected to the output of the phase-locked loop PLL. Accordingly, the pre-stage synchronous register REG_sync1 generates a preliminary synchronous output signal Sync_out_s based on the clock signal input to the clock signal input pin CLK_in and inputs it to the post-stage synchronous register REG_sync2. Then, the post-stage synchronous register REG_sync2 generates a synchronous output signal Sync_out at the data output 317-2 based on the output of the phase-locked loop PLL. Among them, the preliminary synchronous output signal Sync_out_s and the clock signal output from the clock signal output pin CLK_out are of the same frequency, and the synchronous output signal Sync_out and the output of the phase-locked loop PLL are of the same frequency.

[0056] Similarly, in the aforementioned detection chip 32, the input of the phase-locked loop PLL is connected to the clock signal input pin CLK_in. The clock input 325-1 of the pre-stage synchronous register REG_sync1 is connected to the clock signal input by the clock signal input pin CLK_in. The data input 326-1 of the pre-stage synchronous register REG_sync1 is connected to the start signal input by the start signal input pin Start_in. The data output 327-1 of the pre-stage synchronous register REG_sync1 is connected to the data input 326-2 of the post-stage synchronous register REG_sync2. The clock input 325-2 of the post-stage synchronous register REG_sync2 is connected to the output of the phase-locked loop PLL. Accordingly, the pre-stage synchronous register REG_sync1 generates a primary synchronous output signal Sync_out_s according to the clock signal input to the clock signal input pin CLK_in and inputs it to the post-stage synchronous register REG_sync2. Then, the post-stage synchronous register REG_sync2 generates a synchronous output signal Sync_out at the data output 327-2 according to the output of the phase-locked loop PLL. Among them, the primary synchronous output signal Sync_out_s and the clock signal output by the clock signal output pin CLK_out are of the same frequency, and the synchronous output signal Sync_out and the output of the phase-locked loop PLL are of the same frequency.

[0057] In this embodiment, the pre-stage synchronous register REG_sync1 and the post-stage synchronous register REG_sync2 are used to perform two-stage clock synchronization processing, thereby replacing the frequency division function of the frequency divider DIV and achieving the synchronization effect.

[0058] The above embodiments are only examples for convenience of description. The scope of the rights claimed in the present invention shall be subject to what is described in the patent application scope, rather than being limited to the above embodiments.

Claims

1. A touch display detection chip series synchronization device, comprising: A main detection chip, comprising: A first start signal output pin; A first start signal input pin, connected to the first start signal output pin via an external wire; A first clock signal output pin; A first clock signal input pin, connected to the first clock signal output pin via an external wire; A first phase-locked loop, having an input connected to the first clock signal input pin and an output; A first frequency divider, having an input connected to the output of the first phase-locked loop and an output; A first start register, having a data input connected to the clock signal input by the first clock signal input pin and a data output connected to the first start signal output pin; and A first synchronization register, having a clock input connected to the output of the first frequency divider, a data input connected to the first start signal input pin, and a data output; and A slave detection chip, comprising: A second start signal input pin, connected to the first start signal output pin via an external wire; A second clock signal input pin, connected to the first clock signal output pin via an external wire; A second phase-locked loop, having an input connected to the second clock signal input pin and an output; A second frequency divider, having an input connected to the output of the second phase-locked loop and an output; and A second synchronization register, having a clock input connected to the output of the second frequency divider, a data input connected to the second start signal input pin, and a data output.

2. The touch display detection chip series connection synchronization device as described in claim 1, wherein, The clock signal output from the first clock signal output pin is respectively input to the first phase-locked loop and the second phase-locked loop via the first clock signal input pin and the second clock signal input pin; the start signal output from the first start signal output pin is respectively input to the first synchronization register and the second synchronization register via the first start signal input pin and the second start signal input pin.

3. The touch display detection chip series synchronization device according to claim 2, wherein, The first phase-locked loop generates a first system clock based on the clock signal input by the first clock signal input pin; the second phase-locked loop generates a second system clock based on the clock signal input by the second clock signal input pin.

4. The touch display detection chip series synchronization device according to claim 3, wherein, The first frequency divider divides the frequency of the first system clock to generate a first post-frequency division clock; the second frequency divider divides the frequency of the second system clock to generate a second post-frequency division clock.

5. The touch display detection chip series synchronization device as described in claim 4, wherein, The first post-frequency division clock is input to the clock input of the first synchronization register to trigger the start signal input by the first start signal input pin; the second post-frequency division clock is input to the clock input of the second synchronization register to trigger the start signal input by the second start signal input pin.

6. The touch display detection chip series synchronization device as described in claim 5, wherein, The first synchronization register generates a synchronization output signal based on the output of the first frequency divider at the data output of the first synchronization register; the second synchronization register generates a synchronization output signal based on the output of the second frequency divider at the data output of the second synchronization register.

7. The touch display detection chip series synchronization device according to claim 3, wherein, The main detection chip further includes a first microcontroller. The output of the first phase-locked loop is connected to the first microcontroller, and the first microcontroller is driven by the first system clock to perform touch detection. The slave detection chip further includes a second microcontroller. The output of the second phase-locked loop is connected to the second microcontroller, and the second microcontroller is driven by the second system clock to perform touch detection.

8. The touch display detection chip series synchronization device according to claim 1, wherein, The first start register, the first synchronization register, and the second synchronization register are respectively a flip-flop circuit.

9. The touch display detection chip series synchronization device according to claim 1, wherein, The first frequency divider and the second frequency divider are respectively composed of at least one JK flip-flop.

10. A touch display detection chip series synchronization device, comprising: A main detection chip, including: A first start signal output pin; A first start signal input pin, connected to the first start signal output pin via an external wire; A first clock signal output pin; A first clock signal input pin, connected to the first clock signal output pin via an external wire; A first phase-locked loop, having an input connected to the first clock signal input pin and an output; A first start register, having a data input connected to the clock signal input by the first clock signal input pin and a data output connected to the first start signal output pin; A first pre-stage synchronization register, having a clock input connected to the clock signal input by the first clock signal input pin, a data input connected to the start signal input by the first start signal input pin, and a data output; and A first post-stage synchronization register, having a clock input connected to the output of the first phase-locked loop, a data input connected to the data output of the first pre-stage synchronization register, and a data output; and A slave detection chip, including: A second start signal input pin, connected to the first start signal output pin via an external wire; A second clock signal input pin, connected to the first clock signal output pin via an external wire; A second phase-locked loop, having an input connected to the second clock signal input pin and an output; A second pre-stage synchronization register, having a clock input connected to the clock signal input by the second clock signal input pin, a data input connected to the start signal input by the second start signal input pin, and a data output; and A second post-stage synchronization register, having a clock input connected to the output of the second phase-locked loop, a data input connected to the data output of the second pre-stage synchronization register, and a data output.

11. The touch display detection chip series synchronization device according to claim 10, wherein, The main detection chip further includes a first microcontroller. The output of the first phase-locked loop is connected to the first microcontroller, and the first microcontroller is driven by the first system clock generated by the first phase-locked loop to perform touch detection. The slave detection chip further includes a second microcontroller. The output of the second phase-locked loop is connected to the second microcontroller, and the second microcontroller is driven by the second system clock generated by the second phase-locked loop to perform touch detection.

12. A touch display device includes a touch screen and a touch display detection chip series synchronization device. The touch display detection chip series synchronization device is connected to the touch screen to perform touch detection on the touch screen. The touch display detection chip series synchronization device includes: A main detection chip, including: A first start signal output pin; A first start signal input pin, connected to the first start signal output pin via an external wire; A first clock signal output pin; A first clock signal input pin, connected to the first clock signal output pin via an external wire; A first phase-locked loop having an input connected to the first clock signal input pin and an output for outputting a first system clock; A first microcontroller connected to the output of the first phase-locked loop and driven by the first system clock to perform touch detection; A first frequency divider having an input connected to the output of the first phase-locked loop and an output; A first start register having a data input connected to the clock signal input by the first clock signal input pin and a data output connected to the first start signal output pin; and A first synchronization register having a clock input connected to the output of the first frequency divider, a data input connected to the first start signal input pin, and a data output; and A slave detection chip, including: A second start signal input pin, connected to the first start signal output pin via an external wire; A second clock signal input pin, connected to the first clock signal output pin via an external wire; A second phase-locked loop having an input connected to the second clock signal input pin and an output for outputting a second system clock; A second microcontroller connected to the output of the second phase-locked loop and driven by the second system clock to perform touch detection; A second frequency divider having an input connected to the output of the second phase-locked loop and an output; and A second synchronization register having a clock input connected to the output of the second frequency divider, a data input connected to the second start signal input pin, and a data output.

13. A touch display device includes a touch screen and a touch display detection chip series synchronization device. The touch display detection chip series synchronization device is connected to the touch screen to perform touch detection on the touch screen. The touch display detection chip series synchronization device includes: A main detection chip, including: A first start signal output pin; A first start signal input pin, connected to the first start signal output pin via an external wire; A first clock signal output pin; A first clock signal input pin, connected to the first clock signal output pin via an external wire; A first phase-locked loop having an input connected to the first clock signal input pin and an output for outputting a first system clock; A first microcontroller connected to the output of the first phase-locked loop and driven by the first system clock to perform touch detection; A first start register, having a data input connected to a clock signal input through the first clock signal input pin, and a data output connected to the first start signal output pin; A first pre-stage synchronous register, having a clock input connected to a clock signal input through the first clock signal input pin, a data input connected to a start signal input through the first start signal input pin, and a data output; and A first post-stage synchronous register, having a clock input connected to the output of the first phase-locked loop, a data input connected to the data output of the first pre-stage synchronous register, and a data output; and A slave detection chip, including: A second start signal input pin, connected to the first start signal output pin through an external wire; A second clock signal input pin, connected to the first clock signal output pin through an external wire; A second phase-locked loop, having an input connected to the second clock signal input pin, and an output for outputting a second system clock; A second microcontroller, connected to the output of the second phase-locked loop, and driven by the second system clock to perform touch detection; A second pre-stage synchronous register, having a clock input connected to a clock signal input through the second clock signal input pin, a data input connected to a start signal input through the second start signal input pin, and a data output; and A second post-stage synchronous register, having a clock input connected to the output of the second phase-locked loop, a data input connected to the data output of the second pre-stage synchronous register, and a data output.

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