Instruction transfer prediction systems, methods, apparatus, computer devices, and storage media

Abstract

The application discloses a kind of instruction transfer prediction systems, methods, devices, computer equipment and storage medium, the instruction transfer prediction system includes prediction unit, prediction target address queue and fetch unit;Wherein: the prediction unit is used to carry out multistage branch prediction to transfer instruction;The prediction target address queue is used to record the instruction address of the transfer instruction and the first level prediction result under the condition of receiving first level prediction result, and using the second level prediction result to cover corresponding first level prediction result under the condition of receiving the second level prediction result corresponding to the transfer instruction;The fetch unit is used to obtain target prediction address from the prediction target address queue to carry out corresponding fetch operation. Thus, the prediction unit is separated from the original coupling structure, effectively improving the decoupling effect of prediction unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and particularly relates to an instruction transfer prediction system, method, device, computer equipment and storage medium. BACKGROUND

[0002] In modern high-performance processors, a pipeline can be divided into a front-end processing unit and a back-end processing unit. The front-end processing unit is used to provide instructions that need to be executed to the back-end processing unit, and therefore, the efficiency of the front-end processing unit directly affects the execution speed of the back-end processing unit.

[0003] In the related art, a prediction unit and an instruction fetch unit in the front-end processing unit are decoupled to improve the performance of the front-end processing unit. However, the decoupling effect of the prediction unit with a multi-level branch prediction structure needs to be improved. SUMMARY

[0004] The present application aims to at least solve one of the technical problems in the related art. To this end, a first object of the present application is to provide an instruction transfer prediction system, redesign the logic of directing the instruction address for instruction fetching using the prediction result generated by the prediction unit, and separate the prediction unit from the original coupled structure to improve the decoupling effect of the prediction unit.

[0005] A second object of the present application is to provide an instruction transfer prediction method.

[0006] A third object of the present application is to provide an instruction transfer prediction device.

[0007] A fourth object of the present application is to provide a computer equipment.

[0008] A fifth object of the present application is to provide a computer readable storage medium.

[0009] To achieve the above object, the first aspect of the present application provides a method for instruction transfer prediction, which comprises a prediction unit, a prediction target address queue and an instruction fetch unit, the input end of the prediction target address queue is connected to the output end of the prediction unit, and the output end of the prediction target address queue is connected to the input end of the instruction fetch unit; wherein: the prediction unit is used for multi-level branch prediction of a transfer instruction; the multi-level branch prediction comprises a first level branch prediction and a second level branch prediction; the first level branch prediction is used for branch prediction of the transfer instruction, and a first level prediction result is obtained and output; the second level branch prediction is used for branch prediction of the transfer instruction, and a second level prediction result is obtained and output; wherein, the first level prediction result and the second level prediction result respectively comprise a prediction address corresponding to the transfer instruction; the prediction target address queue is used for recording an instruction address of the corresponding transfer instruction and the first level prediction result when the first level prediction result is received, and the second level prediction result corresponding to the transfer instruction is used to overwrite the corresponding first level prediction result when the second level prediction result is received; the instruction fetch unit is used for obtaining a target prediction address corresponding to a target instruction address from the prediction target address queue, and performing corresponding instruction fetch operation according to the obtained target prediction address.

[0010] According to an embodiment of the present application, the prediction target address queue is further used for deleting a target entry corresponding to the target instruction address and the target prediction address from the prediction target address queue when the instruction fetch unit performs instruction fetch operation according to the obtained target prediction address and obtains a corresponding target instruction block from the first instruction cache space.

[0011] According to an embodiment of the present application, the prediction target address queue is further used for filtering the prediction address corresponding to any instruction address in the prediction target address queue to obtain a prediction address satisfying a pre-fetch condition as a pre-fetch address; wherein, the prediction address satisfying the pre-fetch condition is a prediction address whose corresponding instruction address is located in a different cache line; and the pre-fetch address is used for obtaining a pre-fetch instruction block corresponding to the pre-fetch address from the second instruction cache space.

[0012] According to an embodiment of the present application, the prediction target address queue is further used for returning a table entry index of the corresponding table entry to the prediction unit when recording the instruction address of the corresponding transfer instruction and the first level prediction result to the corresponding table entry of the prediction target address queue, so that the prediction unit writes the corresponding second level prediction result into the corresponding table entry according to the corresponding table entry index.

[0013] According to an embodiment of the present application, the predicted target address queue has a dequeue pointer; and the predicted target address queue is further configured to delete the entry currently pointed to by the dequeue pointer from the predicted target address queue and update the dequeue pointer, in a case that the fetch unit performs a fetch operation according to the predicted address included in the entry currently pointed to by the dequeue pointer and obtains a corresponding instruction block from the first instruction cache space.

[0014] According to an embodiment of the present application, the predicted target address queue has a prefetch pointer; and the predicted target address queue is further configured to return a predicted address included in an entry currently pointed to by the prefetch pointer and a prefetch validity signal corresponding to the predicted address to a processor front end in a case that a prefetch request sent by the processor front end is received, and update the prefetch pointer, so that the processor front end takes the predicted address as a prefetch address in a case that the prefetch validity signal received is a prefetch valid signal, and obtains a prefetch instruction block corresponding to the prefetch address from the second instruction cache space; wherein the prefetch valid signal is used to indicate that the predicted address corresponding to the prefetch valid signal is a predicted address satisfying the prefetch condition.

[0015] According to an embodiment of the present application, the predicted target address queue has an enqueue pointer and a read pointer; and the predicted target address queue is further configured to record an instruction address of the corresponding branch instruction and the first-level prediction result to an entry currently pointed to by the enqueue pointer and update the enqueue pointer in a case that the first-level prediction result is received, and return a predicted address included in an entry currently pointed to by the read pointer to the fetch unit and update the read pointer in a case that a read request of the fetch unit is received.

[0016] To achieve the above object, the second aspect of the present application provides a method for instruction transfer prediction, which is applied to an instruction transfer prediction system, the instruction transfer prediction system comprising a prediction unit, a prediction target address queue and an instruction fetch unit, the input end of the prediction target address queue being connected to the output end of the prediction unit, the output end of the prediction target address queue being connected to the input end of the instruction fetch unit; the prediction unit is used for multi-level branch prediction on a transfer instruction; the multi-level branch prediction comprises a first level branch prediction and a second level branch prediction; the method comprises: the prediction unit performs branch prediction on the transfer instruction through the first level branch prediction to obtain a first level prediction result and output, and performs branch prediction on the transfer instruction through the second level branch prediction to obtain a second level prediction result and output; wherein the first level prediction result and the second level prediction result respectively comprise a prediction address corresponding to the transfer instruction; the prediction target address queue records an instruction address of the corresponding transfer instruction and the first level prediction result when receiving the first level prediction result, and covers the first level prediction result with the second level prediction result when receiving the second level prediction result corresponding to the transfer instruction; the instruction fetch unit acquires a target prediction address corresponding to a target instruction address from the prediction target address queue, and performs corresponding instruction fetch operation according to the acquired target prediction address.

[0017] To achieve the above object, the third aspect of the present application provides a branch prediction device, which is applied to a branch prediction system, the branch prediction system comprises a prediction unit, a prediction target address queue and an instruction fetch unit, the input end of the prediction target address queue is connected to the output end of the prediction unit, and the output end of the prediction target address queue is connected to the input end of the instruction fetch unit; the prediction unit is used for multi-level branch prediction on a branch instruction; the multi-level branch prediction comprises a first level branch prediction and a second level branch prediction; the device comprises: a branch prediction module, which is used for the prediction unit to perform branch prediction on the branch instruction through the first level branch prediction to obtain a first level prediction result and output the first level prediction result, and perform branch prediction on the branch instruction through the second level branch prediction to obtain a second level prediction result and output the second level prediction result; wherein the first level prediction result and the second level prediction result respectively comprise a prediction address corresponding to the branch instruction; a recording module, which is used for the prediction target address queue to record an instruction address of the corresponding branch instruction and the first level prediction result in the case of receiving the first level prediction result, and use the second level prediction result to cover the corresponding first level prediction result in the case of receiving the second level prediction result corresponding to the branch instruction; and a prediction address acquisition module, which is used for the instruction fetch unit to acquire a target prediction address corresponding to a target instruction address from the prediction target address queue, and perform corresponding instruction fetch operation according to the acquired target prediction address.

[0018] To achieve the above object, the fourth aspect of the present application provides a computer device, which comprises a memory and a processor, the memory stores a computer program, and the processor realizes the steps of the branch prediction method according to any one of the preceding embodiments when executing the computer program.

[0019] To achieve the above object, the fifth aspect of the present application provides a computer readable storage medium, which stores a computer program, and the computer program realizes the steps of the branch prediction method according to any one of the preceding embodiments when executed by a processor.

[0020] According to the embodiments of the present application, the directional logic of the instruction flow is redesigned, the program counter address required by the instruction fetch is directly directed using the high level prediction result, the participation of the pre-decoding result is cancelled, the prediction unit with the multi-level prediction cover structure is separated from the original structure, and the decoupling effect of the prediction unit is improved.

[0021] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1a A structure diagram of a front-end processing unit according to the present specification.

[0023] Figure 1b A structure diagram of a front-end processing unit according to the present specification.

[0024] Figure 1c A structure diagram of a decoupled structure of a front-end processing unit according to the present specification.

[0025] Figure 1d A structure diagram of a cache prefetch scheme according to the present specification.

[0026] Figure 1e An application scenario diagram of an instruction transfer prediction system according to an embodiment of the present specification

[0027] Figure 2a A structure diagram of an instruction transfer prediction system according to an embodiment of the present specification.

[0028] Figure 2b A flow diagram of a prediction result writing according to an embodiment of the present specification.

[0029] Figure 3 A flow diagram of an instruction transfer prediction method according to an embodiment of the present specification.

[0030] Figure 4 A structure block diagram of an instruction transfer prediction device according to an embodiment of the present specification.

[0031] Figure 5 A structure block diagram of a computer device according to an embodiment of the present specification. DETAILED DESCRIPTION

[0032] Embodiments of the present application are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the drawings are exemplary and are intended to explain the present application, and cannot be understood as a limitation of the present application.

[0033] In modern high-performance processors, a pipeline can be divided into a front-end processing unit and a back-end processing unit. Referring to Figure 1aAs shown, the front-end processing unit and the back-end processing unit are connected together through an instruction buffer or instruction queue, forming a producer-consumer working model, i.e., the front-end processing unit fills the instruction buffer with instructions to be executed, and the back-end processing unit takes instructions from the instruction buffer and executes them. It can be understood that the speed at which the front-end processing unit fills the instruction buffer with instructions directly affects the execution speed of the back-end processing unit, and thus affects the efficiency of the entire pipeline. Therefore, the efficiency of the front-end processing unit must be improved to provide sufficient instructions for the rich functional components in the back-end of the pipeline.

[0034] In the structure of a conventional pipeline front-end processing unit, referring to Figure 1b As shown, the branch prediction unit takes the content of the current program counter (PC) as input to predict the subsequent instruction address, and updates the PC after the prediction is completed. Meanwhile, the instruction fetch unit accesses the instruction cache according to the PC address, and places the fetched new instruction into the instruction issue queue to send to the decode stage. The prediction unit and the instruction fetch unit are tightly coupled together, and work in close coordination. When the instruction fetch unit stalls due to a cache miss or the like, the prediction unit must also stop predicting; and when the prediction unit makes a prediction error, the instruction fetch unit needs to issue a new memory access address and re-fetch instructions. The tight coupling between the two severely limits the performance improvement of the pipeline front-end structure. At the same time, different optimization techniques for the instruction fetch unit and the prediction unit may interfere with each other, making it difficult to evaluate the effectiveness of the design scheme of the front-end processing unit, and bringing great challenges to the processor front-end designers. Therefore, decoupling the prediction unit and the instruction fetch unit to eliminate the strong correlation between them when working, and to increase the design space of each, is of great significance to improving the performance of the front-end processing unit.

[0035] In the related art, a design scheme of a decoupled structure of a pipeline front-end processing unit is proposed. By analogy with the design idea of decoupling the processor front-end and back-end, a first-in-first-out queue structure, i.e., a fetch target queue (FTQ), is introduced between the prediction unit and the instruction fetch unit, and other structures are adjusted accordingly.

[0036] Referring to Figure 1cAs shown, the FTQ queue is located between the prediction unit and the instruction fetch unit. The prediction unit takes the content in the current Program Counter (PC) as input to predict the subsequent instruction address. After the prediction is completed, the PC is updated and the predicted target address is written to the tail of the FTQ queue; at the same time, the instruction fetch unit fetches the instruction address from the head of the FTQ queue and accesses the instruction cache according to the fetched instruction address to fetch the corresponding instruction and send it to the decoding stage. When the subsequent stages of the pipeline find that the branch prediction is wrong or the program control flow needs to be redirected, the table entries in the FTQ queue are emptied in time, and the instruction fetch unit uses the correct PC content to re-fetch instructions, and the prediction unit uses the correct PC content to make predictions.

[0037] On the one hand, when a branch prediction error occurs, the front-end processing unit needs to be updated quickly to restore it to the correct state, in which the global branch history information in the prediction unit and the address sent to the instruction storage need to be updated. A processing structure for recording historical information on a speculative path, a speculative history queue (SHQ), is proposed in the related art. The SHQ queue saves all the globally updated branch history information during the running of the processor. During prediction, the globally updated history is written to the SHQ queue, and if there is updated global history information in the SHQ queue at this time, the prediction unit replaces the content in the history register with the new global history information to ensure the timeliness and effectiveness of the global history information. When an instruction is completed in the back-end of the pipeline, the actual branch result of the instruction is used to update the global history register, and the corresponding table entry in the SHQ queue is removed; when a prediction error occurs, the history information of the mispredicted branch instruction and all the allocated table entries in the SHQ queue need to be removed from the SHQ queue.

[0038] On the other hand, since the FTQ queue saves the predicted target addresses generated by the prediction unit, and these predicted target addresses are also used as the instruction fetch addresses of the instruction fetch unit, the predicted target addresses in the FTQ queue can be used to access the second-level cache in advance by means of prefetching, thereby reducing the miss rate of the instruction cache. Figure 1d As shown, the related art adds a prefetch instruction queue (PIQ) to implement the cache prefetching scheme based on the FTQ queue. The PIQ queue is used to save all the predicted target addresses in the FTQ queue that are waiting to be prefetched. In order to further ensure the effectiveness of the prefetching, a series of prefetching strategies such as cache probe filtering, filtering based on the number of FTQ table entries, cache miss filtering, instruction block eviction filtering, etc. can also be used for prefetching.

[0039] However, compared with the above processor structure, contemporary high-performance processors have undergone significant changes in microstructure. Among them, the prediction unit no longer uses a single prediction technique, but adopts a multi-level coverage branch prediction structure, that is, multiple branch predictors jointly complete the prediction process, and the results of each level of branch prediction are given at different cycles. And branch prediction is carried out together with instruction fetching, and once a prediction error is found, the instruction stream is immediately redirected, and the resulting instructions are placed in the instruction buffer after all prediction stages are completed, and the information related to the transfer prediction is saved.

[0040] In view of the above characteristics, in the decoupling design of the prediction unit and the instruction fetching unit, the branch predictor with a multi-level coverage prediction structure in the processor needs to be separated from the previous structure to form a prediction unit that can work independently. The difficulty lies in that the advanced branch prediction will combine the type information and the transfer target address information obtained from the instruction fetching unit after the instruction expansion and pre-decoding processing to determine whether the previous prediction result needs to be corrected. The decoupled prediction unit is before the instruction fetching unit and cannot obtain the content of the instruction block, so it cannot perform instruction expansion and pre-decoding, and the redirection logic at this stage needs to be redesigned.

[0041] Secondly, in the related art, the FTQ queue is used as a global data structure to save branch prediction information. In the multi-level coverage branch prediction structure, the branch prediction information is constantly changing, and the update of the predictor state needs to use the prediction result before the instruction. The queue not only needs to record the instruction address sequence used for instruction fetching, but also needs to save the branch prediction result of each instruction block and send it to the subsequent instruction fetching component for transmission to the corresponding pipeline stage for processing. In order to use conveniently, a lot of information is repeatedly recorded and transmitted, resulting in waste of hardware resources.

[0042] Therefore, for contemporary high-performance processors, it is necessary to redesign the decoupling structure of the front-end processing unit. Specifically, it is necessary to make corresponding structural improvements to the branch predictor with a multi-level coverage prediction structure, and to design a new efficient global data structure to record the constantly updated branch prediction information, and to make the information to be saved as little as possible to make full use of hardware resources.

[0043] In order to separate the branch predictor with the multi-level coverage prediction structure from the previous structure in the processor, it is necessary to provide an instruction transfer prediction system, method, device, computer equipment and storage medium. By introducing a structure similar to the FTQ queue, the prediction target address queue PTQ in the front-end processing unit of the processor, responsible for recording the instruction execution sequence generated by the branch prediction. The prediction unit will write the generated each level prediction result to the tail of the PTQ queue, and the instruction fetch unit will read the instruction address used by the instruction fetch from the head of the PTQ queue. Only when the instruction fetch unit successfully reads the corresponding instruction block from the instruction cache, the corresponding instruction address in the PTQ queue can complete the de-queue operation to ensure the normal pipelining of the instruction cache and solve the redirection problem of the instruction fetch unit. A fast recovery mechanism for the multi-level coverage prediction structure is designed in the prediction unit, which directly uses the high-level prediction result to cover the low-level prediction result to realize the redirection of the PC address, without combining the type information and the transfer target address information after the expansion and pre-decoding processing of the instructions obtained from the instruction fetch unit to determine whether the low-level prediction result needs to be corrected. Further, a prefetch pointer is introduced in the PTQ queue to determine whether the corresponding instruction block needs to be prefetched. If it needs to be prefetched, the prefetch pointer is used to read the instruction address to the second instruction cache, thereby optimizing the prefetch mechanism of the instruction cache. Thus, the prediction unit can generate the instruction stream sequence required for the subsequent stage of the pipeline in advance without being affected by the instruction fetch unit, thereby effectively improving the overall working efficiency of the front-end processing unit.

[0044] Figure 1e The application scenario of the instruction transfer prediction system, method, device, computer equipment and storage medium provided in the specification is shown in the schematic diagram. Taking the prediction unit with a three-level coverage prediction structure as an example, the output end of the prediction unit is connected with the input end of the prediction target address queue PTQ, and the output end of the PTQ queue is connected with the input end of the instruction fetch unit. The prediction unit will write the corresponding branch prediction result generated by each level branch prediction to the PTQ queue, and the instruction fetch unit will read the instruction address from the head of the PTQ queue to perform the corresponding instruction fetch operation according to the read instruction address.

[0045] In the present scenario example, the prediction unit does not need to write the prediction result into the PTQ queue after the three-level branch prediction result is generated, but writes the corresponding branch prediction result into the PTQ queue after the branch prediction result of each level is generated, and updates the prediction result in the PTQ queue in real time in an overwriting manner. Specifically, after the first-level prediction result is generated by performing the first-level branch prediction on the transfer instruction, the prediction unit writes the first-level prediction result and the instruction address corresponding to the transfer instruction into the tail of the PTQ queue; after the second-level prediction result is generated by performing the second-level branch prediction on the transfer instruction, the first-level prediction result of the corresponding table item in the PTQ queue is overwritten; after the third-level prediction result is generated by performing the third-level branch prediction on the transfer instruction, the second-level prediction result of the corresponding table item in the PTQ queue is overwritten again. Thus, for the multi-level coverage prediction structure, the write operation of the PTQ queue by the prediction unit also forms a coverage structure, and the prediction result of the subsequent stage with higher accuracy will overwrite the prediction result of the corresponding previous stage, but the instruction address written each time remains unchanged. By redesigning the logic of directing the instruction address used for instruction fetching by using the prediction result generated by the prediction unit, the prediction unit is separated from the original coupled structure, and the decoupling effect of the prediction unit can be improved. Further, by using the overwriting write manner, the pipeline can be quickly redirected in the case that fewer incorrect instructions are executed in the pipeline, so that the pipeline can quickly recover the execution.

[0046] Each table item of the PTQ queue not only saves the instruction address, but also records the transfer prediction information of the corresponding instruction block, and the information is saved all the time. Thus, whether the transfer target address predicted by the branch prediction is consistent with the target address obtained by decoding can be directly compared in the pre-decoding stage, so as to determine whether the unconditional direct transfer instruction successfully changes the instruction execution path of the processor.

[0047] In some embodiments, when the prediction unit writes the first-level prediction result corresponding to the transfer instruction and the corresponding instruction address into the target table item at the tail of the PTQ queue, the PTQ queue returns the table item index of the target table item to the prediction unit, so that when the prediction unit generates the corresponding second-level prediction result by performing the second-level branch prediction on the transfer instruction, the second-level prediction result can be written into the corresponding table item according to the table item index to overwrite the corresponding first-level prediction result; similarly, when the prediction unit generates the corresponding third-level prediction result by performing the third-level branch prediction on the transfer instruction, the third-level prediction result can be written into the corresponding table item according to the table item index to overwrite the corresponding second-level prediction result.

[0048] In the present scenario example, only when the instruction address read from the head of the PTQ queue is sent to the instruction cache space by the instruction fetch unit as a fetch request and the corresponding instruction block is successfully read from the instruction cache space, the instruction address at the head of the PTQ queue can complete the dequeue operation, so that the dequeue operation of the PTQ queue and the fetch request sent to the instruction cache space are distinguished. The instruction fetch unit reads the instruction address from the PTQ queue according to the read pointer and sends it to the instruction cache space.

[0049] In some embodiments, when the accuracy of branch prediction is maintained at a high level, the instruction cache pre-fetch mechanism can be optimized by means of the instruction addresses in the PTQ queue. For example, when the instruction fetch unit fails to obtain the corresponding instruction block from the first-level instruction cache according to the instruction address in the PTQ queue, it needs to be pre-fetched from the second-level instruction cache. Specifically, an additional pre-fetch pointer is introduced in the PTQ to determine whether the instruction block corresponding to the instruction address pointed to by the pre-fetch pointer needs to be pre-fetched. If pre-fetching is needed, the instruction address that needs to be sent to the second-level instruction cache is read by the pre-fetch pointer. When the PTQ queue is initialized, the pre-fetch pointer coincides with the head pointer, and at this time, no pre-fetch request is sent to the second-level instruction cache; as the PTQ queue is dequeued and enqueued, the pre-fetch pointer will continuously move towards the tail of the queue when the second-level instruction cache is idle, and in the process of moving, it checks whether the instruction address in each PTQ entry and the predicted address in the corresponding prediction result are in the same cache line of the first-level instruction cache. If it is found that they are not in the same cache line, the predicted address can be aligned and sent to the second-level instruction cache for pre-fetching.

[0050] In the present scenario example, by evaluating the fullness of the PTQ queue, the results show that the percentage of empty PTQ queue is small, indicating that most of the time in the PTQ queue will exist the instruction execution sequence generated by branch prediction, which indirectly proves that the PTQ queue plays its due role in the front-end decoupled structure based on the PTQ queue, so that the prediction unit can be unaffected by the instruction fetch unit and generate the instruction stream sequence needed for the subsequent stages of the pipeline in advance. Further, the number of instructions emitted into the instruction fetch buffer per cycle is used to measure the overall working efficiency of the front-end decoupled structure based on the PTQ queue. From the evaluation results, the instruction fetch efficiency of the program running after decoupling has been improved to a certain extent. Due to the existence of the PTQ queue, the results of branch prediction are recorded in the PTQ queue, and with the increase of the number of entries in the PTQ queue, the third-level prediction results are also continuously updated in the queue, which ensures that the instruction address sequence in the PTQ queue is mostly the same as the actual instruction sequence of the program running, so that the branch prediction error of the pipeline back-end can be reduced accordingly.

[0051] The present specification embodiment provides an instruction branch prediction system, which refers to Figure 2aAs shown, the instruction transfer prediction system 200 comprises a prediction unit 210, a prediction target address queue 220 and an instruction fetch unit 230, an input end of the prediction target address queue 220 is connected to an output end of the prediction unit 210, and an output end of the prediction target address queue 220 is connected to an input end of the instruction fetch unit 230.

[0052] The prediction unit 210 is configured to perform multi-level branch prediction on the transfer instruction; the multi-level branch prediction comprises first-level branch prediction and second-level branch prediction; the first-level branch prediction is performed on the transfer instruction to obtain and output a first-level prediction result; the second-level branch prediction is performed on the transfer instruction to obtain and output a second-level prediction result; the first-level prediction result and the second-level prediction result each comprise a prediction address corresponding to the transfer instruction.

[0053] The prediction target address queue 220 is configured to record an instruction address of the corresponding transfer instruction and the first-level prediction result in a case where the first-level prediction result is received, and to overwrite the corresponding first-level prediction result with the second-level prediction result in a case where the second-level prediction result corresponding to the transfer instruction is received.

[0054] The instruction fetch unit 230 is configured to acquire a target prediction address corresponding to a target instruction address from the prediction target address queue, and to perform corresponding instruction fetch operation according to the acquired target prediction address.

[0055] The transfer instruction can comprise a branch instruction, an unconditional direct transfer instruction, etc. The prediction unit is a branch predictor with a multi-level coverage prediction structure. The prediction address is a next target address of the corresponding instruction address, and can be a transfer target address when the corresponding transfer instruction is predicted to be transferred. The target instruction address is an instruction address included in a corresponding table entry of the prediction target address queue currently read by the instruction fetch unit. The target prediction address is a prediction address included in a current prediction result in the corresponding table entry of the prediction target address queue currently read by the instruction fetch unit, and can be a prediction address included in the first-level prediction result or a prediction address included in the second-level prediction result.

[0056] It can be understood that the prediction unit can comprise a plurality of branch predictors, the first-level prediction result can be obtained by a first-level predictor, and the second-level prediction result can be obtained by a second-level predictor. The first-level prediction result and the second-level prediction result each comprise information about whether the predicted transfer instruction is transferred and a transfer target address when the predicted transfer instruction is transferred. The accuracy of the second-level prediction result is higher than that of the first-level prediction result.

[0057] In some cases, after the prediction unit is decoupled from the instruction fetch unit, because the prediction unit is located before the instruction fetch unit, higher-level branch prediction cannot obtain the instructions fetched by the instruction fetch unit. Therefore, it cannot combine instruction extension, pre-decoding information, etc., to correct the lower-level branch prediction results, so as to redirect the instruction flow and determine the final transfer target address. Considering all factors, since the accuracy of higher-level branch prediction results can be maintained at a high level even without the guidance of instruction extension, pre-decoding information, etc., the higher-level prediction results can be directly used to overwrite the lower-level prediction results to solve the instruction flow redirection problem. Furthermore, the existing branch predictor with a multi-level overlay prediction structure in the processor can be separated from the previous structure to form a prediction unit that can operate independently. Further, since the prediction results of the multi-level overlay prediction structure are multi-level, if the prediction target address queue is updated after the prediction unit provides the final prediction result, previous prediction results will be lost. Therefore, the prediction target address queue can be updated after the prediction result of each level is generated.

[0058] Specifically, refer to Figure 2b As shown, after the prediction unit performs first-level branch prediction on the current transfer instruction and generates a first-level prediction result, the prediction unit outputs the first-level prediction result to the prediction target address queue for a write operation. This writes the instruction address corresponding to the current transfer instruction and the first-level prediction result to the prediction target address queue. The prediction target address queue records the received instruction address and the first-level prediction result in the current tail entry. After the prediction unit performs second-level branch prediction on the current transfer instruction and generates a second-level prediction result, the prediction unit outputs the second-level prediction result to the prediction target address queue for a write operation. This writes the instruction address corresponding to the current transfer instruction and the second-level prediction result to the prediction target address queue. The prediction target address queue records the received instruction address and the second-level prediction result in the entry where the first-level prediction result corresponding to the current transfer instruction is located, so that the second-level prediction result corresponding to the current transfer instruction overwrites the corresponding first-level prediction result.

[0059] It is understandable that the instruction address written to the prediction target address queue after performing first-level branch prediction and second-level branch prediction on the transfer instructions in the same instruction block remains unchanged. Therefore, when the prediction target address queue records the corresponding instruction address and the second-level prediction result, it is possible to use the second-level prediction result to overwrite the corresponding first-level prediction result.

[0060] It should be noted that multi-level branch prediction includes at least first-level branch prediction and second-level branch prediction. Correspondingly, the prediction results generated by the prediction unit include at least first-level prediction results and second-level prediction results. (Continue to refer to...) Figure 2bAs shown, assuming that the prediction unit includes n-level branch prediction, and accordingly, an n-level prediction result can be generated for the current branch instruction, the n-level prediction result is recorded into the prediction target address queue by the above-mentioned override manner.

[0061] Further, the instruction fetch unit obtains a target prediction address corresponding to the target instruction address in the current head table entry of the prediction target address queue. If the current prediction result corresponding to the target instruction address recorded in the current head table entry of the prediction target address queue is the first-level prediction result, the instruction fetch unit can obtain the corresponding target prediction address from the first-level prediction result; if the current prediction result corresponding to the target instruction address recorded in the current head table entry of the prediction target address queue is the second-level prediction result, the instruction fetch unit can obtain the corresponding target prediction address from the second-level prediction result. According to the obtained target prediction address, the instruction fetch unit can perform corresponding instruction fetch operation in the instruction cache space.

[0062] It should be noted that the instruction address and the prediction address in the present specification can be a program counter address, i.e., a PC address. The prediction address can also be a next target address of the corresponding instruction address formed by sequential addressing in the case where the branch instruction does not branch.

[0063] In the above-mentioned embodiments, the directional logic of the instruction stream is redesigned, the program counter address required by the instruction fetch is directly oriented using the high-level prediction result, the participation of the pre-decoding result is cancelled, the prediction unit with the multi-level prediction override structure is separated from the original structure, and the decoupling effect of the prediction unit is improved. Meanwhile, the new efficient global data structure is used to record the constantly updated and changed branch prediction information, the repeated information is reduced, and the utilization rate of the hardware resources can be improved due to the reduction of the information to be saved.

[0064] In some embodiments, the prediction target address queue is further configured to, in a case where the instruction fetch unit performs the instruction fetch operation according to the obtained target prediction address and obtains the corresponding target instruction block from the first instruction cache space, delete the target table entry in which the corresponding target instruction address and the target prediction address are located from the prediction target address queue.

[0065] The first instruction cache space can include a level one instruction cache. Further, the level one instruction cache can be a cache.

[0066] It can be understood that, since the branch instruction is usually used for the transfer between instruction blocks, the instruction fetch unit performs the corresponding instruction fetch operation according to the target prediction address, and sequentially reads the target prediction address from the position pointed by the target prediction address in the first instruction cache space to obtain the target instruction block corresponding to the target prediction address.

[0067] In some cases, due to the changeable prediction results of the multi-level branch prediction, after the instruction fetch unit performs the corresponding instruction fetch operation according to the target prediction address corresponding to the target instruction address, the target prediction address corresponding to the target instruction address in the target prediction address queue may change to a new prediction address, and the instruction fetch unit needs to re-fetch. In order to ensure the normal pipelining of the instruction cache and solve the redirection problem of the instruction fetch unit, the dequeuing operation of the target prediction address queue and the instruction fetch request sent to the first instruction cache space can be separated.

[0068] Specifically, the target instruction address and the target instruction address recorded in the same target entry of the target prediction address queue. The instruction fetch unit obtains the target prediction address corresponding to the target instruction address from the target entry of the target prediction address queue, and then sends an instruction fetch request to the first instruction cache space according to the obtained target prediction address, to perform the corresponding instruction fetch operation. When the instruction fetch unit successfully obtains the target instruction block corresponding to the target prediction address from the first instruction cache space, the content in the target entry in the target prediction address queue can be deleted to complete the dequeuing operation of the target entry.

[0069] In some embodiments, the instruction block stored in the first instruction cache space can include an instruction block pre-fetched from an instruction cache space with a lower priority than the first instruction cache space through a pre-fetch operation.

[0070] In other embodiments, the first instruction cache space can further include a pre-fetch instruction cache space, in which an instruction block pre-fetched from an instruction cache space with a lower priority than the first instruction cache through a pre-fetch operation is stored.

[0071] In some embodiments, the target prediction address queue is further configured to filter the prediction addresses corresponding to any instruction address in the target prediction address queue to obtain a prediction address satisfying a pre-fetch condition as a pre-fetch address.

[0072] The prediction address satisfying the pre-fetch condition is a prediction address whose corresponding instruction address is located in a different cache line; and the pre-fetch address is used to obtain a pre-fetch instruction block corresponding to the pre-fetch address from the second instruction cache space.

[0073] The second instruction cache space can be a two-level instruction cache, or a three-level instruction cache, or a main memory or other storage space. The cache behavior is the unit of storing instructions and instruction blocks, which is a continuous address space.

[0074] In some cases, the predicted target address queue stores the instruction execution sequence predicted by the prediction unit. When the prediction accuracy is maintained at a high level, the instruction execution sequence in the predicted target address queue is very close to the effective instruction execution sequence in the actual program runtime. Therefore, the instruction addresses in the predicted target address queue can be used to optimize the prefetch mechanism of the instruction cache.

[0075] Specifically, for each entry in the predicted target address queue, it can be checked whether the instruction block address where the instruction address in each entry is located and the predicted address in the prediction result corresponding to the instruction address are in the same cache line in the first instruction cache space. If it is found that the instruction block address where the instruction address in any entry is located and the predicted address corresponding to the instruction address are not in the same cache line, the predicted address satisfies the prefetch condition, the predicted address is determined as the prefetch address, and is sent to the second instruction cache space after alignment for prefetching. If it is found that the instruction block address where the instruction address in any entry is located and the predicted address corresponding to the instruction address are in the same cache line in the first instruction cache space, the predicted address does not satisfy the prefetch condition, and does not need to be sent to the second instruction cache space for prefetching.

[0076] In the above embodiment, based on the predicted target address queue, a new cache prefetch strategy is designed. By filtering each entry in the predicted target address queue, the predicted address satisfying the prefetch condition is determined as the prefetch address and is sent to the second instruction cache space for prefetching. Thus, the prefetch addresses sent to the second instruction cache space all come from the predicted target address queue, and no additional prefetch instruction queue is needed, and an efficient prefetch mechanism can be achieved, and the hit rate and hit speed of the instruction fetch unit when fetching instructions can be improved.

[0077] In some embodiments, the predicted target address queue is further configured to return the entry index of the corresponding entry to the prediction unit when recording the instruction address corresponding to the branch instruction and the first-level prediction result to the corresponding entry of the predicted target address queue, so that the prediction unit writes the corresponding second-level prediction result into the corresponding entry according to the corresponding entry index.

[0078] In some embodiments, the corresponding entry is the tail entry of the predicted target address queue.

[0079] Specifically, the prediction target address queue records the instruction address of the corresponding branch instruction and the first-level prediction result into the current tail table entry of the prediction target address queue, and returns the table entry index of the table entry to the prediction unit. The table entry index is passed down the pipeline, so that when the prediction unit generates a second-level prediction result for the same branch instruction, the second-level prediction result can be written into the corresponding same table entry using the corresponding table entry index, so that the second-level prediction result of the branch instruction replaces the first-level prediction result of the branch instruction.

[0080] It can be understood that the tail table entry of the prediction target address queue is always changing during writing.

[0081] Further, in the case that the second-level prediction result obtained by predicting the same branch instruction is different from the first-level prediction result, the prediction address corresponding to the instruction address of the branch instruction will change after the second-level prediction result of the branch instruction replaces the first-level prediction result of the branch instruction. Since the prediction target address queue is responsible for recording the instruction execution sequence generated by the prediction unit, the contents of the subsequent table entries of the table entry where the instruction address is located need to be redirected.

[0082] Specifically, after the second-level prediction result of the current branch instruction replaces the first-level prediction result of the current branch instruction, in the case that the second-level prediction result obtained by predicting the current branch instruction is different from the first-level prediction result of the current branch instruction, the contents of the subsequent table entries of the table entry where the corresponding instruction address is located can be replaced or re-written based on the new second-level prediction result, so that the instruction address and the corresponding prediction address in the subsequent table entries of the table entry can be redirected.

[0083] For example, in period t, the prediction unit performs first-level branch prediction on branch instruction I1 to obtain first-level prediction result R11 of branch instruction I1, and writes instruction address addr1 and first-level prediction result R11 to the prediction target address queue. The prediction target address queue records the received instruction address addr1 and first-level prediction result R11 in the current tail table entry T1, and returns the table entry index S1 of the table entry to the prediction unit. In period t+1, the prediction unit continues to perform first-level branch prediction on the next branch instruction I2 to obtain first-level prediction result R12 of branch instruction I2, and writes instruction address addr2 and first-level prediction result R12 to the prediction target address queue. The prediction target address queue records the received instruction address addr2 and first-level prediction result R12 in the current tail table entry T2, and returns the table entry index S2 of the table entry to the prediction unit.

[0084] In the T period, the prediction unit performs the second-level branch prediction on the branch instruction I1 to obtain the second-level prediction result R21 of the branch instruction I1, and writes the instruction address addr1 and the second-level prediction result R21 into the table entry T1 of the prediction target address queue according to the table entry index S1. The prediction target address queue records the received instruction address addr1 and the second-level prediction result R21 in the table entry T1, so as to overwrite the first-level prediction result R11 with the second-level prediction result R21. In the case where no branch prediction error occurs or the pipeline needs to be redirected, in the T+1 period, the prediction unit can continue to perform the second-level branch prediction on the next branch instruction I2 to obtain the second-level prediction result R22 of the branch instruction I2, and write the instruction address addr2 and the second-level prediction result R22 into the table entry T2 of the prediction target address queue according to the table entry index S2. The prediction target address queue records the received instruction address addr2 and the second-level prediction result R22 in the table entry T2, so as to overwrite the first-level prediction result R12 with the second-level prediction result R22.

[0085] If the prediction of the branch instruction I1 is wrong, or the back-end processing unit of the processor needs to redirect the predicted address corresponding to the instruction address addr1, or the predicted address corresponding to the instruction address addr1 is changed after the first-level prediction result R11 is overwritten with the second-level prediction result R21 in the T period, the prediction target address queue can be redirected from the table entry T2 as the starting position for the subsequent instruction flow.

[0086] It can be understood that in some cases, when a branch prediction error occurs or the back-end processing unit needs to redirect the control flow, the pipeline needs to be emptied and the front-end processing unit needs to be quickly recovered. Compared with the method of waiting for the prediction unit to give the multi-level prediction result corresponding to the current branch instruction and then writing the final prediction result into the prediction target address queue, by making the prediction unit perform the writing operation on the prediction target address queue after generating each level of prediction result, the pipeline can be quickly redirected in the case where fewer incorrect instructions are executed, so as to reduce the instructions that need to be emptied and enable the pipeline to quickly resume execution.

[0087] It should be noted that the rapid recovery of the front-end processing unit also includes the rapid recovery of the transfer predictor state. Specifically, when a transfer prediction error occurs, the historical information required by the prediction unit for prediction also needs to be updated and recovered in a timely manner. This includes the rapid recovery of global historical information, the rapid recovery of predictor metadata, and the rapid recovery of the Return Address Stack (RAS) content. In processor designs of related technologies, global information is passed along the pipeline and is ultimately stored as a copy in the corresponding entry of the processor's Fetch Target Queue (FTQ). Therefore, this specification does not implement an additional rapid recovery mechanism for global historical information. For the rapid recovery of predictor metadata, processor designs of related technologies do not perform speculative updates to the metadata of each transfer predictor. Therefore, updates to predictor metadata are completed during the instruction commit phase. Thus, this specification does not implement an additional rapid recovery mechanism for predictor metadata. For the rapid recovery of RAS content, the classic stack top recovery mechanism can be used. By saving the RAS stack top address corresponding to each instruction block and then writing it into the processor's FTQ queue as part of the instruction block's transfer prediction information, the top entry of the RAS stack can be quickly restored to the correct state when pipeline redirection occurs, using the RAS stack top address in the corresponding FTQ queue entry.

[0088] In the above embodiments, the decoupled prediction unit structure based on the prediction target address queue also forms an overlay structure for the write operation of the prediction target address queue, which can solve the instruction stream redirection problem of the front-end decoupled structure based on the prediction target address queue and realize the rapid recovery of the pipeline.

[0089] In some implementations, the prediction target address queue has a dequeue pointer. The prediction target address queue is also used to delete the entry currently pointed to by the dequeue pointer from the prediction target address queue and update the dequeue pointer when the instruction fetch unit performs an instruction fetch operation based on the predicted address included in the entry currently pointed to by the dequeue pointer and obtains the corresponding instruction block from the first instruction cache space.

[0090] The dequeue pointer can be the head pointer of the target address prediction queue. The entry currently pointed to by the dequeue pointer can be the head entry of the target address prediction queue.

[0091] Understandably, each entry in the target address prediction queue not only stores the corresponding target instruction address but also records the transfer prediction information for the corresponding instruction block, including whether a transfer has occurred and the transfer target address. Therefore, the instruction fetch unit can obtain the predicted address included in the entry currently pointed to by the dequeue pointer.

[0092] In particular, the prediction target address queue internally maintains a deq_ptr pointing to a current head entry of the prediction target address queue. The fetch unit fetches a target prediction address from the current head entry of the prediction target address queue. In a case where the fetch unit fetches a corresponding instruction block from the first instruction cache space according to the prediction address included in the current head entry, it indicates that the fetch unit has successfully performed a fetch operation, and the prediction target address queue can remove the content in the current head entry from the prediction target address queue through the deq_ptr internally maintained to point to the current head entry of the prediction target address queue, to complete a deq operation. After the deq operation is completed, the deq_ptr is automatically incremented by 1 to point to a new head entry of the prediction target address queue.

[0093] In some embodiments, the prediction target address queue can also provide a deq port for completing a deq operation of an entry in the prediction target address queue. In a case where the fetch unit fetches a corresponding instruction block according to the prediction address included in the current head entry, the deq port is used to remove the current head entry of the prediction target address queue from the queue through the deq_ptr pointing to the current head entry of the prediction target address queue.

[0094] In some embodiments, the prediction target address queue has a prefetch pointer. In a case where the prediction target address queue receives a prefetch request sent by the processor front end, the prediction target address queue returns a prediction address included in an entry currently pointed to by the prefetch pointer and a prefetch validity signal corresponding to the prediction address to the processor front end, and updates the prefetch pointer, so that the processor front end takes the prediction address corresponding to the prefetch validity signal as a prefetch address in a case where the received prefetch validity signal is a prefetch valid signal, and fetches a prefetch instruction block corresponding to the prefetch address from the second instruction cache space; wherein the prefetch validity signal is used to indicate that the prediction address corresponding to the prefetch validity signal is a prediction address satisfying a prefetch condition.

[0095] In particular, the processor front end is a front-end processing unit of a processor in which the prediction target address queue is located. The prefetch request is a request generated by the processor front end in a case where the fetch unit fails to fetch a corresponding target instruction block from the first instruction cache space according to a current target prediction address fetched from the prediction target address queue.

[0096] Specifically, the prediction target address queue internally maintains a prefetch pointer `prefetch_ptr`. When the prediction target address queue receives a prefetch request from the processor front end, it indicates that the instruction fetch unit has not retrieved the corresponding target instruction block from the first instruction cache space based on the current target prediction address obtained from the prediction target address queue. This target instruction block needs to be prefetched from the second instruction cache space. The prefetch pointer is then automatically incremented by 1, pointing to the next entry in the prediction target address queue that may require prefetching. The prefetch pointer checks whether the instruction block address in the entry it currently points to is in the same cache line in the first instruction cache space as the prediction address in the prediction result corresponding to that instruction address. It then returns a response to the processor front end, containing a prefetch validity signal corresponding to the prediction address included in the entry currently pointed to by the prefetch pointer. If it is found that the instruction block address in the entry currently pointed to by the prefetch pointer is not in the same cache line as the corresponding predicted address, then the predicted address is a prefetch address that satisfies the prefetch condition. The prediction target address queue can return a reply containing the predicted address and the corresponding prefetch valid signal to the processor front end, which is used to instruct the processor front end to perform prefetching according to the predicted address included in the entry in order to obtain the corresponding prefetch instruction block from the second instruction cache space.

[0097] If the instruction address in the entry currently pointed to by the prefetch pointer is found to be in the same cache line as the corresponding predicted address, then the predicted address does not meet the prefetch condition and does not need to be prefetched. The prediction target address queue can return a reply containing the predicted address and the corresponding prefetch invalidation signal to the processor front end, indicating that the processor front end does not need to prefetch based on the predicted address.

[0098] In some embodiments, the prediction target address queue can also read the prefetch address pointed to by the prefetch pointer from the prediction target address queue via the prefetch port. The prefetch request can be generated by the instruction fetch unit or by the first instruction cache space.

[0099] In the above embodiments, by using a prefetch pointer and a prefetch validity signal to filter entries in the prediction target address queue, instruction block addresses that meet the conditions are selected for prefetching, which improves the hit rate and hit speed of the instruction fetch unit and can save hardware resources to a certain extent.

[0100] In some embodiments, the predicted target address queue has an enqueuing pointer and a reading pointer. The predicted target address queue is further configured to, in response to receiving the first-level prediction result, record the instruction address of the corresponding branch instruction and the first-level prediction result into the entry currently pointed to by the enqueuing pointer and update the enqueuing pointer, and in response to receiving a reading request from the instruction fetch unit, return the predicted address included in the entry currently pointed to by the reading pointer to the instruction fetch unit and update the reading pointer.

[0101] In particular, the predicted target address queue internally maintains an enqueuing pointer enq_ptr and a reading pointer read_ptr, the enqueuing pointer points to the current tail entry of the predicted target address queue, and the reading pointer points to the current head entry of the predicted target address queue. The prediction unit writes the generated prediction result into the current tail empty entry of the predicted target address queue pointed to by the enqueuing pointer through the enqueuing pointer, and the instruction fetch unit reads the address required by the instruction fetch from the current head of the predicted target address queue pointed to by the reading pointer through the reading pointer. When the predicted target address queue is initialized, the predicted target address queue is an empty queue, and the enqueuing pointer and the reading pointer both point to the first empty entry of the predicted target address queue. At this time, only enqueuing operation is allowed, and the instruction fetch unit cannot obtain valid content from the queue. After the enqueuing operation occurs, for example, the prediction unit writes the target instruction address and the first-level prediction result into the predicted target address queue. The predicted target address queue records the received target instruction address and the first-level prediction result to the position pointed to by the enqueuing pointer, and then the enqueuing pointer is automatically incremented by 1 to point to the next entry position for writing, thereby achieving the function of appending entries to the tail of the predicted target address queue. After the reading operation occurs, for example, the predicted target address queue receives a reading request from the instruction fetch unit. The content in the entry pointed to by the reading pointer is read out, and the reading pointer is automatically incremented by 1 to point to the next entry position for reading.

[0102] It can be understood that the predicted address included in the entry currently pointed to by the reading pointer is the target predicted address.

[0103] Further, in some embodiments, when the instruction fetch unit does not obtain the corresponding instruction block from the instruction cache, the predicted target address queue receives a reset signal (reset signal). The predicted target address queue needs to reset the program counter address for instruction fetch and reset the reading pointer so that the reading pointer points to the next entry position of the head pointer.

[0104] In some embodiments, the enqueue pointer is the tail pointer of the prediction target address queue. The internal structure of the prediction target address queue can be designed as a circular queue containing N entries. Initially, both the head pointer and the tail pointer point to the first entry in the queue, and the queue is in an empty state. When the prediction target address queue is empty, only enqueue operations are allowed, and the instruction fetch unit cannot obtain valid instruction addresses from the queue. After the enqueue operation, i.e., after the prediction result generated by the branch prediction unit is written into the prediction target address queue, the tail pointer moves to the next empty entry. When the head pointer and the tail pointer coincide again, the prediction target address queue needs to determine whether the queue is in a full state according to the current enqueue or dequeue operation. When the prediction target address queue is in a full state, only dequeue operations are allowed, and the branch prediction unit cannot write new prediction results into the prediction target address queue, and needs to be re-predicted.

[0105] The prediction target address queue can also provide an enqueue port, i.e., an enq port, so that the branch prediction unit writes new entry contents into the prediction target address queue through the enqueue port. The prediction target address queue can also provide a read port, i.e., a read port, so that the instruction fetch unit reads the predicted addresses needed to be sent to the instruction cache from the prediction target address queue through the read port. The read port realizes sequential reading of the entry contents in the prediction target address queue through a read pointer.

[0106] Further, the prediction target address queue can also provide a corresponding write port for each level of branch prediction. For example, after the branch prediction unit generates a first-level prediction result for the branch instruction I1, the branch prediction unit can write the target instruction address corresponding to the branch instruction I1 and the first-level prediction result into the target entry T1 of the prediction target address queue through the enq port, and the prediction target address queue returns the entry index of the target entry T1 to the branch prediction unit. After the branch prediction unit generates a second-level prediction result for the branch instruction I1, the branch prediction unit can use the entry index of the target entry T1 to write the target instruction address corresponding to the branch instruction I1 and the second-level prediction result into the target entry T1 through the write port corresponding to the second-level branch prediction, i.e., the writeidx1 port. After the branch prediction unit generates a third-level prediction result for the branch instruction I1, the branch prediction unit can use the entry index of the target entry T1 to write the target instruction address corresponding to the branch instruction I1 and the third-level prediction result into the target entry T1 through the write port corresponding to the third-level branch prediction, i.e., the writeidx2 port.

[0107] It should be noted that the target address prediction queue can implement dequeue operations through the combined use of a read pointer and a dequeue pointer. Specifically, when the target address prediction queue receives a dequeue operation instruction, it determines whether the dequeue pointer will exceed the read pointer. If the dequeue pointer will not exceed the read pointer, the dequeue pointer will automatically increment by 1, pointing to the new head entry of the target address prediction queue.

[0108] This specification provides an instruction transfer prediction method applied to an instruction transfer prediction system. The instruction transfer prediction system includes a prediction unit, a prediction target address queue, and an instruction fetch unit. The input of the prediction target address queue is connected to the output of the prediction unit, and the output of the prediction target address queue is connected to the input of the instruction fetch unit. The prediction unit is used to perform multi-level branch prediction on transfer instructions. The multi-level branch prediction includes first-level branch prediction and second-level branch prediction. (Reference) Figure 3 As shown, the instruction transfer prediction method includes the following steps.

[0109] S310. The prediction unit performs branch prediction on the transfer instruction through first-level branch prediction, obtains the first-level prediction result and outputs it, and performs branch prediction on the transfer instruction through second-level branch prediction, obtains the second-level prediction result and outputs it; wherein, the first-level prediction result and the second-level prediction result respectively include the prediction address corresponding to the transfer instruction.

[0110] S320: Upon receiving the first-level prediction result, the target address prediction queue records the instruction address of the corresponding transfer instruction and the first-level prediction result. Upon receiving the second-level prediction result corresponding to the transfer instruction, the second-level prediction result is used to overwrite the corresponding first-level prediction result.

[0111] S330, the instruction fetch unit obtains the target predicted address corresponding to the target instruction address from the target predicted address queue, and performs the corresponding instruction fetch operation based on the obtained target predicted address.

[0112] It should be noted that for the description of the prediction unit, prediction target address queue and instruction fetch unit in the above embodiments, please refer to the description of the prediction unit, prediction target address queue and instruction fetch unit of the instruction transfer prediction system in this specification, and will not be repeated here.

[0113] This specification provides an instruction transfer prediction device applied to an instruction transfer prediction system. The instruction transfer prediction system includes a prediction unit, a prediction target address queue, and an instruction fetch unit. The input of the prediction target address queue is connected to the output of the prediction unit, and the output of the prediction target address queue is connected to the input of the instruction fetch unit. The prediction unit is used to perform multi-level branch prediction on transfer instructions. The multi-level branch prediction includes first-level branch prediction and second-level branch prediction. (Reference) Figure 4As shown, the instruction transfer prediction device 400 comprises a branch prediction module 410, a recording module 420, and a predicted address acquisition module 430.

[0114] The branch prediction module 410 is configured to predict the branch of the transfer instruction by first-level branch prediction to obtain a first-level prediction result and output the first-level prediction result, and predict the branch of the transfer instruction by second-level branch prediction to obtain a second-level prediction result and output the second-level prediction result; wherein the first-level prediction result and the second-level prediction result each comprise a predicted address corresponding to the transfer instruction.

[0115] The recording module 420 is configured to record the instruction address of the corresponding transfer instruction and the first-level prediction result in the case where the prediction target address queue receives the first-level prediction result, and overwrite the corresponding first-level prediction result with the second-level prediction result in the case where the prediction target address queue receives the second-level prediction result corresponding to the transfer instruction.

[0116] The predicted address acquisition module 430 is configured to acquire the target predicted address corresponding to the target instruction address from the prediction target address queue by the instruction fetch unit, and perform corresponding instruction fetch operation according to the acquired target predicted address.

[0117] The specific limitations of the instruction transfer prediction device can be referred to the limitations of the instruction transfer prediction method in the foregoing, which will not be repeated here. Each module in the above instruction transfer prediction device can be realized by software, hardware, and combinations thereof, in whole or in part. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to the above modules.

[0118] The embodiments of the present specification also provide a computer device, which can be referred to the above description of the instruction transfer prediction method. Figure 5 As shown, the computer device 500 comprises a memory 510, a processor 520, and a computer program 530 stored in the memory 510 and executable on the processor 520, and the processor 520 implements the above instruction transfer prediction method when executing the computer program 530.

[0119] The embodiments of the present specification also provide a computer readable storage medium, which stores a computer program executable by a processor to implement the above instruction transfer prediction method.

[0120] It is to be appreciated that the above description and the examples that follow are intended to be illustrative only and that changes can be made to the description, either functionally or chronologically, as well as changes being made concerning the order of implementation. The logic and / or steps represented in the flow diagrams and / or described herein can be considered as a sequence of executable instructions, and can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For purposes of this specification, a "computer-readable medium" can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus) or a propagation medium. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber (optical), and a portable compact disc read-only memory (CDROM). Note that the computer-readable medium can even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example via the optical scanner of a device or device or via an intermediary, such as a facility bureau, then compiled, interpreted, or processed in a suitable manner if necessary, and then stored in a computer storage medium.

[0121] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following techniques, which are well known in the art of making integrated circuits, can be used alone or in any combination: discrete logic circuitry having logic gates for implementing logic functions upon an application of data signals, application-specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field-programmable gate arrays (FPGA), and other implementations known to those with ordinary skill in the art. These various implementations can include

[0122] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the application. The illustrative appearances of the above-mentioned terms in the specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0123] In addition, the terms "first", "second", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implying a number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified and limited.

[0124] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0125] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. An instruction transfer prediction system, characterized in that, The instruction transfer prediction system includes a prediction unit, a prediction target address queue, and an instruction fetch unit. The input of the prediction target address queue is connected to the output of the prediction unit, and the output of the prediction target address queue is connected to the input of the instruction fetch unit. The prediction unit is a branch predictor with a multi-level coverage prediction structure, wherein: The prediction unit is used to perform multi-level branch prediction on the transfer instruction, and after each level of branch prediction result is generated, writes the corresponding branch prediction result into the prediction target address queue, and updates the prediction results in the prediction target address queue in real time by overwriting; the multi-level branch prediction includes first-level branch prediction and second-level branch prediction; the transfer instruction is branch predicted through the first-level branch prediction to obtain a first-level prediction result and output it, and the transfer instruction is branch predicted through the second-level branch prediction to obtain a second-level prediction result and output it; wherein, the first-level prediction result and the second-level prediction result respectively include the prediction address corresponding to the transfer instruction; The prediction target address queue is used to record the instruction address of the corresponding transfer instruction and the first-level prediction result when the first-level prediction result is received, and to directly use the second-level prediction result to overwrite the corresponding first-level prediction result to achieve the redirection of the program counter PC address when the second-level prediction result is received. Specifically, the prediction target address queue returns the table entry index of the target table entry containing the first-level prediction result to the prediction unit, so that the prediction unit writes the second-level prediction result into the corresponding table entry according to the table entry index to overwrite the corresponding first-level prediction result. The instruction fetching unit is used to obtain the target predicted address corresponding to the target instruction address from the predicted target address queue, and perform corresponding instruction fetching operations based on the obtained target predicted address.

2. The system according to claim 1, characterized in that, The predicted target address queue is further configured to delete the corresponding target instruction address and the target table entry where the target predicted address is located from the predicted target address queue when the instruction fetch unit performs an instruction fetch operation based on the obtained target predicted address and obtains the corresponding target instruction block from the first instruction cache space.

3. The system according to claim 1, characterized in that, The prediction target address queue is further used to filter the prediction address corresponding to any instruction address in the prediction target address queue to obtain the prediction address that satisfies the prefetch condition, which is then used as the prefetch address; wherein, the prediction address that satisfies the prefetch condition is the prediction address that is located in a different cache line from the instruction address it corresponds to; the prefetch address is used to obtain the prefetch instruction block corresponding to the prefetch address from the second instruction cache space.

4. The system according to claim 1, characterized in that, The prediction target address queue is further configured to return the entry index of the corresponding entry to the prediction unit when recording the instruction address of the corresponding transfer instruction and the corresponding entry of the first-level prediction result to the prediction target address queue, so that the prediction unit writes the corresponding second-level prediction result to the corresponding entry according to the corresponding entry index.

5. The system according to claim 2, characterized in that, The predicted target address queue has a dequeue pointer; The predicted target address queue is further configured to, when the instruction fetch unit performs an instruction fetch operation based on the predicted address included in the entry currently pointed to by the dequeue pointer and obtains the corresponding instruction block from the first instruction cache space, delete the entry currently pointed to by the dequeue pointer from the predicted target address queue and update the dequeue pointer.

6. The system according to claim 3, characterized in that, The predicted target address queue has a prefetch pointer; The predicted target address queue is further configured to, upon receiving a prefetch request sent by the processor front end, return the predicted address included in the entry currently pointed to by the prefetch pointer and the prefetch validity signal corresponding to the predicted address to the processor front end, and update the prefetch pointer, so that if the received prefetch validity signal is a prefetch validity signal, the processor front end uses the predicted address corresponding to the prefetch validity signal as the prefetch address and obtains the prefetch instruction block corresponding to the prefetch address from the second instruction cache space; wherein, the prefetch validity signal is used to indicate that the predicted address corresponding to the prefetch validity signal is a predicted address that satisfies the prefetch condition.

7. The system according to any one of claims 1 to 6, characterized in that, The predicted target address queue has an enqueue pointer and a read pointer; The predicted target address queue is further configured to, upon receiving the first-level prediction result, record the instruction address of the corresponding transfer instruction and the first-level prediction result to the entry currently pointed to by the enqueue pointer and update the enqueue pointer; and upon receiving a read request from the instruction fetch unit, return the predicted address included in the entry currently pointed to by the read pointer to the instruction fetch unit and update the read pointer.

8. A method for predicting instruction transfers, characterized in that, An instruction transfer prediction system is applied, comprising a prediction unit, a prediction target address queue, and an instruction fetch unit. The input of the prediction target address queue is connected to the output of the prediction unit, and the output of the prediction target address queue is connected to the input of the instruction fetch unit. The prediction unit is a branch predictor with a multi-level overlay prediction structure. The prediction unit performs multi-level branch prediction on transfer instructions, and after each level of branch prediction result is generated, writes the corresponding branch prediction result into the prediction target address queue, and updates the prediction results in the prediction target address queue in real time by overlay writing. The multi-level branch prediction includes first-level branch prediction and second-level branch prediction. The method includes: The prediction unit performs branch prediction on the transfer instruction through the first-level branch prediction to obtain and output the first-level prediction result, and performs branch prediction on the transfer instruction through the second-level branch prediction to obtain and output the second-level prediction result; wherein, the first-level prediction result and the second-level prediction result respectively include the prediction address corresponding to the transfer instruction; Upon receiving the first-level prediction result, the prediction target address queue records the instruction address of the corresponding transfer instruction and the first-level prediction result. Upon receiving the second-level prediction result corresponding to the transfer instruction, it directly uses the second-level prediction result to overwrite the corresponding first-level prediction result to achieve the redirection of the program counter (PC) address. Specifically, the prediction target address queue returns the entry index of the target table entry containing the first-level prediction result to the prediction unit, so that the prediction unit writes the second-level prediction result into the corresponding entry according to the entry index to overwrite the corresponding first-level prediction result. The instruction fetching unit obtains the target predicted address corresponding to the target instruction address from the predicted target address queue, and performs the corresponding instruction fetching operation based on the obtained target predicted address.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method of claim 8.

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