Instruction processing method and apparatus, electronic device, chip, and storage medium

Abstract

This disclosure proposes an instruction processing method, apparatus, electronic device, chip, and storage medium. The method includes: responding to the current instruction being a conditional branch instruction, using a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; responding to the current instruction being a loop branch instruction, using a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; responding to the second prediction result differing from the first prediction result, using the second prediction result to correct the first prediction result, thereby improving the accuracy of the first prediction result. Based on the accurate first prediction result, performance loss caused by prediction errors can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an instruction processing method, apparatus, electronic device, chip, and storage medium. Background Technology

[0002] As program complexity increases, efficient handling of branch instructions has become a core factor limiting processor performance improvement. When dealing with these complex and ever-changing branch instructions, the processor needs to quickly and accurately predict whether to continue jumping in order to avoid delays caused by waiting for condition judgment results. This predictive ability is crucial for maintaining high throughput and low latency of the processor. Summary of the Invention

[0003] This disclosure aims to address, to some extent, one of the technical problems in the related technologies.

[0004] To address this, this disclosure proposes an instruction processing method, apparatus, electronic device, chip, and storage medium. First, when the current instruction is a conditional branch instruction, a first branch predictor is used to predict the branch direction of the current instruction, obtaining a first prediction result. Then, when the current instruction is a loop branch instruction, a second branch predictor is used to predict the branch direction of the current instruction, obtaining a second prediction result. When the second prediction result differs from the first prediction result, the second prediction result is used to correct the first prediction result, thereby improving the accuracy of the first prediction result. Based on the accurate first prediction result, performance loss due to prediction errors can be reduced.

[0005] One embodiment of this disclosure proposes an instruction processing method, including:

[0006] In response to the current instruction being a conditional branch instruction, a first branch predictor is used to predict the branch direction of the current instruction to obtain a first prediction result; wherein, the first prediction result is used to indicate whether the current instruction will jump.

[0007] In response to the current instruction being a loop branch instruction, a second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result; wherein, the second prediction result is used to indicate whether the loop branch instruction has a jump.

[0008] In response to the difference between the second prediction result and the first prediction result, the second prediction result is used to correct the first prediction result.

[0009] Another embodiment of this disclosure provides an instruction processing apparatus, including:

[0010] The first prediction module is configured to, in response to the current instruction being a conditional branch instruction, use a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein, the first prediction result is used to indicate whether the current instruction will jump.

[0011] The second prediction module is used to predict the branch direction of the current instruction in response to the current instruction being a loop branch instruction, using a second branch predictor to obtain a second prediction result; wherein the second prediction result is used to indicate whether the loop branch instruction has a jump.

[0012] A correction module is used to correct the first prediction result using the second prediction result in response to the difference between the second prediction result and the first prediction result.

[0013] Another embodiment of this disclosure provides an electronic device, including: a processor and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the instruction processing method as described in the above-described embodiment.

[0014] Another embodiment of this disclosure provides a chip including processing circuitry configured to execute the instruction processing method as described in the above-described embodiment.

[0015] Another embodiment of this disclosure provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the instruction processing method as described in the above-described embodiment.

[0016] Another embodiment of this disclosure provides a computer program product having a computer program stored thereon, which, when executed by a processor, implements the instruction processing method as described in the foregoing embodiment.

[0017] The instruction processing method proposed in this disclosure, in response to the current instruction being a conditional branch instruction, employs a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the current instruction being a loop branch instruction, employs a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the second prediction result differing from the first prediction result, the second prediction result is used to correct the first prediction result, thereby improving the accuracy of the first prediction result. Based on the accurate first prediction result, performance loss caused by prediction errors can be reduced.

[0018] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 This is a flowchart illustrating an instruction processing method provided in an embodiment of the present disclosure;

[0021] Figure 2 A flowchart illustrating another instruction processing method provided in an embodiment of this disclosure;

[0022] Figure 3 A flowchart illustrating another instruction processing method provided in an embodiment of this disclosure;

[0023] Figure 4 A schematic diagram of the principle of an instruction processing method provided in an embodiment of this disclosure. Figure 1 ;

[0024] Figure 5 A schematic diagram of the principle of an instruction processing method provided in an embodiment of this disclosure. Figure 2 ;

[0025] Figure 6 A schematic diagram of the principle of an instruction processing method provided in an embodiment of this disclosure. Figure 3 ;

[0026] Figure 7 This is a schematic diagram of a cyclic entry provided in an embodiment of the present disclosure;

[0027] Figure 8 This is a schematic diagram of the structure of an instruction processing device provided in an embodiment of the present disclosure;

[0028] Figure 9 A block diagram of an electronic device provided in an embodiment of this disclosure;

[0029] Figure 10 This is a schematic diagram of the chip structure proposed in the embodiments of this disclosure. Detailed Implementation

[0030] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0031] In related technologies, most processors have achieved branch prediction accuracy of over 90%, but loop termination prediction often results in errors, so loop termination errors may account for a large portion of the remaining branch prediction errors. The Tagged Geometric History Length (TAGE) branch predictor is a very effective branch predictor that combines the advantages of multiple predictors, but TAGE predictions are generally unsatisfactory at loop termination.

[0032] In related technologies, loop termination prediction mainly includes the following two aspects. First, conditional branch instructions with negative offsets are considered loop branch instructions. However, predicting all conditional branch instructions with negative offsets using a loop predictor inevitably leads to increased power consumption, which is not conducive to the implementation of high-performance processors. On the other hand, a large number of data structures are used to record the characteristics of the loop body in order to predict the jump direction of each loop branch instruction. This method of predicting all loop branch instructions is more complex than predicting only the loop termination instruction, which is not conducive to implementation in high-performance processors.

[0033] To address the aforementioned issues, this disclosure proposes an instruction processing method, apparatus, electronic device, chip, and storage medium.

[0034] The instruction processing method, apparatus, electronic device, chip, and storage medium of the present disclosure are described below with reference to the accompanying drawings.

[0035] Figure 1 This is a flowchart illustrating an instruction processing method provided in an embodiment of the present disclosure.

[0036] This embodiment illustrates the example of an instruction processing method configured as an instruction processing device. This code update device can be applied to any electronic device with computing capabilities, so that the electronic device can perform instruction processing functions.

[0037] like Figure 1 As shown, the instruction processing method may include the following steps:

[0038] Step 101: In response to the current instruction being a conditional branch instruction, the first branch predictor is used to predict the branch direction of the current instruction to obtain the first prediction result.

[0039] The first prediction result is used to indicate whether a jump occurs after the current instruction is executed.

[0040] Conditional branch instructions are instructions that determine the program execution path based on specific conditions. Conditional branch instructions include loop branch instructions and other types of conditional branch instructions (such as if-else instructions, switch instructions, etc.).

[0041] In this embodiment of the disclosure, when the current instruction is a conditional branch instruction, a first branch predictor is used to predict the branch direction of the current instruction to obtain a first prediction result. The first prediction result indicates whether a jump occurs after the current instruction is executed. A jump means that the next instruction is not executed sequentially, but instead the execution jumps to another address; no jump means that the next instruction is executed sequentially without jumping to another address. It should be noted that, to improve the accuracy of branch prediction, the first branch predictor can be, for example, a TAGE predictor.

[0042] Step 102: In response to the current instruction being a loop branch instruction, a second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result.

[0043] The second prediction result is used to indicate whether a jump occurs after the current instruction is executed.

[0044] In this embodiment of the disclosure, when a loop branch instruction is executed in the current instruction conditional branch instruction, a second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result. The second prediction result is used to indicate whether a jump occurs after the current instruction is executed. A jump means that the current execution process of the innermost loop in the multi-level nested loop in which the current instruction is located has not yet terminated, and no jump means that the current execution process of the innermost loop in the multi-level nested loop in which the current instruction is located has terminated.

[0045] It should be noted that, in order to improve the accuracy of loop termination prediction, in this embodiment of the disclosure, the second branch predictor may be, for example, a loop termination predictor.

[0046] Step 103: In response to the difference between the second prediction result and the first prediction result, the first prediction result is corrected using the second prediction result.

[0047] To improve the accuracy of branch prediction, in this embodiment of the disclosure, when the second prediction result differs from the first prediction result, the second prediction result is used to correct the first prediction result.

[0048] To improve the accuracy of loop termination prediction, in this embodiment of the disclosure, no jump occurs after the second prediction result indicates that the execution is complete, but a jump occurs after the first prediction result indicates that the current instruction is complete. The second prediction result is used to correct the first prediction result, and the corrected first prediction result indicates that no jump occurs after the current instruction is complete.

[0049] The instruction processing method of this disclosure, in response to the current instruction being a conditional branch instruction, uses a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the current instruction being a loop branch instruction, uses a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the second prediction result being different from the first prediction result, the second prediction result is used to correct the first prediction result, thereby improving the accuracy of the first prediction result. Based on the accurate first prediction result, performance loss caused by prediction errors can be reduced.

[0050] To clearly illustrate how the second prediction result is generated in the above embodiments, this disclosure proposes another instruction processing method.

[0051] Figure 2 This is a flowchart illustrating another instruction processing method provided in an embodiment of the present disclosure.

[0052] like Figure 2 As shown, the steps for generating the second prediction result are as follows:

[0053] Step 201: In response to the current instruction being a loop branch instruction in a multi-level nested loop, query the current iteration number of the current execution process of the innermost loop in the multi-level nested loop where the current instruction is located.

[0054] In this embodiment of the disclosure, when the current instruction is a loop branch instruction in a multi-level nested loop, the current iteration number of the current execution process of the innermost loop in the multi-level nested loop is queried to obtain the current iteration number, that is, the number of iterations that the innermost loop variable (such as k) has completed in the current execution process.

[0055] Step 202: In response to the current iteration number being equal to the target number, determine whether the value of the confidence bit is the first target value.

[0056] The target number is determined based on the number of the first iteration of the first complete execution process of the innermost loop, and the value of the confidence bit is used to indicate whether the current execution process has terminated.

[0057] To reduce the complexity of branch prediction, as a possible implementation, prediction is only performed on loop termination. In this embodiment, when the current iteration count equals the target count, it is determined whether the confidence bit value is the first target value. The target count is determined based on the first iteration count of the first complete execution process of the innermost loop. For example, the target count is the iteration count of the first complete execution process of the innermost loop. The confidence bit value is used to indicate whether the current execution process has terminated. For example, a confidence bit value of the first target value indicates that the current execution process has terminated, and a confidence bit value of the second target value indicates that the current execution process has not terminated.

[0058] It should be noted that if the current iteration number is not equal to the target number, the second branch predictor is not used to predict the branch direction of the current instruction, or the second prediction result is not generated.

[0059] When the confidence bit is set to the second target value, a second prediction result is generated to indicate that a jump occurs after the current instruction is completed, which means that the current execution loop has not terminated; or, the second branch predictor is refused to predict the branch direction of the current instruction; or, the second prediction result is refused to be generated.

[0060] As one possible approach, the confidence bit needs to be assigned a value before determining whether the value of the confidence bit is the first target value.

[0061] As an example, in response to the loop branch instruction in the non-first complete execution process of the innermost loop in a multi-level nested loop, the first iteration count of the first complete execution process is obtained; the iteration counts of the non-first complete execution processes are counted to obtain the second iteration count of the non-first complete execution process; in response to the second iteration count being the same as the first iteration count, the decoding result of the current instruction is obtained; and the confidence bit is assigned a value according to the decoding result of the current instruction.

[0062] In other words, in the non-first complete execution process of the innermost loop within a multi-level nested loop, the loop branch instruction obtains the first iteration count (also known as the loop count) of the first complete execution process. For example, taking a 3-level nested loop as an example, i is the index of the outermost loop, j is the index of the middle loop, and k is the index of the innermost loop. The outermost loop counts 10 times, i from 0 to 9; the middle loop counts 10 times, j from 0 to 9; and the innermost loop counts 10 times, k from 0 to 9. When i = 0, j = 0, and k starts from 0... Reaching number 9 signifies the first complete execution of the innermost loop. The loop count for this first complete execution is 10. Execution processes within nested loops other than this first complete execution are considered non-first complete execution processes. For any non-first complete execution process, the number of iterations is counted to obtain a second iteration count. When the second iteration count matches the loop count, the decoding result obtained by the instruction decoding unit for the current instruction is acquired. Then, based on the decoding result, a confidence bit is assigned a value. The value of the confidence bit is determined using the following steps:

[0063] 1. In response to the decoding result of the current instruction indicating that no jump will occur after the current instruction has been executed, the value of the confidence bit is determined to be the first target value.

[0064] In this embodiment of the disclosure, when the iteration count is equal to the loop count, and the decoding result of the current instruction indicates that no jump occurs after the current instruction is executed, that is, the non-first complete execution process of the innermost loop where the current instruction is located is terminated, the value of the confidence bit is set to the first target value (e.g., 1).

[0065] 2. In response to the decoding result of the current instruction indicating that the current instruction has been executed, a jump occurs, and the value of the confidence bit is determined to be the second target value.

[0066] In this embodiment of the disclosure, when the decoding result of the current instruction indicates that a jump occurs after the current instruction has been executed, it means that the non-first complete execution process of the innermost loop containing the current instruction has not terminated. At this time, the value of the confidence bit is set to the second target value (e.g., 0).

[0067] To save resources, as another possible implementation, in the loop branch instruction of the second complete execution process of the innermost loop in a multi-level nested loop, when the iteration count of the second complete execution process is the same as the loop count, the decoding result of the current instruction is obtained, and the confidence bit is assigned a value according to the decoding result of the current instruction. When the execution of each complete execution process after the second complete execution process of the innermost loop ends, it is checked whether the value of the confidence bit is the first target value, and when the value of the confidence bit is the first target value, the first prediction result is corrected.

[0068] It should be noted that the first iteration number of the first complete execution process is determined by the following steps: in response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is completed, the current instruction is determined to be the last loop branch instruction in the first complete execution process; the first iteration number is determined based on the first loop branch instruction and the last loop branch instruction in the first complete execution process.

[0069] In other words, when the current instruction is a loop branch instruction in the first complete execution process of the innermost loop, the decoding result of the current instruction indicates that no jump occurs after the current instruction is completed. This means that the current instruction is the last loop branch instruction in the first complete execution process of the innermost loop. Therefore, the number of loops in the first complete execution process of the innermost loop can be determined based on the first loop branch instruction and the last loop branch instruction in the first complete execution process, i.e., the loop count.

[0070] To improve data access efficiency, in this embodiment of the disclosure, the loop count, current iteration count, and confidence bit value of the loop branch instructions in the same multi-level nested loop are located in the same loop entry. It should be noted that the instruction addresses of the loop branch instructions in the same multi-level nested loop are the same. To facilitate instruction access, the instruction address of the corresponding loop branch instruction can also be stored in the loop entry.

[0071] In addition, in order to save resources while meeting user needs, the number of loop entries can be set to a specified number, for example, the number of loop entries is 4.

[0072] Step 203: In response to the value of the confidence bit being the first target value, a second prediction result is generated to indicate that no jump will occur after the current instruction is executed.

[0073] The first target value is used to indicate the termination of the current execution process loop.

[0074] In this embodiment of the disclosure, when the confidence bit is the first target value, the prediction result of the second branch predictor for the current instruction is obtained, that is, the loop termination prediction result of the innermost non-first complete execution process is used as the second prediction result.

[0075] To achieve effective management of loop entries, in this embodiment of the disclosure, the same loop entry also includes the counter value corresponding to the loop branch instruction in the same multi-level nested loop. After correcting the first prediction result with the second prediction result, when the decoding result of the current instruction indicates that no jump occurs after the current instruction is executed, and the second prediction result indicates that no jump occurs after the current instruction is executed, the calculated value of the counter corresponding to the current instruction is incremented; when the decoding result of the current instruction indicates that no jump occurs after the current instruction is executed, and the second prediction result indicates that a jump occurs after the current instruction is executed, the counter value corresponding to the current instruction is decremented, and when the counter value corresponding to the current instruction reaches a set value (e.g., the counter value is 0), the loop entry corresponding to the current instruction is deleted. That is, when the counter value is the set value, it indicates that the information recorded in the loop entry has low utilization value, and the information in the loop entry is deleted to prepare for the next loop termination prediction.

[0076] For example, the counter includes an aging counter.

[0077] The instruction processing method of this disclosure, in response to the current instruction being a loop branch instruction in a multi-level nested loop, queries the current iteration number of the current execution process of the innermost loop in the multi-level nested loop where the current instruction is located; in response to the current iteration number being equal to the target number, it determines whether the value of the confidence bit is a first target value; wherein, the target number is determined based on the first iteration number of the first complete execution process of the innermost loop, and the value of the confidence bit is used to indicate whether the current execution process has terminated; thereby, it realizes that only the prediction result of loop termination is predicted, reducing the prediction complexity, and when the confidence bit is the first target value, the prediction result of loop termination is used to correct the first prediction result, improving the accuracy of the first prediction result and avoiding performance loss caused by misprediction.

[0078] To clearly illustrate how the above embodiments determine whether the current instruction is a loop branch instruction, this disclosure proposes another instruction processing method.

[0079] Figure 3 This is a flowchart illustrating another instruction processing method provided in an embodiment of the present disclosure.

[0080] like Figure 3 As shown, the instruction processing method may include the following steps:

[0081] Step 301: In response to the current instruction being a conditional branch instruction, the first branch predictor is used to predict the branch direction of the current instruction to obtain a first prediction result.

[0082] The first prediction result is used to indicate whether a jump occurs after the current instruction is executed.

[0083] Step 302: In response to the current instruction having a cyclic characteristic, the current instruction is written to the instruction queue.

[0084] In this embodiment of the disclosure, the current instruction is characterized by feature recognition to obtain the instruction feature of the current instruction. Then, it is determined whether the instruction feature includes a loop feature. When the instruction feature includes a loop feature, it indicates that the current instruction has a loop feature, and the current instruction is written into the instruction queue.

[0085] Step 303: Determine whether the current instruction is a loop branch instruction based on the decoding result of the current instruction.

[0086] To further determine whether the current instruction is a loop branch instruction, in this embodiment of the disclosure, a decoding unit is used to decode the current instruction to obtain the decoding result of the current instruction. The decoding result is then parsed to determine whether the current instruction is a loop branch instruction.

[0087] Step 304: In response to the current instruction being a loop branch instruction, read the current instruction from the instruction queue.

[0088] To filter non-loop branch instructions, as an example, when the current instruction is a loop branch instruction, the current instruction is read from the instruction queue.

[0089] As another example, if the current instruction is not a loop branch instruction, the current instruction is not read from the instruction queue.

[0090] This allows the current instruction to be input into the second branch predictor only when the current instruction is a loop branch instruction, reducing unnecessary power consumption.

[0091] Step 305: Use the second branch predictor to predict the branch direction of the current instruction to obtain the second prediction result.

[0092] Then, a second branch predictor is used to predict the branch direction of the current instruction read from the instruction queue to obtain a second prediction result.

[0093] Step 306: In response to the difference between the second prediction result and the first prediction result, the first prediction result is corrected using the second prediction result.

[0094] It should be noted that the execution processes of steps 301 and 306 can be implemented in any of the various embodiments of this disclosure. This disclosure does not limit these processes and will not elaborate further.

[0095] The instruction processing method of this disclosure, in response to the current instruction having a loop characteristic, writes the current instruction into the instruction queue; determines whether the current instruction is a loop branch instruction based on the decoding result of the current instruction; in response to the current instruction being a loop branch instruction, reads the current instruction from the instruction queue; and uses a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result. This effectively filters out non-loop branch instructions, preventing them from entering the second branch predictor, reducing unnecessary power consumption, and improving resource utilization.

[0096] In any embodiment of this disclosure, such as Figure 4 As shown, taking the first branch predictor as the TAGE predictor and the second branch predictor as the loop termination predictor, and using the instruction processing method of a processor in an electronic device as an example, the instruction processing method of this embodiment can also be implemented based on the following steps:

[0097] 1. When performing branch prediction, if the current instruction is found to have loop branch characteristics, the loop branch filter is turned on, the current instruction is written to the instruction queue, and non-loop branch instructions are filtered out. The decoding result of the current instruction is used to confirm whether the instruction is a real loop branch instruction.

[0098] 2. If it is a loop branch instruction, the current instruction is read from the instruction queue, and the loop termination predictor is started to record the characteristics of the loop branch instruction. Then, the prediction result of loop termination is given when the loop terminates.

[0099] 3. Overwrite the prediction results of the TAGE predictor with the prediction results of the loop termination, thereby achieving the effect of correcting the TAGE prediction results with the loop termination prediction.

[0100] Specifically, such as Figure 5 As shown, the instruction processing method is implemented as follows:

[0101] 1. The memory 501 stores instructions. During instruction execution, the processor accesses the memory 501 through the instruction fetch unit 503 and uses the instruction cache 502 to fetch instructions. The instruction fetch unit 503 includes a branch predictor 504.

[0102] 2. The instruction decoder 505 decodes the instruction and passes the decoded instruction and the decoded data to the instruction execution unit 506;

[0103] 3. The instruction execution unit 506 is used to implement its functions according to specific instructions, such as addition, subtraction, multiplication, and division operations.

[0104] 4. The instruction memory access form 507 is used to interact with memory during the execution of the instruction execution unit.

[0105] 5. The instruction write-back unit 508 is used to write the execution result back to memory after the instruction is executed.

[0106] Among them, such as Figure 6 As shown, the specific steps for the processor to execute instructions are as follows:

[0107] Step 601: When the instruction fetching stage detects a conditional branch instruction and it has loop characteristics, the instruction address is pushed into the instruction queue FIFO. The FIFO filters out non-loop branch instructions. When the instruction decoding stage determines that the instruction is a loop branch, the instruction address is popped from the FIFO. It can be seen that if the instruction pushed into the FIFO is a loop branch instruction, the FIFO has no effect. However, if the pushed instruction is not a loop branch instruction, the non-loop branch instruction will remain in the FIFO. When the FIFO is full, it will push the upstream to stop feeding loop branch instructions into the FIFO. This also indicates that the previously fed loop branch instructions were actually non-loop branch instructions. Therefore, the FIFO filters out non-loop branch instructions, which ensures that not all loop branch instructions enter the loop termination predictor, thereby reducing unnecessary power consumption.

[0108] Step 602: For loop branch instructions pushed into the FIFO, when the instruction decoding unit determines that it is a loop branch instruction and the TAGE branch predictor makes an error, the instruction address of the branch instruction is stored in... Figure 7 The tag bit in the loop entry can be understood as the first termination of the first complete execution process of the innermost loop in a multi-level nested loop, and the loop count (first iteration number) of the first complete execution process is obtained;

[0109] It should be noted that since the TAGE branch predictor predicts branches based on historical information, under normal circumstances, branches within a loop are jumps. However, conditional branch instructions at loop termination do not jump. Therefore, TAGE can accurately predict branch instructions within the loop body, but generally cannot accurately predict those at loop termination. When loop branch instructions are pushed into the FIFO, the iteration count begins (iteration count + 1). When a conditional branch instruction with the same address as the instruction in the entry appears again (i.e., a loop branch instruction in the non-first complete execution process of the innermost loop), if the TAGE predictor predicts that the branch instruction is a jump, and the instruction decoding unit also interprets the conditional branch instruction as a jump, then the iteration count (current iteration count) in the entry needs to be incremented by 1. If the TAGE predictor predicts that the branch instruction is a jump, but the instruction decoding unit interprets the conditional branch instruction as a non-jump, it indicates that the second complete execution process of the innermost loop has terminated. In this case, the iteration count needs to be assigned to the loop count in the entry to record the loop count of the loop body, and then the iteration count is cleared to zero.

[0110] It should be noted that the TAGE predictor will fail to predict the loop when the first complete execution of the innermost loop ends, at which point the processor begins to record the loop count. When the loop enters the second complete execution of the innermost loop, the iteration counter is used to count. When the second complete execution ends, TAGE will still predict an error, but the instruction decoding unit will still give the correct jump result (i.e., no jump occurs after the conditional branch instruction is executed at the end of the loop). Since the iteration counter records all the number of times the loop has been executed from the end of the previous loop to the end of this loop, this iteration counter is the loop count of this loop.

[0111] Step 603: When a conditional branch instruction with the same address as the instruction in the entry reappears, the iteration count starts counting and is compared with the loop count until the iteration count equals the loop count. Then, the confidence bit is checked. If the confidence bit is not 1 (the first target value), and the instruction decoding unit parses that the conditional branch instruction will not jump after execution, the confidence bit is set to 1; otherwise, it is set to 0. No prediction result is given when the confidence bit is 0. If the confidence bit is 1, it is considered that loop termination has occurred, and loop termination prediction information is given, i.e., it is predicted that no jump will occur after the conditional branch instruction is executed. This prediction result overwrites the prediction result of TAGE, thus correcting the prediction result of TAGE using the prediction result of the loop termination predictor.

[0112] Step 604: After the prediction result of the loop termination predictor overwrites the TAGE prediction result, if the prediction result of the loop termination predictor is consistent with the result parsed by the instruction decoding unit, the aging count begins to accumulate. When the entry is first allocated, the aging count is 7, and the maximum count value of the counter is 7. When the prediction result of the loop termination predictor is inconsistent with the result parsed by the instruction decoding unit, the count value of the counter decreases. When the count value of the counter decreases to 0, it indicates that the information recorded in the entry has no value for use, so the information of the entry is cleared to prepare for the next loop prediction. Figure 7 As shown, by setting a number (e.g., 4) of entries, the prediction can be terminated in a loop.

[0113] To implement the above embodiments, this disclosure also proposes an instruction processing device.

[0114] Figure 8 This is a schematic diagram of the structure of an instruction processing device provided in an embodiment of the present disclosure.

[0115] like Figure 8 As shown, the instruction processing device 800 includes: a first prediction module 810, a second prediction module 820, and a correction module 830.

[0116] The first prediction module 810 is used to predict the branch direction of the current instruction using a first branch predictor in response to the current instruction being a conditional branch instruction, so as to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; the second prediction module 820 is used to predict the branch direction of the current instruction using a second branch predictor in response to the current instruction being a loop branch instruction, so as to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; the correction module 830 is used to correct the first prediction result using the second prediction result in response to the second prediction result being different from the first prediction result.

[0117] As one possible implementation, the second prediction result is generated using the following modules: a query module, a judgment module, and a generation module.

[0118] The query module, in response to a loop branch instruction within a nested loop, queries the current iteration count of the innermost loop in which the current instruction is currently executing. The judgment module, in response to the current iteration count being equal to a target count, determines whether the confidence bit value is a first target value; the target count is determined based on the first iteration count of the first complete execution of the innermost loop, and the confidence bit value indicates whether the current execution process has terminated. The generation module, in response to the confidence bit value being the first target value, generates a second prediction result indicating that no jump occurs after the current instruction is completed; the first target value indicates that the current execution process has terminated.

[0119] As one possible implementation, the generation module is also used to generate a second prediction result in response to the value of the confidence bit being a second target value, which is used to indicate that a jump occurs after the current instruction is completed; wherein, the second target value is used to indicate that the current execution process loop has not terminated.

[0120] As one possible implementation, the instruction processing device 800 also includes a rejection module.

[0121] The rejection module is used to refuse to use the second branch predictor to predict the branch direction of the current instruction in response to the current iteration number not being equal to the target number; or, in response to the confidence bit being the value of the second target value, to refuse to use the second branch predictor to predict the branch direction of the current instruction.

[0122] As one possible implementation, the instruction processing device 800 also includes an assignment module.

[0123] The assignment module is used to respond to the loop branch instruction in the non-first complete execution process of the innermost loop in a multi-level nested loop when the current instruction is to obtain the first iteration number of the first complete execution process; to count the iteration number of the non-first complete execution process to obtain the second iteration number of the non-first complete execution process; to obtain the decoding result of the current instruction when the second iteration number is the same as the first iteration number; and to assign a value to the confidence bit according to the decoding result of the current instruction.

[0124] As one possible implementation, the assignment module is used to determine the value of the confidence bit as the first target value in response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed; and to determine the value of the confidence bit as the second target value in response to the decoding result of the current instruction indicating that a jump occurs after the current instruction is executed.

[0125] As one possible implementation, the number of the first iteration is determined by the following modules: a first determining module and a second determining module.

[0126] The first determining module is used to determine that the current instruction is the last loop branch instruction in the first complete execution process in response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is completed; the second determining module is used to determine the first iteration number based on the first loop branch instruction and the last loop branch instruction in the first complete execution process.

[0127] As one possible implementation, the loop count, iteration count, and confidence bit values ​​of loop branch instructions in the same multi-level nested loop are located in the same loop entry.

[0128] As one possible implementation, the first iteration number, the current iteration number, and the value of the confidence bit corresponding to the loop branch instruction in the same multi-level nested loop are located in the same loop entry. The instruction processing device 800 also includes an increment module, a decrement module, and a deletion module.

[0129] The increment module increments the counter value corresponding to the current instruction in response to the decoding result indicating that no jump occurs after the current instruction is executed, and the second prediction result indicating that no jump occurs after the current instruction is executed; the decrement module decrements the counter value corresponding to the current instruction in response to the decoding result indicating that no jump occurs after the current instruction is executed, and the second prediction result indicating that a jump occurs after the current instruction is executed; the deletion module deletes the loop entry corresponding to the current instruction in response to the counter value corresponding to the current instruction reaching a set value.

[0130] As one possible implementation, the second prediction module 820 is used to write the current instruction into the instruction queue in response to the current instruction having a loop feature; determine whether the current instruction is a loop branch instruction based on the decoding result of the current instruction; read the current instruction from the instruction queue in response to the current instruction being a loop branch instruction; and use a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result.

[0131] As one possible implementation, the correction module 830 is used to correct the first prediction result in response to the second prediction result indicating that no jump occurs after the current instruction is completed and the first prediction result indicating that a jump occurs after the current instruction is completed.

[0132] The instruction processing apparatus of this disclosure, in response to the current instruction being a conditional branch instruction, uses a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the current instruction being a loop branch instruction, uses a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the second prediction result being different from the first prediction result, the second prediction result is used to correct the first prediction result, thereby improving the accuracy of the first prediction result. Based on the accurate first prediction result, performance loss caused by prediction errors can be reduced.

[0133] To implement the above embodiments, this disclosure also proposes an electronic device, including a processor and a memory communicatively connected to the processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the instruction processing method as described in the foregoing method embodiments.

[0134] To implement the above embodiments, this disclosure also proposes a chip including a processing circuit configured to execute the instruction processing method as described in the foregoing method embodiments.

[0135] To implement the above embodiments, this disclosure also proposes a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the instruction processing method as described in the foregoing method embodiments.

[0136] To implement the above embodiments, this disclosure also proposes a computer program product having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the instruction processing method as described in the foregoing method embodiments.

[0137] Figure 9 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. For example, the electronic device 900 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness device, personal digital assistant, etc.

[0138] Reference Figure 9 The electronic device 900 may include one or more of the following components: processing component 902, memory 904, power component 906, multimedia component 908, audio component 910, input / output (I / O) interface 912, sensor component 914, and communication component 916.

[0139] Processing component 902 typically controls the overall operation of electronic device 900, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 902 may include one or more processors 920 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 902 may include one or more modules to facilitate interaction between processing component 902 and other components. For example, processing component 902 may include a multimedia module to facilitate interaction between multimedia component 908 and processing component 902.

[0140] Memory 904 is configured to store various types of data to support the operation of electronic device 900. Examples of this data include instructions for any application or method operating on electronic device 900, contact data, phonebook data, messages, pictures, videos, etc. Memory 904 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0141] Power component 906 provides power to various components of electronic device 900. Power component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 900.

[0142] Multimedia component 908 includes a screen that provides an output interface between the electronic device 900 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 908 includes a front-facing camera and / or a rear-facing camera. When the electronic device 900 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0143] Audio component 910 is configured to output and / or input audio signals. For example, audio component 910 includes a microphone (MIC) configured to receive external audio signals when electronic device 900 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 904 or transmitted via communication component 916. In some embodiments, audio component 910 also includes a speaker for outputting audio signals.

[0144] I / O interface 912 provides an interface between processing component 902 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0145] Sensor assembly 914 includes one or more sensors for providing state assessments of various aspects of electronic device 900. For example, sensor assembly 914 can detect the on / off state of electronic device 900, the relative positioning of components such as the display and keypad of electronic device 900, changes in position of electronic device 900 or a component of electronic device 900, the presence or absence of user contact with electronic device 900, orientation or acceleration / deceleration of electronic device 900, and temperature changes of electronic device 900. Sensor assembly 914 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 914 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 914 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0146] Communication component 916 is configured to facilitate wired or wireless communication between electronic device 900 and other devices. Electronic device 900 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 916 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 916 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0147] In an exemplary embodiment, the electronic device 900 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0148] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions, which can be executed by a processor 920 of an electronic device 900 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0149] Figure 10 This is a schematic diagram of the chip structure proposed in an embodiment of this disclosure. See also... Figure 10 The diagram shown is a schematic representation of the structure of chip 1000, but it is not limited to this.

[0150] Chip 1000 includes processing circuit 1001, which is configured to perform any of the above methods.

[0151] In some embodiments, the chip 1000 further includes one or more interface circuits 1002. Optionally, the interface circuit 1002 is connected to the memory 1003, and the interface circuit 1002 can be used to receive signals from the memory 1003 or other devices, and the interface circuit 1002 can be used to send signals to the memory 1003 or other devices. For example, the interface circuit 1002 can read instructions stored in the memory 1003 and send the instructions to the processing circuit 1001.

[0152] In some embodiments, the interface circuit 1002 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 1001 performs other steps.

[0153] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0154] In some embodiments, chip 1000 further includes one or more memories 1003 for storing instructions. Optionally, all or part of the memories 1003 may be located outside of chip 1000.

[0155] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0156] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0157] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of this disclosure pertain.

[0158] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0159] It should be understood that various parts of this disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0160] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0161] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0162] The storage medium mentioned above may be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. An instruction processing method, characterized in that, include: In response to the current instruction being a conditional branch instruction, a first branch predictor is used to predict the branch direction of the current instruction to obtain a first prediction result; wherein, the first prediction result is used to indicate whether a jump occurs after the current instruction is executed. In response to the current instruction being a loop branch instruction, a second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result; wherein, the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; In response to the difference between the second prediction result and the first prediction result, the first prediction result is corrected using the second prediction result; The second prediction result is generated using the following steps: In response to the current instruction being a loop branch instruction in a multi-level nested loop, query the current iteration number of the current execution process of the innermost loop in the multi-level nested loop where the current instruction is located; In response to the current iteration count being equal to the target count, it is determined whether the value of the confidence bit is the first target value; wherein, the target count is determined based on the first iteration count of the first complete execution process of the innermost loop, and the value of the confidence bit is used to indicate whether the current execution process has terminated; In response to the value of the confidence bit being a first target value, a second prediction result is generated to indicate that no jump will occur after the current instruction is executed; wherein, the first target value is used to indicate that the current execution process will terminate in a loop.

2. The method according to claim 1, characterized in that, The second prediction result is also generated using the following steps: In response to the value of the confidence bit being a second target value, a second prediction result is generated to indicate that a jump occurs after the current instruction has been executed; wherein, the second target value is used to indicate that the current execution process loop has not terminated.

3. The method according to claim 1, characterized in that, The method further includes: In response to the current iteration number not being equal to the target number, the second branch predictor is rejected from predicting the branch direction of the current instruction; or, In response to the confidence bit being set to the second target value, the second branch predictor is rejected from predicting the branch direction of the current instruction.

4. The method according to claim 1, characterized in that, Before determining whether the confidence bit value is the first target value in response to the current iteration number being equal to the target number, the method further includes: In response to a loop branch instruction in a non-first complete execution process of the innermost loop in a multi-level nested loop, the first iteration number of the first complete execution process is obtained; The number of iterations of the non-first complete execution process is counted to obtain the second iteration number of the non-first complete execution process; In response to the second iteration number being the same as the first iteration number, the decoding result of the current instruction is obtained; The confidence bit is assigned a value based on the decoding result of the current instruction.

5. The method according to claim 4, characterized in that, Assigning a value to the confidence bit based on the decoding result of the current instruction includes: In response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, the value of the confidence bit is determined to be the first target value; In response to the decoding result of the current instruction indicating that the current instruction has been executed, a jump occurs, and the value of the confidence bit is determined to be the second target value.

6. The method according to claim 4, characterized in that, The first iteration number is determined using the following steps: In response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, the current instruction is determined to be the last loop branch instruction in the first complete execution process; The first iteration number is determined based on the first loop branch instruction and the last loop branch instruction in the first complete execution process.

7. The method according to claim 1, characterized in that, In the same nested loop, the first iteration number, the current iteration number, and the confidence bit value corresponding to the loop branch instruction are all located in the same loop entry.

8. The method according to claim 7, characterized in that, The same loop entry also includes the counter value corresponding to the loop branch instruction in the same multi-level nested loop. After correcting the first prediction result with the second prediction result, the method further includes: In response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, and the second prediction result indicating that no jump occurs after the current instruction is executed, the calculated value of the counter corresponding to the current instruction is incremented; In response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, and the second prediction result indicating that a jump occurs after the current instruction is executed, the count value of the counter corresponding to the current instruction is decremented; In response to the count value corresponding to the current instruction reaching a set value, the loop entry corresponding to the current instruction is deleted.

9. The method according to claim 1, characterized in that, In response to the current instruction being a loop branch instruction, a second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result, including: In response to the current instruction having a cyclic characteristic, the current instruction is written to the instruction queue; Based on the decoding result of the current instruction, determine whether the current instruction is a loop branch instruction; In response to the current instruction being a loop branch instruction, the current instruction is read from the instruction queue; A second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result.

10. The method according to claim 1, characterized in that, The first branch predictor includes a TAGE predictor, and the second branch predictor includes a loop termination predictor.

11. The method according to any one of claims 1-10, characterized in that, The step of correcting the first prediction result using the second prediction result in response to a difference between the second prediction result and the first prediction result includes: In response to the second prediction result indicating that no jump occurs after the current instruction is completed, and the first prediction result indicating that a jump occurs after the current instruction is completed, the second prediction result is used to correct the first prediction result.

12. An instruction processing device, characterized in that, include: The first prediction module is used to predict the branch direction of the current instruction in response to the current instruction being a conditional branch instruction, using a first branch predictor to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed. The second prediction module is used to predict the branch direction of the current instruction in response to the current instruction being a loop branch instruction, using a second branch predictor to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed. A correction module is configured to correct the first prediction result using the second prediction result in response to a difference between the second prediction result and the first prediction result. The second prediction result is generated using the following steps: In response to the current instruction being a loop branch instruction in a multi-level nested loop, query the current iteration number of the current execution process of the innermost loop in the multi-level nested loop where the current instruction is located; In response to the current iteration count being equal to the target count, it is determined whether the value of the confidence bit is the first target value; wherein, the target count is determined based on the first iteration count of the first complete execution process of the innermost loop, and the value of the confidence bit is used to indicate whether the current execution process has terminated; In response to the value of the confidence bit being a first target value, a second prediction result is generated to indicate that no jump will occur after the current instruction is executed; wherein, the first target value is used to indicate that the current execution process will terminate in a loop.

13. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-11.

14. A chip, characterized in that, The chip includes processing circuitry configured to perform the method as described in any one of claims 1-11.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-11.

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