Driving module, driving method and display device

Abstract

The present invention provides a drive module, a drive method, and a display device. The drive module includes a drive circuit and an output control circuit; the drive circuit is electrically connected to a first node, a second node, and a carry output terminal, respectively, and is configured to control the carry output terminal to output a carry signal under the control of the potential of the first node and the potential of the second node; the output control circuit is electrically connected to the carry output terminal, the second node, an output control terminal, and a drive signal output terminal, respectively, and is configured to control the drive signal output terminal to output a drive signal based on the carry signal provided by the carry output terminal under the control of the potential of the second node and an output control signal provided by the output control terminal. The present invention can achieve different refresh frequencies for different areas within a display region without affecting the shift register function of the drive circuit, thereby reducing the power consumption of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving module, a driving method and a display device. Background Art

[0002] In relevant display panels, in certain application scenarios, when the display area requires both high-refresh dynamic images and low-refresh static images, the relevant driving module cannot achieve different refresh rates in different areas of the same display area. Summary of the Invention

[0003] In one aspect, an embodiment of the present invention provides a driving module, comprising a driving circuit and an output control circuit;

[0004] The driving circuit is electrically connected to the first node, the second node and the carry output terminal respectively, and is used to control the carry output terminal to output a carry signal under the control of the potential of the first node and the potential of the second node;

[0005] The output control circuit is electrically connected to the carry output terminal, the second node, the output control terminal and the drive signal output terminal, respectively, and is used to control the drive signal output terminal to output a drive signal according to the carry signal provided by the carry output terminal under the control of the potential of the second node and the output control signal provided by the output control terminal.

[0006] Optionally, the output control circuit is also electrically connected to the first node and the output control clock signal end, and is also used to control the drive signal output end to output the drive signal under the control of the potential of the first node and the output control clock signal provided by the output control clock signal end.

[0007] Optionally, the output control circuit includes a first control circuit and a second control circuit;

[0008] The first control circuit is electrically connected to the second node, the first voltage terminal and the drive signal output terminal respectively, and is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node;

[0009] The second control circuit is electrically connected to the output control terminal, the carry output terminal and the drive signal output terminal respectively, and is used to control the communication between the carry output terminal and the drive signal output terminal under the control of the output control signal provided by the output control terminal.

[0010] Optionally, the output control circuit includes a first control circuit, a second control circuit, a third control circuit, a fourth control circuit and an energy storage circuit;

[0011] The first control circuit is electrically connected to the first node, the first voltage terminal and the control node respectively, and is used to control the connection between the first voltage terminal and the control node under the control of the potential of the first node;

[0012] The second control circuit is electrically connected to the carry output terminal, the control node and the second voltage terminal respectively, and is used to control the connection between the control node and the second voltage terminal under the control of the carry signal provided by the carry output terminal;

[0013] The third control circuit is electrically connected to the control node, the output control terminal and the drive signal output terminal respectively, and is used to control the communication between the drive signal output terminal and the output control terminal under the control of the potential of the control node;

[0014] The fourth control circuit is electrically connected to the second node, the drive signal output terminal and the first voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node;

[0015] A first end of the energy storage circuit is electrically connected to the control node, a second end of the energy storage circuit is electrically connected to the output control clock signal end, and the energy storage circuit is used to store electrical energy.

[0016] Optionally, the first control circuit includes a first transistor, and the second control circuit includes a second transistor;

[0017] The gate of the first transistor is electrically connected to the second node, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the driving signal output terminal;

[0018] A gate of the second transistor is electrically connected to the output control terminal, a first electrode of the second transistor is electrically connected to the carry output terminal, and a second electrode of the second transistor is electrically connected to the drive signal output terminal.

[0019] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, the third control circuit includes a third transistor, and the fourth control circuit includes a fourth transistor; the energy storage circuit includes a first capacitor;

[0020] The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0021] The gate of the second transistor is electrically connected to the carry output terminal, the first electrode of the second transistor is electrically connected to the second voltage terminal, and the second electrode of the second transistor is electrically connected to the control node;

[0022] The gate of the third transistor is electrically connected to the control node, the first electrode of the third transistor is electrically connected to the output control terminal, and the second electrode of the third transistor is electrically connected to the drive signal output terminal;

[0023] The gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the drive signal output terminal;

[0024] A first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to the output control clock signal end.

[0025] Optionally, the driving circuit further includes a third node control circuit, a fourth node control circuit, a first node control circuit, a fifth node control circuit, a second node control circuit, an output circuit and an output reset circuit;

[0026] The third node control circuit is electrically connected to the first clock signal terminal, the first voltage terminal, the third node, and the second node, respectively, and is configured to control the communication between the third node and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the communication between the third node and the first clock signal terminal under the control of the potential of the second node;

[0027] The fourth node control circuit is electrically connected to the third node, the fourth node, and the second clock signal terminal, respectively, and is configured to control the connection between the fourth node and the second clock signal terminal under the control of the potential of the third node, and to control the potential of the fourth node according to the potential of the third node;

[0028] The first node control circuit is electrically connected to the fourth node, the second clock signal terminal, the first node, the second node, and the second voltage terminal, respectively, and is configured to control the fourth node to be connected to the first node and maintain the potential of the first node under the control of the second clock signal provided by the second clock signal terminal, and to control the first node to be connected to the second voltage terminal under the control of the potential of the second node;

[0029] The fifth node control circuit is electrically connected to the third node, the second voltage terminal, the fifth node, the second clock signal terminal, and the second node, respectively, and is configured to control the communication between the fifth node and the second voltage terminal under the control of the potential of the third node, control the communication between the fifth node and the second clock signal terminal under the control of the potential of the second node, and control the potential of the fifth node according to the potential of the second node;

[0030] The second node control circuit is electrically connected to the first clock signal terminal, the input terminal and the second node respectively, and is used to control the communication between the second node and the input terminal under the control of the first clock signal provided by the first clock signal terminal;

[0031] The output circuit is electrically connected to the first node, the carry output terminal and the second voltage terminal respectively, and is used to control the communication between the carry output terminal and the second voltage terminal under the control of the potential of the first node;

[0032] The output reset circuit is electrically connected to the second node, the carry output terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node.

[0033] Optionally, the third node control circuit includes a fifth transistor and a sixth transistor;

[0034] The gate of the fifth transistor is electrically connected to the first clock signal terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the third node;

[0035] The gate of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the third node;

[0036] The fourth node control circuit includes a seventh transistor and a second capacitor;

[0037] The gate of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node;

[0038] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fourth node;

[0039] The first node control circuit includes an eighth transistor, a ninth transistor and a third capacitor;

[0040] The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the first node;

[0041] The gate of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the second voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0042] A first end of the third capacitor is electrically connected to the first node, and a second end of the third capacitor is electrically connected to the second voltage end;

[0043] The fifth node control circuit includes a tenth transistor, an eleventh transistor and a fourth capacitor;

[0044] The gate of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fifth node;

[0045] The gate of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the eleventh transistor is electrically connected to the fifth node;

[0046] A first end of the fourth capacitor is electrically connected to the second node, and a second end of the fourth capacitor is electrically connected to the fifth node;

[0047] The second node control circuit includes a twelfth transistor;

[0048] The gate of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the input terminal, and the second electrode of the twelfth transistor is electrically connected to the second node;

[0049] The output circuit includes an output transistor, and the output reset circuit includes an output reset transistor;

[0050] The gate of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the second voltage terminal, and the second electrode of the output transistor is electrically connected to the carry output terminal;

[0051] The gate of the output reset transistor is electrically connected to the second node, the first electrode of the output reset transistor is electrically connected to the carry output terminal, and the second electrode of the output reset transistor is electrically connected to the first voltage terminal.

[0052] Optionally, the driving circuit further includes a thirteenth transistor and / or a fourteenth transistor;

[0053] The thirteenth transistor is arranged between the second electrode of the fifth transistor and the gate of the seventh transistor, and the gate of the thirteenth transistor is electrically connected to the first voltage terminal;

[0054] The fourteenth transistor is disposed between the second electrode of the twelfth transistor and the gate of the output reset transistor, and the gate of the fourteenth transistor is electrically connected to the first voltage terminal.

[0055] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned driving module. The driving method includes:

[0056] The driving circuit controls the carry output terminal to output a carry signal under the control of the potential of the first node and the potential of the second node;

[0057] The output control circuit controls the driving signal output terminal to output the driving signal according to the carry signal under the control of the potential of the second node and the output control signal provided by the output control terminal.

[0058] Optionally, the output control circuit includes a first control circuit and a second control circuit; and the step of the output control circuit controlling the drive signal output terminal to output the drive signal according to the carry signal under the control of the potential of the second node and the output control signal provided by the output control terminal includes:

[0059] When the potential of the second node is an effective voltage, the first control circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the second node;

[0060] When the output control signal is a valid voltage signal, the second control circuit controls the carry output terminal to be connected to the drive signal output terminal under the control of the output control signal.

[0061] Optionally, the output control circuit includes a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, and a tank circuit; and the step of the output control circuit controlling the drive signal output terminal to output the drive signal according to the carry signal under the control of the potential of the second node and the output control signal provided by the output control terminal includes:

[0062] When the potential of the first node is a valid voltage signal, the first control circuit controls the communication between the first voltage terminal and the control node under the control of the potential of the first node, and the third control circuit controls the communication between the drive signal output terminal and the output control terminal under the control of the potential of the control node;

[0063] When the potential of the second node is a valid voltage signal, the second control circuit controls the connection between the control node and the second voltage terminal under the control of the carry signal, and the fourth control circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node.

[0064] In a third aspect, an embodiment of the present invention provides a display device including the above-mentioned driving module.

[0065] Optionally, the display device according to at least one embodiment of the present invention further includes a multi-row and multi-column pixel circuit; the pixel circuit includes a light-emitting element, a display driving circuit, and a compensation control circuit;

[0066] The control terminal of the compensation control circuit is electrically connected to the first drive signal terminal, the first terminal of the compensation control circuit is electrically connected to the control terminal of the display drive circuit, and the second terminal of the compensation control circuit is electrically connected to the second terminal of the display drive circuit, and the compensation control circuit is used to control the communication between the control terminal of the display drive circuit and the second terminal of the display drive circuit under the control of the first drive signal provided by the first drive signal terminal;

[0067] A first terminal of the display driving circuit is electrically connected to a power supply voltage terminal, a second terminal of the display driving circuit is electrically connected to the light emitting element, and the display driving circuit is configured to drive the light emitting element under the control of the potential of its control terminal;

[0068] The first driving signal terminal is electrically connected to a driving signal output terminal included in the driving module. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 is a structural diagram of the relevant display panel;

[0070] Figure 2 is a circuit diagram of at least one embodiment of a pixel circuit in a display device according to an embodiment of the present invention;

[0071] Figure 3 yes Figure 2 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0072] Figure 4 is a timing diagram of the first driving signal of each row;

[0073] Figure 5 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0074] Figure 6 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0075] Figure 7 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0076] Figure 8 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0077] Figure 9 is a circuit diagram of a portion of the circuit of a driving module according to at least one embodiment of the present invention;

[0078] Figure 10 is a circuit diagram of a portion of the circuit of a driving module according to at least one embodiment of the present invention;

[0079] Figure 11 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0080] Figure 12 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0081] Figure 13 is a circuit diagram of a driving module according to at least one embodiment of the present invention;

[0082] Figure 14 This invention Figure 13 A simulation operation timing diagram of at least one embodiment of the driving module shown in FIG. 1 at low-frequency refresh;

[0083] Figure 15 This invention Figure 13 A simulation operation timing diagram of at least one embodiment of the driving module shown in FIG. 1 during normal refresh;

[0084] Figure 16 is a circuit diagram of a driving module according to at least one embodiment of the present invention;

[0085] Figure 17 This invention Figure 16 A simulation operation timing diagram of at least one embodiment of the driving module shown in FIG. 1 at low-frequency refresh;

[0086] Figure 18 This invention Figure 16 A simulation operation timing diagram of at least one embodiment of the driving module shown in FIG. 1 during normal refresh;

[0087] Figure 19 is a circuit diagram of at least one embodiment of a pixel circuit in a display device according to an embodiment of the present invention;

[0088] Figure 20 is a circuit diagram of at least one embodiment of a pixel circuit in a display device according to an embodiment of the present invention;

[0089] Figure 21 is a circuit diagram of at least one embodiment of a pixel circuit in a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0090] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0091] The transistors used in all embodiments of the present invention may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0092] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain, and the second electrode may be a source; or, the first electrode may be a source, and the second electrode may be a drain.

[0093] The driving module described in the embodiment of the present invention includes a driving circuit and an output control circuit;

[0094] The driving circuit is electrically connected to the first node, the second node and the carry output terminal respectively, and is used to control the carry output terminal to output a carry signal under the control of the potential of the first node and the potential of the second node;

[0095] The output control circuit is electrically connected to the carry output terminal, the second node, the output control terminal and the drive signal output terminal, respectively, and is used to control the drive signal output terminal to output a drive signal according to the carry signal provided by the carry output terminal under the control of the potential of the second node and the output control signal provided by the output control terminal.

[0096] The driving module described in the embodiment of the present invention adopts an output control circuit. The output control circuit controls the driving signal output terminal to output the driving signal according to the carry signal under the control of the potential of the second node and the output control signal. By controlling the driving signal, whether the data voltage is written into the pixel circuit is controlled. Under the premise of not affecting the shift register function of the driving circuit, different areas in the display area can have different refresh frequencies, thereby reducing the power consumption of the display panel.

[0097] In some application scenarios, the display area needs to display both high-refresh dynamic images and low-refresh static images. Based on this, the embodiment of the present invention adopts an output control circuit to achieve the effect of different refresh frequencies in different areas of the display area.

[0098] In at least one embodiment of the present invention, the driving circuit may be a 10T3C driving circuit, a 12T3C driving circuit, a 13T3C driving circuit, or a 16T3C driving circuit, but is not limited thereto.

[0099] like Figure 1 As shown, the display panel may include a plurality of rows and columns of pixel circuits arranged in the display area A0 and the following three units:

[0100] The data processing unit 11 is used to determine whether the image to be displayed is a dynamic image or a static image based on the data voltage, and to determine the dividing point between the static image and the dynamic image, and to transmit the dividing point to the scanning control unit 12;

[0101] The scanning control unit 12 is used to control the writing of data voltage and reset signal into the pixel circuit in the display area A0, and control the pixel circuit to complete reset, data writing, and reset. The scanning control unit 12 is used to generate a first drive signal NS, a second drive signal PS, a first reset control signal PSR1, and a second reset control signal PSR2. The first drive signal NS controls whether the data voltage regulates and compensates the luminous brightness in the pixel circuit, the second drive signal PS controls whether the data voltage is written into the pixel circuit, the first reset control signal PSR1 controls the resetting of the drain of the drive transistor by the first initial voltage, and the second reset control signal PSR2 controls the resetting of the first electrode of the light-emitting element by the second initial voltage.

[0102] The light emitting control unit 13 is configured to generate a light emitting control signal EM, and to control the light emitting of the pixel circuit via the light emitting control signal EM.

[0103] exist Figure 1 In the figure, only one pixel circuit P0 disposed in the display area A0 is schematically shown. In actual operation, multiple rows and columns of pixel circuits are disposed in the display area A0.

[0104] In at least one embodiment of the present invention, the driving signal provided by the driving module may be the first driving signal, but is not limited thereto.

[0105] Figure 2 is a circuit diagram of at least one embodiment of a pixel circuit in a display device according to an embodiment of the present invention.

[0106] like Figure 2 As shown, at least one embodiment of the pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an organic light emitting diode O1 and a storage capacitor Cst;

[0107] The gate of M1 is connected to the first reset control signal PSR1;

[0108] The gate of M2 is connected to the first driving signal NS;

[0109] The gate of M4 is connected to the second driving signal PS;

[0110] The gate of M5 is connected to the light emitting control signal EM;

[0111] The gate of M6 is connected to the light emitting control signal EM;

[0112] The gate of M7 is connected to the second reset control signal PSR2;

[0113] exist Figure 2 In the figure, the terminal labeled VDD is the power supply voltage terminal, the terminal labeled VSS is the low level terminal, the terminal labeled DT is the data line, the terminal labeled I1 is the first initial voltage terminal, and the terminal labeled I2 is the second initial voltage terminal. The first initial voltage terminal I1 is used to provide the first initial voltage Vinit1, and the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2.

[0114] exist Figure 2 In at least one embodiment of the pixel circuit shown, M2 is an n-type transistor and the other transistors are p-type transistors;

[0115] M2 is an oxide transistor, and transistors other than M2 may be LTPS (low temperature polysilicon) transistors.

[0116] like Figure 3 As shown, Figure 2 When at least one embodiment of the pixel circuit shown operates in a high-frequency driving mode, a refresh frame may include a first reset phase S1, a data writing phase S2, a second reset phase S3, and a light emitting phase S4, which are arranged in sequence;

[0117] In the first reset phase S1, PSR1 is a low voltage signal, M2 is turned on, the potential of NS jumps high, M2 is turned on, and the first initial voltage Vinit1 is written to the gate of M3, refreshing the signal of the previous frame to Vinit1, and preparing to write the data voltage of the new frame;

[0118] In the data writing phase S2, PSR1 is a high voltage signal;

[0119] At the beginning of the data writing phase S2, M3 is in the open state, NS is a high voltage signal, M2 is continuously open, PS is a low voltage signal, and the data voltage Vdata provided by DT charges Cst through M4, M3 and M2 to complete the charging compensation process;

[0120] In the second reset phase S3, NS is a low voltage signal, PSR2 is a low voltage signal, M7 is turned on, and the second initial voltage Vinit2 provided by I2 is written to the anode of O1, ensuring that in the light-emitting phase S4, the anode of O1 can be smoothly applied with the required voltage to complete light emission;

[0121] In the light-emitting stage S4, EM is a low voltage signal, M5 and M6 are turned on, and M3 drives O1 to emit light;

[0122] The above process is repeated continuously to complete the normal mode display refresh and light-emitting process.

[0123] Figure 2 At least one embodiment of the pixel circuit shown is implemented as follows when performing mixed refresh rate driving:

[0124] like Figure 4 As shown, according to actual needs, when the data processing unit determines that the current row image is a static image through the data voltage, the required refresh frequency is low at this time. In the second frame of the row, the potential of NS can be controlled to be long low. In the second frame of the row, M2 is not turned on, the potential of the gate of M3 is not refreshed, and the reset, data writing and charging compensation of the gate potential of M3 cannot be performed. The gate potential of M3 still maintains the voltage of the first frame. At this time, the data voltage of the row is no longer input, and low-frequency refresh is achieved;

[0125] When the data processing unit determines that the current row image is a dynamic image through the data voltage, it controls the normal output NS.

[0126] exist Figure 4 Among them, the time labeled F1 is the first frame display time, the time labeled F2 is the second frame display time, the time labeled F3 is the third frame display time, and the time labeled F4 is the fourth frame display time;

[0127] The signal labeled PS is the second driving signal, the signal labeled NS1 is the first driving signal of the first row, the signal labeled NS2 is the first driving signal of the second row, the signal labeled NS3 is the first driving signal of the third row, the signal labeled PS is the second driving signal, the signal labeled NSn-1 is the first driving signal of the n-1th row, the signal labeled NSn-m is the first driving signal of the nth row to the first driving signal of the mth row, the signal labeled NSm+1-x is the first driving signal of the m+1th row to the first driving signal of the xth row, and the signal labeled Vdata is the data voltage;

[0128] Wherein, n, m and x are all positive integers.

[0129] like Figure 5 As shown, the driving module according to at least one embodiment of the present invention includes a driving circuit 51 and an output control circuit 52;

[0130] The driving circuit 51 is electrically connected to the first node N1, the second node N2 and the carry output terminal CR, respectively, and is used to control the carry output terminal CR to output a carry signal under the control of the potential of the first node N1 and the potential of the second node N2;

[0131] The output control circuit 52 is electrically connected to the carry output terminal CR, the second node N2, the output control terminal MS and the drive signal output terminal OT, respectively, and is used to control the drive signal output terminal OT to output a drive signal according to the carry signal provided by the carry output terminal CR under the control of the potential of the second node N2 and the output control signal provided by the output control terminal MS.

[0132] The driving module described in at least one embodiment of the present invention adopts an output control circuit 52. Under the control of the potential of the second node N2 and the output control signal, the output control circuit 52 controls the driving signal output terminal OT to output the driving signal according to the carry signal. By controlling the driving signal, it is controlled whether the data voltage is written into the pixel circuit. Under the premise of not affecting the shift register function of the driving circuit, different areas in the display area can have different refresh frequencies, thereby reducing the power consumption of the display panel.

[0133] At least one embodiment of the present invention controls the output drive signal through the output control circuit 52 , and can control the potential of the drive signal to be high or low according to actual needs.

[0134] At least one embodiment of the present invention can realize arbitrary control of the row scanning signal to achieve arbitrary refresh rate of any area in the display area. Different refresh rates can be realized for different areas of the display area of ​​the display panel according to actual needs, and dynamic refresh of any area can be realized.

[0135] In at least one embodiment of the present invention, the output control circuit is also electrically connected to the first node and the output control clock signal terminal, and is also used to control the drive signal output terminal to output the drive signal under the control of the potential of the first node and the output control clock signal provided by the output control clock signal terminal.

[0136] In a specific implementation, the output control circuit may further control the drive signal output terminal to output the drive signal under the control of the potential of the first node and the output control clock signal.

[0137] In at least one embodiment of the present invention, the output control clock signal may be a first clock signal or a second clock signal, but is not limited thereto.

[0138] like Figure 6 As shown, in Figure 5Based on at least one embodiment of the driving module shown, the output control circuit is also electrically connected to the first node N1 and the first clock signal terminal CK, and is also used to control the driving signal output terminal OT to output the driving signal under the control of the potential of the first node N1 and the first clock signal provided by the first clock signal terminal CK.

[0139] Optionally, the output control circuit includes a first control circuit and a second control circuit;

[0140] The first control circuit is electrically connected to the second node, the first voltage terminal and the drive signal output terminal respectively, and is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node;

[0141] The second control circuit is electrically connected to the output control terminal, the carry output terminal and the drive signal output terminal respectively, and is used to control the communication between the carry output terminal and the drive signal output terminal under the control of the output control signal provided by the output control terminal.

[0142] In a specific implementation, the output control circuit may include a first control circuit and a second control circuit. The first control circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node, and the second control circuit controls the connection between the carry output terminal and the drive signal output terminal under the control of the output control signal.

[0143] Optionally, the first voltage end may be a low voltage end, but is not limited thereto.

[0144] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the driving module shown, the output control circuit includes a first control circuit 71 and a second control circuit 72;

[0145] The first control circuit 71 is electrically connected to the second node N2, the first voltage terminal V1 and the drive signal output terminal OT respectively, and is used to control the connection between the drive signal output terminal OT and the first voltage terminal V1 under the control of the potential of the second node N2;

[0146] The second control circuit 72 is electrically connected to the output control terminal MS, the carry output terminal CR and the drive signal output terminal OT respectively, and is used to control the connection between the carry output terminal CR and the drive signal output terminal OT under the control of the output control signal Vms provided by the output control terminal MS.

[0147] Optionally, the output control circuit includes a first control circuit, a second control circuit, a third control circuit, a fourth control circuit and an energy storage circuit;

[0148] The first control circuit is electrically connected to the first node, the first voltage terminal and the control node respectively, and is used to control the connection between the first voltage terminal and the control node under the control of the potential of the first node;

[0149] The second control circuit is electrically connected to the carry output terminal, the control node and the second voltage terminal respectively, and is used to control the connection between the control node and the second voltage terminal under the control of the carry signal provided by the carry output terminal;

[0150] The third control circuit is electrically connected to the control node, the output control terminal and the drive signal output terminal respectively, and is used to control the communication between the drive signal output terminal and the output control terminal under the control of the potential of the control node;

[0151] The fourth control circuit is electrically connected to the second node, the drive signal output terminal and the first voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node;

[0152] A first end of the energy storage circuit is electrically connected to the control node, a second end of the energy storage circuit is electrically connected to the output control clock signal end, and the energy storage circuit is used to store electrical energy.

[0153] In a specific implementation, the output control circuit may include a first control circuit, a second control circuit, a third control circuit, a fourth control circuit and a storage circuit; the first control circuit controls the connection between the first voltage terminal and the control node under the control of the potential of the first node; the second control circuit controls the connection between the control node and the second voltage terminal under the control of the carry signal; the third control circuit controls the connection between the drive signal output terminal and the output control terminal under the control of the potential of the control node; the fourth control circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node.

[0154] Optionally, the first voltage terminal may be a low voltage terminal, and the second voltage terminal may be a high voltage terminal.

[0155] like Figure 8 As shown, in Figure 6 Based on at least one embodiment of the driving module shown, the output control circuit includes a first control circuit 71, a second control circuit 72, a third control circuit 73, a fourth control circuit 74 and an energy storage circuit 75;

[0156] The first control circuit 71 is electrically connected to the first node N1, the first voltage terminal V1 and the control node NC respectively, and is used to control the connection between the first voltage terminal V1 and the control node NC under the control of the potential of the first node N1;

[0157] The second control circuit 72 is electrically connected to the carry output terminal CR, the control node NC and the second voltage terminal V2, respectively, and is used to control the connection between the control node NC and the second voltage terminal V2 under the control of the carry signal provided by the carry output terminal CR;

[0158] The third control circuit 73 is electrically connected to the control node NC, the output control terminal MS, and the drive signal output terminal OT, respectively, and is used to control the connection between the drive signal output terminal OT and the output control terminal MS under the control of the potential of the control node NC; the output control terminal MS is used to provide the output control signal Vms;

[0159] The fourth control circuit 74 is electrically connected to the second node N2, the drive signal output terminal OT and the first voltage terminal V1 respectively, and is used to control the connection between the drive signal output terminal OT and the first voltage terminal V1 under the control of the potential of the second node N2;

[0160] A first end of the energy storage circuit 75 is electrically connected to the control node NC, and a second end of the energy storage circuit 75 is electrically connected to the first clock signal terminal CK. The energy storage circuit 75 is used to store electrical energy.

[0161] exist Figure 8 In at least one embodiment shown, the output control clock signal terminal is the first clock signal terminal, but the present invention is not limited thereto.

[0162] In at least one embodiment of the present invention, the first control circuit includes a first transistor, and the second control circuit includes a second transistor;

[0163] The gate of the first transistor is electrically connected to the second node, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the driving signal output terminal;

[0164] A gate of the second transistor is electrically connected to the output control terminal, a first electrode of the second transistor is electrically connected to the carry output terminal, and a second electrode of the second transistor is electrically connected to the drive signal output terminal.

[0165] In at least one embodiment of the present invention, the first control circuit includes a first transistor, the second control circuit includes a second transistor, the third control circuit includes a third transistor, and the fourth control circuit includes a fourth transistor; the energy storage circuit includes a first capacitor;

[0166] The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0167] The gate of the second transistor is electrically connected to the carry output terminal, the first electrode of the second transistor is electrically connected to the second voltage terminal, and the second electrode of the second transistor is electrically connected to the control node;

[0168] The gate of the third transistor is electrically connected to the control node, the first electrode of the third transistor is electrically connected to the output control terminal, and the second electrode of the third transistor is electrically connected to the drive signal output terminal;

[0169] The gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the drive signal output terminal;

[0170] A first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to the output control clock signal end.

[0171] like Figure 9 As shown, in Figure 7 Based on at least one embodiment of the driving module shown, the first control circuit includes a first transistor T1, and the second control circuit includes a second transistor T2;

[0172] The gate of the first transistor T1 is electrically connected to the second node N2, the source of the first transistor T1 is electrically connected to the low voltage terminal VGL, and the drain of the first transistor T1 is electrically connected to the driving signal output terminal OT;

[0173] The gate of the second transistor T2 is electrically connected to the output control terminal MS, the source of the second transistor T2 is electrically connected to the carry output terminal CR, and the drain of the second transistor T2 is electrically connected to the drive signal output terminal OT;

[0174] exist Figure 9 , the output transistor labeled To is included in the driving circuit, and the output reset transistor labeled Tf is included in the driving circuit;

[0175] The gate of To is electrically connected to the first node N1, the source of To is electrically connected to the high voltage terminal VGH, and the drain of To is electrically connected to the carry output terminal CR;

[0176] A gate of Tf is electrically connected to the second node N2 , a source of Tf is electrically connected to the carry output terminal CR, and a drain of Tf is electrically connected to the low voltage terminal VGL.

[0177] exist Figure 9 In the embodiment, T1, T2, To and Tf are all p-type transistors, but the present invention is not limited thereto.

[0178] The present invention Figure 9 At least one embodiment of the driving module shown is in operation.

[0179] When the potential of N2 is low, Tf is turned on and CR outputs a low voltage signal. At the same time, T1 is turned on, OT is connected to the low voltage terminal VGL, and OT outputs a low voltage signal to keep M2 in the pixel circuit closed.

[0180] When the potential of N2 jumps to a high level, Tf and T1 are turned off; when MS provides a low voltage signal, OT and CR are connected, and when MS provides a high voltage signal, OT and CR are disconnected;

[0181] When the current row image is a static image and needs to be refreshed at a low frequency, the waveform of Vms is the same as the waveform of the carry signal provided by CR, and OT outputs a low voltage signal;

[0182] When the current row image is a dynamic image and needs to be refreshed normally, the Vms provided by MS is a low voltage signal, T2 is turned on, OT and CR are connected, and the driving signal output by OT is the same as the carry signal provided by CR.

[0183] like Figure 10 As shown, in Figure 8 Based on at least one embodiment of the driving module shown, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2; the third control circuit includes a third transistor T3, the fourth control circuit includes a fourth transistor T4; the energy storage circuit includes a first capacitor C1;

[0184] The gate of the first transistor T1 is electrically connected to the first node N1, the source of the first transistor T1 is electrically connected to the low voltage terminal VGL, and the drain of the first transistor T1 is electrically connected to the control node NC;

[0185] The gate of the second transistor T2 is electrically connected to the carry output terminal CR, the source of the second transistor T2 is electrically connected to the high voltage terminal VGH, and the drain of the second transistor T2 is electrically connected to the control node NC;

[0186] The gate of the third transistor T3 is electrically connected to the control node NC, the source of the third transistor T3 is electrically connected to the output control terminal MS, and the drain of the third transistor T3 is electrically connected to the drive signal output terminal OT;

[0187] The gate of the fourth transistor T4 is electrically connected to the second node N2, the source of the fourth transistor T4 is electrically connected to the low voltage terminal VGL, and the drain of the fourth transistor T4 is electrically connected to the driving signal output terminal OT;

[0188] A first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the first clock signal terminal CK;

[0189] exist Figure 10 , the output transistor labeled To is included in the driving circuit, and the output reset transistor labeled Tf is included in the driving circuit;

[0190] The gate of To is electrically connected to the first node N1, the source of To is electrically connected to the high voltage terminal VGH, and the drain of To is electrically connected to the carry output terminal CR;

[0191] A gate of Tf is electrically connected to the second node N2 , a source of Tf is electrically connected to the carry output terminal CR, and a drain of Tf is electrically connected to the low voltage terminal VGL.

[0192] exist Figure 10 In at least one embodiment of the driving module shown, T1 , T2 , T3 , T4 , To and Tf are all p-type transistors, but the present invention is not limited thereto.

[0193] Figure 10 At least one embodiment of the driving module shown is in operation.

[0194] When the potential of N1 is low, To is turned on, CR outputs a high voltage signal, T1 is turned on, the potential of NC is low, T3 is turned on, and OT is connected to MS;

[0195] When the potential of N2 is low, CR outputs a low voltage signal, T2 is turned on, the potential of NC is high voltage, T3 is turned off, OT is disconnected from MS, T4 is turned on, and OT outputs a low voltage signal.

[0196] Figure 10 At least one embodiment of the driving module shown is in operation.

[0197] When the potential of NC is low, or the potential of NC is pulled down to a lower level by the first clock signal provided by the first clock signal terminal CK, Vms remains a low voltage signal. At this time, even if CR outputs a high voltage signal, OT will also output a low voltage signal.

[0198] When the potential of NC is low, or the potential of NC is pulled down to a lower level by the first clock signal provided by the first clock signal terminal CK, the waveform of Vms remains the same as the waveform of the carry signal output by CR, and the driving signal output by OT is the same as the carry signal provided by CR;

[0199] When CR outputs a low voltage signal, the potential of N2 is low, T4 is turned on, OT outputs a low voltage signal, T2 is turned on to control the connection between NC and VGH, so that the potential of NC is stable at a high level, so that T3 remains in the off state.

[0200] Optionally, the driving circuit further includes a third node control circuit, a fourth node control circuit, a first node control circuit, a fifth node control circuit, a second node control circuit, an output circuit and an output reset circuit;

[0201] The third node control circuit is electrically connected to the first clock signal terminal, the first voltage terminal, the third node, and the second node, respectively, and is configured to control the communication between the third node and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the communication between the third node and the first clock signal terminal under the control of the potential of the second node;

[0202] The fourth node control circuit is electrically connected to the third node, the fourth node, and the second clock signal terminal, respectively, and is configured to control the connection between the fourth node and the second clock signal terminal under the control of the potential of the third node, and to control the potential of the fourth node according to the potential of the third node;

[0203] The first node control circuit is electrically connected to the fourth node, the second clock signal terminal, the first node, the second node, and the second voltage terminal, respectively, and is configured to control the fourth node to be connected to the first node and maintain the potential of the first node under the control of the second clock signal provided by the second clock signal terminal, and to control the first node to be connected to the second voltage terminal under the control of the potential of the second node;

[0204] The fifth node control circuit is electrically connected to the third node, the second voltage terminal, the fifth node, the second clock signal terminal, and the second node, respectively, and is configured to control the communication between the fifth node and the second voltage terminal under the control of the potential of the third node, control the communication between the fifth node and the second clock signal terminal under the control of the potential of the second node, and control the potential of the fifth node according to the potential of the second node;

[0205] The second node control circuit is electrically connected to the first clock signal terminal, the input terminal and the second node respectively, and is used to control the communication between the second node and the input terminal under the control of the first clock signal provided by the first clock signal terminal;

[0206] The output circuit is electrically connected to the first node, the carry output terminal and the second voltage terminal respectively, and is used to control the communication between the carry output terminal and the second voltage terminal under the control of the potential of the first node;

[0207] The output reset circuit is electrically connected to the second node, the carry output terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node.

[0208] like Figure 11 As shown, in Figure 7 Based on at least one embodiment of the driving module shown, the driving circuit further includes a third node control circuit 111, a fourth node control circuit 112, a first node control circuit 113, a fifth node control circuit 114, a second node control circuit 115, an output circuit 116 and an output reset circuit 117;

[0209] The third node control circuit 111 is electrically connected to the first clock signal terminal CK, the first voltage terminal V1, the third node N3, and the second node N2, respectively, and is configured to control the communication between the third node N3 and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal, and to control the communication between the third node N3 and the first clock signal terminal CK under the control of the potential of the second node N2;

[0210] The fourth node control circuit 112 is electrically connected to the third node N3, the fourth node N4, and the second clock signal terminal CB, respectively, and is configured to control the connection between the fourth node N4 and the second clock signal terminal CB under the control of the potential of the third node N3, and to control the potential of the fourth node N4 according to the potential of the third node N3;

[0211] The first node control circuit 113 is electrically connected to the fourth node N4, the second clock signal terminal CB, the first node N1, the second node N2, and the second voltage terminal V2, respectively, and is configured to control the fourth node N4 to be connected to the first node N1 and maintain the potential of the first node N1 under the control of the second clock signal provided by the second clock signal terminal CB, and to control the first node N1 to be connected to the second voltage terminal V2 under the control of the potential of the second node N2;

[0212] The fifth node control circuit 114 is electrically connected to the third node N3, the second voltage terminal V2, the fifth node N5, the second clock signal terminal CB, and the second node N2, respectively, and is configured to control the communication between the fifth node N5 and the second voltage terminal V2 under the control of the potential of the third node N3, control the communication between the fifth node N5 and the second clock signal terminal CB under the control of the potential of the second node N2, and control the potential of the fifth node N5 according to the potential of the second node N2;

[0213] The second node control circuit 115 is electrically connected to the first clock signal terminal CK, the input terminal I0 and the second node N2 respectively, and is used to control the connection between the second node N2 and the input terminal I0 under the control of the first clock signal provided by the first clock signal terminal CK;

[0214] The output circuit 116 is electrically connected to the first node N1, the carry output terminal CR, and the second voltage terminal V2, respectively, and is used to control the communication between the carry output terminal CR and the second voltage terminal V2 under the control of the potential of the first node N1;

[0215] The output reset circuit 117 is electrically connected to the second node N2, the carry output terminal CR and the first voltage terminal V1 respectively, and is used to control the communication between the carry output terminal CR and the first voltage terminal V1 under the control of the potential of the second node N2.

[0216] like Figure 12 As shown, in Figure 8 Based on at least one embodiment of the driving module shown, the driving circuit further includes a third node control circuit 111, a fourth node control circuit 112, a first node control circuit 113, a fifth node control circuit 114, a second node control circuit 115, an output circuit 116 and an output reset circuit 117;

[0217] The third node control circuit 111 is electrically connected to the first clock signal terminal CK, the first voltage terminal V1, the third node N3, and the second node, respectively, and is configured to control the communication between the third node N3 and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal, and to control the communication between the third node N3 and the first clock signal terminal CK under the control of the potential of the second node N2;

[0218] The fourth node control circuit 112 is electrically connected to the third node N3, the fourth node N4, and the second clock signal terminal CB, respectively, and is configured to control the connection between the fourth node N4 and the second clock signal terminal CB under the control of the potential of the third node N3, and to control the potential of the fourth node N4 according to the potential of the third node N3;

[0219] The first node control circuit 113 is electrically connected to the fourth node N4, the second clock signal terminal CB, the first node N1, the second node N2, and the second voltage terminal V2, respectively, and is configured to control the fourth node N4 to be connected to the first node N1 and maintain the potential of the first node N1 under the control of the second clock signal provided by the second clock signal terminal CB, and to control the first node N1 to be connected to the second voltage terminal V2 under the control of the potential of the second node N2;

[0220] The fifth node control circuit 114 is electrically connected to the third node N3, the second voltage terminal V2, the fifth node N5, the second clock signal terminal CB, and the second node N2, respectively, and is configured to control the communication between the fifth node N5 and the second voltage terminal V2 under the control of the potential of the third node N3, control the communication between the fifth node N5 and the second clock signal terminal CB under the control of the potential of the second node N2, and control the potential of the fifth node N5 according to the potential of the second node N2;

[0221] The second node control circuit 115 is electrically connected to the first clock signal terminal CK, the input terminal I0 and the second node N2 respectively, and is used to control the connection between the second node N2 and the input terminal I0 under the control of the first clock signal provided by the first clock signal terminal CK;

[0222] The output circuit 116 is electrically connected to the first node N1, the carry output terminal CR, and the second voltage terminal V2, respectively, and is used to control the communication between the carry output terminal CR and the second voltage terminal V2 under the control of the potential of the first node N1;

[0223] The output reset circuit 117 is electrically connected to the second node N2, the carry output terminal CR and the first voltage terminal V1 respectively, and is used to control the communication between the carry output terminal CR and the first voltage terminal V1 under the control of the potential of the second node N2.

[0224] Optionally, the third node control circuit includes a fifth transistor and a sixth transistor;

[0225] The gate of the fifth transistor is electrically connected to the first clock signal terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the third node;

[0226] The gate of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the third node;

[0227] The fourth node control circuit includes a seventh transistor and a second capacitor;

[0228] The gate of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node;

[0229] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fourth node;

[0230] The first node control circuit includes an eighth transistor, a ninth transistor and a third capacitor;

[0231] The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the first node;

[0232] The gate of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the second voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0233] A first end of the third capacitor is electrically connected to the first node, and a second end of the third capacitor is electrically connected to the second voltage end;

[0234] The fifth node control circuit includes a tenth transistor, an eleventh transistor and a fourth capacitor;

[0235] The gate of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fifth node;

[0236] The gate of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the eleventh transistor is electrically connected to the fifth node;

[0237] A first end of the fourth capacitor is electrically connected to the second node, and a second end of the fourth capacitor is electrically connected to the fifth node;

[0238] The second node control circuit includes a twelfth transistor;

[0239] The gate of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the input terminal, and the second electrode of the twelfth transistor is electrically connected to the second node;

[0240] The output circuit includes an output transistor, and the output reset circuit includes an output reset transistor;

[0241] The gate of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the second voltage terminal, and the second electrode of the output transistor is electrically connected to the carry output terminal;

[0242] The gate of the output reset transistor is electrically connected to the second node, the first electrode of the output reset transistor is electrically connected to the carry output terminal, and the second electrode of the output reset transistor is electrically connected to the first voltage terminal.

[0243] In at least one embodiment of the present invention, the driving circuit further includes a thirteenth transistor and / or a fourteenth transistor;

[0244] The thirteenth transistor is arranged between the second electrode of the fifth transistor and the gate of the seventh transistor, and the gate of the thirteenth transistor is electrically connected to the first voltage terminal;

[0245] The fourteenth transistor is disposed between the second electrode of the twelfth transistor and the gate of the output reset transistor, and the gate of the fourteenth transistor is electrically connected to the first voltage terminal.

[0246] like Figure 13 As shown, in Figure 11 Based on at least one embodiment of the driving module shown, the first control circuit includes a first transistor T1, and the second control circuit includes a second transistor T2;

[0247] The gate of the first transistor T1 is electrically connected to the second node N2, the source of the first transistor T1 is electrically connected to the low voltage terminal VGL, and the drain of the first transistor T1 is electrically connected to the driving signal output terminal OT;

[0248] The gate of the second transistor T2 is electrically connected to the output control terminal MS, the source of the second transistor T2 is electrically connected to the carry output terminal CR, and the drain of the second transistor T2 is electrically connected to the drive signal output terminal OT; the output control terminal MS is used to provide an output control signal Vms;

[0249] The third node control circuit includes a fifth transistor T5 and a sixth transistor T6;

[0250] The gate of the fifth transistor T5 is electrically connected to the first clock signal terminal CK, the source of the fifth transistor T5 is electrically connected to the low voltage terminal VGL, and the drain of the fifth transistor T5 is electrically connected to the third control node NC3;

[0251] The gate of the sixth transistor T6 is electrically connected to the second control node NC2, the source of the sixth transistor T6 is electrically connected to the first clock signal terminal CK, and the drain of the sixth transistor T6 is electrically connected to the third node N3;

[0252] The fourth node control circuit includes a seventh transistor T7 and a second capacitor C2;

[0253] The gate of the seventh transistor T7 is electrically connected to the third node N3, the source of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and the drain of the seventh transistor T7 is electrically connected to the fourth node N4;

[0254] A first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the fourth node;

[0255] The first node control circuit includes an eighth transistor T8, a ninth transistor T9 and a third capacitor C3;

[0256] The gate of the eighth transistor T8 is electrically connected to the second clock signal terminal CB, the source of the eighth transistor T8 is electrically connected to the fourth node N4, and the drain of the eighth transistor T8 is electrically connected to the first node N1;

[0257] The gate of the ninth transistor T9 is electrically connected to the second control node NC2, the source of the ninth transistor T9 is electrically connected to the high voltage terminal VGH, and the drain of the ninth transistor T9 is electrically connected to the first node N1;

[0258] A first end of the third capacitor C3 is electrically connected to the first node N1, and a second end of the third capacitor C3 is electrically connected to the high voltage terminal VGH;

[0259] The fifth node control circuit includes a tenth transistor T10, an eleventh transistor T11 and a fourth capacitor C4;

[0260] The gate of the tenth transistor T10 is electrically connected to the third control node NC3, the source of the tenth transistor T10 is electrically connected to the high voltage terminal VGH, and the drain of the tenth transistor T10 is electrically connected to the fifth node N5;

[0261] The gate of the eleventh transistor T11 is electrically connected to the second node N2, the source of the eleventh transistor T11 is electrically connected to the second clock signal terminal CB, and the drain of the eleventh transistor T11 is electrically connected to the fifth node N5;

[0262] A first end of the fourth capacitor C4 is electrically connected to the second node N2, and a second end of the fourth capacitor C4 is electrically connected to the fifth node N5;

[0263] The second node control circuit includes a twelfth transistor T12;

[0264] The gate of the twelfth transistor T12 is electrically connected to the first clock signal terminal CK, the source of the twelfth transistor T12 is electrically connected to the input terminal I0, and the drain of the twelfth transistor T12 is electrically connected to the second control node NC2;

[0265] The output circuit includes an output transistor To, and the output reset circuit includes an output reset transistor Tf;

[0266] The gate of the output transistor To is electrically connected to the first node N1, the source of the output transistor To is electrically connected to the high voltage terminal VGH, and the drain of the output transistor To is electrically connected to the carry output terminal CR;

[0267] The gate of the output reset transistor Tf is electrically connected to the second node N2, the source of the output reset transistor Tf is electrically connected to the carry output terminal CR, and the drain of the output reset transistor Tf is electrically connected to the low voltage terminal VGL;

[0268] The driving circuit further includes a thirteenth transistor T13 and a fourteenth transistor T14;

[0269] The gate of the thirteenth transistor T13 is electrically connected to the low voltage terminal VGL, the source of T13 is electrically connected to the third control node NC3, and the drain of T13 is electrically connected to the third node N3;

[0270] The gate of the fourteenth transistor T14 is electrically connected to the low voltage terminal VGL, the source of T14 is electrically connected to the second control node NC2, and the drain of T14 is electrically connected to the second node N2.

[0271] exist Figure 13 In at least one embodiment of the driving module shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0272] The present invention Figure 13 At least one embodiment of the driving module shown is in operation.

[0273] When the potential of N2 is low, Tf is turned on, CR outputs a low voltage signal to the input terminal of the adjacent next-stage driving module. At the same time, T1 is turned on, OT outputs a low voltage signal to the pixel circuit provided in the display area to maintain the second display control transistor in the pixel circuit in the off state. The potential of NC2 is low, T9 is turned on, N1 is connected to VGH, the potential of N1 is high, and To is turned off.

[0274] When the potential of N2 jumps to a high level, T9 is closed. Only when the second clock signal provided by CB is a low voltage signal, the low voltage signal can be written to the first node N1, and C3 stores the low voltage signal. At this time, To remains in the on state before T9 is turned on, and the high voltage signal provided by VH is transmitted to CR. At this time, whether the high voltage signal is output to the display area as a row scan signal is controlled by T2. When the potential of Vms is a low level, OT can output a high voltage signal normally, and the second display control transistor in the pixel circuit in the display area can be turned on to refresh the data voltage; when the potential of Vms is a high voltage, T2 is turned off, and OT maintains the output of a low voltage signal. The second display control transistor in the pixel circuit in the display area cannot be turned on, the data voltage cannot be refreshed, and the pixel circuit will maintain the luminous state of the previous frame.

[0275] The present invention Figure 13 At least one embodiment of the driving module shown is in operation.

[0276] When the current row image is a static image and needs to be refreshed at a low frequency, the waveform of Vms can be the same as the waveform of the carry signal provided by CR, OT outputs a low voltage signal, and the second display control transistor in the pixel circuit in the display area is turned off;

[0277] When the current row image is a dynamic image and needs to be refreshed normally, MS outputs a low voltage signal, and the driving signal output by OT is the same as the carry signal provided by CR.

[0278] Figure 14 This invention Figure 13 A simulation operation timing diagram of at least one embodiment of the driving module shown in FIG. 1 at low-frequency refresh;

[0279] Figure 15 This invention Figure 13 The diagram shows a simulated operation timing diagram of at least one embodiment of the driving module during normal refresh.

[0280] like Figure 16 As shown, in Figure 12 Based on at least one embodiment of the driving module shown, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2; the third control circuit includes a third transistor T3, the fourth control circuit includes a fourth transistor T4; the energy storage circuit includes a first capacitor C1;

[0281] The gate of the first transistor T1 is electrically connected to the first node N1, the source of the first transistor T1 is electrically connected to the low voltage terminal VGL, and the drain of the first transistor T1 is electrically connected to the control node NC;

[0282] The gate of the second transistor T2 is electrically connected to the carry output terminal CR, the source of the second transistor T2 is electrically connected to the high voltage terminal VGH, and the drain of the second transistor T2 is electrically connected to the control node NC;

[0283] The gate of the third transistor T3 is electrically connected to the control node NC, the source of the third transistor T3 is electrically connected to the output control terminal MS, and the drain of the third transistor T3 is electrically connected to the drive signal output terminal OT; the output control terminal MS is used to provide an output control signal Vms;

[0284] The gate of the fourth transistor T4 is electrically connected to the second node N2, the source of the fourth transistor T4 is electrically connected to the low voltage terminal VGL, and the drain of the fourth transistor T4 is electrically connected to the driving signal output terminal OT;

[0285] A first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the first clock signal terminal CK;

[0286] The third node control circuit includes a fifth transistor T5 and a sixth transistor T6;

[0287] The gate of the fifth transistor T5 is electrically connected to the first clock signal terminal CK, the source of the fifth transistor T5 is electrically connected to the low voltage terminal VGL, and the drain of the fifth transistor T5 is electrically connected to the third node N3;

[0288] The gate of the sixth transistor T6 is electrically connected to the second control node NC2, the source of the sixth transistor T6 is electrically connected to the first clock signal terminal CK, and the drain of the sixth transistor T6 is electrically connected to the third node N3;

[0289] The fourth node control circuit includes a seventh transistor T7 and a second capacitor C2;

[0290] The gate of the seventh transistor T7 is electrically connected to the third node N3, the source of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and the drain of the seventh transistor T7 is electrically connected to the fourth node N4;

[0291] A first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the fourth node;

[0292] The first node control circuit includes an eighth transistor T8, a ninth transistor T9 and a third capacitor C3;

[0293] The gate of the eighth transistor T8 is electrically connected to the second clock signal terminal CB, the source of the eighth transistor T8 is electrically connected to the fourth node N4, and the drain of the eighth transistor T8 is electrically connected to the first node N1;

[0294] The gate of the ninth transistor T9 is electrically connected to the second control node NC2, the source of the ninth transistor T9 is electrically connected to the high voltage terminal VGH, and the drain of the ninth transistor T9 is electrically connected to the first node N1;

[0295] A first end of the third capacitor C3 is electrically connected to the first node N1, and a second end of the third capacitor C3 is electrically connected to the high voltage terminal VGH;

[0296] The fifth node control circuit includes a tenth transistor T10, an eleventh transistor T11 and a fourth capacitor C4;

[0297] The gate of the tenth transistor T10 is electrically connected to the third node N3, the source of the tenth transistor T10 is electrically connected to the high voltage terminal VGH, and the drain of the tenth transistor T10 is electrically connected to the fifth node N5;

[0298] The gate of the eleventh transistor T11 is electrically connected to the second node N2, the source of the eleventh transistor T11 is electrically connected to the second clock signal terminal CB, and the drain of the eleventh transistor T11 is electrically connected to the fifth node N5;

[0299] A first end of the fourth capacitor C4 is electrically connected to the second node N2, and a second end of the fourth capacitor C4 is electrically connected to the fifth node N5;

[0300] The second node control circuit includes a twelfth transistor T12;

[0301] The gate of the twelfth transistor T12 is electrically connected to the first clock signal terminal CK, the source of the twelfth transistor T12 is electrically connected to the input terminal I0, and the drain of the twelfth transistor T12 is electrically connected to the second control node NC2;

[0302] The output circuit includes an output transistor To, and the output reset circuit includes an output reset transistor Tf;

[0303] The gate of the output transistor To is electrically connected to the first node N1, the source of the output transistor To is electrically connected to the high voltage terminal VGH, and the drain of the output transistor To is electrically connected to the carry output terminal CR;

[0304] The gate of the output reset transistor Tf is electrically connected to the second node N2, the source of the output reset transistor Tf is electrically connected to the carry output terminal CR, and the drain of the output reset transistor Tf is electrically connected to the low voltage terminal VGL;

[0305] The driving circuit further includes a fourteenth transistor T14;

[0306] The gate of the fourteenth transistor T14 is electrically connected to the low voltage terminal VGL, the source of T14 is electrically connected to the second control node NC2, and the drain of T14 is electrically connected to the second node N2.

[0307] exist Figure 16 In at least one embodiment of the driving module shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0308] The present invention Figure 16 At least one embodiment of the driving module shown is in operation.

[0309] When the potential of the second clock signal provided by CB jumps to a low voltage, the potential of N1 is low. At this time, VGH outputs a high voltage signal to CR, and CR transmits the high voltage signal to the input end of the adjacent next-stage driver. At the same time, T1 is turned on and the potential of N4 is pulled low. When the potential of Vms is high, OT can output a high voltage signal.

[0310] When the potential of the input signal connected to I0 jumps to a low voltage and the potential of the first clock signal provided by CK is a low voltage, a low voltage signal is written into N2. When the potential of the second clock signal provided by CB jumps from a high voltage to a low voltage, the potential of N2 is pulled down to a lower potential by the bootstrap effect (the lower potential may be, for example, -14V, but is not limited thereto). At this time, Tf is fully turned on, VGL outputs a low voltage signal to CR, T4 is turned on, OT outputs a low voltage signal to the gate of the second display control transistor in the pixel circuit in the display area, T2 is turned on, and VGH provides a high voltage signal to NC, stabilizing the potential of NC at a high level, thereby avoiding unnecessary turning on of T3 due to the bootstrap effect of the first clock signal provided by CK.

[0311] The above process ensures that the driver module can drive the display normally and the basic shift register functions are not disturbed.

[0312] When the present invention Figure 16 When at least one embodiment of the driving module shown needs to be refreshed at a low frequency,

[0313] When the potential of NC is low, or is pulled to a lower level by the first clock signal provided by CK, the potential of Vms remains low. At this time, even if CR outputs a high voltage signal, OT will still output a low voltage signal.

[0314] When CR outputs a low voltage signal, OT still outputs a low voltage signal, and the potential of NC is still stabilized to a high voltage by the high voltage signal provided by VGH, ensuring that when the potential of the first clock signal provided by CK jumps, T3 remains in the off state;

[0315] The shielding and opening of the row scanning signal (the row scanning signal is the driving signal output by OT) can be achieved through the change of Vms.

[0316] Figure 17 This invention Figure 16 The working timing diagram of at least one embodiment of the driving module shown in FIG. 1 when performing low-frequency refresh;

[0317] Figure 18 This invention Figure 16 The illustrated embodiment of the driving module is a timing diagram of operation during normal refresh.

[0318] Under normal circumstances, according to actual needs, the driving signal output terminal OT needs to provide a high voltage signal within multiple clock cycles to stabilize the reset and bias processes. At this time, Vms can be designed to be at least one according to actual needs to ensure that the signals do not overlap.

[0319] The driving method according to an embodiment of the present invention is applied to the above-mentioned driving module, and the driving method includes:

[0320] The driving circuit controls the carry output terminal to output a carry signal under the control of the potential of the first node and the potential of the second node;

[0321] The output control circuit controls the driving signal output terminal to output the driving signal according to the carry signal under the control of the potential of the second node and the output control signal provided by the output control terminal.

[0322] In at least one embodiment of the present invention, the output control circuit includes a first control circuit and a second control circuit; the output control circuit controls the drive signal output terminal to output the drive signal according to the carry signal under the control of the potential of the second node and the output control signal provided by the output control terminal, including the following steps:

[0323] When the potential of the second node is an effective voltage, the first control circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the second node;

[0324] When the output control signal is a valid voltage signal, the second control circuit controls the carry output terminal to be connected to the drive signal output terminal under the control of the output control signal.

[0325] In at least one embodiment of the present invention, the output control circuit includes a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, and a tank circuit; the output control circuit, under the control of the potential of the second node and the output control signal provided by the output control terminal, controls the drive signal output terminal to output the drive signal according to the carry signal, including the following steps:

[0326] When the potential of the first node is a valid voltage signal, the first control circuit controls the first voltage terminal to be connected to the control node under the control of the potential of the first node, and the third control circuit controls the drive signal output terminal to be connected to the output control terminal under the control of the potential of the control node;

[0327] When the potential of the second node is a valid voltage signal, the second control circuit controls the connection between the control node and the second voltage terminal under the control of the carry signal, and the fourth control circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node.

[0328] The display device according to the embodiment of the present invention includes the above-mentioned driving module.

[0329] The display device according to at least one embodiment of the present invention further includes a multi-row and multi-column pixel circuit; the pixel circuit includes a light-emitting element, a display driving circuit, and a compensation control circuit;

[0330] The control terminal of the compensation control circuit is electrically connected to the first drive signal terminal, the first terminal of the compensation control circuit is electrically connected to the control terminal of the display drive circuit, and the second terminal of the compensation control circuit is electrically connected to the second terminal of the display drive circuit, and the compensation control circuit is used to control the communication between the control terminal of the display drive circuit and the second terminal of the display drive circuit under the control of the first drive signal provided by the first drive signal terminal;

[0331] A first terminal of the display driving circuit is electrically connected to a power supply voltage terminal, a second terminal of the display driving circuit is electrically connected to the light emitting element, and the display driving circuit is configured to drive the light emitting element under the control of the potential of its control terminal;

[0332] The first driving signal terminal is electrically connected to a driving signal output terminal included in the driving module.

[0333] In at least one embodiment of the present invention, the structure of the pixel circuit needs to meet the requirement that the control signal for resetting the gate of the driving transistor must and can only pass through one transistor (the transistor is the second display control transistor). The structure of at least one embodiment of the pixel circuit can also be as follows: Figure 18 、 Figure 19 or Figure 20 shown.

[0334] like Figure 19 As shown, at least one embodiment of the pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an organic light emitting diode O1 and a storage capacitor Cst;

[0335] The gate of M1 is connected to the first reset control signal PSR1;

[0336] The gate of M2 is connected to the first driving signal NS;

[0337] The gate of M4 is connected to the second driving signal PS;

[0338] The gate of M5 is connected to the light emitting control signal EM, and the gate of M6 is connected to the light emitting control signal EM;

[0339] The gate of M7 is connected to the second reset control signal PSR2;

[0340] A first terminal of Cst is electrically connected to the gate of M3, and a second terminal of Cst is electrically connected to the power supply voltage terminal VDD;

[0341] exist Figure 19 In FIG, DT is a data line, VSS is a low level terminal, I1 is a first initial voltage terminal, and I2 is a second initial voltage terminal.

[0342] exist Figure 19 In at least one embodiment of the pixel circuit shown, all transistors are LTPS transistors, and all transistors are p-type transistors, but the present invention is not limited thereto.

[0343] like Figure 20 As shown, at least one embodiment of the pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, an organic light emitting diode O1 and a storage capacitor Cst;

[0344] The gate of M1 is connected to the first reset control signal PSR1;

[0345] The gate of M2 is connected to the first driving signal NS;

[0346] The gate of M4 is connected to the second driving signal PS;

[0347] The gate of M5 is connected to the light emitting control signal EM, and the gate of M6 is connected to the light emitting control signal EM;

[0348] The gates of M7 and M8 are both connected to the second reset control signal PSR2;

[0349] A first terminal of Cst is electrically connected to the gate of T3, and a second terminal of Cst is electrically connected to the power supply voltage terminal VDD;

[0350] exist Figure 20 In FIG, DT is a data line, VSS is a low level terminal, I1 is a first initial voltage terminal, I2 is a second initial voltage terminal, and Bs is a bias voltage terminal.

[0351] exist Figure 20 In at least one embodiment of the pixel circuit shown, all transistors are LTPS transistors, and all transistors are p-type transistors, but the present invention is not limited thereto.

[0352] like Figure 21 As shown, at least one embodiment of the pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, an organic light emitting diode O1 and a storage capacitor Cst;

[0353] The gate of M1 is connected to the first reset control signal PSR1;

[0354] The gate of M2 is connected to the first driving signal NS;

[0355] The gate of M4 is connected to the second driving signal PS;

[0356] The gate of M5 is connected to the light emitting control signal EM, and the gate of M6 is connected to the light emitting control signal EM;

[0357] The gates of M7 and M8 are both connected to the second reset control signal PSR2;

[0358] A first terminal of Cst is electrically connected to the gate of T3, and a second terminal of Cst is electrically connected to the power supply voltage terminal VDD;

[0359] exist Figure 21 In FIG, DT is a data line, VSS is a low level terminal, I1 is a first initial voltage terminal, I2 is a second initial voltage terminal, and Bs is a bias voltage terminal.

[0360] exist Figure 21In at least one embodiment of the pixel circuit shown, M2 is an oxide transistor, M2 is an n-type transistor, and transistors other than M2 are LTPS transistors, and transistors other than M2 are p-type transistors, but the present invention is not limited thereto.

[0361] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0362] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A driving module, characterized in that: Including driving circuit and output control circuit; The driving circuit is electrically connected to the first node, the second node and the carry output terminal respectively, and is used to control the carry output terminal to output a carry signal under the control of the potential of the first node and the potential of the second node; The output control circuit is electrically connected to the carry output terminal, the second node, the output control terminal and the drive signal output terminal respectively, and is used to control the drive signal output terminal to output the drive signal according to the carry signal provided by the carry output terminal under the control of the potential of the second node and the output control signal provided by the output control terminal; The output control circuit includes a first control circuit and a second control circuit; the first control circuit is electrically connected to the second node, the first voltage terminal and the drive signal output terminal, respectively, and is used to control the communication between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node; the second control circuit is electrically connected to the output control terminal, the carry output terminal and the drive signal output terminal, respectively, and is used to control the communication between the carry output terminal and the drive signal output terminal under the control of the output control signal provided by the output control terminal; or, The output control circuit includes a first control circuit, a second control circuit, a third control circuit, a fourth control circuit and an energy storage circuit; the first control circuit is electrically connected to a first node, a first voltage terminal and a control node, respectively, for controlling the connection between the first voltage terminal and the control node under the control of the potential of the first node; the second control circuit is electrically connected to the carry output terminal, the control node and the second voltage terminal, respectively, for controlling the connection between the control node and the second voltage terminal under the control of a carry signal provided by the carry output terminal; the third control circuit is electrically connected to the control node, the output control terminal and the drive signal output terminal, respectively, for controlling the connection between the drive signal output terminal and the output control terminal under the control of the potential of the control node; the fourth control circuit is electrically connected to the second node, the drive signal output terminal and the first voltage terminal, respectively, for controlling the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node; a first terminal of the energy storage circuit is electrically connected to the control node, a second terminal of the energy storage circuit is electrically connected to the output control clock signal terminal, and the energy storage circuit is used to store electrical energy.

2. The driving module according to claim 1, wherein: The output control circuit is also electrically connected to the first node and the output control clock signal terminal, and is also used to control the drive signal output terminal to output a drive signal under the control of the potential of the first node and the output control clock signal provided by the output control clock signal terminal.

3. The driving module according to claim 1, wherein: The output control circuit includes a first control circuit and a second control circuit; the first control circuit includes a first transistor, and the second control circuit includes a second transistor; The gate of the first transistor is electrically connected to the second node, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the driving signal output terminal; A gate of the second transistor is electrically connected to the output control terminal, a first electrode of the second transistor is electrically connected to the carry output terminal, and a second electrode of the second transistor is electrically connected to the drive signal output terminal.

4. The driving module according to claim 1, wherein: The output control circuit includes a first control circuit, a second control circuit, a third control circuit, a fourth control circuit and an energy storage circuit; the first control circuit includes a first transistor, the second control circuit includes a second transistor, the third control circuit includes a third transistor, and the fourth control circuit includes a fourth transistor; the energy storage circuit includes a first capacitor; The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the control node; The gate of the second transistor is electrically connected to the carry output terminal, the first electrode of the second transistor is electrically connected to the second voltage terminal, and the second electrode of the second transistor is electrically connected to the control node; The gate of the third transistor is electrically connected to the control node, the first electrode of the third transistor is electrically connected to the output control terminal, and the second electrode of the third transistor is electrically connected to the drive signal output terminal; The gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the drive signal output terminal; A first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to the output control clock signal end.

5. The driving module according to any one of claims 1 to 4, wherein: The driving circuit further includes a third node control circuit, a fourth node control circuit, a first node control circuit, a fifth node control circuit, a second node control circuit, an output circuit and an output reset circuit; The third node control circuit is electrically connected to the first clock signal terminal, the first voltage terminal, the third node, and the second node, respectively, and is configured to control the communication between the third node and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the communication between the third node and the first clock signal terminal under the control of the potential of the second node; The fourth node control circuit is electrically connected to the third node, the fourth node, and the second clock signal terminal, respectively, and is configured to control the connection between the fourth node and the second clock signal terminal under the control of the potential of the third node, and to control the potential of the fourth node according to the potential of the third node; The first node control circuit is electrically connected to the fourth node, the second clock signal terminal, the first node, the second node, and the second voltage terminal, respectively, and is configured to control the fourth node to be connected to the first node and maintain the potential of the first node under the control of the second clock signal provided by the second clock signal terminal, and to control the first node to be connected to the second voltage terminal under the control of the potential of the second node; The fifth node control circuit is electrically connected to the third node, the second voltage terminal, the fifth node, the second clock signal terminal, and the second node, respectively, and is configured to control the communication between the fifth node and the second voltage terminal under the control of the potential of the third node, control the communication between the fifth node and the second clock signal terminal under the control of the potential of the second node, and control the potential of the fifth node according to the potential of the second node; The second node control circuit is electrically connected to the first clock signal terminal, the input terminal and the second node respectively, and is used to control the communication between the second node and the input terminal under the control of the first clock signal provided by the first clock signal terminal; The output circuit is electrically connected to the first node, the carry output terminal and the second voltage terminal respectively, and is used to control the communication between the carry output terminal and the second voltage terminal under the control of the potential of the first node; The output reset circuit is electrically connected to the second node, the carry output terminal and the first voltage terminal respectively, and is used to control the communication between the carry output terminal and the first voltage terminal under the control of the potential of the second node.

6. The driving module according to claim 5, wherein: The third node control circuit includes a fifth transistor and a sixth transistor; The gate of the fifth transistor is electrically connected to the first clock signal terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the third node; The gate of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the third node; The fourth node control circuit includes a seventh transistor and a second capacitor; The gate of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fourth node; The first node control circuit includes an eighth transistor, a ninth transistor and a third capacitor; The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the first node; The gate of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the second voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node; A first end of the third capacitor is electrically connected to the first node, and a second end of the third capacitor is electrically connected to the second voltage end; The fifth node control circuit includes a tenth transistor, an eleventh transistor and a fourth capacitor; The gate of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fifth node; The gate of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the eleventh transistor is electrically connected to the fifth node; A first end of the fourth capacitor is electrically connected to the second node, and a second end of the fourth capacitor is electrically connected to the fifth node; The second node control circuit includes a twelfth transistor; The gate of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the input terminal, and the second electrode of the twelfth transistor is electrically connected to the second node; The output circuit includes an output transistor, and the output reset circuit includes an output reset transistor; The gate of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the second voltage terminal, and the second electrode of the output transistor is electrically connected to the carry output terminal; The gate of the output reset transistor is electrically connected to the second node, the first electrode of the output reset transistor is electrically connected to the carry output terminal, and the second electrode of the output reset transistor is electrically connected to the first voltage terminal.

7. The driving module according to claim 6, wherein: The driving circuit further includes a thirteenth transistor and / or a fourteenth transistor; The thirteenth transistor is arranged between the second electrode of the fifth transistor and the gate of the seventh transistor, and the gate of the thirteenth transistor is electrically connected to the first voltage terminal; The fourteenth transistor is disposed between the second electrode of the twelfth transistor and the gate of the output reset transistor, and the gate of the fourteenth transistor is electrically connected to the first voltage terminal.

8. A driving method, applied to the driving module according to any one of claims 1 to 7, characterized in that: The driving method includes: The driving circuit controls the carry output terminal to output a carry signal under the control of the potential of the first node and the potential of the second node; The output control circuit controls the drive signal output terminal to output the drive signal according to the carry signal under the control of the potential of the second node and the output control signal provided by the output control terminal; The output control circuit includes a first control circuit and a second control circuit; the output control circuit controls the drive signal output terminal to output the drive signal according to the carry signal under the control of the potential of the second node and the output control signal provided by the output control terminal, including the following steps: When the potential of the second node is an effective voltage, the first control circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the second node; When the output control signal is a valid voltage signal, the second control circuit controls the communication between the carry output terminal and the drive signal output terminal under the control of the output control signal; or The output control circuit includes a first control circuit, a second control circuit, a third control circuit, a fourth control circuit and a tank circuit; the output control circuit controls the drive signal output terminal to output the drive signal according to the carry signal under the control of the potential of the second node and the output control signal provided by the output control terminal, including the following steps: When the potential of the first node is a valid voltage signal, the first control circuit controls the first voltage terminal to be connected to the control node under the control of the potential of the first node, and the third control circuit controls the drive signal output terminal to be connected to the output control terminal under the control of the potential of the control node; When the potential of the second node is a valid voltage signal, the second control circuit controls the connection between the control node and the second voltage terminal under the control of the carry signal, and the fourth control circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node.

9. A display device, characterized in that: The drive module comprises the drive module according to any one of claims 1 to 7.

10. The display device according to claim 9, wherein It also includes a multi-row and multi-column pixel circuit; the pixel circuit includes a light-emitting element, a display driving circuit and a compensation control circuit; The control terminal of the compensation control circuit is electrically connected to the first drive signal terminal, the first terminal of the compensation control circuit is electrically connected to the control terminal of the display drive circuit, and the second terminal of the compensation control circuit is electrically connected to the second terminal of the display drive circuit, and the compensation control circuit is used to control the communication between the control terminal of the display drive circuit and the second terminal of the display drive circuit under the control of the first drive signal provided by the first drive signal terminal; A first terminal of the display driving circuit is electrically connected to a power supply voltage terminal, a second terminal of the display driving circuit is electrically connected to the light emitting element, and the display driving circuit is configured to drive the light emitting element under the control of the potential of its control terminal; The first driving signal terminal is electrically connected to a driving signal output terminal included in the driving module.

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