A digital-to-analog converter calibration method based on digital domain coding remapping

Abstract

The application discloses a digital-to-analog converter calibration method based on digital domain coding remapping, which comprises an error measurement step and an error compensation step; the error measurement step adopts an auxiliary ADC to measure the weight of each DAC cell and stores the weight in a weight register; the error compensation step is realized through coding remapping in a pure digital domain, input original code words are stored in a buffer register, and a successive approximation loop controlled by a finite state machine is adopted to perform multiple digital domain comparisons, so that the inner product value of the mapping result code word and the real DAC cell weight gradually approaches the value of the buffer register, and finally ensures that the deviation between the analog domain output value and the ideal value is less than the weight of the minimum DAC cell.

Description

TECHNICAL FIELD

[0001] The present application relates to a digital-to-analog converter calibration method based on digital domain coding remapping, and relates to the technical field of electronics. BACKGROUND

[0002] Digital signal processing plays a crucial role in modern industry such as industrial control, automation production, and intelligent manufacturing. High-performance digital-to-analog converter chips are one of the foundations of digital signal processing, often used to convert digital signals into accurate analog signals, and often need to ensure high precision and high reliability.

[0003] Due to the uncertainty of chip manufacturing process, there are small process mismatches between the unit circuits that constitute the digital-to-analog converter. These mismatches will affect the accuracy of the digital-to-analog converter, and the effect on each digital-to-analog converter chip is different [1]. This effect mainly manifests in the following aspects:

[0004] Absolute deviation: the difference between the actual output value of the digital-to-analog converter and the theoretical output value. Process mismatches of on-chip devices will cause the chip output analog value to deviate from the result it should get, resulting in a decrease in the output accuracy of the digital-to-analog converter;

[0005] Nonlinearity: Process mismatches of on-chip devices will cause the output analog quantity of the digital-to-analog converter to not change linearly with the input code, resulting in nonlinear errors in the conversion curve. In communication transmitters and other applications, there will be more spurs and out-of-band energy in the signal spectrum, resulting in poor communication quality, and even the device does not meet the communication standard;

[0006] Noise: When the input code of the digital-to-analog converter switches randomly enough, the effect of process mismatches of on-chip devices can be manifested as random fluctuations superimposed on the output analog quantity, and its probability characteristics and spectral characteristics are similar to noise, which deteriorates the output signal-to-noise ratio;

[0007] Therefore, chip manufacturing process mismatches are a problem that must be solved in the design of high-precision digital-to-analog converter chips.

[0008] In order to calibrate, compensate, or circumvent the effect of process mismatches of on-chip devices on the accuracy of the digital-to-analog converter, there are currently the following existing technologies:

[0009] Dynamic element matching (DEM) [2]

[0010] Since the mathematical function of the analog-to-digital converter is to input the code word in the digital domain, and output the corresponding analog quantity (usually current or voltage), the general on-chip circuit implementation is to let each bit code word control an analog circuit unit (such as a unit capacitor or current mirror unit), so as to get the relationship between the desired analog output and the digital input code word. In digital coding, each bit corresponds to a fixed weight, and when the output values of all analog circuit units meet the corresponding bit weight, the output of the digital-to-analog converter can meet the expectation. If there is a proportional mismatch between the analog circuit units, a nonlinear error will be generated.

[0011] The dynamic unit matching technology designs a part of the digital code word as bit positions with the same weight, and when controlling the analog unit, the bit positions are disturbed from the corresponding order of the analog unit, so as to convert the nonlinear error caused by the mismatch into noise. This method of improving linearity by sacrificing noise is widely used in communication transmitter design due to the improvement of spectrum performance, but needs oversampling to realize its effect, and cannot be competent for use in instruments and industrial control.

[0012] Mismatch noise shaping (NS)

[0013] The mismatch noise shaping technology is similar to the dynamic unit matching technology, the only difference is that when disturbing the corresponding order of the bit position and the analog unit, it is not completely random, but follows a certain mathematical rule, so that the mismatch error energy scattered into noise can be concentrated in certain out-of-band frequency bands in the spectrum, and the influence on the signal-to-noise ratio of the in-band signal is minimized. Typical technologies include dynamic weighted averaging (DWA) [4]. Similarly, the effect of mismatch noise shaping technology also needs multiple data to realize, and needs oversampling.

[0014] Error compensation circuit

[0015] The error compensation technology is the most common process mismatch calibration method. This method directly eliminates the output error in the analog domain by adding an additional circuit for reverse compensation. The basic principle is as shown in Figure 1 When working normally, the input code word controls the digital-to-analog conversion unit DAC cell(1)-DAC cell(N) respectively, and at the same time, the expected output analog quantity error is calculated in the digital domain (according to the true weight value of all DAC cells measured in the factory or during the boot process), and the calculation result is used to control a compensation DAC, i.e. DAC cell(1)-DAC cell(M), and the output of the compensation DAC is subtracted from the total output of the analog-to-digital converter to get the correct result after the error is offset, Figure 1 The traditional error compensation circuit principle diagram is shown in

[0016] There are two main drawbacks to using error compensation circuits: First, additional analog circuits need to be designed, increasing the chip layout area and design complexity; second, due to the limited precision of modeling and manufacturing processes, the compensation circuit itself also has errors. More importantly, the DAC cell weight measurement is not completely accurate, and there is still a certain degree of nonlinearity after compensation, resulting in spurs in the spectrum. Summary of the Invention

[0017] This patent provides a pure digital domain DAC error compensation technology that does not increase layout area and design complexity, nor does it worsen in-band or out-of-band noise, and can further improve linearity with slight modifications.

[0018] This application provides a digital-to-analog converter calibration method based on digital domain code remapping, characterized by including an error measurement step and an error compensation step;

[0019] The error measurement step uses an auxiliary ADC to measure the weight of each DAC cell and stores it in a weight register.

[0020] The error compensation step is achieved through encoding remapping in the pure digital domain. The original input codeword is stored in a buffer register, and multiple digital domain comparisons are performed using a successive approximation loop controlled by a finite state machine. This makes the inner product of the mapped codeword and the weight of the real DAC cell gradually approach the value of the buffer register, ultimately ensuring that the deviation between the analog domain output value and the ideal value is less than the weight of the smallest DAC cell.

[0021] The technical solution further defined by the present invention is as follows: the system used in the method includes digital circuits and analog circuits, and the analog circuits include registers, digital comparators, weight registers and finite state machines.

[0022] Preferably, in the error compensation step, the digital domain performs an encoding conversion in advance, and finds an encoding representation that will not introduce errors based on the weights of each analog DAC cell pre-determined at the factory or during power-on. Then, it controls the DAC cell array in the analog domain. There is a fixed or random mapping relationship between the input original digital codeword and the codeword finally applied to the DAC cell array.

[0023] This application has at least the following technical effects or advantages: The present invention proposes a calibration and compensation method for analog-to-digital converters (ADCs). Its basic principle is based on digital domain coding remapping, which has the advantages of not increasing noise, not requiring the design of additional analog circuitry, eliminating DAC mismatch errors with minimal analog layout area and noise performance cost, not increasing analog layout and circuit complexity, and being compatible with various traditional linearity improvement techniques. It is suitable for application in high-precision DAC products. The solution of this invention is also compatible with various existing random perturbation techniques, such as dithering and shuffling, further improving the linearity of the ADC and enhancing spectral quality. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a traditional error compensation circuit.

[0025] Figure 2 This is a basic principle diagram of digital domain encoding remapping in an embodiment of the present invention;

[0026] Figure 3 This is the implementation algorithm for digital field encoding remapping in this embodiment of the invention. Implementation

[0027] The principle of this invention is to perform a pre-encoding conversion in the digital domain. Based on the pre-determined weights of each analog DAC cell during manufacturing or power-on, an encoding representation that will not introduce errors is found. This representation is then used to control the DAC cell array in the analog domain. There is a fixed or random mapping relationship between the input original digital codeword and the codeword finally applied to the DAC cell array. Therefore, it is called a digital domain encoding remapping calibration method. Its basic idea and principle diagram are shown below. Figure 2 As shown.

[0028] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0029] This embodiment provides an algorithm similar to binary search, which can be used to implement digital domain mapping. This mapping process is similar to the conversion process of an analog-to-digital converter, except that it is performed in a pure digital domain. Therefore, various variations of the conversion algorithm can also be used. Here, the working principle of this scheme is explained using a successive approximation conversion algorithm as an example. Figure 3 As shown:

[0030] Similar to traditional DAC calibration schemes, this scheme consists of two parts: error measurement and error compensation.

[0031] Error measurement still requires the use of an auxiliary ADC to measure the weight of each DAC cell. This technique is a commonly used technique and will not be elaborated upon. The weight is stored in the weight register.

[0032] The compensation algorithm is implemented through encoding remapping in the pure digital domain. The original codeword is input, usually in binary form, and stored in a buffer register. A successive approximation loop controlled by a finite state machine is used to make the inner product of the mapped codeword and the weight of the real DAC cell gradually approach the value of the buffer register after multiple comparisons in the digital domain. This ensures that the deviation between the analog domain output value and the ideal value is less than the weight of the smallest DAC cell. Mathematically, this is equivalent to solving a system of linear equations. The solved codeword is stored in another set of registers and output to the analog circuit.

[0033] Therefore, this technology neither generates additional noise nor requires the design of additional analog circuitry. It can eliminate DAC mismatch errors with minimal analog layout area and noise performance cost, and linearity can be further improved with slight modifications; it is suitable for application in high-precision DAC products.

[0034] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements can be made without departing from the principle of the present invention, and these improvements should also be considered within the scope of protection of the present invention.

Claims

1. A digital-to-analog converter calibration method based on digital domain code remapping, characterized in that: This includes error measurement steps and error compensation steps; The error measurement uses an auxiliary ADC to measure the weight of each DAC cell and stores it in a weight register; The error compensation is achieved through encoding remapping in the pure digital domain. The original input codeword is stored in a buffer register, and multiple digital domain comparisons are performed using a successive approximation loop controlled by a finite state machine. This makes the inner product of the mapped codeword and the weight of the real DAC cell gradually approach the value of the buffer register, ultimately ensuring that the deviation between the analog domain output value and the ideal value is less than the weight of the smallest DAC cell.

2. The digital-to-analog converter calibration method based on digital domain code remapping according to claim 1, characterized in that: The system used in the method is a digital circuit.

3. The digital-to-analog converter calibration method based on digital domain code remapping according to claim 1, characterized in that: In the error compensation step, the digital domain performs an encoding conversion in advance. Based on the weights of each analog DAC cell pre-determined at the factory or during power-on, an encoding representation that will not introduce errors is found. Then, the DAC cell array in the analog domain is controlled. There is a fixed or random mapping relationship between the input original digital encoding codeword and the codeword finally applied to the DAC cell array.

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