A method for eliminating time delay error of optical fiber bidirectional signal transmission and time-frequency system

Abstract

The application discloses a kind of optical fiber bidirectional signal transmission time delay error elimination method and time-frequency system, the method includes three stages, specifically: initialization delay measurement stage;Pulse sending stage;Dynamic timing delay stage.The method realized by the application combines optical fiber bidirectional signal transmission time delay error elimination technology with time service technology, realizes the time service synchronization between each site, and the communication signal (instruction pulse) generated by DBF host is synchronously transmitted to each DBF extension, the communication signal of each DBF extension and DBF host keeps synchronization, so as to realize the time delay error elimination of communication signal, guarantee the signal synchronization between communication equipment, ensure the reliability of communication system;In addition, time service signal and communication signal are transmitted using the same optical fiber link, so as to also realize the saving of link resource.

Description

Technical Field

[0001] This invention belongs to the fields of time unification and signal communication technology, and specifically relates to a method for eliminating time delay errors in optical fiber bidirectional signal transmission and a time-frequency system. Background Technology

[0002] Communication devices synchronize their time through time unification domain devices (time-frequency devices) mounted on their respective sites. These devices often transmit time synchronization data via fiber optic cables. The current traditional fiber optic time synchronization method is PTP (Pulse-Converted Telecommunications) fiber optic time synchronization. Before PTP, fiber optic links must be established between the time unification domain devices. Through these links, the time unification domain devices transmit PTP messages to complete time synchronization between the communication devices. Therefore, time synchronization transmission is based on a separately established fiber optic link, separate from the signal communication links between the communication devices. While PTP time synchronization is being transmitted, the service communication signals between the communication devices cannot be transmitted synchronously, and the latency of the service communication signals between the communication devices cannot be corrected. Transmitting time synchronization signals through separately established fiber optic links between time unification domain devices, while transmitting service communication signals between communication devices through a separate communication link, results in significant waste of line resources, especially for long-distance communication devices. Furthermore, the inability to eliminate the latency of service communication signals between communication devices leads to a deterioration in synchronization performance. If the communication equipment consists of various radar communication terminals within a radar detection system, then the asynchrony between signals will cause the performance of the radar detection system to drop sharply, or even prevent it from working properly.

[0003] In summary, reducing the cost of establishing links between communication devices, achieving signal communication while completing time synchronization, and eliminating high-precision time delay errors between communication signals are the key research areas in the field of time unification. Summary of the Invention

[0004] The purpose of this invention is to overcome one or more shortcomings of the prior art and provide a method for eliminating time delay errors in optical fiber bidirectional signal transmission and a time-frequency system.

[0005] The objective of this invention is achieved through the following technical solution: First aspect The first aspect of the present invention provides a method for eliminating time delay errors in bidirectional optical fiber signal transmission. The method is applied to a communication system comprising a master station and multiple slave stations. The master station includes a time-frequency host and a DBF host. Each slave station includes a time-frequency extension and a DBF extension. The DBF host is connected to the time-frequency host, and the time-frequency extensions are connected to the DBF extensions. The time-frequency host and each time-frequency extension are connected via optical fiber communication. The method includes the following steps: Power on and initialize the communication system; The time and frequency host generates an initialization pulse based on the time synchronization information it acquires, and generates a first time synchronization code without service information based on the initialization pulse. The first time synchronization code is then sent to each slave station. The initialization pulse and the first time synchronization code are kept synchronized. The time-frequency host receives the first timing code returned by each slave station, and determines various delay values ​​to characterize the transmission delay of the link between the master station and each slave station based on its own first timing code and the first timing codes returned by each slave station. Each delay value corresponds one-to-one with each slave station. The time-frequency master determines the time delay adjustment value corresponding to each slave station based on the time delay value corresponding to each slave station, and determines the time delay adjustment value of the master station itself based on all time delay values. Then, the initialization pulse is delayed according to each time delay adjustment value. After the delay, the target pulse corresponding to the time delay adjustment value is obtained. The delay value between the target pulse and the initialization pulse is the time delay adjustment value. The time-frequency host generates each second timing code containing service information based on each target pulse, and performs SerDes framing with each second timing code and the instruction pulse generated by the DBF host. After the SerDes framing is completed, each communication string code corresponding to each second timing code is generated, and each communication string code is sent to each slave station and the communication string code corresponding to the master station is sent back to the master station. Each slave station and the master station receive their respective communication string codes at the same time. The time-frequency host and each time-frequency extension unit perform SerDes deframes on the communication serial code they receive. After SerDes deframes, they obtain command pulses and second timing codes. The time-frequency host transmits the command pulses obtained from the deframes to the DBF host and performs master station time correction according to the second timing code. The time-frequency extension units transmit the command pulses obtained from the deframes to the corresponding connected DBF extension units and perform slave station time correction according to the second timing code.

[0006] Preferably, the method further includes: Each time and frequency extension unit transmits the second timing code obtained after deframing the SerDes frame back to the time and frequency host; The time and frequency host determines the dynamic update value of each delay value based on the first time synchronization code it sends and the second time synchronization code returned by each slave station, and updates each delay value stored in the time and frequency host to the corresponding dynamic update value.

[0007] Preferably, the first timing code and the second timing code are both non-standard IRIG-B codes, wherein the non-standard IRIG-B code is an IRIG-B code with a different rate and symbol pulse width than the standard IRIG-B code; the instruction pulses generated by the DBF host include BW pulses, CPI pulses, FR pulses and sub-FR pulses.

[0008] Preferably, the time-frequency host generates an initialization pulse based on the timing information it acquires, specifically including the following sub-steps: The time and frequency host receives timing information generated by a satellite receiver connected to the main station; The time and frequency host tames the local crystal oscillator according to the timing information, and the crystal oscillator generates an initialization pulse after taming.

[0009] Preferably, the time-frequency host determines the delay adjustment value corresponding to each slave station based on the delay value corresponding to each slave station, and determines the delay adjustment value of the master station itself based on all delay values, specifically including the following sub-steps: The time-frequency host determines the maximum value among the delay values ​​corresponding to each slave station; The time-frequency host sets the delay adjustment value of the slave station corresponding to the maximum delay value to zero, and sets the delay adjustment value of each other slave station to the difference between the maximum delay value and the delay value corresponding to that slave station; The time-frequency host determines its own latency adjustment value as the sum of the maximum latency value and a first preset value based on all latency values. The first preset value is the hardware latency for the time-frequency extension of each slave station to perform SerDes frame decomposition, and the hardware latency is the same for each slave station.

[0010] The beneficial effects of the first aspect of the present invention are as follows: (1) In the first stage: after the system is powered on and initialized, the time and frequency host sends a first timing code (a code pattern with empty business information, not including the year, day, hour, minute, second, etc. required for timing transmission) to each time and frequency extension. Each time and frequency extension sends the first timing code back to the time and frequency host. Based on the round-trip first timing code, the time and frequency host completes the transmission link delay measurement between the time and frequency host and each time and frequency extension. In the second stage: the time-frequency host determines the delay adjustment value based on the delay values ​​of each transmission link, then delays the second timing code required to transmit the timing information to each slave station accordingly, and performs SerDes framing with each communication signal (command pulse) generated by the DBF host. The communication serial codes obtained after SerDes framing are sent one-to-one to each slave station and back to the master station, so that the communication serial codes received by the time-frequency host and each time-frequency extension are synchronized. Both the time-frequency host and the time-frequency extension perform SerDes deframing operation on the communication serial codes they receive to obtain the second timing code and each communication signal generated by the DBF host, and then pass through each communication signal generated by the DBF host to each DBF extension and the DBF host. Thus, the method implemented in the first aspect of the present invention combines optical fiber bidirectional signal transmission delay error elimination technology with time synchronization technology, realizing simultaneous time synchronization between various stations and synchronous transmission of communication signals (command pulses) generated by the DBF host to each DBF extension. The communication signals of each DBF extension and the DBF host remain synchronized, thereby eliminating the delay error of the communication signal, ensuring the synchronization of signals between communication devices, and ensuring the reliability of the communication system. In addition, both the time synchronization signal and the communication signal are transmitted using the same optical fiber link, thereby saving link resources.

[0011] (2) Each time and frequency sub-unit transmits the second timing code obtained after the SerDes frame is deframed back to the time and frequency host. The time and frequency host dynamically updates each locked delay value in real time, which further improves the accuracy of signal transmission delay error elimination.

[0012] Second aspect A second aspect of the present invention provides a time-frequency system, including a time-frequency host and multiple time-frequency sub-units. The time-frequency host and each time-frequency sub-unit have the same internal structure. The time-frequency host is located in a master station, and each time-frequency sub-unit is located in a corresponding slave station. The time-frequency host is used to connect to a DBF host in the master station and a reference clock source connected to the master station. Each time-frequency sub-unit is used to connect to a DBF sub-unit in its respective slave station. The time-frequency host and each time-frequency sub-unit are connected via optical fiber communication. The time-frequency host includes an FPGA module, a TDC time difference measurement module, and a main control module. The main control module is connected to the FPGA module and is also used to connect to the reference clock source. The FPGA module is used to connect to the DBF host and is also used to connect to each time-frequency sub-unit via optical fiber. The FPGA module is also connected to the TDC time difference measurement module. The main control module is used to obtain timing information from the reference clock source, generate an initialization pulse based on the obtained timing information, and send the initialization pulse to the FPGA module; The FPGA module is used to generate a first timing code without service information based on the initialization pulse, and send the first timing code to each time and frequency extension via optical fiber. The initialization pulse and the first timing code are kept synchronized. The FPGA module is also used to receive the first timing code returned by each time-frequency extension unit, and send the first timing code issued by the FPGA module itself and the first timing code returned by each time-frequency extension unit to the TDC time difference measurement module. The TDC time difference measurement module is used to measure the time difference between the first time code issued by the FPGA module itself and the first time code returned by each time-frequency extension, and sends each time difference to the main control module via the FPGA module. The main control module is used to determine each delay value according to each time difference. Each delay value is used to characterize the link transmission delay between the master station and each slave station in a one-to-one correspondence. Each delay value corresponds to each slave station. Then, based on the delay value corresponding to each slave station, the delay adjustment value corresponding to each slave station is determined. Based on all delay values, the delay adjustment value of the master station itself is determined, and each delay adjustment value is sent to the FPGA module. The FPGA module is used to delay the initialization pulse according to each delay adjustment value, and obtain the target pulse corresponding to the delay adjustment value after delay. The delay value between the target pulse and the initialization pulse is the delay adjustment value. The FPGA module is also used to generate each second timing code containing service information based on each target pulse, and then to perform SerDes framing with each second timing code using the instruction pulse generated by the DBF host. After the SerDes framing is completed, each communication string code corresponding to each second timing code is generated, and each communication string code is sent to each slave station in a one-to-one correspondence, and the communication string code corresponding to the master station is sent back to the master station. Each slave station and the master station receive their respective communication string codes at the same time. The FPGA module is also used to perform SerDes deframe on the communication serial code it receives. After SerDes deframe, the instruction pulse and the second timing code are obtained. The time and frequency host transmits the instruction pulse obtained from the deframe to the DBF host, and performs master station time correction according to the second timing code.

[0013] Preferably, the time and frequency host further includes a DPLL phase modulation module and an optical module; the DPLL phase modulation module is connected to the FPGA module and the main control module respectively, the optical module is connected to the FPGA module, and the optical module is also used to connect to the optical transceiver in the main station, and the optical transceiver in the main station is connected to each time and frequency sub-unit via optical fiber; The optical module is used to perform electro-optical conversion on the first timing code and each communication serial code generated by the FPGA module, and send the electro-optically converted first timing code and each communication serial code to the optical terminal in the main station. The main control module is also used to generate a first working clock based on the acquired timing information, and send the first working clock to the FPGA module and the DPLL phase modulation module; The main control module is also used to decompose each delay adjustment value into a first value and a second value, and send the first value to the FPGA module and the second value to the DPLL phase modulation module. The first value is the product of the quotient of the delay adjustment value divided by the first working clock cycle and the first working clock cycle, and the second value is the remainder of the delay adjustment value divided by the first working clock cycle. The DPLL phase modulation module is used to phase-shift the first working clock according to each second value, generating local delay clocks corresponding to each second value, and sending each local delay clock to the FPGA module. The delay of each local delay clock compared to the first working clock is the second value corresponding to that local delay clock. The FPGA module is also used to delay the initialization pulse according to each first value by register hopping, generating target pulses corresponding to each first value. The delay value between the target pulse and the initialization pulse is the delay adjustment value corresponding to the first value of the target pulse. The number of register hoppings is the quotient of the first value divided by the period of the first working clock. The clock of the register hopping is the corresponding local delay clock, which is the local delay clock corresponding to the second value corresponding to the delay adjustment value of the first value.

[0014] Preferably, the FPGA module in the time-frequency extension is used to connect with the DBF extension in the slave station where the time-frequency extension is located; the FPGA module in each time-frequency extension performs SerDes deframe on the communication serial code received by the time-frequency extension itself, and obtains the command pulse and the second timing code after SerDes deframe, and transmits the command pulse obtained by deframe to the corresponding connected DBF extension, and performs slave station time correction according to the second timing code; The FPGA modules in each time and frequency sub-unit also transmit the second timing code obtained after SerDes frame de-framing back to the FPGA module in the time and frequency host. The FPGA module in the time and frequency host is also used to transmit the second timing code returned by each slave station to the TDC time difference measurement module; The TDC time difference measurement module in the time and frequency host is also used to measure the new time difference between the first time code issued by the FPGA module in the time and frequency host and the second time code returned by each time and frequency extension, and send each new time difference to the main control module in the time and frequency host via the FPGA module; The main control module in the time and frequency host is also used to determine the dynamic update value of each delay value according to each new time difference, and update each stored delay value to the corresponding dynamic update value.

[0015] Preferably, the reference clock source is a satellite receiver connected to the master station; the frequency of the first operating clock is 200MHz; and the DPLL phase modulation module uses a DPLL chip of model AD9545.

[0016] Preferably, the master control module determines the latency adjustment value for each slave station based on the latency value corresponding to each slave station, and determines the latency adjustment value for the master station itself based on all latency values. The specific process is as follows: The master control module determines the maximum value among the delay values ​​corresponding to each slave station; The main control module sets the delay adjustment value of the slave station corresponding to the maximum delay value to zero, and sets the delay adjustment value of each other slave station to the difference between the maximum delay value and the delay value corresponding to that slave station. The main control module determines the main station's own latency adjustment value based on all latency values ​​as the sum of the maximum latency value and the first preset value. The first preset value is the hardware latency for the FPGA module of each slave station to perform SerDes frame de-framing, and the hardware latency is the same for each slave station.

[0017] The second aspect of the present invention brings the same beneficial effects as the first aspect, which will not be repeated here. Meanwhile, through the configuration of the DPLL phase modulation module, the first stage of delay adjustment is implemented by the DPLL phase modulation module, and the second stage of delay adjustment is implemented by the FPGA module. The value of the first stage delay adjustment is lower than the first operating clock cycle, and the value of the second stage delay adjustment is an integer multiple of the first operating clock cycle. By selecting the first operating clock frequency and a DPLL chip that matches the required phase shift accuracy, high-precision delay compensation for each station is achieved. For example, in this embodiment of the present invention, the selected first operating clock frequency is 200MHz, and the DPLL chip is AD9545. The phase shift accuracy of AD9545 is at the ps level, thereby achieving nanosecond-level delay compensation for each station, and thus achieving nanosecond-level synchronization of the delayed instruction pulses when they arrive at each station. Attached Figure Description

[0018] Figure 1 A flowchart illustrating a method for eliminating delay errors in bidirectional optical fiber signal transmission; Figure 2 This is a network diagram of a communication system; Figure 3 This is a network diagram of a time-frequency system; Figure 4 This is a block diagram of a time-frequency main unit / time-frequency extension unit; Figure 5 This is a schematic diagram showing the time delay of the first timing code reaching each time-frequency extension unit during the first-stage time delay measurement. Figure 6 This is a schematic diagram showing how the communication serial codes after the second-stage delay compensation arrive at the DBF host and each DBF extension. Figure 7 A schematic diagram of the code pattern of the second timing code and command pulse when framing SerDes; Figure 8 This is the first part of a timing diagram illustrating a method for eliminating delay errors in bidirectional optical fiber signal transmission. Figure 9This is the second part of a timing diagram illustrating a method for eliminating delay errors in bidirectional optical fiber signal transmission. Detailed Implementation

[0019] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The following is an explanation of the technical terms used in the embodiments below: DBF: Radar host computer; BW pulse: Radar signal wave position indication pulse; FR pulse: Frame-length pulse in radar signals; Sub-FR pulse: Subframe long pulse; CPI pulse: A pulse of a specific length; FR_LOCK pulse: Frame lock indicator pulse; SerDes: Short for SERializer / DESerializer; IRIG-B code: inter-range instrumentation group-B, is an electrical term published in 2020 and has now become an internationally recognized standard code for time codes.

[0021] Example 1 See Figures 1-9 This embodiment provides a method for eliminating delay errors in bidirectional fiber optic signal transmission, applied to a communication system. The communication system includes a master station and multiple slave stations. The master station includes a time-frequency host and a DBF host. Each slave station includes a time-frequency extension and a DBF extension. The DBF host is connected to the time-frequency host, and the time-frequency extension is connected to the DBF extension. The time-frequency host and each time-frequency extension are connected via fiber optic communication. The master station and each slave station transmit timing information and communication signals via fiber optics. The communication signals are command pulses generated by the DBF host. The command pulses include BW pulse, CPI pulse, FR pulse, sub-FR pulse, FR data pulse, FR CLK pulse, and FR_LOCK pulse. The master station is connected to a satellite receiver and a satellite antenna, which receive timing information transmitted by GNSS satellites.

[0022] like Figure 1 As shown, a method for eliminating time delay errors in bidirectional optical fiber signal transmission includes the following two steps: S100. First Phase: Initialize delay measurement.

[0023] S200. Second Phase: Pulse transmission.

[0024] Specifically, the first phase includes the following sub-steps: S101. Power on and initialize the communication system.

[0025] S102. The time-frequency host generates an initialization pulse based on the time synchronization information it acquires, and generates a first time synchronization code without service information based on the initialization pulse, and sends the first time synchronization code to each slave station. The first time synchronization code generated based on the initialization pulse is synchronized with the initialization pulse.

[0026] Specifically, the time-frequency host generates an initialization pulse based on the timing information it acquires. This process adopts the timing process based on crystal oscillator discipline in a common embodiment, including the following sub-steps: the time-frequency host receives timing information generated by a satellite receiver connected to the master station; the time-frequency host disciplines the local crystal oscillator according to the timing information, and generates an initialization pulse after the crystal oscillator is disciplined. The type of timing information generated by the satellite receiver is preferably a 1PPS+TOD signal. The frequency of the initialization pulse is 10MHz. It is known that the command pulse generated by the DBF host is an indeterminate periodic signal, and the minimum interval between two command pulses is 200us. Therefore, in this embodiment, the first timing code adopts the non-standard IRIG-B code from the non-standard time codes. The non-standard IRIG-B code is an IRIG-B code with a different rate and symbol pulse width than the standard IRIG-B code. Specifically, the non-standard IRIG-B code has a rate of 10MHz, a pulse width of 0.1µs per symbol, and a total of 100 symbols, occupying 10µs. This ensures that the first stage of delay measurement is completed within the minimum interval between two command pulses. Alternatively, other rates of non-standard IRIG-B codes can be used, as long as the first stage of delay measurement can be completed within the minimum interval between two command pulses. Because delay measurement is required after the communication system is powered on and initialized, the first timing code generated at this time does not transmit timing information; it only performs delay measurement based on bidirectional fiber optic transmission technology. Therefore, "not containing service information" means it does not include the day, hour, minute, and second information required for timing transmission.

[0027] S103. The time-frequency host receives the first timing code returned by each slave station, and determines each delay value to characterize the magnitude of the link transmission delay (fiber optic link delay) between the master station and each slave station based on the first timing code it sends and the first timing code returned by each slave station. Each delay value corresponds one-to-one with each slave station.

[0028] Specifically, the second phase includes the following sub-steps: S201. The time-frequency host determines the time delay adjustment value corresponding to each slave station based on the time delay value corresponding to each slave station, and determines the time delay adjustment value of the master station itself based on all time delay values. The initialization pulse is delayed according to each time delay adjustment value, and the target pulse corresponding to the time delay adjustment value is obtained after the delay. The delay value between the target pulse and the initialization pulse is the time delay adjustment value.

[0029] S202. The time-frequency host generates a second timing code containing service information based on each target pulse, with each target pulse synchronized with each second timing code. The host then performs SerDes framing with each second timing code, combining the command pulse generated by the DBF host with each second timing code. After SerDes framing, a communication serial code corresponding to each second timing code is generated. This communication serial code is sent to each slave station, and the communication serial code corresponding to the master station is sent back to the master station. Each slave station and the master station receive their respective communication serial codes simultaneously. A schematic diagram illustrating the synchronous arrival of each communication serial code at the DBF host and each DBF extension station is provided. Figure 6 As shown. For example: Based on the delay value corresponding to the first slave station (the fiber optic link delay between the first slave station and the master station), the delay adjustment value corresponding to the first slave station is determined. The initialization pulse is delayed to obtain the target pulse, and the delay size is the delay adjustment value. Based on the target pulse corresponding to the delay adjustment value, a second timing code containing service information is generated. The command pulse generated by the DBF host and the second timing code are then used for SerDes framing. After the SerDes framing is completed, a communication string code corresponding to the second timing code is generated, and this communication string code is sent to the first slave station accordingly. In this step, timing information and command pulses are transmitted. Therefore, the second timing code contains service information, which means it contains the day, hour, minute, second, and other information required for timing transmission. For the SerDes framing code of the 10MHz non-standard IRIG-B code and the code of each command pulse, please refer to [link to SerDes framing code]. Figure 7 .

[0030] S203. The time-frequency host and each time-frequency extension unit respectively perform SerDes deframing on the communication serial code they receive. After SerDes deframing, a command pulse and a second timing code are obtained. The time-frequency host transmits the command pulse obtained from the deframing to the DBF host and performs master station time correction according to the second timing code. The time-frequency extension unit transmits the command pulse obtained from the deframing to the corresponding connected DBF extension unit and performs slave station time correction according to the second timing code. SerDes framing and SerDes deframing are inverse processes. Preferably, SerDes framing and SerDes deframing are implemented based on the SerDes serial deserialization unit within the time-frequency host. Both the SerDes framing and SerDes deframing processes are based on the process in the general embodiment.

[0031] Through the first and second stages, the master station can simultaneously provide time synchronization to each slave station and transmit command pulses, ensuring that each command pulse arrives at the DBF extension and the DBF master station at the same time, thus eliminating the asynchrony between the command pulses arriving at each DBF extension and the DBF master station.

[0032] As a preferred embodiment, in S201, the time-frequency master determines the delay adjustment value corresponding to each slave station based on the delay value corresponding to each slave station, and determines the delay adjustment value of the master station itself based on all delay values, specifically including the following sub-steps: The time-frequency host determines the maximum value among the delay values ​​corresponding to each slave station.

[0033] The time-frequency host sets the delay adjustment value of the slave station corresponding to the maximum delay value to zero, and sets the delay adjustment value of each other slave station to the difference between the maximum delay value and the delay value corresponding to that slave station.

[0034] The time-frequency host determines its own latency adjustment value as the sum of the maximum latency value and the first preset value based on all latency values. The first preset value is the hardware latency for the time-frequency extension of each slave station to perform SerDes frame decomposition. The hardware latency for SerDes frame decomposition is the same for each slave station. At the same time, the hardware latency for the time-frequency host of the master station to perform SerDes frame decomposition is also the same for each slave station.

[0035] The following explanation uses a scenario with three slave stations, each with a different distance from the master station, to illustrate the process of determining the delay adjustment value for each slave station based on its corresponding delay value. When the number of slave stations changes, the conversion from delay value to delay adjustment value can be performed by analogy to the process described below.

[0036] Specifically: such as Figure 5As shown in the figure, the three slave stations are the first slave station, the second slave station, and the third slave station respectively. The fiber optic link delay value between the first slave station and the master station obtained through the first-stage measurement is t1, the fiber optic link delay value between the second slave station and the master station is t2, and the fiber optic link delay value between the third slave station and the master station is t3, and t1 < t2 < t3. First, the delay adjustment value of the third slave station is determined to be zero, the delay adjustment value of the second slave station is determined to be t3 - t2, and the delay adjustment value of the first slave station is determined to be t3 - t1. Finally, according to all the delay values, the delay adjustment value of the master station itself is determined to be t3 + a, where a is a first preset value and represents the hardware delay of the SerDes deframing of the time-frequency extender of each slave station. The hardware delay of the SerDes deframing corresponding to each slave station is the same, and at the same time, the hardware delay of the SerDes deframing of the time-frequency host of the master station is also the same as that of each slave station. In this embodiment, based on the specific hardware structure of the time-frequency extender and the time-frequency extender, a is taken as 6 ns. Finally, the delay of the command pulse received by the DBF extender of each slave station and the DBF host of the master station compared to the initialization pulse is t3 + 6 ns, achieving that each command pulse arrives at each slave station and the master station simultaneously, and completing the delay compensation. In addition, in this embodiment, because the transmission link between the DBF host and the time-frequency host is very short, and the transmission link between the DBF extender and the time-frequency extender is very short, it is defaulted that there is no delay. If the delay value of this transmission link needs to be accurately determined, the cable delay measurement method in the general embodiment can be used to test the actual cable of this transmission link to determine the specific delay value.

[0037] Further, after S200, the following steps are further included: S300. The third stage: Dynamically measure the delay.

[0038] Specifically, the third stage includes the following sub-steps: S301. Each time-frequency extender respectively returns the second timing code obtained after SerDes deframing to the time-frequency host.

[0039] S302. The time-frequency host determines the dynamic update value of each delay value according to the first timing code sent by itself and the second timing codes returned by each slave station, and updates each delay value stored in the time-frequency host one by one to the dynamic update value of each delay value.

[0040] Embodiment 2 This embodiment provides a time-frequency system, and this time-frequency system performs time-frequency transmission and communication signal transmission based on a fiber optic bidirectional signal transmission delay error elimination method provided in Embodiment 1.

[0041] Specifically, as Figure 3As shown, the time-frequency system is applied within a communication system for time synchronization and communication signal transmission between the master station and various slave stations. The time-frequency system includes a time-frequency master unit and multiple time-frequency extension units. The master unit and each extension unit have identical internal structures. The master unit is located within the master station of the communication system, and each extension unit is correspondingly located within its respective slave station. The master unit connects to the DBF master unit within the master station and to the reference clock source connected to the master station. It also connects to the optical array transceiver within the master station. The optical array transceiver within the master station connects to the in-cabin optical transceiver within the master station. Each extension unit connects to the DBF extension unit within its respective slave station, and also connects to the optical array transceiver within its corresponding slave station. The optical array transceiver within the slave station connects to the in-cabin optical transceiver within its slave station. The in-cabin optical transceiver within the master station is connected to the in-cabin optical transceiver within the slave station via fiber optic communication.

[0042] like Figure 4 As shown, the time and frequency host includes an FPGA module, a TDC time difference measurement module, a main control module, a crystal oscillator, and a PLL module. The main control module is connected to the FPGA module, the crystal oscillator, and the PLL module respectively. The main control module is also used to connect to a reference clock source. The FPGA module is used to connect to the DBF host. The FPGA module is also used to connect to each time and frequency sub-unit via the array optical transceiver in the main station, the cabin optical transceiver in the main station, and optical fiber. The FPGA module is also connected to the TDC time difference measurement module.

[0043] The main control module acquires timing information from a reference clock source, generates an initialization pulse based on the acquired timing information, and sends the initialization pulse to the FPGA module. In this embodiment, the reference clock source is preferably a satellite receiver connected to the main station. The timing information type sent by the satellite receiver to the main control module is preferably a 1PPS+TOD signal, and the initialization pulse frequency is preferably 10MHz. After receiving the timing information from the satellite receiver, the main control module performs local crystal oscillator training based on the timing information from the satellite receiver. During local crystal oscillator training, the PLL module measures the time difference between the local reference clock output by the crystal oscillator and the 1PPS second pulse generated by the satellite receiver. The main control module generates a voltage control signal based on the time difference measurement result, and the crystal oscillator adjusts its output frequency according to the voltage control signal, thereby realizing the training of the crystal oscillator and the time synchronization of the local reference clock. As can be seen from the above description, this crystal oscillator training process is the training process in a typical embodiment.

[0044] The FPGA module generates a first timing code (without service information) based on the initialization pulse and transmits it via optical fiber to each time and frequency extension unit. The first timing code generated based on the initialization pulse is synchronized with the initialization pulse. The first timing code is preferably a non-standard timing code, preferably a non-standard IRIG-B code. A non-standard IRIG-B code is an IRIG-B code with a different rate and symbol pulse width than the standard IRIG-B code. In this embodiment, the non-standard IRIG-B code has a rate of 10MHz, a pulse width of 0.1µs per symbol, and a total of 100 symbols. "Without service information" means it does not contain the day, hour, minute, second, or other information required for timing transmission.

[0045] The FPGA module is also used to receive the first timing code returned by each time-frequency extension unit, and send the first timing code issued by the FPGA module itself and the first timing code returned by each time-frequency extension unit to the TDC time difference measurement module.

[0046] The TDC time difference measurement module is used to measure the time difference between the first time code issued by the FPGA module itself and the first time code returned by each time-frequency extension, and sends each time difference to the main control module via the FPGA module.

[0047] The main control module determines various delay values ​​based on different time differences. Each delay value represents the transmission delay of the link between the master station and each slave station, with each delay value corresponding to a specific slave station. The main control module then determines the delay adjustment value for each slave station based on its corresponding delay value, and also determines the master station's own delay adjustment value based on all delay values. These delay adjustment values ​​are then sent to the FPGA module. Furthermore, the main control module also stores these delay values.

[0048] The FPGA module is used to delay the initialization pulse according to each delay adjustment value, and the target pulse corresponding to the delay adjustment value is obtained after the delay. The delay value between the target pulse and the initialization pulse is the delay adjustment value.

[0049] The FPGA module is also used to generate each second timing code containing service information based on each target pulse. Then, the instruction pulse generated by the DBF host is used to perform SerDes framing with each second timing code. After the SerDes framing is completed, each communication string code corresponding to each second timing code is generated. Each communication string code is sent to each slave station and the communication string code corresponding to the master station is sent back to the master station. Each slave station and the master station receive their respective communication string codes at the same time.

[0050] The FPGA module is also used to perform SerDes deframes on the communication serial codes it receives. After SerDes deframes, a command pulse and a second timing code are obtained. The time and frequency host transmits the command pulse obtained from the deframes to the DBF host, and performs master station time correction based on the second timing code. The SerDes framing and deframes performed by the FPGA module are inverse processes. Preferably, both SerDes framing and deframes are implemented using the SerDes serial deserialization unit within the FPGA module. Both the SerDes framing and deframes processes are based on the process described in the standard embodiment.

[0051] As a preferred method, the master control module determines the latency adjustment value for each slave station based on its corresponding latency value, and determines the latency adjustment value for the master station itself based on all latency values. The specific process is as follows: The master control module determines the maximum value among the delay values ​​corresponding to each slave station.

[0052] The master control module sets the delay adjustment value of the slave station corresponding to the maximum delay value to zero, and sets the delay adjustment value of each other slave station to the difference between the maximum delay value and the delay value corresponding to that slave station.

[0053] The master control module determines the master station's own latency adjustment value as the sum of the maximum latency value and the first preset value based on all latency values. The first preset value is the hardware latency for SerDes frame de-framing of the FPGA module of each slave station. The hardware latency for SerDes frame de-framing is the same for each slave station. At the same time, the hardware latency for SerDes frame de-framing of the FPGA module of the master station is also the same as that of each slave station.

[0054] The following takes the case where the number of slave stations is three and the distances between the three slave stations and the master station are different, and illustrates the process of determining the delay adjustment value corresponding to each slave station based on the delay value corresponding to the slave station. When the number of slave stations changes, the conversion from the delay value to the delay adjustment value can be analogized based on the following process and the like. Specifically: Each slave station is the first slave station, the second slave station, and the third slave station respectively; the main control module sorts each delay value in ascending order, and the sorted delay values are the delay value t1, the delay value t2, and the delay value t3 in sequence, where the delay value t1 is the delay value corresponding to the first slave station, the delay value t2 is the delay value corresponding to the second slave station, the delay value t3 is the delay value corresponding to the third slave station, and t1 < t2 < t3; the delay adjustment value of the third slave station is determined to be zero, the delay adjustment value of the second slave station is determined to be t3 - t2, and the delay adjustment value of the first slave station is determined to be t3 - t1; the delay adjustment value of the master station itself is determined to be t3 + a according to all the delay values, where a is a first preset value and represents the hardware delay of the FPGA module of each slave station for SerDes deframing, and the SerDes deframing hardware delays in each slave station and the master station are the same. In this embodiment, the hardware delay a of the FPGA module for SerDes deframing takes a value of 6 ns. Based on the delay compensation of the above delay adjustment value, finally, the delay of the command pulse received by the DBF extension of each slave station and the DBF host of the master station compared to the initialization pulse is t3 + 6 ns.

[0055] [[ID=?]]As a preference, the time-frequency host further includes a DPLL phase modulation module and an optical module. The DPLL (Digital Phase Locked Loop) phase modulation module is respectively connected to the FPGA module and the main control module, the optical module is connected to the FPGA module, and the optical module is further used to connect to the array optical terminal in the master station. The DPLL phase modulation module is preferably a DPLL chip of model AD9545.

[0056] The optical module is used for electro-optical conversion of the first timing code generated by the FPGA module and each communication serial code, and sending the electro-optical converted first timing code and each communication serial code to the array optical terminal in the master station.

[0057] The main control module is further used for generating a first working clock based on the acquired timing information, and sending the first working clock to the FPGA module and the DPLL phase modulation module. In this embodiment, the frequency of the first working clock is preferably 200 MHz.

[0058] It should be noted that there is a question mark in the translation of item [3] as the original text seems to be numbered as [3] but the content starts with "作为一种优选" which might be a misnumbering in the original. I translated it as best as possible based on the context.The main control module is also used to decompose each delay adjustment value into a first value and a second value, and send the first value to the FPGA module and the second value to the DPLL phase modulation module. The first value is the product of the quotient of the delay adjustment value divided by the first working clock period and the first working clock period, and the second value is the remainder of the delay adjustment value divided by the first working clock period. For example, if the delay adjustment value is 5005ps, then the first value = 5ns and the second value = 5ps.

[0059] The DPLL phase modulation module is used to phase shift the first working clock according to each second value. After phase shifting, each local delay clock is generated that corresponds one-to-one with each second value. Each local delay clock is then sent to the FPGA module. The delay of each local delay clock compared to the first working clock is the second value corresponding to that local delay clock.

[0060] The FPGA module is also used to delay the initialization pulse using register ticking based on each first value. After delay, a target pulse corresponding to each first value is generated. The delay between the target pulse and the initialization pulse is the delay adjustment value corresponding to the first value of the target pulse. The number of register ticks is the quotient of the first value divided by the first working clock cycle. The clock for register ticking is the corresponding local delay clock, which is the local delay clock corresponding to the second value corresponding to the delay adjustment value of the first value. For example, when the delay adjustment value is 5005ps, the first value is 5ns, the second value is 5ps, the number of register ticks is 1, and the clock for register ticking is a local delay clock delayed by 5ps compared to the first working clock. One register tick means delaying the initialization pulse by one first working clock cycle, and the final target pulse is delayed by 5005ps compared to the initialization pulse. Accordingly, if the first value is equal to 10ns, then the number of register ticks is 2, which means that the initialization pulse is delayed by 2 first working clock cycles, which is 10ns; if the first value is equal to 15ns, then the number of register ticks is 3, which means that the initialization pulse is delayed by 3 first working clock cycles, which is 15ns; and so on.

[0061] Because the internal structure of the time-frequency extension unit and the time-frequency master unit is the same, it is known to those skilled in the art that the FPGA module in the time-frequency extension unit is used to connect with the DBF extension unit in the slave station where the time-frequency extension unit is located. The FPGA module in each time-frequency extension unit also performs SerDes deframe on the communication serial code received by the time-frequency extension unit itself. After the SerDes deframe, the command pulse and the second timing code are obtained. The command pulse obtained by the deframe is then transmitted to the corresponding connected DBF extension unit, and the slave station time is corrected according to the second timing code.

[0062] As a preferred embodiment, the FPGA module within each time-frequency substation also transmits the second timing code obtained after SerDes frame de-framing back to the FPGA module within the time-frequency host. The FPGA module within the time-frequency host further transmits the second timing codes transmitted from each slave station to the TDC time difference measurement module. The TDC time difference measurement module within the time-frequency host measures the new time difference between the first timing code emitted by the FPGA module within the time-frequency host and the second timing code transmitted back by each time-frequency substation, and sends each new time difference to the main control module within the time-frequency host via the FPGA module. The main control module within the time-frequency host determines the dynamic update value of each delay value based on each new time difference, and updates the stored delay values ​​one-to-one with the dynamic update values.

[0063] As an alternative, the FPGA module also receives the accompanying clock (accompanying CLK) generated by the DPLL phase modulation module. When framing the second timing code and the instruction pulse generated by the DBF host using SerDes, the accompanying clock is also framed using SerDes. The frequency of the accompanying clock is 50MHz. The accompanying clock enters the optical module, the array optical transceiver, and the cabin optical transceiver to perform calibration and optimization of the internal sampling delay of the optical module, the array optical transceiver, and the cabin optical transceiver.

[0064] Figure 8 and Figure 9 This diagram illustrates a timing diagram for eliminating delay errors in bidirectional fiber optic signal transmission using a time-frequency system implemented in this embodiment.

[0065] Combination Figure 8 It can be seen that after the first stage of time delay measurement, the time delay values ​​t1 corresponding to the first slave station, t2 corresponding to the second slave station, and t3 corresponding to the third slave station can all be calculated using the following formula: The delay value is calculated as [(T6-T3)-(T5-T4)] / 2 (Formula 1), where T5-T4 = T3-T2, representing the hardware delay caused by the FPGA module's transmission processing, which is approximately 5~6ns. In this embodiment, it is calibrated to 6ns. T6-T3 is the time difference between the first timing code sent by the FPGA module itself and the first timing code returned by each slave station, calculated by the TDC time difference measurement module.

[0066] In the diagram, ofm1 represents delay value t1, ofm2 represents delay value t2, and ofm3 represents delay value t3. ofm1 + non-standard time code represents the second timing code sent to the first slave station, and is included in the communication serial code sent to the first slave station. ofm2 + non-standard time code represents the second timing code sent to the second slave station, and is included in the communication serial code sent to the second slave station. ofm3 + non-standard time code represents the second timing code sent to the third slave station, and is included in the communication serial code sent to the third slave station.

[0067] After testing the synchronization of the command pulse, the time-frequency system implemented in this embodiment achieved a synchronization accuracy of 3ns (1 segma) for the command pulse, and the peak-to-peak value was within 10ns. It can be seen that the time delay error at the ns level was eliminated, and the timing accuracy reached a synchronization accuracy within 10ns, thus achieving a timing accuracy at the ns level.

[0068] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for eliminating time delay error in bidirectional optical fiber signal transmission, characterized in that, The method is applied to a communication system, which includes a master station and multiple slave stations. The master station includes a time-frequency host and a DBF host. Each slave station includes a time-frequency extension and a DBF extension. The DBF host is connected to the time-frequency host, and the time-frequency extensions are connected to the DBF extensions. The time-frequency host and each time-frequency extension are connected via optical fiber communication. The method includes the following steps: Power on and initialize the communication system; The time and frequency host generates an initialization pulse based on the time synchronization information it acquires, and generates a first time synchronization code without service information based on the initialization pulse. The first time synchronization code is then sent to each slave station. The initialization pulse and the first time synchronization code are kept synchronized. The time-frequency host receives the first timing code returned by each slave station, and determines various delay values ​​to characterize the transmission delay of the link between the master station and each slave station based on its own first timing code and the first timing codes returned by each slave station. Each delay value corresponds one-to-one with each slave station. The time-frequency master determines the delay adjustment value corresponding to each slave station based on the delay value corresponding to each slave station, and determines the delay adjustment value of the master station itself based on all delay values. It also delays the initialization pulse according to each delay adjustment value, and obtains the target pulse corresponding to the delay adjustment value after delay. The delay value between the target pulse and the initialization pulse is the delay adjustment value. The time-frequency host generates each second timing code containing service information based on each target pulse, and performs SerDes framing with each second timing code and the instruction pulse generated by the DBF host. After the SerDes framing is completed, each communication string code corresponding to each second timing code is generated, and each communication string code is sent to each slave station and the communication string code corresponding to the master station is sent back to the master station. Each slave station and the master station receive their respective communication string codes at the same time. The time and frequency host and each time and frequency extension unit respectively perform SerDes deframing on the communication serial code they receive. After SerDes deframing, the command pulse and the second timing code are obtained. The time and frequency host transmits the command pulse obtained from the deframing to the DBF host and performs master station time correction according to the second timing code. The time and frequency extension unit transmits the command pulse obtained from the deframing to the corresponding connected DBF extension unit and performs slave station time correction according to the second timing code. The method further includes: each time-frequency substation transmits the second timing code obtained after deframing SerDes back to the time-frequency host; the time-frequency host determines the dynamic update value of each delay value based on the first timing code it sends and the second timing code transmitted back by each slave station, and updates each delay value stored in the time-frequency host to the dynamic update value of each delay value.

2. The method for eliminating time delay error in bidirectional optical fiber signal transmission according to claim 1, characterized in that, The first and second timing codes are both non-standard IRIG-B codes, wherein the non-standard IRIG-B code is an IRIG-B code with a different rate and symbol pulse width than the standard IRIG-B code; the instruction pulses generated by the DBF host include BW pulses, CPI pulses, FR pulses and sub-FR pulses.

3. The method for eliminating time delay error in bidirectional optical fiber signal transmission according to claim 1, characterized in that, The time-frequency host generates an initialization pulse based on the timing information it acquires, specifically including the following sub-steps: The time and frequency host receives timing information generated by a satellite receiver connected to the main station; The time and frequency host tames the local crystal oscillator according to the timing information, and the crystal oscillator generates an initialization pulse after taming.

4. The method for eliminating time delay error in bidirectional optical fiber signal transmission according to claim 1, characterized in that, The time-frequency host determines the delay adjustment value for each slave station based on the delay value corresponding to each slave station, and determines the delay adjustment value for the master station itself based on all delay values. Specifically, it includes the following sub-steps: The time-frequency host determines the maximum value among the delay values ​​corresponding to each slave station; The time-frequency master determines the delay adjustment value of the slave station corresponding to the largest delay value as zero, and determines the delay adjustment value corresponding to each other slave station as the difference between the largest delay value and the delay value corresponding to that slave station; The time-frequency host determines its own latency adjustment value as the sum of the maximum latency value and a first preset value based on all latency values. The first preset value is the hardware latency for the time-frequency extension of each slave station to perform SerDes frame decomposition, and the hardware latency is the same for each slave station.

5. A time-frequency system, characterized in that, The system includes a time-frequency master unit and multiple time-frequency extension units. The time-frequency master unit and each time-frequency extension unit have identical internal structures. The time-frequency master unit is located within a master station, and each time-frequency extension unit is correspondingly located within a slave station. The time-frequency master unit connects to the DBF master unit within the master station and to a reference clock source connected to the master station. Each time-frequency extension unit connects to its corresponding DBF extension unit within its slave station. The time-frequency master unit and each time-frequency extension unit are connected via optical fiber communication. The time-frequency master unit includes an FPGA module, a TDC time difference measurement module, and a main control module. The main control module is connected to the FPGA module and is also connected to the reference clock source. The FPGA module is connected to the DBF master unit and is also connected to each time-frequency extension unit via optical fiber. The FPGA module is also connected to the TDC time difference measurement module. The main control module is used to obtain timing information from the reference clock source, generate an initialization pulse based on the obtained timing information, and send the initialization pulse to the FPGA module; The FPGA module is used to generate a first timing code without service information based on the initialization pulse, and send the first timing code to each time and frequency extension via optical fiber. The initialization pulse and the first timing code are kept synchronized. The FPGA module is also used to receive the first timing code returned by each time-frequency extension unit, and send the first timing code issued by the FPGA module itself and the first timing code returned by each time-frequency extension unit to the TDC time difference measurement module. The TDC time difference measurement module is used to measure the time difference between the first time code issued by the FPGA module itself and the first time code returned by each time-frequency extension, and sends each time difference to the main control module via the FPGA module. The main control module is used to determine each delay value according to each time difference. Each delay value is used to characterize the link transmission delay between the master station and each slave station in a one-to-one correspondence. Each delay value corresponds to each slave station. Then, based on the delay value corresponding to each slave station, the delay adjustment value corresponding to each slave station is determined. Based on all delay values, the delay adjustment value of the master station itself is determined, and each delay adjustment value is sent to the FPGA module. The FPGA module is used to delay the initialization pulse according to each delay adjustment value, and obtain the target pulse corresponding to the delay adjustment value after delay. The delay value between the target pulse and the initialization pulse is the delay adjustment value. The FPGA module is also used to generate each second timing code containing service information based on each target pulse, and then to perform SerDes framing with each second timing code using the instruction pulse generated by the DBF host. After the SerDes framing is completed, each communication string code corresponding to each second timing code is generated, and each communication string code is sent to each slave station in a one-to-one correspondence, and the communication string code corresponding to the master station is sent back to the master station. Each slave station and the master station receive their respective communication string codes at the same time. The FPGA module is also used to perform SerDes deframe on the communication serial code it receives. After SerDes deframe, the instruction pulse and the second timing code are obtained. The time and frequency host transmits the instruction pulse obtained from the deframe to the DBF host, and performs master station time correction according to the second timing code.

6. A time-frequency system according to claim 5, characterized in that, The time and frequency host also includes a DPLL phase modulation module and an optical module; the DPLL phase modulation module is connected to the FPGA module and the main control module respectively, the optical module is connected to the FPGA module, and the optical module is also used to connect to the optical transceiver in the main station. The optical transceiver in the main station is connected to each time and frequency sub-unit via optical fiber. The optical module is used to perform electro-optical conversion on the first timing code and each communication serial code generated by the FPGA module, and send the electro-optically converted first timing code and each communication serial code to the optical terminal in the main station. The main control module is also used to generate a first working clock based on the acquired timing information, and send the first working clock to the FPGA module and the DPLL phase modulation module; The main control module is also used to decompose each delay adjustment value into a first value and a second value, and send the first value to the FPGA module and the second value to the DPLL phase modulation module. The first value is the product of the quotient of the delay adjustment value divided by the first working clock cycle and the first working clock cycle, and the second value is the remainder of the delay adjustment value divided by the first working clock cycle. The DPLL phase modulation module is used to phase shift the first working clock according to each second value, generate local delay clocks that correspond one-to-one with each second value, and send each local delay clock to the FPGA module. The delay of each local delay clock compared to the first working clock is the second value corresponding to the local delay clock. The FPGA module is further configured to delay the initialization pulse by register hopping according to each first value, and generate a target pulse that corresponds one-to-one with each first value. The delay value between the target pulse and the initialization pulse is the time delay adjustment value corresponding to the first value of the target pulse. The number of register hoppings is the quotient of the first value divided by the first working clock period. The clock of the register hopping is the corresponding local delay clock, which is the local delay clock corresponding to the second value corresponding to the time delay adjustment value of the first value.

7. A time-frequency system according to claim 5, characterized in that, The FPGA module in the time-frequency extension is used to connect with the DBF extension in the slave station where the time-frequency extension is located; the FPGA module in each time-frequency extension performs SerDes deframe on the communication serial code received by the time-frequency extension itself. After SerDes deframe, the command pulse and the second timing code are obtained. The command pulse obtained by deframe is then transmitted to the corresponding connected DBF extension, and the slave station time is corrected according to the second timing code. The FPGA modules in each time and frequency sub-unit also transmit the second timing code obtained after SerDes frame de-framing back to the FPGA module in the time and frequency host. The FPGA module in the time and frequency host is also used to transmit the second timing code returned by each slave station to the TDC time difference measurement module; The TDC time difference measurement module in the time and frequency host is also used to measure the new time difference between the first time code issued by the FPGA module in the time and frequency host and the second time code returned by each time and frequency extension, and send each new time difference to the main control module in the time and frequency host via the FPGA module; The main control module in the time and frequency host is also used to determine the dynamic update value of each delay value according to each new time difference, and update each stored delay value to the corresponding dynamic update value.

8. A time-frequency system according to claim 6, characterized in that, The reference clock source is a satellite receiver connected to the main station; the frequency of the first operating clock is 200MHz; the DPLL phase modulation module uses a DPLL chip of model AD9545.

9. A time-frequency system according to claim 5, characterized in that, The master control module determines the latency adjustment value for each slave station based on its latency value, and determines the latency adjustment value for the master station itself based on all latency values. The specific process is as follows: The master control module determines the maximum value among the delay values ​​corresponding to each slave station; The main control module sets the delay adjustment value of the slave station corresponding to the largest delay value to zero, and sets the delay adjustment value of each other slave station to the difference between the largest delay value and the delay value corresponding to that slave station. The main control module determines the main station's own latency adjustment value as the sum of the maximum latency value and the first preset value based on all latency values. The first preset value is the hardware latency for the FPGA module of each slave station to perform SerDes frame decomposition, and the hardware latency is the same for each slave station.

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