Solid-state imaging devices

Abstract

The present invention provides a solid-state imaging device. A plurality of unit pixels in the solid-state imaging device are arranged in a matrix along row and column directions. Each unit pixel includes a plurality of light-sensing regions for sensing a plurality of colors and a signal readout circuit region. Each light-sensing region includes an on-chip lens, a color filter, one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion region. The signal readout circuit region includes a plurality of in-pixel transistors. In each unit pixel, the floating diffusion region and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors. The elements in each unit pixel are arranged symmetrically with respect to the center line of each unit pixel.

Description

Technical Field

[0001] The present application relates to a solid-state imaging device. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensors are solid-state imaging devices that convert light into electrical signals. In a CMOS image sensor pixel, multiple photodiodes share a single signal readout circuit, allowing for smaller pixels without sacrificing performance.

[0003] The Bayer arrangement is commonly used as a color filter layout for pixels. In this arrangement, a unit pixel includes two green sensors, one blue sensor, and one red sensor. The two green sensors are required to have the same sensitivity. However, if incident light reflects off the signal readout circuitry, this reflected light can enter the sensors. If the amount of light entering the two green sensors differs, the signal levels output from the two sensors become different. This difference creates a maze-like fixed-pattern noise in the output image. Summary of the Invention

[0004] According to a first aspect of the present application, a solid-state imaging device is provided. A plurality of unit pixels in the solid-state imaging device are arranged in a matrix along row and column directions. Each unit pixel includes a plurality of light sensing regions and a signal readout circuit region for sensing a plurality of colors. Each light sensing region includes an on-chip lens, a color filter, one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion region. The signal readout circuit region includes a plurality of in-pixel transistors. In each unit pixel, the floating diffusion region and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors. The elements in each unit pixel are arranged symmetrically with respect to the center line of each unit pixel.

[0005] According to a second aspect of the present application, the plurality of in-pixel transistors include a reset transistor, a source follower transistor, and a row select transistor. The reset transistor and the row select transistor have the same size and are arranged symmetrically with respect to the center line. The source follower transistor is arranged on the center line and has a shape symmetrical with respect to the center line.

[0006] According to a third aspect of the present application, the plurality of in-pixel transistors include a reset transistor, a dual conversion gain transistor, a source follower transistor, and a row select transistor. The reset transistor and the row select transistor have the same size and are arranged symmetrically with respect to the center line. The dual conversion gain transistor and the source follower transistor have the same size and are arranged symmetrically with respect to the center line.

[0007] According to the present invention, the elements within a unit pixel are arranged symmetrically with respect to the center line of the unit pixel. As a result, the light reflected in the signal readout circuit region is balanced, and the signal levels output from the photodiodes are also balanced, thereby suppressing the maze-like fixed pattern noise in the output image. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A Bayer arrangement of color filters is shown.

[0009] Figure 2 The layout of elements in one unit pixel of the solid-state imaging device provided by the first embodiment of the present application is shown.

[0010] Figure 3 The layout of elements in one unit pixel of the solid-state imaging device provided by the second embodiment of the present application is shown.

[0011] Figure 4 A circuit in one unit pixel of a solid-state imaging device provided by a second embodiment of the present application is shown.

[0012] Figure 5 The layout of elements in one unit pixel of a solid-state imaging device provided in the third embodiment of the present application is shown.

[0013] Figure 6 The layout of elements in one unit pixel of a solid-state imaging device provided in the fourth embodiment of the present application is shown.

[0014] Figure 7 The layout of elements in one unit pixel of a solid-state imaging device provided in the fifth embodiment of the present application is shown.

[0015] Figure 8 The layout of elements in one unit pixel of a solid-state imaging device provided by the sixth embodiment of the present application is shown.

[0016] Figure 9 The layout of elements in one unit pixel of a solid-state imaging device provided by the seventh embodiment of the present application is shown.

[0017] Figure 10 The layout of elements in one unit pixel of a solid-state imaging device provided in the eighth embodiment of the present application is shown.

[0018] Figure 11 The layout of elements in one unit pixel of a solid-state imaging device provided by the ninth embodiment of the present application is shown.

[0019] Figure 12 An exemplary imaging device using the solid-state imaging device provided by the present application is shown.

[0020] Figure 13 The following shows the application fields using the solid-state imaging device provided by the present application. DETAILED DESCRIPTION

[0021] Figure 1 The figure shows a Bayer arrangement of color filters. In the Bayer arrangement, three color filters, including green, blue, and red filters, are arranged in a matrix along the rows and columns. A unit pixel includes a set of four filters, including two green filters (Gb filter and Gr filter), one blue filter (B filter), and one red filter (R filter). In the row direction, the Gb filter is the green filter next to the B filter, and the Gr filter is the green filter next to the R filter.

[0022] Figure 2 The layout of elements in a unit pixel of a solid-state imaging device provided by the first embodiment of the present application is shown. A unit pixel includes four light sensing areas (i.e., a Gb sensing area, a B sensing area, an R sensing area, and a Gr sensing area) and a signal readout circuit area. Each light sensing area includes an on-chip lens (OCL), a color filter (Gb filter, B filter, R filter, or Gr filter), two photodiodes, two transfer transistors, and a portion of a floating diffusion area. The signal readout circuit area includes three in-pixel transistors TR1, TR2, and TR3, and two pixel well (PW) contacts. However, the number of elements included in the signal readout circuit area is not limited to the above number.

[0023] Photodiodes PD1 and PD2 are covered with a Gb filter and an on-chip lens (OCL). Photodiodes PD3 and PD4 are covered with an R filter and an on-chip lens (OCL). Photodiodes PD5 and PD6 are covered with a B filter and an on-chip lens (OCL). Photodiodes PD7 and PD8 are covered with a Gr filter and an on-chip lens (OCL).

[0024] The eight photodiodes PD1 to PD8 are respectively connected to eight transfer transistors TX1 to TX8 , which are connected to a floating diffusion (FD) region.

[0025] A signal readout circuit region is arranged on the boundary of the unit pixel below the R sensing region and the Gr sensing region, and pixel well (PW) contacts are arranged on the lower left and lower right of the boundary.

[0026] A floating diffusion region (FD) and a signal readout circuit are shared by eight photodiodes PD1 to PD8 and transfer transistors TX1 to TX8 .

[0027] The elements within a unit pixel are arranged symmetrically about the unit pixel's center line YY'. In-pixel transistors TR1 and TR3 have the same size and are arranged symmetrically about center line YY'. In-pixel transistor TR2 is arranged on center line YY' and has a symmetrical shape about center line YY'.

[0028] Due to these arrangements, light reflected at the region of the signal readout circuit is balanced, and signal levels output from the Gb sensing region and the Gr sensing region are balanced, thereby suppressing maze-like fixed pattern noise in the output image.

[0029] Figure 3 The layout of elements in a unit pixel of a solid-state imaging device provided in a second embodiment of the present application is shown. In the second embodiment, the signal readout circuit region includes a reset transistor (RST), a source follower (SF) transistor, and a row select (SEL) transistor as three in-pixel transistors.

[0030] A floating diffusion region (FD), a reset transistor (RST), a source follower (SF) transistor, and a row select (SEL) transistor are shared by eight photodiodes PD1 to PD8 and transfer transistors TX1 to TX8 .

[0031] The elements in the unit pixel are arranged symmetrically with respect to the center line YY' of the unit pixel. The reset transistor (RST) and the row select (SEL) transistor have the same size and are arranged symmetrically with respect to the center line YY'. The source follower (SF) transistor is arranged on the center line YY', has a symmetrical shape with respect to the center line YY', and is larger than the reset transistor (RST) and the row select (SEL) transistor. The rest of the configuration is the same as the first embodiment.

[0032] Figure 4 The circuit in a unit pixel of a solid-state imaging device provided by the second embodiment of the present application is shown. The reset transistor (RST) is turned on in response to a reset signal and resets the charge accumulated in the floating diffusion region (FD). The photodiodes PD1 to PD8 generate a charge corresponding to the amount of incident light through photoelectric conversion and accumulate the generated charge. One of the transfer transistors TX1 to TX8 is turned on in response to a transfer signal and transfers the charge accumulated in one of the photodiodes PD1 to PD8 to the floating diffusion region (FD). The voltage of the floating diffusion region (FD) is determined by the transferred charge. This voltage is applied to the gate of the source follower (SF) transistor. The source follower (SF) transistor sends a pixel signal corresponding to the voltage of the floating diffusion region (FD) to the row select (SEL) transistor. The row selection (SEL) transistor is connected to a vertical signal line (VSL) and transmits a pixel signal to the vertical signal line (VSL) in response to a row selection signal.

[0033] Figure 5The layout of elements in a unit pixel of a solid-state imaging device provided by the third embodiment of the present application is shown. In the third embodiment, the channel direction of the reset transistor (RST) and the row select (SEL) transistor forms a 90-degree angle with respect to the channel direction of the source follower (SF) transistor. The source of the source follower (SF) transistor and the drain of the row select (SEL) transistor are independent active regions and are connected by metal wiring. Therefore, the resistance of this node is reduced, and the signal linearity and RC delay are improved. The rest of the structure is the same as the second embodiment.

[0034] Figure 6 The layout of elements in a unit pixel of a solid-state imaging device provided by the fourth embodiment of the present application is shown. In the fourth embodiment, the source follower (SF) transistor is divided into four sub-transistors. These four sub-transistors are connected in parallel to each other. Multiple source follower transistors improve pixel noise and pixel reset noise. Two sub-transistors and the remaining two sub-transistors are arranged symmetrically with respect to the center line YY'. The rest of the structure is the same as the third embodiment.

[0035] Figure 7 The fifth embodiment of the present invention provides a solid-state imaging device with a unit pixel layout. In the fifth embodiment, two sub-transistors are combined with gates located on the same side relative to the center line YY'. The rest of the structure is the same as the fourth embodiment.

[0036] Figure 8 The sixth embodiment of the present invention provides a solid-state imaging device with a unit pixel layout. In the sixth embodiment, two dual conversion gain (DCG) transistors and two sub-transistors (source-follower transistors) have the same size and are symmetrically arranged relative to the center line YY'. The symmetrical layout with dual conversion gain (DCG) transistors enhances the dynamic range. The rest of the structure is the same as the fifth embodiment.

[0037] Figure 9The layout of elements in a unit pixel of a solid-state imaging device provided by the seventh embodiment of the present application is shown. In the seventh embodiment, a portion of the channel of the reset transistor (reset transistor, RST) overlaps with a portion of the photodiode PD3, a portion of the channel of the dual conversion gain (dual conversion gain, DCG) transistor overlaps with a portion of the photodiode PD4, a portion of the channel of the sub-transistor (source follower transistor) overlaps with a portion of the photodiode PD7, and a portion of the channel of the row select (SEL) transistor overlaps with a portion of the photodiode PD8. These arrangements increase the volume of the photodiode, thereby increasing the saturation capacitance. Therefore, the dynamic range is enhanced and the S / N under strong light is improved. The rest of the structure is the same as the sixth embodiment.

[0038] Figure 10 The figure shows the layout of elements within a unit pixel of a solid-state imaging device provided in the eighth embodiment of this application. In the eighth embodiment, a photodiode is covered with a color filter and an on-chip lens. Therefore, a unit pixel includes four photodiodes PD1 to PD4, which are connected to four transfer transistors TX1 to TX4, respectively. The rest of the structure is the same as in the seventh embodiment.

[0039] Figure 11 The layout of elements in a unit pixel of a solid-state imaging device provided by the ninth embodiment of the present application is shown. In the ninth embodiment, the row selection (SEL) transistor is arranged on the boundary of the unit pixel on the left side of the Gb sensing region and on the row direction center line of the Gb sensing region. The reset transistor (reset transistor, RST) is arranged on the boundary of the unit pixel on the left side of the R sensing region and on the row direction center line of the R sensing region. The dual conversion gain (dual conversion gain, DCG) transistor is arranged on the column direction center line of the R sensing region. The sub-transistor (source follower transistor) is arranged on the column direction center line of the Gr sensing region. The rest of the structure is the same as the eighth embodiment.

[0040] In other embodiments, a unit pixel may include a different number of photodiodes than in the above embodiment. For example, it is possible to include two photodiodes along the row direction by four photodiodes along the column direction. Similarly, 4×4, 8×2, and 2×8 are also possible.

[0041] The present application can be applied to array devices. For these devices, various substrates can be used, such as bulk silicon substrates, silicon-on-insulator substrates, silicon-germanium substrates, and other photosensitive substrates.

[0042] Figure 12An exemplary imaging device using the solid-state imaging device provided by the present application is shown. The imaging device includes a lens 1, a shutter 2, a solid-state imaging device 3, a signal processing circuit 4, and a display 5. The lens 1 forms an image of an object on the solid-state imaging device 3. The shutter 2 controls the incident light entering the solid-state imaging device 3. The solid-state imaging device 3 outputs a pixel signal corresponding to the incident light. The signal processing circuit 4 performs various signal processing on the pixel signal. The display 5 displays the image of the object corresponding to the processed pixel signal.

[0043] In the imaging device using the solid-state imaging device 3 provided by the present application, the display 5 can display an image in which maze-like fixed pattern noise is suppressed.

[0044] Figure 13 The solid-state imaging device provided by this application can be used in various application fields, such as mobile phone cameras, digital cameras, webcams, security cameras, video cameras, automotive and traffic cameras, medical cameras, and machine vision.

Claims

1. A solid-state imaging device, characterized in that A plurality of unit pixels in the solid-state imaging device are arranged in a matrix along row and column directions; Each unit pixel includes a plurality of light sensing regions for sensing a plurality of colors and a signal readout circuit region; Each light sensing region includes an on-chip lens, a color filter, one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion region; The signal readout circuit region includes a plurality of in-pixel transistors; In each unit pixel, the floating diffusion region and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors; The elements in each unit pixel are arranged symmetrically with respect to the center line of each unit pixel; wherein the plurality of light sensing regions in each unit pixel include two green sensing regions, one blue sensing region, and one red sensing region in a Bayer arrangement; and The multiple in-pixel transistors include a reset transistor, a source follower transistor and a row selection transistor; the reset transistor and the row selection transistor have the same size and are arranged symmetrically with respect to the center line; the source follower transistor is arranged on the center line and has a shape symmetrical with respect to the center line.

2. The solid-state imaging device according to claim 1, wherein Channel directions of the reset transistor and the row selection transistor form a 90-degree angle with respect to the channel direction of the source follower transistor.

3. The solid-state imaging device according to claim 2, wherein The source follower transistor is divided into a plurality of sub-transistors.

4. The solid-state imaging device according to claim 3, wherein The sub-transistors are combined with their gates located on the same side with respect to the center line.

5. The solid-state imaging device according to claim 1, wherein A portion of the in-pixel transistor overlaps a portion of the photodiode.

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