Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes: a display area, a fan-out area, and a binding area arranged sequentially along the column direction; the display area includes a central display area and an edge display area arranged along the row direction on at least one side of the central display area; the display area includes multiple data lines arranged along the row direction; the binding area is provided with a driver chip; the data lines arranged sequentially along the direction from the edge display area to the central display area are defined as a sequential arrangement; the fan-out traces connecting the data lines in the edge display area are arranged between the fan-out traces connecting the data lines in the central display area, so that the data signals on the sequentially arranged fan-out traces are arranged in a random order; the driver chip includes a sequence adjustment module for forming a random data signal queue that matches the random order of the data signals on the fan-out traces, so that the driver chip provides the randomized data signals to the fan-out traces. The present invention can achieve a narrow-frame design for the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, users have higher and higher requirements for the screen ratio of display panels, and narrow frame design has become a major development trend of display panels. However, fan-out traces need to be set at the bottom frame of the display panel, such as Figure 1 As shown, in the prior art, each output terminal C0 of the driver chip 01 is connected to each data line S0 in the display area AA0 through each fan-out line LS0, and many fan-out lines LS0 are usually wired diagonally. However, with the continuous improvement of the resolution of the display panel, the number of data lines S0 and fan-out lines LS0 has gradually increased. In order to avoid line short circuits and signal interference, it is necessary to set a larger frame width d0 so that there is sufficient distance between the diagonally arranged fan-out lines LS0. In particular, for the arc chamfered area at the lower end of the display area AA0, the wiring of the fan-out lines LS0 is relatively dense, and the frame width d0 needs to be sufficiently large. Therefore, in the prior art, it is necessary to reserve a wider layout space for the fan-out lines LS0, so that the frame of the display panel is wider. Summary of the Invention

[0003] The present invention provides a display panel and a display device to achieve a narrow frame design of the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a display panel comprising: a display area, a fan-out area, and a binding area arranged sequentially along a column direction; the display area comprising a central display region and an edge display region arranged along a row direction on at least one side of the central display region; the display area comprising a plurality of data lines arranged along the row direction and extending along the column direction; a driver chip being provided in the binding area; the driver chip providing a data signal to each of the data lines via a plurality of fan-out traces located in the fan-out area;

[0005] The data lines arranged in sequence along the direction from the edge display area to the central display area are defined as being arranged in sequence; the fan-out traces for connecting the data lines in the edge display area are arranged between the fan-out traces for connecting the data lines in the central display area, so that the data signals on the fan-out traces arranged in sequence are arranged in a disordered order;

[0006] The driver chip includes: a sequence adjustment module for forming a disordered data signal queue that matches the disordered manner of the data signals on each fan-out line, so that the driver chip provides disordered data signals to each fan-out line.

[0007] Optionally, the driver chip includes data signal output terminals having the same number as the fan-out lines, and along the row direction, each of the data signal output terminals is correspondingly connected to each of the fan-out lines in sequence;

[0008] The sequence adjustment module includes a plurality of data output terminals connected to the data signal output terminals in a one-to-one correspondence.

[0009] Optionally, the driver chip further includes: a plurality of output channels corresponding one-to-one to the data output terminals, the output channels being connected between the corresponding data output terminals and the data signal output terminals, the output channels being used to adjust the data signals in the disordered data signal queue to form the data signals required by the sub-pixels connected to the data lines corresponding to the output channels.

[0010] Optionally, the output channel includes: a buffer module, a potential conversion module, a digital-to-analog converter, and an amplifier connected in sequence; wherein the buffer module is electrically connected to the corresponding data output terminal, and the amplifier is electrically connected to the corresponding data signal output terminal;

[0011] Preferably, the driver chip further comprises: a gamma adjustment module connected to the digital-to-analog converter in each of the output channels.

[0012] Optionally, the driver chip further comprises: a data mapping module, wherein an input end of the data mapping module is connected to the target image data, and an output end of the data mapping module is connected to an input end of the sequence adjustment module; the data mapping module is configured to convert the target image data into a sequential data signal queue that matches the sequentially arranged data lines;

[0013] The sequence adjustment module is used to convert the sequential data signal queue into the disordered data signal queue.

[0014] Optionally, the fan-out routing corresponding to the data line in the edge display area includes: a first connection portion located in the display area and a second connection portion located in the fan-out area; the first connection portion is connected to the corresponding data line through a switching line, the first connection portion is connected to the second connection portion, and the second connection portion is connected to the driver chip;

[0015] Each of the first connecting portions is arranged between each of the data lines in the central display area according to a preset rule, and each of the second connecting portions is correspondingly arranged between each of the fan-out traces connected to each of the data lines in the central display area;

[0016] Preferably, the preset rule includes: for each fan-out routing connected to each data line of any side edge display area, in the central display area, starting from the side of the central display area close to the edge display area, k first connection parts are set every m data lines; m and k are both positive integers.

[0017] Optionally, it is defined that along a direction from the edge display area to the central display area, the plurality of data lines in the edge display area are arranged in sequence, and the plurality of first connection portions in the central display area are arranged in sequence;

[0018] The i-th data line in the edge display area is connected to the i-th first connecting portion;

[0019] Alternatively, the i-th data line in the edge display area is connected to the i-th first connection portion from the end; i is a positive integer.

[0020] Optionally, the driver chip further comprises: a data mapping module, wherein an input end of the data mapping module is connected to the target image data, and an output end of the data mapping module is connected to an input end of the sequence adjustment module; the data mapping module is configured to convert the target image data into a sequential data signal queue that matches the sequentially arranged data lines;

[0021] When the i-th data line of the edge display area is connected to the i-th first connection portion, the sequence adjustment module shifts the data signal corresponding to the edge display area in the sequential data signal queue and inserts it between the data signals corresponding to the central display area according to the preset rule;

[0022] When the i-th data line of the edge display area is connected to the i-th first connection part from the end, the sequence adjustment module first arranges the data signals corresponding to the edge display area in the sequential data signal queue in reverse order; and then, according to the preset rule, shifts the data signals corresponding to the edge display area in reverse order and inserts them between the data signals corresponding to the central display area.

[0023] Optionally, along a direction from the edge display area to the central display area, the first n data lines in the edge display area correspond to the first n data signals to be shifted in the sequential data signal queue; for the first n data signals to be shifted in the sequential data signal queue, a group is defined as k consecutive data signals, where n is an integer multiple of k;

[0024] When the i-th data line in the edge display area is connected to the i-th first connection portion, the data signals in the sequential data signal queue are shifted as follows:

[0025] Starting from the first group of data signals among the first n data signals, shifting the jth group of data signals among the first n data signals to before the (n+j)th data signal, until the shifting of the last group of data signals among the first n data signals is completed;

[0026] or,

[0027] Starting from the first group of data signals among the first n data signals, the jth group of data signals among the first n data signals are shifted to after the (n+j)th data signal until the shifting of the last group of data signals among the first n data signals is completed.

[0028] Optionally, along the direction from the edge display area to the central display area, the n data lines in the edge display area correspond to the first n data signals to be shifted in the sequential data signal queue;

[0029] When the i-th data line in the edge display area is connected to the i-th first connection portion from the end, the data signals in the sequential data signal queue are shifted as follows:

[0030] Arrange the first n data signals in the sequential data signal queue in reverse order to form a rearranged data signal queue; for the first n data signals to be shifted in the rearranged data signal queue, define k consecutive data signals therein as a group, where n is an integer multiple of k;

[0031] Starting from the first group of data signals in the first n data signals in the rearranged data signal queue, shifting the jth group of data signals in the first n data signals to before the n+jth data signal in the rearranged data signal queue until the shifting of the last group of data signals in the first n data signals is completed;

[0032] or,

[0033] Starting from the first group of data signals among the first n data signals in the rearranged data signal queue, the jth group of data signals among the first n data signals are shifted to after the n+jth data signal in the rearranged data signal queue until the shift of the last group of data signals among the first n data signals is completed.

[0034] Optionally, a chamfered area is provided on a side of the edge display area close to the fan-out area, and the length of the data line corresponding to the chamfered area is smaller than the length of the data line in the central display area.

[0035] In a second aspect, an embodiment of the present invention further provides a display device, comprising a display panel provided by any embodiment of the present invention.

[0036] The display panel provided by an embodiment of the present invention arranges the fan-out traces used to connect the data lines in the edge display area between the fan-out traces used to connect the data lines in the center display area, and incorporates a sequence adjustment module in the driver chip to provide a random data signal queue that matches the random order of the data signals on the fan-out traces. This minimizes the tilt angle of the fan-out traces in the edge display area while ensuring normal driving of each sub-pixel in the display area. This reduces the bezel width of the display panel while preventing short circuits and signal interference between adjacent fan-out traces. Furthermore, in this embodiment of the present invention, the fan-out traces are concentrated below the center display area, ensuring that the width of the fan-out area does not exceed that of the center display area. Therefore, the chamfer design of the edge display area is not limited by the space required for fan-out trace routing, facilitating flexible reduction of the display area chamfer size. Furthermore, by adding the sequence adjustment module to the driver chip to create the random data signal queue, the embodiment of the present invention eliminates the need to modify the structures of other modules in the driver chip, thereby reducing the complexity of the implementation. Therefore, compared to the prior art, this embodiment of the present invention can achieve a narrow bezel design for the display panel.

[0037] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 This is a structural diagram of an existing display panel;

[0040] Figure 2 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0041] Figure 3 yes Figure 2 Enlarged schematic diagram of the middle area DD1;

[0042] Figure 4 This is a schematic structural diagram of a driver chip provided by an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of a process in which a sequence adjustment module generates a disordered data signal queue based on a sequence data signal queue, provided by an embodiment of the present invention;

[0044] Figure 6 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0045] Figure 7 It is a schematic diagram of a process in which another sequence adjustment module provided by an embodiment of the present invention generates a disordered data signal queue based on a sequence data signal queue. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0048] An embodiment of the present invention provides a display panel, which can realize a narrow-frame design of the display panel based on FIAA (fanout in AA area) technology. Figure 2 is a structural schematic diagram of a display panel provided by an embodiment of the present invention; Figure 3 yes Figure 2 An enlarged schematic diagram of the middle area D1. Figure 2 and Figure 3 The display panel includes a display area, a fan-out area FA, and a binding area BA, arranged sequentially along the column direction Y. The display area includes a central display area AA1 and an edge display area AA2 arranged along the row direction X to at least one side of the central display area AA1. The display area includes a plurality of data lines arranged along the row direction X and extending along the column direction Y. Each data line can connect to sub-pixels in a corresponding column (not shown in the figure). A driver chip 100 is provided in the binding area BA; the driver chip 100 provides data signals to each data line via a plurality of fan-out traces F located in the fan-out area FA.

[0049] Data lines arranged sequentially from the edge display area to the center display area are defined as being arranged sequentially. Fan-out traces F connecting the data lines in the edge display area AA2 are inserted between the fan-out traces F connecting the data lines in the center display area AA1, causing the data signals on the sequentially arranged fan-out traces F to be out of order. The driver chip 100 includes a sequence adjustment module 110 for forming an out-of-order data signal queue Qdata that matches the out-of-order data signals on the fan-out traces LS, enabling the driver chip 100 to provide out-of-order data signals to the fan-out traces LS.

[0050] Figure 2 In the figure, two edge display areas AA2 are shown on both sides of the central display area AA1 along the row direction X. It should be noted that when the display area includes two edge display areas AA2, the direction along the edge display area to the central display area can be understood as the direction from any edge display area AA2 to the central display area AA1, for example, from left to right, or from right to left. Alternatively, the central display area is divided into two left and right sub-display areas with the central axis of the central display area AA1 in the row direction as the boundary. Then, for the left edge display area AA2, the direction along the edge display area to the central display area is the direction along the left edge display area AA2 to the left sub-display area, that is, the direction from left to right; for the right edge display area AA2, the direction along the edge display area to the central display area is the direction along the right edge display area AA2 to the right sub-display area, that is, the direction from right to left.

[0051] For ease of explanation, the data lines located in the edge display area AA2 are referred to as edge data lines, and the data lines located in the center display area AA1 are referred to as center data lines. Furthermore, the fan-out traces connected to the edge data lines are referred to as edge fan-out traces, and the fan-out traces connected to the center data lines are referred to as center fan-out traces. Furthermore, in the figures, to distinguish between edge fan-out traces and center fan-out traces, the center fan-out traces are drawn as solid lines, and the edge fan-out traces are drawn as dashed lines.

[0052] Exemplarily, the positive direction of the row direction X is defined as from left to right. The sequential arrangement of the data lines can be understood as follows: along the positive direction of the row direction X, the numbers of the data lines are S1, S2, ..., Sn, which constitute the sequential numbering of the data lines. The order of the data signals on the fan-out traces arranged in sequence is disordered, which means that along the positive direction of the row direction X, the numbering of the fan-out traces is sequential, but the numbering of the data signals on the fan-out traces is non-sequential (i.e., disordered). Among them, the numbering order of the data signals on the fan-out traces is the same as the numbering order of the data signals required by the data lines connected to the fan-out traces arranged in sequence. The disordered data signal queue Qdata matches the disordered manner of the data signals on each fan-out trace LS, which means that along the positive direction of the row direction X, the numbering order of each data signal in the disordered data signal queue Qdata is the same as the numbering order of the data signals required by the data lines connected to the fan-out traces arranged in sequence. The numbering order of each data signal in the out-of-order data signal queue Qdata is related to the way in which the edge fan-out traces are inserted into the center fan-out traces, and the connection order between the edge fan-out traces and the edge data lines.

[0053] The following combination Figure 3 Taking the four edge data lines in the left edge display area AA2 and the five center data lines in the center display area AA1 as examples, the setting method of the fan-out routing and the arrangement method of the data signals in the out-of-order data signal queue Qdata in an embodiment of the present invention are explained.

[0054] Specifically, along the positive direction of the row direction X, the data lines are numbered S1 to S9, wherein the data lines numbered S1 to S4 are edge data lines, and the data line S9 numbered S5 to S9 is the center data line. The fan-out lines are numbered F1 to F9. For example, the fan-out lines numbered F1, F3, F5, F7 and F9 are center fan-out lines, corresponding to the data lines numbered S5, S6, S7, S8 and S9, respectively. The fan-out lines numbered F2, F4, F6 and F8 are edge fan-out lines inserted between the center fan-out lines, and the edge fan-out lines numbered F2, F4, F6 and F8 correspond to the edge data lines numbered S1, S2, S3 and S4, respectively. Among them, each center fan-out line may only include the portion located in the fan-out area FA, and each edge fan-out line may be extended from the fan-out area FA to the center display area AA1, and connected to the corresponding data line by punching and switching lines.

[0055] Along the positive direction of the row direction X, the data signals in the out-of-order data signal queue Qdata are numbered as follows: d5, d1, d6, d2, d7, d3, d8, d4 and d9. The data signals numbered d5, d1, d6, d2, d7, d3, d8, d4 and d9 are respectively transmitted to the fan-out lines numbered F1, F2, F3, F4, F5, F6, F7, F8 and F9, so that each data line can receive the data signal with the corresponding number, thereby ensuring the normal driving of each sub-pixel in the display area.

[0056] For example, the sequence adjustment module 110 can be connected to a sequential data signal queue that matches the arrangement order of the data lines, and form a final disordered data signal queue Qdata by swapping the positions of the data signals in the sequential data signal queue. The sequential data signal queue can be obtained by processing the target display image by the original data processing-related modules in the driver chip 100. Therefore, the embodiment of the present invention only needs to add the sequence adjustment module 110 to the output path of the sequential data signal queue on the basis of the existing driver chip 100 structure to obtain the disordered data signal queue, without having to make other complex changes to the original data processing modules in the driver chip 100 in order to generate the disordered data signal queue, which is conducive to the actual implementation and mass production of the driver chip 100.

[0057] The display panel provided by an embodiment of the present invention arranges the fan-out traces F used to connect the data lines in the edge display area AA2 between the fan-out traces F used to connect the data lines in the center display area AA1, and provides a sequence adjustment module 110 in the driver chip 100 to provide a random data signal queue Qdata that matches the random order of the data signals on the fan-out traces LS. This minimizes the tilt angle of the fan-out traces corresponding to the edge display area AA2 within the fan-out area FA while ensuring normal driving of each sub-pixel in the display area. This reduces the bezel width of the display panel while ensuring that adjacent fan-out traces F do not short-circuit and signal interference. Furthermore, in this embodiment of the present invention, the fan-out traces are concentrated below the center display area AA1, ensuring that the width of the fan-out area FA does not exceed that of the center display area AA1. Therefore, the chamfer design of the edge display area AA2 is not restricted by the space required for fan-out trace routing, facilitating flexible reduction of the chamfer size of the display area. Furthermore, the embodiment of the present invention adds a sequence adjustment module 110 to the driver chip 100 to generate the out-of-order data signal queue Qdata, without modifying the structures of other modules in the driver chip 100, which helps reduce the complexity of the solution implementation. Therefore, compared with the existing technology, the embodiment of the present invention can achieve a narrow-frame design for the display panel.

[0058] Continue to see Figure 3Based on the above embodiments, optionally, the edge fan-out routing includes: a first connection portion LS1 located in the display area and a second connection portion LS2 located in the fan-out area FA; the first connection portion LS1 is connected to the corresponding edge data line through a line change, the first connection portion LS1 is connected to the second connection portion LS2, and the second connection portion LS2 is connected to the driver chip 100. Each first connection portion LS1 is inserted between each center data line in the center display area AA1 according to a preset pattern, and each second connection portion LS2 is inserted between each center fan-out routing according to the same movement pattern as the first connection portion LS1. Exemplarily, the preset pattern can be: for each fan-out routing connected to each data line of the edge display area AA2 on either side, within the center display area AA1, starting from the side of the center display area AA1 close to the edge display area AA2, k first connection portions are provided every m data lines; m and k are both positive integers. The values of m and k can be selected according to actual needs.

[0059] Illustratively, each first connection portion LS1 is located in the central display area AA1 and extends along the column direction Y. Illustratively, the first connection portion LS1, the second connection portion LS2, the central fan-out trace, and each data line may be located on the same metal layer, and the edge data line and the corresponding first connection portion LS1 are connected via a jumper wire LH located on another metal layer, and the jumper wire LH is connected to the edge data line and the first connection portion LS1 via vias.

[0060] Among them, arc chamfers can be set at all four corners of the display area. Then, the edge display area AA2 forms a chamfered area at the angle formed by the edge close to the fan-out area FA in the column direction Y and the edge away from the center display area AA1 in the row direction X. The length of the edge data line corresponding to the chamfered area is shorter than that of the center data line. In addition, the edge data line does not need to extend to the chamfered edge to provide sufficient layout space for the fan-out line. Figure 3 As shown in , the portion of each edge data line within the dotted triangle area DD2 (i.e., below the junction of the edge data line and each jumper LH, including the chamfered area) can be deleted to make the chamfering of the display area more flexible.

[0061] The above embodiments mainly focus on the configuration of the fan-out lines and the corresponding relationship between the data signals in the out-of-order data signal queue Qdata.

[0062] Continue to see Figure 3 On the basis of the above embodiments, the driver chip 100 may optionally include the same number of data signal output terminals as the number of fan-out lines (numbered C1, C2, C3, ... in the positive direction of the row direction X). Along the row direction X, each data signal output terminal is connected to each fan-out line in sequence. Figure 3 As described above, for example, the data signal output terminals numbered C1, C2, C3, C4, C5, C6, C7, C8, and C9 are sequentially connected to the fan-out traces numbered F1, F2, F3, F4, F5, F6, F7, F8, and F9. Accordingly, the sequence adjustment module 110 includes a plurality of data output terminals (numbered E1, E2, E3, ... in the positive direction of the row direction X) that are connected one-to-one with the data signal output terminals. After generating the out-of-order data signal queue Qdata, the sequence adjustment module 110 can distribute each data signal in the queue to each data output terminal in a one-to-one correspondence.

[0063] Figure 4 This is a schematic diagram of the structure of a driver chip provided by an embodiment of the present invention, see Figure 4 Based on the above embodiments, the driver chip 100 may optionally further include: a plurality of output channels 120 corresponding one-to-one to the data output terminals, the output channels 120 being connected between the corresponding data output terminals and the data signal output terminals. The output channels 120 are configured to adjust the data signals in the out-of-order data signal queue to form the data signals required by the sub-pixels connected to the data lines corresponding to the output channels. For example, the output channels 120 may amplify and perform digital-to-analog conversion on the data signals in the out-of-order data signal queue so that the data signals ultimately transmitted to the corresponding data lines meet the driving requirements of the sub-pixels on the data lines.

[0064] Furthermore, the output channel 120 may include: a cache module 121, a potential conversion module 122, a digital-to-analog converter 123 and an amplifier 124 connected in sequence; wherein the cache module 121 is electrically connected to the corresponding data output end, and the amplifier 124 is electrically connected to the corresponding data signal output end.

[0065] For example, the buffer module 121 can be composed of a first buffer 21 and a second buffer 22 connected in series, so that the data signal corresponding to the output channel 120 in the out-of-order data signal queue is transmitted toward the screen display area after being buffered at two levels. The potential conversion module 122 can be used to raise the potential of the data signal output by the buffer module 121. The raised data signal is then converted by the digital-to-analog converter 123 and amplified by the amplifier 124 to form the data signal required to drive the sub-pixels on the data line.

[0066] Furthermore, the driver chip 100 may further include a gamma adjustment module 130 connected to the DAC 123 in each output channel 120 , for transmitting a gamma voltage to each DAC 123 to implement gamma adjustment on each data signal.

[0067] Continue to see Figure 4Based on the above embodiments, the driver chip 100 may optionally further include a data mapping module 140, wherein the target image data Ddata is connected to an input of the data mapping module 140, and the output of the data mapping module 140 is connected to an input of the sequence adjustment module 110. The data mapping module 140 is configured to convert the target image data Ddata into a sequential data signal queue that matches the sequentially arranged data lines. The sequential data signal queue is a queue of data signals whose numbers increase sequentially along the positive direction of the row direction X.

[0068] Exemplarily, the data mapping module 140 includes a latch control unit 141 and a data mapping unit 142 connected in series. The latch control unit 141 can store target image data Ddata, and the data mapping unit 142 is configured to convert the target image data Ddata into a sequential data signal sequence. Exemplarily, the target image data Ddata can be a matrix of target image data for each subpixel corresponding to the arrangement of subpixels in the display area, representing a target display effect, and specifically including information such as target display brightness for each subpixel of different colors.

[0069] As described above, the sequence adjustment module 110 is used to convert a sequential data signal queue into a disordered data signal queue. Exemplarily, the sequence adjustment module 110 can implement the reordering of the data signal queue through a software program or a hardware circuit. Specifically, the sequential data signal queue can be stored in the form of a data matrix; developers can write corresponding programs based on the reordering requirements of converting the sequential data signal queue into a disordered data signal queue, and swap the positions of the data signals in the data matrix. Alternatively, the sequence adjustment module 110 may include a storage matrix composed of registers for correspondingly storing the data signals in the data signal queue. The reordering of the data signal queue can be achieved by adjusting the position of each register in the storage matrix or the corresponding connection relationship between each register and each data output terminal in the sequence adjustment module 110.

[0070] Next, the conversion process of the sequence data signal queue by the sequence adjustment module 110 is described in combination with the rule of inserting the edge fan-out traces between the center fan-out traces and the connection sequence of the inserted edge fan-out traces and the edge data lines.

[0071] In one embodiment, optionally, a preset rule for inserting the edge fan-out routing into the center fan-out routing includes: for each edge fan-out routing connected to each edge data line in any side edge display area AA2: within the center display area AA1, starting from the side of the center display area AA1 close to the edge display area AA2, k first connection portions are set every m center data lines; m and k are both positive integers.

[0072] On this basis, see Figure 3 For example, the first connection portions LS1 connected to the edge data lines in any side edge display area AA2 are arranged in positive order, forming a positive order FIAA. That is, the first connection portions LS1 connected to the edge data lines arranged along the positive direction of the row direction X are also arranged in sequence along the positive direction of the row direction X. Specifically, along the direction from the edge display area AA2 to the center display area AA1, the multiple data lines in the edge display area AA2 are arranged in sequence, and the multiple first connection portions LS1 in the center display area AA1 are arranged in sequence, and the i-th data line in the edge display area AA2 is connected to the i-th first connection portion LS1.

[0073] When the first connection parts LS1 corresponding to the edge display area AA2 are arranged in positive sequence, the sequence adjustment module 110 can shift the data signal corresponding to the edge display area AA2 in the sequential data signal queue and insert it between the data signals corresponding to the central display area AA1 according to the same rule as the above-mentioned preset rule.

[0074] Specifically, taking the shifting method of the data signals corresponding to the edge display area AA2 as an example, along the direction from the edge display area AA2 to the center display area AA1, the first n data lines in the edge display area AA2 correspond to the first n data signals to be shifted in the sequential data signal queue. Accordingly, the sequence adjustment module 110 can reorder the data signals in the sequential data signal queue in the following manner:

[0075] For the first n data signals to be shifted in the sequential data signal queue, a group of k consecutive data signals is defined, where n is an integer multiple of k. The sequence adjustment module 110 shifts the data signals in the sequential data signal queue as follows:

[0076] Starting from the first group of data signals among the first n data signals, the jth group of data signals among the first n data signals are shifted to after the (n+j)th data signal until the shifting of the last group of data signals among the first n data signals is completed.

[0077] For example, Figure 3 In the connection structure shown, n=4, m=1 and k=1, a first connection portion LS1 is inserted between two adjacent center data lines, and accordingly, the sequence adjustment module 110 inserts a data signal corresponding to an edge data line between the data signals corresponding to the two adjacent center data lines.

[0078] The above shifting method is not intended to limit the present invention. In other embodiments, optionally, starting from the first group of data signals among the first n data signals, the data signals of the jth group among the first n data signals may be shifted to before the n+jth data signal, until the shifting of the last group of data signals among the first n data signals is completed. The following describes this data signal sequence adjustment method in conjunction with practical applications.

[0079] For example, if the display panel has a resolution of 1080*2400, then the display area needs to have a total of 1080*2 data lines, or 1080*3 data lines. For example, each edge display area AA2 includes n=200 data lines, so the 200 fan-out lines corresponding to each edge display area AA2 need to be routed to the center display area AA1.

[0080] Figure 5 This is a schematic diagram of a process in which a sequence adjustment module generates a disordered data signal queue based on a sequence data signal queue according to an embodiment of the present invention. Figure 5 For example, a square represents a data signal in the data signal queue, and the number in the square is the number corresponding to the data signal. Data signals corresponding to edge data lines (i.e., data signals that need to be shifted) are represented by dense dotted shading. Among the data signals corresponding to the center data lines, data signals located at positions corresponding to data signals corresponding to edge data lines that need to be inserted are represented by sparse dotted shading, and data signals located at positions corresponding to data signals corresponding to edge data lines that do not need to be inserted are not shaded.

[0081] like Figure 5 As shown, exemplarily, in the preset rule, m=1, k=2, and the first connection parts corresponding to the edge display area are arranged in positive order. Taking the shifting method of the data signal corresponding to the left edge display area as an example, it is necessary to shift the 200 data signals of the edge display area in the sequential data signal queue Qini to between the first 100 data signals in the central display area, that is, it is necessary to shift the data signals numbered d1 to d200 in pairs and insert them between the data signals numbered d201 to d300. Specifically, the sequence adjustment module 110 can shift and insert the two data signals numbered d1 and d2 in the sequential data signal queue Qini before the data signal numbered d201, shift and insert the two data signals numbered d3 and d4 before the data signal numbered d202, ..., shift and insert the two data signals numbered d199 and d200 before the data signal numbered d300. After the shift is completed, the shifted data signals may be aligned with the positions of the data signals in the sequential data signal queue Qini to form a disordered data signal queue Qdata.

[0082] At this point, the data signal output terminals numbered C1 and C2 in the driver chip output data signals numbered d1 and d2, respectively, after being processed by the output channel. The data signal output terminal numbered C3 outputs data signals numbered d201, respectively, after being processed by the output channel. The data signal output terminals numbered C4 and C5 output data signals numbered d3 and d4, respectively, after being processed by the output channel. The data signal output terminals numbered C298 and C299 output data signals numbered d199 and d200, respectively, after being processed by the output channel. Starting with the data signal output terminal numbered C300, each data signal output terminal in the non-signal insertion area of the central display area can output the data signal with the same port number. This allows out-of-order driving from the sequential data signal queue Qini to the out-of-order data signal queue Qdata under positive-sequence FIAA. The data signals corresponding to the right edge display area can be shifted and inserted using the same method as the left, which will not be further described.

[0083] It should be noted that the resolution of the display panel, the total number of data lines, the number of edge data lines, the value of m and the value of k are all for illustrative purposes only and are not intended to limit the present invention.

[0084] The above embodiments exemplarily illustrate that the first connection portions LS1 connected to the edge data lines in the edge display area AA2 on either side are arranged in a positive order, that is, along the positive direction of the row direction X, the edge data lines are connected to the first connection portions LS1 in a positive order, but this is not intended to limit the present invention. In other embodiments, for example, Figure 6 As shown, the first connection portions LS1 connected to the edge data lines in any side edge display area AA2 can also be arranged in reverse order, forming a reverse order FIAA. That is, the first connection portions LS1 connected to the edge data lines arranged along the positive direction of the row direction X are arranged in sequence along the negative direction of the row direction X. Specifically, along the direction from the edge display area AA2 to the center display area AA1, the multiple data lines in the edge display area AA2 are arranged in sequence, and the multiple first connection portions LS1 in the center display area AA1 are arranged in sequence, and the i-th data line in the edge display area AA2 is connected to the i-th first connection portion LS1 from the end.

[0085] In this connection mode, see Figure 7The adjustment process of the sequence adjustment module 110 includes: firstly, reversing the order of the data signals corresponding to the edge display area in the sequential data signal queue Qini, for example, reversing the order of the 200 data signals numbered d1 to d200 to obtain data signals numbered d200 to d1 in the positive direction of the row direction X; and then, according to a preset rule, shifting the reversed order of the data signals corresponding to the edge display area and inserting them between the data signals corresponding to the central display area to obtain a disordered data signal queue Qdata.

[0086] Specifically, taking the shifting method of the data signals corresponding to the edge display area AA2 as an example, along the direction from the edge display area AA2 to the center display area AA1, the first n data lines in the edge display area AA2 correspond to the first n data signals to be shifted in the sequential data signal queue. Accordingly, the sequence adjustment module 110 can reorder the data signals in the sequential data signal queue in the following manner:

[0087] The first n data signals in the sequential data signal queue Qini are arranged in reverse order to form a rearranged data signal queue Qre; for the first n data signals to be shifted in the rearranged data signal queue Qre, consecutive k data signals are defined as a group, where n is an integer multiple of k.

[0088] Starting from the first group of data signals among the first n data signals in the rearranged data signal queue Qre, the jth group of data signals among the first n data signals are shifted to before the n+jth data signal in the rearranged data signal queue until the shift of the last group of data signals among the first n data signals is completed.

[0089] like Figure 7 As shown, exemplarily, n=200, m=1, k=2.

[0090] Compared to Figure 5 In the adjustment method in the embodiment, before shifting the data signal, the data signals corresponding to the edge display area are first arranged in reverse order, and then the same Figure 5 The data signal is shifted by the same position movement method as in Figure 5 The different out-of-order data signal queues Qdata are made to correspond to the connection sequence of the edge data lines and the first connection parts LS1.

[0091] The above-mentioned shifting method is also not intended to limit the present invention. In other embodiments, it can also be set to start from the first group of data signals among the first n data signals in the rearranged data signal queue Qre, and shift the jth group of data signals among the first n data signals to after the n+jth data signal in the rearranged data signal queue, until the shift of the last group of data signals among the first n data signals is completed.

[0092] The present invention also provides a display device including a display panel as provided in any embodiment of the present invention. The technical principles and effects thereof are similar and will not be described in detail. For example, the display device may be a mobile phone, a wearable device, a tablet computer, a computer, etc.

[0093] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0094] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: include: A display area, a fan-out area, and a binding area are sequentially arranged along the column direction; the display area includes a central display area and an edge display area arranged along the row direction on at least one side of the central display area; the display area includes a plurality of data lines arranged along the row direction and extending along the column direction; the binding area is provided with a driver chip; the driver chip provides data signals to each of the data lines through a plurality of fan-out traces located in the fan-out area; The data lines arranged in sequence along the direction from the edge display area to the central display area are defined as being arranged in sequence; the fan-out traces for connecting the data lines in the edge display area are arranged between the fan-out traces for connecting the data lines in the central display area, so that the data signals on the fan-out traces arranged in sequence are arranged in a disordered order; The driver chip includes: a sequence adjustment module for forming a disordered data signal queue that matches the disordered manner of the data signals on each fan-out line, so that the driver chip provides disordered data signals to each fan-out line.

2. The display panel according to claim 1, wherein: The driver chip includes data signal output terminals having the same number as the fan-out lines, and along the row direction, each of the data signal output terminals is correspondingly connected to each of the fan-out lines in sequence; The sequence adjustment module includes a plurality of data output terminals connected to the data signal output terminals in a one-to-one correspondence.

3. The display panel according to claim 2, wherein: The driver chip also includes: a plurality of output channels corresponding one-to-one to the data output terminals, the output channels being connected between the corresponding data output terminals and the data signal output terminals, the output channels being used to adjust the data signals in the disordered data signal queue to form the data signals required by the sub-pixels connected to the data lines corresponding to the output channels.

4. The display panel according to claim 3, wherein: The output channel includes: a cache module, a potential conversion module, a digital-to-analog converter and an amplifier connected in sequence; wherein the cache module is electrically connected to the corresponding data output end, and the amplifier is electrically connected to the corresponding data signal output end.

5. The display panel according to claim 4, wherein: The driving chip further includes: a gamma adjustment module connected to the digital-to-analog converter in each of the output channels.

6. The display panel according to claim 1, wherein: The driver chip further includes: a data mapping module, wherein an input end of the data mapping module is connected to the target image data, and an output end of the data mapping module is connected to an input end of the sequence adjustment module; the data mapping module is used to convert the target image data into a sequential data signal queue that matches the sequentially arranged data lines; The sequence adjustment module is used to convert the sequential data signal queue into the disordered data signal queue.

7. The display panel according to claim 1, wherein: The fan-out routing corresponding to the data line in the edge display area includes: a first connection portion located in the display area and a second connection portion located in the fan-out area; the first connection portion is connected to the corresponding data line through a switching line, the first connection portion is connected to the second connection portion, and the second connection portion is connected to the driver chip; Each of the first connection portions is arranged between each of the data lines in the central display area according to a preset rule, and each of the second connection portions is correspondingly arranged between each of the fan-out traces connected to each of the data lines in the central display area.

8. The display panel according to claim 7, wherein: The preset rule includes: for each fan-out routing connected to each data line of any side edge display area, in the central display area, starting from the side of the central display area close to the edge display area, k first connection parts are set every m data lines; m and k are both positive integers.

9. The display panel according to claim 8, wherein: Along the direction from the edge display area to the central display area, the plurality of data lines in the edge display area are arranged in sequence, and the plurality of first connection portions in the central display area are arranged in sequence; The i-th data line in the edge display area is connected to the i-th first connecting portion; Alternatively, the i-th data line in the edge display area is connected to the i-th first connection portion from the end; i is a positive integer.

10. The display panel according to claim 9, wherein: The driver chip further includes: a data mapping module, wherein an input end of the data mapping module is connected to the target image data, and an output end of the data mapping module is connected to an input end of the sequence adjustment module; the data mapping module is used to convert the target image data into a sequential data signal queue that matches the sequentially arranged data lines; When the i-th data line of the edge display area is connected to the i-th first connection portion, the sequence adjustment module shifts the data signal corresponding to the edge display area in the sequential data signal queue and inserts it between the data signals corresponding to the central display area according to the preset rule; When the i-th data line of the edge display area is connected to the i-th first connection part from the end, the sequence adjustment module first arranges the data signals corresponding to the edge display area in the sequential data signal queue in reverse order; and then, according to the preset rule, shifts the data signals corresponding to the edge display area in reverse order and inserts them between the data signals corresponding to the central display area.

11. The display panel according to claim 10, wherein: Along the direction from the edge display area to the central display area, the first n data lines in the edge display area correspond to the first n data signals to be shifted in the sequential data signal queue; for the first n data signals to be shifted in the sequential data signal queue, a group of k consecutive data signals is defined, where n is an integer multiple of k; When the i-th data line in the edge display area is connected to the i-th first connection portion, the data signals in the sequential data signal queue are shifted as follows: Starting from the first group of data signals among the first n data signals, shifting the jth group of data signals among the first n data signals to before the (n+j)th data signal, until the shifting of the last group of data signals among the first n data signals is completed; or, Starting from the first group of data signals among the first n data signals, the jth group of data signals among the first n data signals are shifted to after the (n+j)th data signal until the shifting of the last group of data signals among the first n data signals is completed.

12. The display panel according to claim 10, wherein: Along the direction from the edge display area to the central display area, the n data lines in the edge display area correspond to the first n data signals to be shifted in the sequential data signal queue; When the i-th data line in the edge display area is connected to the i-th first connection portion from the end, the data signals in the sequential data signal queue are shifted as follows: Arrange the first n data signals in the sequential data signal queue in reverse order to form a rearranged data signal queue; for the first n data signals to be shifted in the rearranged data signal queue, define k consecutive data signals therein as a group, where n is an integer multiple of k; Starting from the first group of data signals in the first n data signals in the rearranged data signal queue, shifting the jth group of data signals in the first n data signals to before the n+jth data signal in the rearranged data signal queue until the shifting of the last group of data signals in the first n data signals is completed; or, Starting from the first group of data signals among the first n data signals in the rearranged data signal queue, the jth group of data signals among the first n data signals are shifted to after the n+jth data signal in the rearranged data signal queue until the shift of the last group of data signals among the first n data signals is completed.

13. The display panel according to claim 1, wherein A chamfered area is provided on a side of the edge display area close to the fan-out area, and the length of the data line corresponding to the chamfered area is smaller than the length of the data line in the central display area.

14. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 13.

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