Video overlay method

Abstract

The present application relates to a video overlay method implemented by an FPGA. The method comprises: decoding an input first video signal to obtain a second video signal, and caching the second video signal in a memory, wherein the first video signal is a DP video signal output by a graphics processing unit (GPU); upon detecting a third video signal, decoding the third video signal to obtain a fourth video signal, wherein the third video signal is an input ARINC818 video signal; superimposing the second video signal read from the memory with the fourth video signal to obtain a fifth video signal; encoding the fifth video signal to obtain a sixth video signal, and outputting the sixth video signal to a display panel. Embodiments of the present application can achieve superposition of a 4K resolution DP video signal and an ARINC818 video signal.

Description

Technical Field

[0001] The present application relates to the field of airborne video processing, and in particular to a video overlay method. Background Art

[0002] In related technologies, onboard displays typically overlay camera video with video generated by a graphics processing unit (GPU) before sending it to a display panel for display. Currently, 4K (3840×2160@60Hz) ultra-high-definition video is widely used in the civilian market, but has yet to be applied in the airborne sector. With the development of aircraft displays, 4K technology will gradually be applied on aircraft. Therefore, a method for overlaying 4K ultra-high-definition video is urgently needed. Summary of the Invention

[0003] In view of this, a video superposition method is proposed.

[0004] The video overlay method of an embodiment of the present application is implemented by FPGA, and the method includes: decoding an input first video signal to obtain a second video signal, and caching the second video signal in a memory, where the first video signal is a DP video signal output by an image processor (GPU); when a third video signal is detected, decoding the third video signal to obtain a fourth video signal, where the third video signal is an input ARINC818 video signal; superimposing the second video signal read from the memory with the fourth video signal to obtain a fifth video signal; encoding the fifth video signal to obtain a sixth video signal, and outputting the sixth video signal to a display panel.

[0005] In one possible implementation, the method further includes: generating a seventh video signal when the third video signal is not detected; superimposing the second video signal read from the memory with the seventh video signal to obtain an eighth video signal; encoding the eighth video signal to obtain a ninth video signal, and outputting the ninth video signal to the display panel.

[0006] In a possible implementation, the method further includes: after the FPGA is powered on, training a first link between the FPGA and the display panel; after the first link is successfully trained, training a second link between the FPGA and the GPU.

[0007] In one possible implementation, decoding the third video signal to obtain the fourth video signal includes: when the third video signal includes multiple ARINC818 video signals, decoding each ARINC818 video signal separately to obtain a corresponding tenth video signal; and splicing the multiple tenth video signals to obtain the fourth video signal.

[0008] In one possible implementation, the FPGA includes a control module, a DP physical layer module, a DP link layer receiving module, a DP link layer sending module, a video access module, an ARINC818 decoding module, a video splicing module, a video generation and detection module, a video overlay module and a memory control module.

[0009] In one possible implementation, the training of the first link between the FPGA and the display panel includes: the control module obtaining the EDI D of the display panel; the control module training the first link between the DP link layer sending module of the FPGA and the display panel to obtain the link rate and link number of the first link.

[0010] In one possible implementation, the training of the second link between the FPGA and the GPU includes: the control module configuring the DP link layer receiving module according to the EDI D, the link rate and the number of links; the DP link layer receiving module sending a hot plug detection HPD signal to the GPU to trigger the training of the second link between the DP link layer receiving module and the GPU; after the second link training is successful, the control module sends the MSA value to the DP link layer sending module and enables the DP link layer sending module.

[0011] In one possible implementation, the DP physical layer module is used to: receive the first video signal and send the first video signal to the DP link layer receiving module for decoding; receive the sixth video signal sent by the DP link layer sending module, and output the sixth video signal to the display panel.

[0012] In a possible implementation, the video generation and detection module is configured to: detect whether the third video signal exists; and generate a seventh video signal if the third video signal is not detected.

[0013] In a possible implementation, the resolution of the first video signal is 3840×2160@60 Hz, and the third video signal includes four ARINC818 video signals, and the resolution of each ARINC818 video signal is 960×2160@60 Hz.

[0014] The video overlay method of the embodiment of the present application is implemented through FPGA, and can decode and overlay the ARINC818 video signal output by the camera and the DP video signal output by the GPU, and then encode the overlaid video signal and output it to the display panel for display. This not only enables the overlay of 4K resolution DP video signals and ARINC818 video signals, solving the problem of high-resolution driving screen display for airborne display control, but also completely encodes and decodes the video signal through FPGA, is not limited by the DP codec chips on the market, and can also reduce peripheral devices to reduce costs, power consumption and board area.

[0015] These and other aspects of the present application will become more readily apparent from the following description of the embodiment(s). BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the application and, together with the description, serve to explain the principles of the application.

[0017] Figure 1 A schematic diagram illustrating an application scenario of a video overlay method according to an embodiment of the present application.

[0018] Figure 2 A schematic diagram of an FPGA according to an embodiment of the present application is shown.

[0019] Figure 3 A schematic diagram illustrating an FPGA configuration process according to an embodiment of the present application is shown.

[0020] Figure 4 A flowchart of a video overlay method according to an embodiment of the present application is shown.

[0021] Figure 5 A schematic diagram illustrating a video overlay method according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] Various exemplary embodiments, features, and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0023] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0024] In addition, numerous specific details are provided in the detailed description below to better illustrate the present application. Those skilled in the art will appreciate that the present application can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present application.

[0025] Aircraft displays typically overlay camera video with GPU-generated video before sending it to a display panel for display. Cameras typically use the ARINC 818 protocol, an avionics digital video bus, for video output, so the camera's video signal can be considered an ARINC 818 video signal. GPUs typically use the DisplayPort (DP) protocol for video output, so the GPU's video signal can be considered a DP video signal.

[0026] Currently, 4K (3840×2160@60Hz) ultra-high-definition video is widely used in the civilian market, but has yet to be applied in the airborne field. With the development of aircraft displays, 4K technology will gradually be applied on aircraft. Therefore, a method for overlaying 4K ultra-high-definition video is urgently needed.

[0027] In order to solve the above technical problems, an embodiment of the present application provides a video overlay method, which is implemented by an FPGA (Field Programmable Gate Array). The method includes: decoding an input first video signal to obtain a second video signal, and caching the second video signal into a memory, where the first video signal is a DP video signal output by an image processor (GPU); detecting whether there is a third video signal, where the third video signal is an input ARINC818 video signal; when the third video signal is detected, decoding the third video signal to obtain a fourth video signal; superimposing the second video signal read from the memory with the fourth video signal to obtain a fifth video signal; encoding the fifth video signal to obtain a sixth video signal, and outputting the sixth video signal to a display panel.

[0028] The video overlay method of the embodiment of the present application is implemented through FPGA, and can decode and overlay the ARINC818 video signal output by the camera and the DP video signal output by the GPU, and then encode the overlaid video signal and output it to the display panel for display. This not only enables the overlay of 4K resolution DP video signals and ARINC818 video signals, solving the problem of high-resolution driving screen display for airborne display control, but also completely encodes and decodes the video signal through FPGA, is not limited by the DP codec chips on the market, and can also reduce peripheral devices to reduce costs, power consumption and board area.

[0029] Figure 1 A schematic diagram showing an application scenario of a video overlay method according to an embodiment of the present application is shown. Figure 1 As shown, the video overlay method of the embodiment of the present application is implemented by FPGA 130. FPGA 130 is connected to GPU 110, camera 120, display panel 140, and memory (DDR) 150. The GPU 110 has a DP interface, and the display panel 140 is a 4K ultra-high-definition LCD panel with an eDP (embedded DisplayPort) interface. DP / eDP supports a maximum link rate of 5.4 Gbps.

[0030] During video overlay, FPGA 130 receives the first video signal (DP video signal) output by GPU 110, decodes the first video signal to obtain a second video signal, and caches the second video signal in memory 150. Simultaneously, FPGA 130 receives the third video signal (ARINC818 video signal) output by camera 120, decodes the third video signal to obtain a fourth video signal. FPGA 130 then reads the second video signal from memory 150 and overlays the read second video signal with the fourth video signal to obtain a fifth video signal. FPGA 130 then encodes the fifth video signal to obtain a sixth video signal, which it outputs to display panel 140. In other words, the input signals to FPGA 130 include the first video signal (DP video signal) output by GPU 110 and the third video signal (ARINC818 video signal) output by camera 120, and the output signal from FPGA 130 is the sixth video signal. Memory 150 is used to cache the second video signal.

[0031] The first video signal and the third video signal are both 4K ultra-high-definition video signals. For example, the first video signal has a resolution of 3840×2160@60Hz. The third video signal may include multiple ARINC818 video signals. For example, the third video signal includes four ARINC818 video signals, each with a resolution of 960×2160@60Hz.

[0032] It should be noted that the first video signal and the third video signal can also be downwardly compatible with video signals of other resolutions, and this application does not impose any restrictions on this. Figure 1 In the application scenario described, the maximum resolution of the video signal is 4K (3840×2160)@60Hz.

[0033] In one possible implementation, when the video overlay method of an embodiment of the present application is implemented through FPGA, the FPGA may include a control module, a DP physical layer module, a DP link layer receiving module, a DP link layer sending module, a video access module, an ARINC818 decoding module, a video splicing module, a video generation and detection module, a video overlay module and a memory control module.

[0034] The control module can be considered the soft core of the FPGA. It can configure the DP physical layer module, DP link layer receiving module, DP link layer transmitting module, video access module, ARINC818 decoding module, video splicing module, video generation and detection module, video overlay module, etc. The control module is also responsible for the scheduling and operation of the entire FPGA. An example of a control module is Microblaze.

[0035] The DP physical layer module (DP PHY module) includes a high-speed serial transceiver (e.g., GTX) and physical layer configuration information for the DP link layer receiving module (DP RX MAC module) and the DP link layer transmitting module (DP TX MAC module). The DP physical layer module supports link rates of 1.62 Gbps, 2.7 Gbps, and 5.4 Gbps. The high-speed serial transceiver can be used to receive the first video signal (the DP video signal from the GPU) and transmit the sixth video signal (the video signal output by the FPGA). The DP physical layer module can also perform 8B / 10B encoding and decoding.

[0036] The DP link layer receiving module (DP RX MAC module) is the RX MAC protocol layer of DP, which is used to: perform link training with the GPU (Source Device) through the AUX (Auxiliary) channel; decode the first video signal from the DP physical layer module to obtain a second video signal. During the decoding process, the DP link layer receiving module can also extract the MSA (Main Stream Attribute) value of the first video signal. The data interface of the DP link layer receiving module is the AXI Stream interface, that is, after the DP link layer receiving module decodes the first video signal, the second video signal obtained is an AXI Stream video signal. In addition, since the DP video signal does not have a clock signal for synchronous transmission, the DP link layer receiving module can also perform clock recovery, data serial-to-parallel conversion and other processing.

[0037] Among them, the MSA value may include the total number of rows H_TOTAL, the total number of columns V_TOTAL, the row synchronization polarity HSyncPo l arity, the column synchronization polarity VSyncPo l ar ity, the row synchronization width HSyncWidth, the column synchronization width VSyncWidth, the row resolution H_Resol l ut ion, the column resolution V_Resol l ut ion, the row signal starting position H_Start, the column signal starting position V_Start, the M-VID register, the N-VID register, the DP pixel width UserPixsWidth and other information.

[0038] The DP link layer transmitter module (DP TX MAC module) is the DP TX MAC protocol layer, responsible for encoding AXI Stream video signals into DP protocol data and performing link training with the display panel (Sink Device). The DP link layer transmitter module also performs data parallel-to-serial conversion. During encoding, the DP link layer transmitter module can be configured via the AXI Line bus, such as the link rate, number of links, and MSA value.

[0039] The video access module (VDMA) is used to cache the decoded DP video signal (i.e., the second video signal) in DDR memory. The clock source used by the video access module to cache the second video signal in DDR is the clock recovered by the DP link layer receiving module. The video access module uses a local clock source to read the second video signal from DDR. Furthermore, the local clock source is also provided to the ARINC818 decoding module, thereby achieving timing conversion of the video signal.

[0040] The ARINC818 decoding module decodes the input ARINC818 video signal, automatically matching the link rate and ICD profile, and reporting status to the control module. The maximum link rate supported by the ARINC818 decoding module is 4.25Gpbs.

[0041] The video splicing module is used to splice the decoded video signals (fourth video signal) of multiple (for example, four) ARINC818 video signals. Due to the high resolution of 4K, the standard link rate can only reach a maximum of 4.25Gbps. Therefore, multiple video channels can be spliced ​​and transmitted. The resolution of each video channel is 960x2160@60Hz.

[0042] The video generation and detection module is used to directly output the video signal from the video access module, detect the presence of an input ARINC818 video signal, and generate a video signal (for example, using a TPG (Test Pattern Generator)). Based on the detection results of the video generation and detection module, the video overlay module can choose to overlay the ARINC818 video signal or the generated video signal with the video signal (second video signal) decoded from the DP video signal. The input and output interfaces of the video generation and detection module are both AXI Stream interfaces.

[0043] The video overlay module is used to overlay the video signal (second video signal) after decoding the DP video signal with the video signal (fourth video signal) after decoding the ARINC818 video signal. Its data input and output interfaces are both AXI Stream interfaces. When no ARINC818 video signal is detected (i.e., when no ARINC818 video signal is input), the video overlay module overlays the video signal (second video signal) after decoding the DP video signal with the generated video signal.

[0044] The memory control module is a DDR controller, such as a MIG (Memory Interface Generator), which is used to control the reading and writing of DDR data.

[0045] Figure 2 FIG. 1 shows a schematic diagram of an FPGA according to an embodiment of the present application. Figure 2As shown, FPGA 200 includes a control module 201, a DP physical layer module 202, a DP link layer receiving module 203, a DP link layer transmitting module 204, a memory control module 205, a video access module 206, a video generation and detection module 207, a video overlay module 208, a video splicing module 209, an ARINC818 decoding module 210, an ARINC818 decoding module 211, an ARINC818 decoding module 212, and an ARINC818 decoding module 213. The video access module 206 is connected to the memory control module 205 via an AXI bus.

[0046] The DP physical layer module 202 is configured to receive video signals via the DP interface and output video signals via the eDP interface. The ARINC 818 video signals include four channels: ARINC 818 video signal 0, ARINC 818 video signal 1, ARINC 818 video signal 2, and ARINC 818 video signal 3. ARINC 818 video signal 0 is input to the ARINC 818 decoding module 210 for decoding, ARINC 818 video signal 1 is input to the ARINC 818 decoding module 211 for decoding, ARINC 818 video signal 2 is input to the ARINC 818 decoding module 212 for decoding, and ARINC 818 video signal 3 is input to the ARINC 818 decoding module 210 for decoding.

[0047] The video splicing module 209 splices the decoded ARINC818 video signals. The splicing method is as follows: the 0th pixel data of each row corresponds to the 0th pixel of ARINC818 video signal 0 after decoding, the 1st pixel data corresponds to the 0th pixel of ARINC818 video signal 1 after decoding, the 2nd pixel data corresponds to the 0th pixel of ARINC818 video signal 2 after decoding, and the 3rd pixel data corresponds to the 0th pixel of ARINC818 video signal 3 after decoding; the 4th pixel data corresponds to the 1st pixel of ARINC818 video signal 0 after decoding, the 5th pixel data corresponds to the 1st pixel of ARINC818 video signal 1 after decoding, the 6th pixel data corresponds to the 1st pixel of ARINC818 video signal 2 after decoding, the 7th pixel data corresponds to the 1st pixel of ARINC818 video signal 3 after decoding; the 8th pixel data corresponds to the 2nd pixel of ARINC818 video signal 0 after decoding, and so on, completing the splicing of the four decoded ARINC818 video signals.

[0048] In one possible implementation, before the FPGA runs the video overlay method of the embodiment of the present application, it needs to be configured. After the FPGA is powered on, its control module first trains the first link between the FPGA and the display panel. Specifically, the control module of the FPGA can obtain the EDI D (Extended Display Identification Data) of the display panel and train the first link between the DP link layer sending module and the display panel; after obtaining the link rate and the number of links (lanes) of the first link, the first link training can be considered successful. For example, when the first video signal is a 4K@60Hz DP video signal, the third video signal is a 4-channel ARINC818 video signal and the resolution of each ARINC818 video signal is 960×2160@Hz, and the display panel is a 4K@60Hz eDP interface LCD display panel, the link rate of the first link obtained by training is 5.4Gbps and the number of links is 4.

[0049] Afterwards, the control module trains the second link between the FPGA and the GPU. Specifically, the control module can copy the EDID, link rate, and number of links to the relevant registers of the DP link layer receiving module, and then configure the DP link layer receiving module according to EDI D, link rate, and number of links: configure EDI D as the EDI D of the DP link layer receiving module, and configure the DP link layer receiving module to operate at the link rate and the number of links. For example, assuming that the link rate obtained through training is 5.4Gbps and the number of links is 4, then the control module can configure the DP link layer receiving module to operate in a mode with a link rate of 5.4Gbps and a number of links of 4.

[0050] After the DP link layer receiving module is configured, the DP link layer receiving module sends a hot plug detection HPD (HotPlug Detect) signal to the GPU to trigger the training of the second link between the DP link layer receiving module and the GPU. When the link rate and link number of the second link obtained through training are consistent with its configuration, the second link training can be considered successful; otherwise, the second link training can be considered a failure. For example, assuming that the control module configures the DP link layer receiving module to operate in a mode with a link rate of 5.4Gbps and a link number of 4, then when training the second link, if the link rate of the second link obtained through training is 5.4Gbps and the link number is 4, the second link training can be considered successful; otherwise, the second link training can be considered a failure.

[0051] After the second link training is successful, the GPU will send a DP video signal to the FPGA; after the FPGA receives the DP video signal, its DP link layer receiving module extracts the MSA value from the DP video signal; the control module sends the MSA value extracted by the DP link layer receiving module to the DP link layer sending module (for example, copies the MSA value to the relevant register of the DP link layer sending module), and enables the DP link layer sending module.

[0052] Among them, the MSA value extracted by the DP link layer receiving module from the DP video signal is, for example: the total number of rows H_TOTAL is 0x0fa0, the total number of columns V_TOTAL is 0x08ae, the row synchronization polarity HSyncPo l ar ity is 1, the column synchronization polarity VSyncPo l ar ity is 1, the row synchronization width HSyncWidth is 0x40, the column synchronization width VSyncWidth is 0x5, the row resolution H_Resol ut ion is 0xf00, the column resolution V_Resol ut ion is 0x870, the row signal starting position H_Start is 0x70, the column signal starting position V_Start is 0x3b, the M-VID register is 0x7e67, the N-VID register is 0x8000, and the DP pixel width UserPixsWidth is 0x4.

[0053] Figure 3 FIG. 1 is a schematic diagram showing an FPGA configuration process according to an embodiment of the present application. Figure 3 As shown in the figure, the FPGA configuration process includes:

[0054] Step S310: The control module of the FPGA obtains the EDI D of the display panel and trains the first link between the DP link layer sending module and the display panel;

[0055] Step S320, detecting whether the first link is successfully trained: after obtaining the link rate and the number of links (lanes) of the first link, the first link training may be considered successful, otherwise the first link training may be considered failed;

[0056] If the first link training fails, step S310 is executed again; if the first link training succeeds, step S330 is executed below;

[0057] Step S330: The control module configures the DP link layer receiving module according to the EDI D, link rate, and number of links;

[0058] Step S340: The DP link layer receiving module sends an HPD signal to the GPU to trigger training of the second link between the DP link layer receiving module and the GPU;

[0059] Step S350 , detecting whether the second link is successfully trained: if the link rate and link number of the second link obtained through training are consistent with its configuration, the second link training is considered successful; otherwise, the second link training is considered failed;

[0060] If the second link training fails, step S310 is executed again; if the second link training succeeds, step S360 is executed below;

[0061] Step S360: The control module sends the MSA value to the DP link layer sending module and enables the DP link layer sending module.

[0062] After the above configuration, the FPGA starts to run, that is, the FPGA starts to superimpose the input DP video signal and ARINC818 video signal.

[0063] Figure 4 FIG. 1 is a flow chart showing a video overlay method according to an embodiment of the present application. Figure 4 As shown, the video overlay method includes:

[0064] Step S410: decode the input first video signal to obtain a second video signal, and cache the second video signal in a memory.

[0065] The first video signal is a DP video signal output by the GPU.

[0066] After the first video signal is input into the FPGA, the DP physical layer module of the FPGA receives the first video signal and sends the first video signal to the DP link layer receiving module; the DP link layer receiving module decodes the first video signal received from the DP physical layer module to obtain a second video signal, which is an AXI Stream video signal.

[0067] After the second video signal is obtained, the second video signal can be cached in a memory connected to the FPGA through the video storage module and the memory control module of the FPGA.

[0068] Step S420: When the third video signal is detected, the third video signal is decoded to obtain a fourth video signal.

[0069] The third video signal is an input ARINC818 video signal.

[0070] The presence of the third video signal (ie, the presence of the input ARINC818 video signal) may be detected by the video generation and detection module of the FPGA.

[0071] When the third video signal is detected, the ARINC818 decoding module of the FPGA can decode the third video signal to obtain a fourth video signal, which is an AXI Stream video signal. If the third video signal includes multiple ARINC818 video signals, the ARINC818 decoding module can decode each ARINC818 video signal to obtain a corresponding tenth video signal; then, the video splicing module splices the multiple tenth video signals to obtain the fourth video signal.

[0072] For example, when the third video signal includes 4 ARINC818 video signals and the resolution of each ARINC818 video signal is 960×2160@Hz, the 4 ARINC818 video signals can be decoded by 4 ARINC818 decoding modules (that is, 1 ARINC818 decoding module decodes 1 ARINC818 video signal, and the ARINC818 decoding module corresponds one to one to the ARINC818 video signal) to obtain 4 tenth video signals; then, the 4 tenth video signals are spliced ​​by the video splicing module to obtain a fourth video signal, which is a 1-channel video signal with a resolution of 4K (3840×2160)@Hz.

[0073] In step S430 , the second video signal read from the memory is superimposed on the fourth video signal to obtain a fifth video signal.

[0074] After obtaining the second video signal and the fourth video signal, the second video signal can be read from the memory through the FPGA video storage module and the memory control module, and the second video signal read from the memory and the fourth video signal can be superimposed through the FPGA video overlay module to obtain the fifth video signal.

[0075] Step S440 : Encode the fifth video signal to obtain a sixth video signal, and output the sixth video signal to a display panel.

[0076] After obtaining the fifth video signal, the fifth video signal can be encoded through the DP link layer sending module of the FPGA to obtain the sixth video signal, and then the sixth video signal can be sent to the DP physical layer module; after the DP physical layer module receives the sixth video signal, the sixth video signal can be output to the display panel for display through the eDP interface.

[0077] In one possible implementation, when the third video signal is not detected, a seventh video signal can be generated by the video generation and detection module of the FPGA; then, the second video signal read from the memory and the generated seventh video signal are superimposed by the video overlay module of the FPGA to obtain an eighth video signal; then, the eighth video signal is encoded by the DP link layer sending module of the FPGA to obtain a ninth video signal, and the ninth video signal is sent to the DP physical layer module; after the DP physical layer module receives the ninth video signal, the ninth video signal can be output to the display panel for display through the eDP interface.

[0078] Figure 5 FIG. 1 is a schematic diagram showing a video overlay method according to an embodiment of the present application. Figure 5 As shown, the video overlay method includes:

[0079] Step S510: decoding the input first video signal to obtain a second video signal, and buffering the second video signal into a memory, wherein the first video signal is a DP video signal output by the GPU;

[0080] Step S520, detecting whether a third video signal exists, where the third video signal is an input ARINC818 video signal;

[0081] In case the third video signal is detected, the following steps are performed:

[0082] Step S530, decoding the third video signal to obtain a fourth video signal;

[0083] Step S540: superimpose the second video signal read from the memory and the fourth video signal to obtain a fifth video signal;

[0084] Step S550, encoding the fifth video signal to obtain a sixth video signal, and outputting the sixth video signal to a display panel;

[0085] In the case that the third video signal is not detected, the following steps are performed:

[0086] Step S560, generating a seventh video signal;

[0087] Step S570: superimpose the second video signal read from the memory and the seventh video signal to obtain an eighth video signal;

[0088] Step S580 , encoding the eighth video signal to obtain a ninth video signal, and outputting the ninth video signal to the display panel.

[0089] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, systems, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a part for a module, program segment or instruction, and the part for the module, program segment or instruction comprises one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous boxes can actually be performed substantially in parallel, and they can sometimes also be performed in the opposite order, depending on the function involved.

[0090] It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented by hardware that performs the corresponding function or action (such as a circuit or ASIC (Application Specific Integrated Circuit)), or can be implemented by a combination of hardware and software, such as firmware.

[0091] Although the present invention has been described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit may implement several functions listed in the claims. The fact that certain measures are recorded in different dependent claims does not mean that these measures cannot be combined to produce good results.

[0092] The embodiments of the present application have been described above. The above description is illustrative and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A video overlay method, characterized in that: The method is implemented by FPGA, and the method includes: Decoding an input first video signal to obtain a second video signal, and buffering the second video signal in a memory, where the first video signal is a DP video signal output by a graphics processing unit (GPU); When a third video signal is detected, the third video signal is decoded to obtain a fourth video signal, where the third video signal is an ARINC818 video signal output by the FPGA receiving camera and is a 4K ultra-high-definition video signal; superimposing the second video signal read from the memory and the fourth video signal to obtain a fifth video signal; encoding the fifth video signal to obtain a sixth video signal, and outputting the sixth video signal to a display panel; The decoding of the third video signal to obtain the fourth video signal includes: In the case where the third video signal includes multiple ARINC818 video signals, decoding each ARINC818 video signal to obtain a corresponding tenth video signal; splicing the multiple tenth video signals to obtain a fourth video signal; The method further comprises: generating a seventh video signal when the third video signal is not detected; superimposing the second video signal read from the memory with the seventh video signal to obtain an eighth video signal; encoding the eighth video signal to obtain a ninth video signal, and outputting the ninth video signal to a display panel; The resolution of the first video signal is 3840×2160@60Hz, and the third video signal includes four ARINC818 video signals, which are ARINC818 video signal 0, ARINC818 video signal 1, ARINC818 video signal 2, and ARINC818 video signal 3, respectively. The resolution of each ARINC818 video signal is 960×2160@60Hz. The FPGA includes a control module, a DP physical layer module, a DP link layer receiving module, a DP link layer sending module, a video access module, an ARINC818 decoding module, a video splicing module, a video generation and detection module, a video overlay module and a memory control module; The video splicing module is used to splice the four decoded ARINC818 video signals in the following manner: the 0th pixel data of each row corresponds to the 0th pixel of ARINC818 video signal 0 after decoding, the 1st pixel data corresponds to the 0th pixel of ARINC818 video signal 1 after decoding, the 2nd pixel data corresponds to the 0th pixel of ARINC818 video signal 2 after decoding, and the 3rd pixel data corresponds to the 0th pixel of ARINC818 video signal 3 after decoding; the 4th pixel data corresponds to the 1st pixel of ARINC818 video signal 0 after decoding, the 5th pixel data corresponds to the 1st pixel of ARINC818 video signal 1 after decoding, the 6th pixel data corresponds to the 1st pixel of ARINC818 video signal 2 after decoding, the 7th pixel data corresponds to the 1st pixel of ARINC818 video signal 3 after decoding; the 8th pixel data corresponds to the 2nd pixel of ARINC818 video signal 0 after decoding; and so on, to complete the splicing of the four decoded ARINC818 video signals.

2. The method according to claim 1, characterized in that The method further comprises: After the FPGA is powered on, training a first link between the FPGA and the display panel; After the first link is successfully trained, the second link between the FPGA and the GPU is trained.

3. The method according to claim 2, characterized in that The training of the first link between the FPGA and the display panel includes: The control module obtains the EDID of the display panel; The control module trains the first link between the DP link layer sending module of the FPGA and the display panel to obtain a link rate and a link number of the first link.

4. The method according to claim 3, characterized in that The training of the second link between the FPGA and the GPU includes: The control module configures the DP link layer receiving module according to the EDID, the link rate and the number of links; The DP link layer receiving module sends a hot plug detection HPD signal to the GPU to trigger training of a second link between the DP link layer receiving module and the GPU; After the second link training is successful, the control module sends the MSA value to the DP link layer sending module and enables the DP link layer sending module.

5. The method according to claim 1, wherein The DP physical layer module is used to: receive the first video signal and send the first video signal to the DP link layer receiving module for decoding; receive the sixth video signal sent by the DP link layer sending module, and output the sixth video signal to the display panel.

6. The method according to claim 1, wherein The video generation and detection module is configured to: detect whether the third video signal exists; and generate a seventh video signal if the third video signal is not detected.

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